| /* |
| * Copyright (c) 2019 Intel Corporation |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <xtensa/xtensa.dtsi> |
| #include <mem.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx4"; |
| reg = <0>; |
| i-cache-line-size = <64>; |
| d-cache-line-size = <64>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx4"; |
| reg = <1>; |
| }; |
| }; |
| |
| sram0: memory@be000000 { |
| compatible = "mmio-sram"; |
| reg = <0xbe000000 DT_SIZE_K(512)>; |
| }; |
| |
| sram1: memory@be800000 { |
| compatible = "mmio-sram"; |
| reg = <0xbe800000 DT_SIZE_K(128)>; |
| }; |
| |
| sysclk: system-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <19200000>; |
| #clock-cells = <0>; |
| }; |
| |
| audioclk: audio-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <24576000>; |
| #clock-cells = <0>; |
| }; |
| |
| pllclk: pll-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <96000000>; |
| #clock-cells = <0>; |
| }; |
| |
| clkctl: clkctl { |
| compatible = "intel,adsp-shim-clkctl"; |
| adsp-clkctl-clk-lpro = <0>; |
| adsp-clkctl-clk-hpro = <2>; |
| adsp-clkctl-freq-enc = <0x3 0x1 0x0>; |
| adsp-clkctl-freq-default = <1>; |
| adsp-clkctl-freq-lowest = <0>; |
| }; |
| |
| soc { |
| shim: shim@1000 { |
| compatible = "intel,adsp-shim"; |
| reg = <0x1000 0x100>; |
| }; |
| |
| l2cc: l2cc@1500 { |
| compatible = "intel,cavs-l2cc"; |
| reg = <0x1500 0x40>; |
| }; |
| |
| mem_window0: mem_window@1580 { |
| compatible = "intel,adsp-mem-window"; |
| reg = <0x1580 0x8>; |
| offset = <0x4000>; |
| memory = <&sram0>; |
| initialize; |
| read-only; |
| }; |
| mem_window1: mem_window@1588 { |
| compatible = "intel,adsp-mem-window"; |
| reg = <0x1588 0x8>; |
| memory = <&sram0>; |
| }; |
| |
| mem_window2: mem_window@1590 { |
| compatible = "intel,adsp-mem-window"; |
| reg = <0x1590 0x8>; |
| memory = <&sram0>; |
| }; |
| |
| mem_window3: mem_window@1598 { |
| compatible = "intel,adsp-mem-window"; |
| reg = <0x1598 0x8>; |
| memory = <&sram0>; |
| offset = <0>; |
| read-only; |
| }; |
| |
| timer: timer { |
| compatible = "intel,adsp-timer"; |
| syscon = <&shim>; |
| }; |
| |
| core_intc: core_intc@0 { |
| compatible = "cdns,xtensa-core-intc"; |
| reg = <0x00 0x400>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| adsp_host_ipc: cavs_host_ipc@1180 { |
| compatible = "intel,adsp-host-ipc"; |
| reg = <0x1180 0x30>; |
| interrupts = <7 0 0>; |
| interrupt-parent = <&cavs_intc0>; |
| }; |
| |
| cavs_intc0: cavs@1600 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x1600 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <6 0 0>; |
| interrupt-parent = <&core_intc>; |
| }; |
| |
| cavs_intc1: cavs@1610 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x1610 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0xA 0 0>; |
| interrupt-parent = <&core_intc>; |
| }; |
| |
| cavs_intc2: cavs@1620 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x1620 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0XD 0 0>; |
| interrupt-parent = <&core_intc>; |
| }; |
| |
| cavs_intc3: cavs@1630 { |
| compatible = "intel,cavs-intc"; |
| reg = <0x1630 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0x10 0 0>; |
| interrupt-parent = <&core_intc>; |
| }; |
| |
| adsp_idc: idc@1200 { |
| compatible = "intel,adsp-idc"; |
| reg = <0x1200 0x80>; |
| interrupts = <8 0 0>; |
| interrupt-parent = <&cavs_intc0>; |
| }; |
| |
| lpgpdma0: dma@c000 { |
| compatible = "intel,adsp-gpdma"; |
| #dma-cells = <1>; |
| reg = <0x0000c000 0x1000>; |
| shim = <0x00000c00 0x080>; |
| interrupts = <0x10 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dma-buf-size-alignment = <4>; |
| dma-copy-alignment = <4>; |
| |
| status = "okay"; |
| }; |
| |
| lpgpdma1: dma@d000 { |
| compatible = "intel,adsp-gpdma"; |
| #dma-cells = <1>; |
| reg = <0x0000d000 0x1000>; |
| shim = <0x00000c80 0x080>; |
| interrupts = <0x0F 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dma-buf-size-alignment = <4>; |
| dma-copy-alignment = <4>; |
| |
| status = "okay"; |
| }; |
| |
| hda_link_out: dma@2400 { |
| compatible = "intel,adsp-hda-link-out"; |
| #dma-cells = <1>; |
| reg = <0x00002400 0x20>; |
| dma-channels = <2>; |
| dma-buf-addr-alignment = <128>; |
| dma-buf-size-alignment = <32>; |
| dma-copy-alignment = <32>; |
| |
| status = "okay"; |
| }; |
| |
| hda_link_in: dma@2600 { |
| compatible = "intel,adsp-hda-link-in"; |
| #dma-cells = <1>; |
| reg = <0x00002600 0x20>; |
| dma-channels = <2>; |
| dma-buf-addr-alignment = <128>; |
| dma-buf-size-alignment = <32>; |
| dma-copy-alignment = <32>; |
| |
| status = "okay"; |
| }; |
| |
| hda_host_out: dma@2800 { |
| compatible = "intel,adsp-hda-host-out"; |
| #dma-cells = <1>; |
| reg = <0x00002800 0x40>; |
| dma-channels = <6>; |
| dma-buf-addr-alignment = <128>; |
| dma-buf-size-alignment = <32>; |
| dma-copy-alignment = <32>; |
| |
| status = "okay"; |
| }; |
| |
| hda_host_in: dma@2c00 { |
| compatible = "intel,adsp-hda-host-in"; |
| #dma-cells = <1>; |
| reg = <0x00002c00 0x40>; |
| dma-channels = <7>; |
| dma-buf-addr-alignment = <128>; |
| dma-buf-size-alignment = <32>; |
| dma-copy-alignment = <32>; |
| |
| status = "okay"; |
| }; |
| |
| ssp0: ssp@8000 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008000 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x01 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 2 |
| &lpgpdma0 3>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| ssp1: ssp@8200 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008200 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x01 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 4 |
| &lpgpdma0 5>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| ssp2: ssp@8400 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008400 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x02 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 6 |
| &lpgpdma0 7>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| ssp3: ssp@8600 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008600 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 8 |
| &lpgpdma0 9>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| ssp4: ssp@8800 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008800 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 10 |
| &lpgpdma0 11>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| ssp5: ssp@8a00 { |
| compatible = "intel,ssp-dai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x00008A00 0x200 |
| 0x00008E00 0x008>; |
| interrupts = <0x03 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| dmas = <&lpgpdma0 12 |
| &lpgpdma0 13>; |
| dma-names = "tx", "rx"; |
| |
| status = "okay"; |
| }; |
| |
| dmic0: dmic0@4000 { |
| compatible = "intel,dai-dmic"; |
| reg = <0x4000 0x8000>; |
| shim = <0x1000>; |
| fifo = <0x0008>; |
| interrupts = <0x08 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| }; |
| |
| dmic1: dmic1@4000 { |
| compatible = "intel,dai-dmic"; |
| reg = <0x4000 0x8000>; |
| shim = <0x1000>; |
| fifo = <0x0108>; |
| interrupts = <0x09 0 0>; |
| interrupt-parent = <&cavs_intc3>; |
| }; |
| |
| }; |
| }; |
