| /* |
| * Copyright (c) 2023-2024 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
| #include <zephyr/dt-bindings/clock/stm32wba_clock.h> |
| #include <zephyr/dt-bindings/reset/stm32wba_reset.h> |
| #include <zephyr/dt-bindings/adc/stm32u5_adc.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/power/stm32_pwr.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| st,lptim-stdby-timer = &rtc; |
| zephyr,bt-hci = &bt_hci_wba; |
| zephyr,ieee802154 = &ieee802154; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| /* Do not add &standby here since CONFIG_PM_S2RAM is disabled by default */ |
| cpu-power-states = <&stop0 &stop1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| |
| power-states { |
| stop0: state0 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| min-residency-us = <100>; |
| }; |
| |
| stop1: state1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <2>; |
| min-residency-us = <500>; |
| }; |
| |
| standby: state2 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-ram"; |
| substate-id = <1>; |
| min-residency-us = <1000>; |
| /* |
| * From DS: worst case Twu_stdby with retention = 51.49 us |
| * Add extra margin to take resume code into account. |
| */ |
| exit-latency-us = <150>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "SRAM0"; |
| }; |
| |
| /* Defining this memory solves unaligned memory access issue */ |
| sram6: memory@48028000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x48028000 DT_SIZE_K(16)>; |
| device_type = "memory"; |
| zephyr,memory-region = "SRAM6"; |
| zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32wba-hse-clock"; |
| clock-frequency = <DT_FREQ_M(32)>; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <1>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll1: pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32wba-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcos { |
| mco1: mco1 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <6 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <16>; |
| erase-block-size = <8192>; |
| /* maximum erase time(ms) for a 8K sector */ |
| max-erase-time = <5>; |
| }; |
| }; |
| |
| rcc: rcc@46020c00 { |
| compatible = "st,stm32wba-rcc"; |
| clocks-controller; |
| #clock-cells = <2>; |
| reg = <0x46020c00 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| pwr: power@46020800 { |
| compatible = "st,stm32-pwr"; |
| reg = <0x46020800 0x400>; |
| wkup-pins-nb = <8>; |
| wkup-pin-srcs = <2>; |
| wkup-pins-pol; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| |
| wkup-pin@1 { |
| reg = <0x1>; |
| wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_EVT_SRC_0>, |
| <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>; |
| }; |
| |
| wkup-pin@2 { |
| reg = <0x2>; |
| wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_EVT_SRC_1>; |
| }; |
| |
| wkup-pin@3 { |
| reg = <0x3>; |
| wkup-gpios = <&gpioa 1 STM32_PWR_WKUP_EVT_SRC_1>, |
| <&gpiob 6 STM32_PWR_WKUP_EVT_SRC_2>; |
| }; |
| |
| wkup-pin@4 { |
| reg = <0x4>; |
| wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_EVT_SRC_0>, |
| <&gpiob 1 STM32_PWR_WKUP_EVT_SRC_1>; |
| }; |
| |
| wkup-pin@5 { |
| reg = <0x5>; |
| wkup-gpios = <&gpioa 3 STM32_PWR_WKUP_EVT_SRC_1>, |
| <&gpiob 7 STM32_PWR_WKUP_EVT_SRC_2>; |
| }; |
| |
| wkup-pin@6 { |
| reg = <0x6>; |
| wkup-gpios = <&gpioa 12 STM32_PWR_WKUP_EVT_SRC_0>, |
| <&gpioa 5 STM32_PWR_WKUP_EVT_SRC_1>; |
| }; |
| |
| wkup-pin@7 { |
| reg = <0x7>; |
| wkup-gpios = <&gpiob 14 STM32_PWR_WKUP_EVT_SRC_0>, |
| <&gpioa 6 STM32_PWR_WKUP_EVT_SRC_1>; |
| }; |
| |
| wkup-pin@8 { |
| reg = <0x8>; |
| wkup-gpios = <&gpioa 7 STM32_PWR_WKUP_EVT_SRC_1>, |
| <&gpiob 9 STM32_PWR_WKUP_EVT_SRC_2>; |
| }; |
| }; |
| |
| exti: interrupt-controller@46022000 { |
| compatible = "st,stm32g0-exti", "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0x46022000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB7, 1)>; |
| num-lines = <32>; |
| interrupts = <11 0>, <12 0>, <13 0>, <14 0>, |
| <15 0>, <16 0>, <17 0>, <18 0>, |
| <19 0>, <20 0>, <21 0>, <22 0>, |
| <23 0>, <24 0>, <25 0>, <26 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5", "line6", "line7", |
| "line8", "line9", "line10", "line11", |
| "line12", "line13", "line14", "line15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 1>, <6 1>, <7 1>, |
| <8 1>, <9 1>, <10 1>, <11 1>, |
| <12 1>, <13 1>, <14 1>, <15 1>; |
| }; |
| |
| pinctrl: pin-controller@42020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x42020000 0x2000>; |
| |
| gpioa: gpio@42020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 0)>; |
| }; |
| |
| gpiob: gpio@42020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 1)>; |
| }; |
| |
| gpioc: gpio@42020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 2)>; |
| }; |
| |
| gpioh: gpio@42021c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 7)>; |
| }; |
| }; |
| |
| rtc: rtc@46007800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x46007800 0x400>; |
| interrupts = <2 0>; |
| clocks = <&rcc STM32_CLOCK(APB7, 21)>; |
| alarms-count = <2>; |
| status = "disabled"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11)>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14)>; |
| resets = <&rctl STM32_RESET(APB2, 14)>; |
| interrupts = <46 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17)>; |
| resets = <&rctl STM32_RESET(APB1L, 17)>; |
| interrupts = <47 0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@46002400 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x46002400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB7, 6)>; |
| resets = <&rctl STM32_RESET(APB7, 6)>; |
| interrupts = <48 0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| interrupts = <45 5>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12)>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@46002000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x46002000 0x400>; |
| interrupts = <63 5>; |
| clocks = <&rcc STM32_CLOCK(APB7, 5)>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21)>; |
| interrupts = <43 0>, <44 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@46002800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x46002800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB7, 7)>; |
| interrupts = <54 0>, <55 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 11)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 11)>; |
| interrupts = <37 0>, <38 0>, <39 0>, <40 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 0)>; |
| interrupts = <41 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 1)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 1)>; |
| interrupts = <42 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 17)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 17)>; |
| interrupts = <51 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 18)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 18)>; |
| interrupts = <52 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| adc4: adc@46021000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x46021000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 5)>, |
| <&rcc STM32_SRC_HCLK1 ADC_SEL(0)>; |
| interrupts = <65 0>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <2 4 8 13 20 40 80 815>; |
| num-sampling-time-common-channels = <2>; |
| st,adc-clock-source = "ASYNC"; |
| st,adc-sequencer = "fixed"; |
| st,adc-oversampler = "minimal"; |
| st,adc-internal-regulator = "startup-hw-status"; |
| status = "disabled"; |
| }; |
| |
| lptim1: timers@46004400 { |
| compatible = "st,stm32-lptim"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x46004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB7, 11)>; |
| interrupts = <49 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| lptim2: timers@40009400 { |
| compatible = "st,stm32-lptim"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40009400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 5)>; |
| interrupts = <50 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| rng: rng@420c0800 { |
| compatible = "st,stm32-rng"; |
| reg = <0x420c0800 0x400>; |
| interrupts = <59 0>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 18)>, |
| <&rcc STM32_SRC_HSI16 RNG_SEL(2)>; |
| nist-config = <0xf00d>; |
| health-test-config = <0xaac7>; |
| status = "disabled"; |
| }; |
| |
| gpdma1: dma@40020000 { |
| compatible = "st,stm32u5-dma"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x1000>; |
| interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0)>; |
| dma-channels = <8>; |
| dma-requests = <52>; |
| dma-offset = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3000>; |
| io-channels = <&adc4 13>; |
| status = "disabled"; |
| }; |
| |
| bt_hci_wba: bt_hci_wba { |
| compatible = "st,hci-stm32wba"; |
| status = "okay"; |
| }; |
| |
| ieee802154: ieee802154 { |
| compatible = "st,stm32wba-ieee802154"; |
| status = "disabled"; |
| }; |
| |
| swj_port: swj_port { |
| compatible = "swj-connector"; |
| pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14 |
| &debug_jtdi_pa15 &debug_jtdo_swo_pb3 |
| /* temp fix to cover current wba5 pin naming */ |
| &debug_jtrst_pb4>; |
| pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15 |
| &analog_pb3 &analog_pb4>; |
| pinctrl-names = "default", "sleep"; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus3: smbus3 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
