| /* |
| * Copyright (c) 2018 Seitz & Associates |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/f3/stm32f3.dtsi> |
| |
| / { |
| soc { |
| usb: usb@40005c00 { |
| /* Remap USB_LP IRQ to enable use with CAN_1 */ |
| interrupts = <75 0>; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>, |
| /* I2C clock source should always be defined, |
| * even for the default value |
| */ |
| <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40007800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40007800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>, |
| /* I2C clock source should always be defined, |
| * even for the default value |
| */ |
| <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>; |
| interrupts = <72 0>, <73 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| interrupts = <36 5>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40003c00 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0X40003c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; |
| interrupts = <51 5>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| resets = <&rctl STM32_RESET(APB1, 2U)>; |
| interrupts = <30 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| adc1: adc@50000000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| temp-channel = <16>; |
| vref-channel = <18>; |
| }; |
| }; |
| }; |