commit 5a7f80feb3f731254fbdc516387ff9e8b8eb757c
author Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no> Fri Mar 24 09:03:01 2023 +0100
committer Anas Nashif <anas.nashif@intel.com> Sat May 27 06:26:13 2023 -0400
tree 00a7b682de1eb4658e6e244f50b73f1272dc4771
parent b0585be1c4447642cdd8d34ddb413c3586de66e9

tests: kernel: usage: Relax timing requirements for RISCV

Test was previously relaxed for RISCV machine timer. I have a
platform where it fails on RISCV requiring further relaxation.
Relaxing precision for RISCV architecture.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>

tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c

diff --git a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c
index fe42c93..211cc11 100644
--- a/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c
+++ b/tests/kernel/usage/thread_runtime_stats/src/test_thread_runtime_stats.c
@@ -15,8 +15,8 @@
 	((((val1) * 100) < ((val2) * (100 + (pcnt)))) &&              \
 	 (((val1) * 100) > ((val2) * (100 - (pcnt))))) ? true : false
 
-#if defined(CONFIG_RISCV_MACHINE_TIMER)
-#define IDLE_EVENT_STATS_PRECISION 5
+#if defined(CONFIG_RISCV)
+#define IDLE_EVENT_STATS_PRECISION 7
 #else
 #define IDLE_EVENT_STATS_PRECISION 1
 #endif