| /* |
| * Copyright (c) 2015, Freescale Semiconductor, Inc. |
| * Copyright 2016-2018 NXP |
| * All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include "fsl_gpio.h" |
| |
| /* Component ID definition, used by tools. */ |
| #ifndef FSL_COMPONENT_ID |
| #define FSL_COMPONENT_ID "platform.drivers.gpio" |
| #endif |
| |
| /******************************************************************************* |
| * Variables |
| ******************************************************************************/ |
| |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; |
| static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; |
| #endif |
| |
| #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
| |
| #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL |
| |
| #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
| /*! @brief Array to map FGPIO instance number to clock name. */ |
| static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; |
| #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
| |
| #endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ |
| |
| #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |
| |
| /******************************************************************************* |
| * Prototypes |
| ******************************************************************************/ |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| /*! |
| * @brief Gets the GPIO instance according to the GPIO base |
| * |
| * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) |
| * @retval GPIO instance |
| */ |
| static uint32_t GPIO_GetInstance(GPIO_Type *base); |
| #endif |
| /******************************************************************************* |
| * Code |
| ******************************************************************************/ |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| static uint32_t GPIO_GetInstance(GPIO_Type *base) |
| { |
| uint32_t instance; |
| |
| /* Find the instance index from base address mappings. */ |
| for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) |
| { |
| if (s_gpioBases[instance] == base) |
| { |
| break; |
| } |
| } |
| |
| assert(instance < ARRAY_SIZE(s_gpioBases)); |
| |
| return instance; |
| } |
| #endif |
| /*! |
| * brief Initializes a GPIO pin used by the board. |
| * |
| * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. |
| * Then, call the GPIO_PinInit() function. |
| * |
| * This is an example to define an input pin or an output pin configuration. |
| * code |
| * // Define a digital input pin configuration, |
| * gpio_pin_config_t config = |
| * { |
| * kGPIO_DigitalInput, |
| * 0, |
| * } |
| * //Define a digital output pin configuration, |
| * gpio_pin_config_t config = |
| * { |
| * kGPIO_DigitalOutput, |
| * 0, |
| * } |
| * endcode |
| * |
| * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| * param pin GPIO port pin number |
| * param config GPIO pin configuration pointer |
| */ |
| void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) |
| { |
| assert(config); |
| |
| if (config->pinDirection == kGPIO_DigitalInput) |
| { |
| base->PDDR &= ~(1U << pin); |
| } |
| else |
| { |
| GPIO_PinWrite(base, pin, config->outputLogic); |
| base->PDDR |= (1U << pin); |
| } |
| } |
| |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| /*! |
| * brief Reads the GPIO port interrupt status flag. |
| * |
| * If a pin is configured to generate the DMA request, the corresponding flag |
| * is cleared automatically at the completion of the requested DMA transfer. |
| * Otherwise, the flag remains set until a logic one is written to that flag. |
| * If configured for a level sensitive interrupt that remains asserted, the flag |
| * is set again immediately. |
| * |
| * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the |
| * pin 0 and 17 have the interrupt. |
| */ |
| uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) |
| { |
| uint8_t instance; |
| PORT_Type *portBase; |
| instance = GPIO_GetInstance(base); |
| portBase = s_portBases[instance]; |
| return portBase->ISFR; |
| } |
| |
| /*! |
| * brief Clears multiple GPIO pin interrupt status flags. |
| * |
| * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| * param mask GPIO pin number macro |
| */ |
| void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) |
| { |
| uint8_t instance; |
| PORT_Type *portBase; |
| instance = GPIO_GetInstance(base); |
| portBase = s_portBases[instance]; |
| portBase->ISFR = mask; |
| } |
| #endif |
| |
| #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER |
| /*! |
| * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit |
| * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| * bytes in the GACR follow a standard little endian |
| * data convention. |
| * |
| * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) |
| * param mask GPIO pin number macro |
| */ |
| void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) |
| { |
| base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | |
| ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); |
| } |
| #endif |
| |
| #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT |
| |
| /******************************************************************************* |
| * Variables |
| ******************************************************************************/ |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; |
| #endif |
| /******************************************************************************* |
| * Prototypes |
| ******************************************************************************/ |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| /*! |
| * @brief Gets the FGPIO instance according to the GPIO base |
| * |
| * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) |
| * @retval FGPIO instance |
| */ |
| static uint32_t FGPIO_GetInstance(FGPIO_Type *base); |
| #endif |
| /******************************************************************************* |
| * Code |
| ******************************************************************************/ |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| static uint32_t FGPIO_GetInstance(FGPIO_Type *base) |
| { |
| uint32_t instance; |
| |
| /* Find the instance index from base address mappings. */ |
| for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) |
| { |
| if (s_fgpioBases[instance] == base) |
| { |
| break; |
| } |
| } |
| |
| assert(instance < ARRAY_SIZE(s_fgpioBases)); |
| |
| return instance; |
| } |
| #endif |
| #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL |
| /*! |
| * brief Initializes the FGPIO peripheral. |
| * |
| * This function ungates the FGPIO clock. |
| * |
| * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| */ |
| void FGPIO_PortInit(FGPIO_Type *base) |
| { |
| #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
| /* Ungate FGPIO periphral clock */ |
| CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); |
| #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
| } |
| #endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ |
| |
| /*! |
| * brief Initializes a FGPIO pin used by the board. |
| * |
| * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. |
| * Then, call the FGPIO_PinInit() function. |
| * |
| * This is an example to define an input pin or an output pin configuration: |
| * code |
| * // Define a digital input pin configuration, |
| * gpio_pin_config_t config = |
| * { |
| * kGPIO_DigitalInput, |
| * 0, |
| * } |
| * //Define a digital output pin configuration, |
| * gpio_pin_config_t config = |
| * { |
| * kGPIO_DigitalOutput, |
| * 0, |
| * } |
| * endcode |
| * |
| * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| * param pin FGPIO port pin number |
| * param config FGPIO pin configuration pointer |
| */ |
| void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) |
| { |
| assert(config); |
| |
| if (config->pinDirection == kGPIO_DigitalInput) |
| { |
| base->PDDR &= ~(1U << pin); |
| } |
| else |
| { |
| FGPIO_PinWrite(base, pin, config->outputLogic); |
| base->PDDR |= (1U << pin); |
| } |
| } |
| #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) |
| /*! |
| * brief Reads the FGPIO port interrupt status flag. |
| * |
| * If a pin is configured to generate the DMA request, the corresponding flag |
| * is cleared automatically at the completion of the requested DMA transfer. |
| * Otherwise, the flag remains set until a logic one is written to that flag. |
| * If configured for a level-sensitive interrupt that remains asserted, the flag |
| * is set again immediately. |
| * |
| * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the |
| * pin 0 and 17 have the interrupt. |
| */ |
| uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) |
| { |
| uint8_t instance; |
| instance = FGPIO_GetInstance(base); |
| PORT_Type *portBase; |
| portBase = s_portBases[instance]; |
| return portBase->ISFR; |
| } |
| |
| /*! |
| * brief Clears the multiple FGPIO pin interrupt status flag. |
| * |
| * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| * param mask FGPIO pin number macro |
| */ |
| void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) |
| { |
| uint8_t instance; |
| instance = FGPIO_GetInstance(base); |
| PORT_Type *portBase; |
| portBase = s_portBases[instance]; |
| portBase->ISFR = mask; |
| } |
| #endif |
| #if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER |
| /*! |
| * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit |
| * words. Each 32-bit data port includes a GACR register, which defines the byte-level |
| * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data |
| * bytes in the GACR follow a standard little endian |
| * data convention. |
| * |
| * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) |
| * param mask FGPIO pin number macro |
| */ |
| void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) |
| { |
| base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | |
| (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); |
| } |
| #endif |
| |
| #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ |