| /* |
| * Copyright (c) 2020 Michael Schaffner |
| * Copyright (c) 2020 ITE Corporation. All Rights Reserved. |
| * |
| * SPDX-License-Identifier: SHL-0.51 |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef RISCV_CSR_ENCODING_H |
| #define RISCV_CSR_ENCODING_H |
| |
| #define MSTATUS_UIE 0x00000001 |
| #define MSTATUS_SIE 0x00000002 |
| #define MSTATUS_HIE 0x00000004 |
| #define MSTATUS_MIE 0x00000008 |
| #define MSTATUS_UPIE 0x00000010 |
| #define MSTATUS_SPIE 0x00000020 |
| #define MSTATUS_HPIE 0x00000040 |
| #define MSTATUS_MPIE 0x00000080 |
| #define MSTATUS_SPP 0x00000100 |
| #define MSTATUS_HPP 0x00000600 |
| #define MSTATUS_MPP 0x00001800 |
| #define MSTATUS_FS 0x00006000 |
| #define MSTATUS_XS 0x00018000 |
| #define MSTATUS_MPRV 0x00020000 |
| #define MSTATUS_PUM 0x00040000 |
| #define MSTATUS_MXR 0x00080000 |
| #define MSTATUS_VM 0x1F000000 |
| #define MSTATUS32_SD 0x80000000 |
| #define MSTATUS64_SD 0x8000000000000000 |
| |
| |
| #define MCAUSE32_CAUSE 0x7FFFFFFF |
| #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF |
| #define MCAUSE32_INT 0x80000000 |
| #define MCAUSE64_INT 0x8000000000000000 |
| |
| #define SSTATUS_UIE 0x00000001 |
| #define SSTATUS_SIE 0x00000002 |
| #define SSTATUS_UPIE 0x00000010 |
| #define SSTATUS_SPIE 0x00000020 |
| #define SSTATUS_SPP 0x00000100 |
| #define SSTATUS_FS 0x00006000 |
| #define SSTATUS_XS 0x00018000 |
| #define SSTATUS_PUM 0x00040000 |
| #define SSTATUS32_SD 0x80000000 |
| #define SSTATUS64_SD 0x8000000000000000 |
| |
| #define MIP_SSIP (1 << IRQ_S_SOFT) |
| #define MIP_HSIP (1 << IRQ_H_SOFT) |
| #define MIP_MSIP (1 << IRQ_M_SOFT) |
| #define MIP_STIP (1 << IRQ_S_TIMER) |
| #define MIP_HTIP (1 << IRQ_H_TIMER) |
| #define MIP_MTIP (1 << IRQ_M_TIMER) |
| #define MIP_SEIP (1 << IRQ_S_EXT) |
| #define MIP_HEIP (1 << IRQ_H_EXT) |
| #define MIP_MEIP (1 << IRQ_M_EXT) |
| |
| #define SIP_SSIP MIP_SSIP |
| #define SIP_STIP MIP_STIP |
| |
| #define PRV_U 0 |
| #define PRV_S 1 |
| #define PRV_H 2 |
| #define PRV_M 3 |
| |
| #define VM_MBARE 0 |
| #define VM_MBB 1 |
| #define VM_MBBID 2 |
| #define VM_SV32 8 |
| #define VM_SV39 9 |
| #define VM_SV48 10 |
| |
| #define IRQ_S_SOFT 1 |
| #define IRQ_H_SOFT 2 |
| #define IRQ_M_SOFT 3 |
| #define IRQ_S_TIMER 5 |
| #define IRQ_H_TIMER 6 |
| #define IRQ_M_TIMER 7 |
| #define IRQ_S_EXT 9 |
| #define IRQ_H_EXT 10 |
| #define IRQ_M_EXT 11 |
| #define IRQ_COP 12 |
| #define IRQ_HOST 13 |
| |
| #define DEFAULT_RSTVEC 0x00001000 |
| #define DEFAULT_NMIVEC 0x00001004 |
| #define DEFAULT_MTVEC 0x00001010 |
| #define EXT_IO_BASE 0x40000000 |
| #define DRAM_BASE 0x80000000 |
| |
| #ifdef __riscv64 |
| # define MSTATUS_SD MSTATUS64_SD |
| # define SSTATUS_SD SSTATUS64_SD |
| # define MCAUSE_INT MCAUSE64_INT |
| # define MCAUSE_CAUSE MCAUSE64_CAUSE |
| # define RISCV_PGLEVEL_BITS 9 |
| #else |
| # define MSTATUS_SD MSTATUS32_SD |
| # define SSTATUS_SD SSTATUS32_SD |
| # define RISCV_PGLEVEL_BITS 10 |
| # define MCAUSE_INT MCAUSE32_INT |
| # define MCAUSE_CAUSE MCAUSE32_CAUSE |
| #endif /* __riscv64 */ |
| |
| #define RISCV_PGSHIFT 12 |
| #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) |
| |
| #endif |
