| /* |
| * Copyright (c) 2017 Linaro Limited |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32f1_clock.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/stm32f1_adc.h> |
| #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/power/stm32_pwr.h> |
| #include <zephyr/dt-bindings/sensor/qdec_stm32.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &flash; |
| zephyr,cortex-m-idle-timer = &rtc; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m3"; |
| cpu-power-states = <&stop0 &stop1>; |
| reg = <0>; |
| }; |
| |
| power-states { |
| stop0: stop0 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <0>; |
| min-residency-us = <1000000>; |
| exit-latency-us = <400>; |
| }; |
| |
| stop1: stop1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| min-residency-us = <1000000>; |
| exit-latency-us = <600>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "SRAM0"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(8)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(40)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32f1-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcos { |
| mco1: mco1 { |
| compatible = "st,stm32f1-clock-mco"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <3 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 4)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <2>; |
| /* maximum erase time for a 2K sector */ |
| max-erase-time = <40>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32f1-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40010400 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40010400 0x400>; |
| num-lines = <32>; |
| interrupts = <6 0>, <7 0>, <8 0>, <9 0>, |
| <10 0>, <23 0>, <40 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5-9", "line10-15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 5>, <10 6>; |
| }; |
| |
| pinctrl: pin-controller@40010800 { |
| compatible = "st,stm32f1-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40010800 0x1C00>; |
| |
| gpioa: gpio@40010800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40010800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 2)>; |
| }; |
| |
| gpiob: gpio@40010c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40010c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 3)>; |
| }; |
| |
| gpioc: gpio@40011000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 4)>; |
| }; |
| |
| gpiod: gpio@40011400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 5)>; |
| }; |
| |
| gpioe: gpio@40011800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40011800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 6)>; |
| }; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14)>; |
| resets = <&rctl STM32_RESET(APB2, 14U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17)>; |
| resets = <&rctl STM32_RESET(APB1, 17U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 18)>; |
| resets = <&rctl STM32_RESET(APB1, 18U)>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21)>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 22)>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12)>; |
| interrupts = <35 5>; |
| status = "disabled"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11)>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 11)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1, 0U)>; |
| interrupts = <28 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 1)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1, 1U)>; |
| interrupts = <29 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 2)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1, 2U)>; |
| interrupts = <30 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 28)>; |
| prescaler = <32768>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32f1-adc", "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 9)>; |
| interrupts = <18 0>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32F1_ADC_RES(12)>; |
| sampling-times = <2 8 14 29 42 56 72 240>; |
| st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_NONE"; |
| st,adc-internal-regulator = "none"; |
| status = "disabled"; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma-v2bis"; |
| #dma-cells = <2>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0)>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| pwr: power@40007000 { |
| compatible = "st,stm32-pwr"; |
| reg = <0x40007000 0x400>; /* PWR register bank */ |
| status = "disabled"; |
| |
| wkup-pins-nb = <1>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| wkup-pin@1 { |
| reg = <0x1>; |
| wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp"; |
| io-channels = <&adc1 16>; |
| status = "disabled"; |
| avgslope = "4.3"; |
| v25 = <1430>; |
| ntc; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus2: smbus2 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
