| /* |
| * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> |
| * Copyright (c) 2019-2024 STMicroelectronics |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * Copyright (C) 2020 Framework Computer LLC <ktl@frame.work> |
| * Copyright (c) 2021 G-Technologies Sdn. Bhd. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv6-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32g0_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/adc/stm32l4_adc.h> |
| #include <zephyr/dt-bindings/power/stm32_pwr.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/sensor/qdec_stm32.h> |
| #include <zephyr/dt-bindings/reset/stm32g0_reset.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m0+"; |
| reg = <0>; |
| cpu-power-states = <&stop0 &stop1>; |
| }; |
| |
| power-states { |
| stop0: state0 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| min-residency-us = <20>; |
| }; |
| |
| stop1: state1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <2>; |
| min-residency-us = <100>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "SRAM0"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "st,stm32g0-hsi-clock"; |
| hsi-div = <1>; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32g0-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcos { |
| mco1: mco1 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| |
| mco2: mco2 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <3 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 8)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <8>; |
| erase-block-size = <2048>; |
| /* maximum erase time(ms) for a 2K sector */ |
| max-erase-time = <40>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32f0-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40021800 { |
| compatible = "st,stm32g0-exti", "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40021800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; |
| num-lines = <32>; |
| interrupts = <5 0>, <6 0>, <7 0>; |
| interrupt-names = "line0-1", "line2-3", "line4-15"; |
| line-ranges = <0 2>, <2 2>, <4 12>; |
| }; |
| |
| pinctrl: pin-controller@50000000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x50000000 0x2000>; |
| |
| gpioa: gpio@50000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(IOP, 0)>; |
| }; |
| |
| gpiob: gpio@50000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(IOP, 1)>; |
| }; |
| |
| gpioc: gpio@50000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(IOP, 2)>; |
| }; |
| |
| gpiod: gpio@50000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(IOP, 3)>; |
| }; |
| |
| gpiof: gpio@50001400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x50001400 0x400>; |
| clocks = <&rcc STM32_CLOCK(IOP, 5)>; |
| }; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <2 0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 10)>; |
| prescaler = <32768>; |
| alarms-count = <2>; |
| alrm-exti-line = <19>; |
| status = "disabled"; |
| |
| /* In STM32G0, the backup registers are defined as part of the TAMP |
| * peripheral. This peripheral is not implemented in Zephyr yet, however, |
| * the reference manual states that tamp_pclk is connected to rtc_pclk. |
| * It makes sense to have BBRAM instantiated as a child of RTC, so that |
| * the driver can verify that its parent device (RTC) is ready. |
| */ |
| bbram: backup_regs { |
| compatible = "st,stm32-bbram"; |
| st,backup-regs = <5>; |
| status = "disabled"; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11)>; |
| interrupts = <0 2>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 14)>; |
| resets = <&rctl STM32_RESET(APB1H, 14U)>; |
| interrupts = <27 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17)>; |
| resets = <&rctl STM32_RESET(APB1L, 17U)>; |
| interrupts = <28 0>; |
| status = "disabled"; |
| }; |
| |
| lptim1: timers@40007c00 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB1, 31)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40007c00 0x400>; |
| interrupts = <17 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 11)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1H, 11U)>; |
| interrupts = <13 0>, <14 0>; |
| interrupt-names = "brk_up_trg_com", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 1)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 1U)>; |
| interrupts = <16 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| |
| qdec { |
| compatible = "st,stm32-qdec"; |
| st,input-filter-level = <NO_FILTER>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers14: timers@40002000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 15)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1H, 15U)>; |
| interrupts = <19 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 17)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1H, 17U)>; |
| interrupts = <21 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 18)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1H, 18U)>; |
| interrupts = <22 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21)>; |
| interrupts = <23 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 22)>; |
| interrupts = <24 0>; |
| interrupt-names = "combined"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 12)>; |
| interrupts = <25 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 14)>; |
| interrupts = <26 0>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 20)>; |
| interrupts = <12 0>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| /* Errata ES0418: For sampling time set to 1.5 or 3.5 |
| * cycles, the sampling in a single ADC conversion or in |
| * the first conversion of a sequence takes one extra |
| * cycle. |
| * So instead of 2 4, we set 3 5. |
| */ |
| sampling-times = <3 5 8 13 20 40 80 161>; |
| num-sampling-time-common-channels = <2>; |
| st,adc-sequencer = "NOT_FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_MINIMAL"; |
| st,adc-internal-regulator = "startup-sw-delay"; |
| status = "disabled"; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma-v2"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x400>; |
| interrupts = <9 0 10 0 10 0 11 0 11 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0)>; |
| dma-requests = <5>; |
| dma-offset = <0>; |
| status = "disabled"; |
| }; |
| |
| /* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */ |
| dmamux1: dmamux@40020800 { |
| compatible = "st,stm32-dmamux"; |
| #dma-cells = <3>; |
| reg = <0x40020800 0x800>; |
| interrupts = <11 0>; |
| dma-channels = <5>; |
| dma-generators = <4>; |
| dma-requests = <49>; |
| status = "disabled"; |
| }; |
| |
| pwr: power@40007000 { |
| compatible = "st,stm32-pwr"; |
| reg = <0x40007000 0x400>; /* PWR register bank */ |
| status = "disabled"; |
| |
| wkup-pins-nb = <6>; /* 6 system wake-up pins */ |
| wkup-pins-pol; |
| wkup-pins-pupd; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| wkup-pin@1 { |
| reg = <0x1>; |
| wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| |
| wkup-pin@2 { |
| reg = <0x2>; |
| wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_NOT_MUXED>, |
| <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| |
| /* wkup-pin@3 only available for g0b0/1 and g0c1 variants */ |
| |
| wkup-pin@4 { |
| reg = <0x4>; |
| wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| |
| wkup-pin@5 { |
| reg = <0x5>; |
| wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| |
| wkup-pin@6 { |
| reg = <0x6>; |
| wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_NOT_MUXED>; |
| }; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FFF75A8>; |
| ts-cal2-addr = <0x1FFF75CA>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3000>; |
| io-channels = <&adc1 12>; |
| status = "disabled"; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x1FFF75AA>; |
| vrefint-cal-mv = <3000>; |
| io-channels = <&adc1 13>; |
| status = "disabled"; |
| }; |
| |
| vbat: vbat { |
| compatible = "st,stm32-vbat"; |
| ratio = <3>; |
| io-channels = <&adc1 14>; |
| status = "disabled"; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus2: smbus2 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <2>; |
| }; |
