dts/arm/st/l4/stm32l496.dtsi

/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/l4/stm32l475.dtsi>

/ {
	soc {
		clocks {
			clk_hsi48: clk-hsi48 {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <DT_FREQ_M(48)>;
				status = "disabled";
			};
		};

		rng: rng@50060800 {
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
		};

		i2c4: i2c@40008400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40008400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
			interrupts = <83 0>, <84 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		pinctrl: pin-controller@48000000 {
			reg = <0x48000000 0x2400>;

			gpioi: gpio@48002000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48002000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
			};
		};

		adc3: adc@50040200 {
			compatible = "st,stm32-adc";
			reg = <0x50040200 0x100>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
			interrupts = <47 0>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		usbotg_fs: otgfs@50000000 {
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
		};

		sdmmc1: sdmmc@40012800 {
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
		};
	};

	die_temp: dietemp {
		ts-cal2-temp = <130>;
	};
};