| /* |
| * Copyright (c) 2024-2025 Analog Devices, Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <mem.h> |
| #include <zephyr/dt-bindings/dma/max32657_dma.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &trng; |
| zephyr,flash-controller = &flc0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpu-power-states = <&idle &standby &powerdown>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| |
| power-states { |
| /* Sleep Mode */ |
| idle: idle { |
| compatible = "zephyr,power-state"; |
| power-state-name = "runtime-idle"; |
| min-residency-us = <50>; |
| exit-latency-us = <5>; |
| }; |
| |
| /* Standby Mode */ |
| standby: standby { |
| compatible = "zephyr,power-state"; |
| power-state-name = "standby"; |
| min-residency-us = <1000>; |
| exit-latency-us = <20>; |
| }; |
| |
| /* Powerdown Mode */ |
| powerdown: powerdown { |
| compatible = "zephyr,power-state"; |
| power-state-name = "soft-off"; |
| min-residency-us = <2147483647>; |
| exit-latency-us = <0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| clocks { |
| clk_ipo: clk_ipo { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_M(50)>; |
| status = "disabled"; |
| }; |
| |
| clk_inro: clk_inro { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_K(8)>; |
| status = "disabled"; |
| }; |
| |
| clk_ibro: clk_ibro { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <7372800>; |
| status = "disabled"; |
| }; |
| |
| clk_ertco: clk_ertco { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| status = "disabled"; |
| }; |
| |
| clk_erfo: clk_erfo { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_M(32)>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &sram { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| sram0: memory@0 { |
| compatible = "mmio-sram"; |
| reg = <0x0 DT_SIZE_K(32)>; |
| }; |
| |
| sram1: memory@8000 { |
| compatible = "mmio-sram"; |
| reg = <0x8000 DT_SIZE_K(32)>; |
| }; |
| |
| sram2: memory@10000 { |
| compatible = "mmio-sram"; |
| reg = <0x10000 DT_SIZE_K(64)>; |
| }; |
| |
| sram3: memory@20000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000 DT_SIZE_K(64)>; |
| }; |
| |
| sram4: memory@30000 { |
| compatible = "mmio-sram"; |
| reg = <0x30000 DT_SIZE_K(64)>; |
| }; |
| }; |
| |
| &peripheral { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gcr: clock-controller@0 { |
| reg = <0x0 0x400>; |
| compatible = "adi,max32-gcr"; |
| #clock-cells = <2>; |
| clocks = <&clk_ipo>; |
| sysclk-prescaler = <1>; |
| status = "okay"; |
| }; |
| |
| pinctrl: pin-controller@8000 { |
| compatible = "adi,max32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x8000 0x1000>; |
| |
| gpio0: gpio@8000 { |
| reg = <0x8000 0x1000>; |
| compatible = "adi,max32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>; |
| interrupts = <14 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| i3c0: i3c@18000 { |
| compatible = "adi,max32-i3c"; |
| reg = <0x18000 0x1000>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 13>; |
| interrupts = <10 0>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@42000 { |
| compatible = "adi,max32-uart"; |
| reg = <0x42000 0x1000>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| interrupts = <11 0>; |
| status = "disabled"; |
| }; |
| |
| trng: trng@4d000 { |
| compatible = "adi,max32-trng"; |
| reg = <0x4d000 0x1000>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>; |
| status = "disabled"; |
| }; |
| |
| wdt0: watchdog@3000 { |
| compatible = "adi,max32-watchdog"; |
| reg = <0x3000 0x400>; |
| interrupts = <1 0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS1 27>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| status = "disabled"; |
| }; |
| |
| timer0: timer@10000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x10000 0x1000>; |
| interrupts = <4 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 15>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer1: timer@11000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x11000 0x1000>; |
| interrupts = <5 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 16>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer2: timer@12000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x12000 0x1000>; |
| interrupts = <6 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 17>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer3: timer@13000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x13000 0x1000>; |
| interrupts = <7 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 18>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer4: timer@14000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x14000 0x1000>; |
| interrupts = <8 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 19>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer5: timer@15000 { |
| compatible = "adi,max32-timer"; |
| reg = <0x15000 0x1000>; |
| interrupts = <9 0>; |
| status = "disabled"; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 20>; |
| clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; |
| prescaler = <1>; |
| |
| pwm { |
| compatible = "adi,max32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "adi,max32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| wut0: timer@6400 { |
| compatible = "adi,max32-timer"; |
| reg = <0x6400 0x200>; |
| interrupts = <24 0>; |
| status = "disabled"; |
| prescaler = <1>; |
| |
| counter { |
| compatible = "adi,max32-wut"; |
| status = "disabled"; |
| }; |
| }; |
| |
| wut1: timer@6600 { |
| compatible = "adi,max32-timer"; |
| reg = <0x6600 0x200>; |
| interrupts = <25 0>; |
| status = "disabled"; |
| prescaler = <1>; |
| |
| counter { |
| compatible = "adi,max32-wut"; |
| status = "disabled"; |
| }; |
| }; |
| |
| rtc_counter: rtc_counter@6000 { |
| compatible = "adi,max32-rtc-counter"; |
| reg = <0x6000 0x400>; |
| interrupts = <2 0>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@46000 { |
| compatible = "adi,max32-spi"; |
| reg = <0x46000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>; |
| interrupts = <12 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |
