dts/arm/adi/max32/max78000.dtsi

/*
 * Copyright (c) 2025 Analog Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>
#include <zephyr/dt-bindings/dma/max78000_dma.h>

&clk_ipo {
	clock-frequency = <DT_FREQ_M(100)>;
};

&clk_inro {
	clock-frequency = <DT_FREQ_K(30)>;
};

/delete-node/ &clk_erfo;

&pinctrl {
	reg = <0x40008000 0x2200>;

	gpio2: gpio@40080400 {
		reg = <0x40080400 0x200>;
		compatible = "adi,max32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupts = <26 0>;
		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
		status = "disabled";
	};

	gpio3: gpio@40080600 {
		reg = <0x40080600 0x200>; // Address and size are dummy.
		compatible = "adi,max32-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupts = <54 0>;
		status = "disabled";
	};
};

/* MAX78000 extra peripherals. */
/ {
	soc {
		sram1: memory@20008000 {
			compatible = "mmio-sram";
			reg = <0x20008000 DT_SIZE_K(32)>;
		};

		sram2: memory@20010000 {
			compatible = "mmio-sram";
			reg = <0x20010000 DT_SIZE_K(48)>;
		};

		sram3: memory@2001c000 {
			compatible = "mmio-sram";
			reg = <0x2001c000 DT_SIZE_K(16)>;
		};

		uart3: serial@40081400 {
			compatible = "adi,max32-uart";
			reg = <0x40081400 0x400>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
			interrupts = <88 0>;
			status = "disabled";
		};

		spi0: spi@400be000 {
			compatible = "adi,max32-spi";
			reg = <0x400be000 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
			interrupts = <56 0>;
			status = "disabled";
		};

		spi1: spi@40046000 {
			compatible = "adi,max32-spi";
			reg = <0x40046000 0x2000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
			interrupts = <16 0>;
			status = "disabled";
		};

		dma0: dma@40028000 {
			compatible = "adi,max32-dma";
			reg = <0x40028000 0x1000>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
			dma-channels = <4>;
			status = "disabled";
			#dma-cells = <2>;
		};

		w1: w1@4003d000 {
			compatible = "adi,max32-w1";
			reg = <0x4003d000 0x1000>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
			interrupts = <67 0>;
			status = "disabled";
		};

		wdt1: watchdog@40080800 {
			compatible = "adi,max32-watchdog";
			reg = <0x40080800 0x400>;
			interrupts = <57 0>;
			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
			status = "disabled";
		};

		lptimer0: timer@40080c00 {
			compatible = "adi,max32-timer";
			reg = <0x40080c00 0x400>;
			interrupts = <9 0>;
			status = "disabled";
			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
			prescaler = <1>;

			pwm {
				compatible = "adi,max32-pwm";
				status = "disabled";
				pinctrl-0 = <&lptmr0b_ioa_p2_4>;
				pinctrl-names = "default";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "adi,max32-counter";
				status = "disabled";
			};
		};

		lptimer1: timer@40081000 {
			compatible = "adi,max32-timer";
			reg = <0x40081000 0x400>;
			interrupts = <10 0>;
			status = "disabled";
			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
			prescaler = <1>;

			pwm {
				compatible = "adi,max32-pwm";
				status = "disabled";
				pinctrl-0 = <&lptmr1b_ioa_p2_5>;
				pinctrl-names = "default";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "adi,max32-counter";
				status = "disabled";
			};
		};
	};
};