| /* |
| * Copyright 2024-2025 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <freq.h> |
| #include "armv6-m.dtsi" |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/clock/kinetis_pcc.h> |
| #include <zephyr/dt-bindings/clock/kinetis_scg.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &ftfe; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-m0+"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| reg = <0>; |
| cpu-power-states = <&idle &stop &pstop1 &pstop2>; |
| }; |
| |
| power-states { |
| idle: idle { |
| compatible = "zephyr,power-state"; |
| power-state-name = "runtime-idle"; |
| }; |
| |
| stop: stop { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <0>; |
| }; |
| |
| pstop1: pstop1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| }; |
| |
| pstop2: pstop2 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <2>; |
| }; |
| }; |
| }; |
| |
| sram_l: memory@1fffe000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x1FFFE000 DT_SIZE_K(8)>; |
| zephyr,memory-region = "SRAML"; |
| }; |
| |
| sram_u: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(24)>; |
| zephyr,memory-region = "SRAMU"; |
| }; |
| |
| pinctrl: pinctrl { |
| compatible = "nxp,port-pinctrl"; |
| }; |
| |
| soc { |
| scg: scg@40064000 { |
| sosc-mode = <KINETIS_SCG_SOSC_MODE_LOW_POWER>; |
| compatible = "nxp,kinetis-scg"; |
| reg = <0x40064000 0x1000>; |
| #clock-cells = <1>; |
| |
| sirc_clk: sirc_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(8)>; |
| #clock-cells = <0>; |
| }; |
| |
| firc_clk: firc_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| #clock-cells = <0>; |
| }; |
| |
| core_clk: core_clk { |
| compatible = "fixed-factor-clock"; |
| clocks = <&firc_clk>; |
| clock-div = <1>; |
| #clock-cells = <0>; |
| }; |
| |
| bus_clk: bus_clk { |
| compatible = "fixed-factor-clock"; |
| clocks = <&core_clk>; |
| clock-div = <4>; |
| #clock-cells = <0>; |
| }; |
| |
| sircdiv2_clk: sircdiv2_clk { |
| compatible = "fixed-factor-clock"; |
| clocks = <&sirc_clk>; |
| clock-div = <2>; |
| #clock-cells = <0>; |
| }; |
| |
| fircdiv2_clk: fircdiv2_clk { |
| compatible = "fixed-factor-clock"; |
| clocks = <&firc_clk>; |
| clock-div = <1>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| pcc: pcc@40065000 { |
| compatible = "nxp,kinetis-pcc"; |
| reg = <0x40065000 0x1000>; |
| #clock-cells = <2>; |
| }; |
| |
| ftfe: flash-controller@40020000 { |
| compatible = "nxp,kinetis-ftfe"; |
| reg = <0x40020000 0x1000>; |
| interrupts = <5 0>; |
| interrupt-names = "command-complete"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@0 { |
| compatible = "soc-nv-flash"; |
| reg = <0 DT_SIZE_K(256)>; |
| erase-block-size = <DT_SIZE_K(2)>; |
| write-block-size = <8>; |
| }; |
| }; |
| |
| adc0: adc@4003b000 { |
| compatible = "nxp,adc12"; |
| reg = <0x4003b000 0x1000>; |
| interrupts = <15 0>; |
| clocks = <&pcc 0xec KINETIS_PCC_SRC_SIRC_ASYNC>; |
| clk-source = <0>; |
| clk-divider = <1>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| ewm0: ewm@40061000 { |
| compatible = "nxp,ewm"; |
| reg = <0x40061000 0x6>; |
| status = "disabled"; |
| interrupts = <28 0>; |
| clk-divider = <0x0>; |
| }; |
| |
| lpuart0: uart@4006a000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4006a000 0x1000>; |
| interrupts = <12 0>; |
| clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: uart@4006b000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4006b000 0x1000>; |
| interrupts = <13 0>; |
| clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| }; |
| |
| lpuart2: uart@4006c000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4006c000 0x1000>; |
| interrupts = <14 0>; |
| clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| }; |
| |
| lptmr0: lptmr@40040000 { |
| compatible = "nxp,lptmr"; |
| reg = <0x40040000 0x1000>; |
| interrupts = <29 0>; |
| clock-frequency = <DT_FREQ_K(128)>; |
| prescaler = <1>; |
| clk-source = <1>; |
| resolution = <16>; |
| }; |
| |
| porta: pinmux@40049000 { |
| compatible = "nxp,port-pinmux"; |
| reg = <0x40049000 0x1000>; |
| clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>; |
| }; |
| |
| portb: pinmux@4004a000 { |
| compatible = "nxp,port-pinmux"; |
| reg = <0x4004a000 0x1000>; |
| clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>; |
| }; |
| |
| portc: pinmux@4004b000 { |
| compatible = "nxp,port-pinmux"; |
| reg = <0x4004b000 0x1000>; |
| clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>; |
| }; |
| |
| portd: pinmux@4004c000 { |
| compatible = "nxp,port-pinmux"; |
| reg = <0x4004c000 0x1000>; |
| clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>; |
| }; |
| |
| porte: pinmux@4004d000 { |
| compatible = "nxp,port-pinmux"; |
| reg = <0x4004d000 0x1000>; |
| clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>; |
| }; |
| |
| pmc: pmc@4007d000 { |
| reg = <0x4007d000 0x1000>; |
| |
| lpo: lpo128k { |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(128)>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| wdog: watchdog@40052000 { |
| compatible = "nxp,wdog32"; |
| reg = <0x40052000 0x1000>; |
| interrupts = <28 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <256>; |
| status = "disabled"; |
| }; |
| |
| gpios0: gpios0@400ff000 { |
| compatible = "nxp,gpio-cluster"; |
| interrupts = <7 2>; |
| reg = <0x400ff000 0x200>; |
| ranges = <0x0 0x400ff000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gpioa: gpio@400ff000 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0x0 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&porta>; |
| }; |
| |
| gpioe: gpio@400ff100 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0x100 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&porte>; |
| }; |
| |
| fgpioa: gpio@f8000000 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xf8000000 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&porta>; |
| }; |
| |
| fgpioe: gpio@f8000100 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xf8000100 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&porte>; |
| }; |
| }; |
| |
| gpios1: gpios1@400ff040 { |
| compatible = "nxp,gpio-cluster"; |
| interrupts = <26 2>; |
| reg = <0x400ff040 0x200>; |
| ranges = <0x40 0x400ff040 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gpiob: gpio@400ff040 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0x40 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portb>; |
| }; |
| |
| gpioc: gpio@400ff080 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0x80 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portc>; |
| }; |
| |
| gpiod: gpio@400ff0c0 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xc0 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portd>; |
| }; |
| |
| fgpiob: gpio@f8000040 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xf8000040 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portb>; |
| }; |
| |
| fgpioc: gpio@f8000080 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xf8000080 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portc>; |
| }; |
| |
| fgpiod: gpio@f80000c0 { |
| compatible = "nxp,kinetis-gpio"; |
| status = "disabled"; |
| reg = <0xf80000c0 0x40>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| nxp,kinetis-port = <&portd>; |
| }; |
| }; |
| |
| lpit0: lpit@40037000 { |
| compatible = "nxp,lpit"; |
| reg = <0x40037000 0x1000>; |
| interrupts = <22 0>; |
| clocks = <&pcc 0xdc KINETIS_PCC_SRC_SIRC_ASYNC>; |
| status = "disabled"; |
| enable-run-in-doze; |
| max-load-value = <0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lpit0_channel0: lpit_channel@0 { |
| compatible = "nxp,lpit-channel"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| lpit0_channel1: lpit_channel@1 { |
| compatible = "nxp,lpit-channel"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| lpit0_channel2: lpit_channel@2 { |
| compatible = "nxp,lpit-channel"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| lpit0_channel3: lpit_channel@3 { |
| compatible = "nxp,lpit-channel"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| ftm0: ftm@40038000 { |
| compatible = "nxp,ftm"; |
| reg = <0x40038000 0x1000>; |
| interrupts = <17 0>; |
| clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| prescaler = <16>; |
| status = "disabled"; |
| }; |
| |
| ftm1: ftm@40039000 { |
| compatible = "nxp,ftm"; |
| reg = <0x40039000 0x1000>; |
| interrupts = <18 0>; |
| clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| prescaler = <16>; |
| status = "disabled"; |
| }; |
| |
| ftm2: ftm@4003a000 { |
| compatible = "nxp,ftm"; |
| reg = <0x4003a000 0x1000>; |
| interrupts = <19 0>; |
| clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| prescaler = <16>; |
| status = "disabled"; |
| }; |
| |
| pwt: pwt@40056000 { |
| compatible = "nxp,kinetis-pwt"; |
| reg = <0x40056000 0x1000>; |
| interrupts = <29 0>; |
| clocks = <&scg KINETIS_SCG_BUS_CLK>; |
| prescaler = <1>; |
| status = "disabled"; |
| |
| #pwm-cells = <3>; |
| }; |
| |
| lpi2c0: i2c@40066000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40066000 0x1000>; |
| interrupts = <8 0>; |
| clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| }; |
| |
| lpi2c1: i2c@40067000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40067000 0x1000>; |
| interrupts = <9 0>; |
| clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@4003d000 { |
| compatible = "nxp,rtc"; |
| reg = <0x4003d000 0x1000>; |
| interrupts = <20 0>; |
| clock-frequency = <32768>; |
| prescaler = <32768>; |
| status = "disabled"; |
| }; |
| |
| cmp0: cmp@40073000 { |
| compatible = "nxp,kinetis-acmp"; |
| reg = <0x40073000 0x1000>; |
| interrupts = <16 0>; |
| clocks = <&scg KINETIS_SCG_BUS_CLK>; |
| status = "disabled"; |
| }; |
| |
| lpspi0: spi@4002c000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x4002c000 0x1000>; |
| interrupts = <10 0>; |
| clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| tx-fifo-size = <4>; |
| rx-fifo-size = <4>; |
| }; |
| |
| lpspi1: spi@4002d000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x4002d000 0x1000>; |
| interrupts = <11 0>; |
| clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| tx-fifo-size = <4>; |
| rx-fifo-size = <4>; |
| }; |
| |
| edma: dma-controller@40008000 { |
| compatible = "nxp,mcux-edma"; |
| nxp,version = <2>; |
| dma-channels = <8>; |
| dma-requests = <64>; |
| nxp,mem2mem; |
| reg = <0x40008000 0x1000>, <0x40021000 0x1000>; |
| interrupts = <0 0>, <1 0>, <2 0>, <3 0>, |
| <4 0>; |
| status = "disabled"; |
| #dma-cells = <2>; |
| irq-shared-offset = <4>; |
| }; |
| |
| flexio: flexio@4005a000 { |
| compatible = "nxp,flexio"; |
| reg = <0x4005a000 0x1000>; |
| status = "disabled"; |
| interrupts = <23 0>; |
| clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <2>; |
| }; |
