| /* |
| * Copyright 2024-2025 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <dt-bindings/clock/imx_ccm_rev2.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/ethernet/dsa_tag_proto.h> |
| |
| / { |
| aliases { |
| watchdog0 = &rtwdog0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33f"; |
| reg = <0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| d-cache-line-size = <32>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m7"; |
| reg = <1>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| d-cache-line-size = <32>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv7m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| }; |
| |
| /* USB PLL */ |
| usbclk: usbpll-clock { |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(24)>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| &peripheral { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| anatop: anatop@4480000 { |
| compatible = "nxp,imx-anatop"; |
| reg = <0x4480000 0x4000>; |
| #clock-cells = <4>; |
| #pll-clock-cells = <3>; |
| }; |
| |
| /* |
| * Note that the offsets here are relative to the base address |
| * defined in either nxp_rt118x_cm33_ns.dtsi, nxp_rt118x_cm33.dtsi |
| * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ |
| * between non-secure (0x40000000) and secure modes (0x50000000). |
| */ |
| iomuxc: pinctrl@2A10000 { |
| compatible = "nxp,imx-iomuxc"; |
| reg = <0x2A10000 0x4000>; |
| |
| pinctrl: pinctrl { |
| status = "okay"; |
| compatible = "nxp,mcux-rt11xx-pinctrl"; |
| }; |
| }; |
| |
| iomuxc_aon: pinctrl@43C0000 { |
| compatible = "nxp,mcux-rt-pinctrl"; |
| reg = <0x43C0000 0x4000>; |
| status = "okay"; |
| }; |
| |
| blkctrl_ns_aon: blkctrl_ns_aon@4210000 { |
| compatible = "nxp,imx-blkctrl-ns-aon"; |
| reg = <0x4210000 0x4000>; |
| status = "okay"; |
| #pinmux-cells = <2>; |
| }; |
| |
| blkctrl_wakeup: blkctrl_wakeup@2420000 { |
| compatible = "nxp,imx-blkctrl-wakeup"; |
| reg = <0x2420000 0x4000>; |
| status = "okay"; |
| #pinmux-cells = <2>; |
| }; |
| |
| ccm: clock-controller@4450000 { |
| compatible = "nxp,imx-ccm-rev2"; |
| reg = <0x4450000 0x4000>; |
| #clock-cells = <3>; |
| |
| lpo: lpo32k { |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| lpuart1: serial@4380000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4380000 0x4000>; |
| interrupts = <19 0>; |
| clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>; |
| dmas = <&edma3 0 16>, <&edma3 1 17>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart2: serial@4390000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4390000 0x4000>; |
| interrupts = <20 0>; |
| clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x68 28>; |
| dmas = <&edma3 2 18>, <&edma3 3 19>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart3: serial@2570000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2570000 0x4000>; |
| interrupts = <68 0>; |
| clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x68 12>; |
| dmas = <&edma4 0 17>, <&edma4 1 18>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart4: serial@2580000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2580000 0x4000>; |
| interrupts = <69 0>; |
| clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x6c 24>; |
| dmas = <&edma4 2 19>, <&edma4 3 20>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart5: uart@2590000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2590000 0x4000>; |
| interrupts = <70 0>; |
| clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 2>; |
| dmas = <&edma4 4 21>, <&edma4 5 22>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart6: serial@25A0000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x25A0000 0x4000>; |
| interrupts = <71 0>; |
| clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 6>; |
| dmas = <&edma4 6 23>, <&edma4 7 24>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart7: serial@4570000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4570000 0x4000>; |
| interrupts = <196 0>; |
| clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x7c 26>; |
| dmas = <&edma3 4 29>, <&edma3 5 30>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart8: serial@2DA0000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2DA0000 0x4000>; |
| interrupts = <197 0>; |
| clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x80 14>; |
| dmas = <&edma4 8 178>, <&edma4 9 179>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart9: serial@2D70000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2D70000 0x4000>; |
| interrupts = <156 0>; |
| clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>; |
| dmas = <&edma4 10 172>, <&edma4 11 173>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart10: serial@2D80000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2D80000 0x4000>; |
| interrupts = <157 0>; |
| clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>; |
| dmas = <&edma4 12 174>, <&edma4 13 175>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart11: serial@2D90000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x2D90000 0x4000>; |
| interrupts = <158 0>; |
| clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>; |
| dmas = <&edma4 14 176>, <&edma4 15 177>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| lpuart12: serial@4580000 { |
| compatible = "nxp,lpuart"; |
| reg = <0x4580000 0x4000>; |
| interrupts = <159 0>; |
| clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>; |
| dmas = <&edma3 6 31>, <&edma3 7 32>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| gpio1: gpio@7400000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x7400000 0x4000>; |
| interrupts = <10 0>, <11 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio2: gpio@3810000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x3810000 0x4000>; |
| interrupts = <57 0>, <58 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio3: gpio@3820000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x3820000 0x4000>; |
| interrupts = <59 0>, <60 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio4: gpio@3830000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x3830000 0x4000>; |
| interrupts = <232 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio5: gpio@3840000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x3840000 0x4000>; |
| interrupts = <234 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio6: gpio@3850000 { |
| compatible = "nxp,imx-rgpio"; |
| reg = <0x3850000 0x4000>; |
| interrupts = <236 0>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| lpi2c1: i2c@4340000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x4340000 0x4000>; |
| interrupts = <13 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 6>; |
| status = "disabled"; |
| }; |
| |
| lpi2c2: i2c@4350000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x4350000 0x4000>; |
| interrupts = <14 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0102_CLK 0x70 8>; |
| status = "disabled"; |
| }; |
| |
| lpi2c3: i2c@2530000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2530000 0x4000>; |
| interrupts = <62 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x70 10>; |
| status = "disabled"; |
| }; |
| |
| lpi2c4: i2c@2540000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2540000 0x4000>; |
| interrupts = <63 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0304_CLK 0x80 24>; |
| status = "disabled"; |
| }; |
| |
| lpi2c5: i2c@2d30000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2d30000 0x4000>; |
| interrupts = <152 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>; |
| status = "disabled"; |
| }; |
| |
| lpi2c6: i2c@2d40000 { |
| compatible = "nxp,lpi2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2d40000 0x4000>; |
| interrupts = <153 0>; |
| clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>; |
| status = "disabled"; |
| }; |
| |
| gpt1: timer@46c0000 { |
| compatible = "nxp,imx-gpt"; |
| reg = <0x46c0000 0x4000>; |
| interrupts = <209 0>; |
| gptfreq = <DT_FREQ_M(240)>; |
| clocks = <&ccm IMX_CCM_GPT1_CLK 0x41 0>; |
| status = "disabled"; |
| }; |
| |
| gpt2: timer@2ec0000 { |
| compatible = "nxp,imx-gpt"; |
| reg = <0x2ec0000 0x4000>; |
| interrupts = <210 0>; |
| gptfreq = <DT_FREQ_M(240)>; |
| clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>; |
| }; |
| |
| acmp1: comparator@2dc0000 { |
| compatible = "nxp,kinetis-acmp"; |
| reg = <0x2dc0000 0x4000>; |
| interrupts = <200 0>; |
| status = "disabled"; |
| }; |
| |
| acmp2: comparator@2dd0000 { |
| compatible = "nxp,kinetis-acmp"; |
| reg = <0x2dd0000 0x4000>; |
| interrupts = <201 0>; |
| status = "disabled"; |
| }; |
| |
| acmp3: comparator@2de0000 { |
| compatible = "nxp,kinetis-acmp"; |
| reg = <0x2de0000 0x4000>; |
| interrupts = <202 0>; |
| status = "disabled"; |
| }; |
| |
| acmp4: comparator@2df0000 { |
| compatible = "nxp,kinetis-acmp"; |
| reg = <0x2df0000 0x4000>; |
| interrupts = <203 0>; |
| status = "disabled"; |
| }; |
| |
| lpadc1: adc@2600000 { |
| compatible = "nxp,lpc-lpadc"; |
| reg = <0x2600000 0x304>; |
| interrupts = <93 0>; |
| status = "disabled"; |
| voltage-ref = <1>; |
| calibration-average = <128>; |
| no-power-level; |
| offset-value-a = <10>; |
| offset-value-b = <10>; |
| #io-channel-cells = <1>; |
| clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>; |
| }; |
| |
| lpadc2: adc@2e00000 { |
| compatible = "nxp,lpc-lpadc"; |
| reg = <0x2e00000 0x304>; |
| interrupts = <189 0>; |
| status = "disabled"; |
| clk-divider = <8>; |
| clk-source = <0>; |
| voltage-ref = <1>; |
| calibration-average = <128>; |
| no-power-level; |
| offset-value-a = <10>; |
| offset-value-b = <10>; |
| #io-channel-cells = <1>; |
| clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>; |
| }; |
| |
| dac: dac@42e20000 { |
| compatible = "nxp,dac12"; |
| reg = <0x42e20000 0x1000>; |
| interrupts = <193 0>; |
| voltage-reference = <2>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| qtmr1: timer@2690000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x2690000 0x4000>; |
| interrupts = <0 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr1_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr1_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr1_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr1_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr2: timer@26a0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26a0000 0x4000>; |
| interrupts = <233 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr2_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr2_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr2_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr2_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr3: timer@26b0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26b0000 0x4000>; |
| interrupts = <164 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr3_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr3_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr3_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr3_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr4: timer@26c0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26c0000 0x4000>; |
| interrupts = <151 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr4_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr4_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr4_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr4_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr5: timer@26d0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26d0000 0x4000>; |
| interrupts = <4 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr5_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr5_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr5_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr5_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr6: timer@26e0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26e0000 0x4000>; |
| interrupts = <5 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr6_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr6_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr6_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr6_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr7: timer@26f0000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x26f0000 0x4000>; |
| interrupts = <6 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr7_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr7_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr7_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr7_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qtmr8: timer@2700000 { |
| compatible = "nxp,imx-qtmr"; |
| reg = <0x2700000 0x4000>; |
| interrupts = <7 0>; |
| clocks = <&ccm IMX_CCM_QTMR_CLK 0x0 0>; |
| |
| qtmr8_timer0: timer0 { |
| compatible = "nxp,imx-tmr"; |
| channel = <0>; |
| status = "disabled"; |
| }; |
| |
| qtmr8_timer1: timer1 { |
| compatible = "nxp,imx-tmr"; |
| channel = <1>; |
| status = "disabled"; |
| }; |
| |
| qtmr8_timer2: timer2 { |
| compatible = "nxp,imx-tmr"; |
| channel = <2>; |
| status = "disabled"; |
| }; |
| |
| qtmr8_timer3: timer3 { |
| compatible = "nxp,imx-tmr"; |
| channel = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| netc: ethernet { |
| compatible = "nxp,imx-netc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| enetc_psi0: ethernet@60b00000 { |
| compatible = "nxp,imx-netc-psi"; |
| reg = <0x60b00000 0x10000>, |
| <0x60003000 0x1000>; |
| reg-names = "port", "pfconfig"; |
| mac-index = <0>; |
| si-index = <0>; |
| status = "disabled"; |
| }; |
| |
| enetc_psi1: ethernet@60b40000 { |
| compatible = "nxp,imx-netc-psi"; |
| reg = <0x60b40000 0x10000>, |
| <0x60004000 0x1000>; |
| reg-names = "port", "pfconfig"; |
| mac-index = <1>; |
| si-index = <1>; |
| phy-connection-type = "internal"; |
| status = "disabled"; |
| }; |
| |
| emdio: mdio@60ba0000 { |
| compatible = "nxp,imx-netc-emdio"; |
| reg = <0x60ba0000 0x1c44>, |
| <0x60001000 0x1000>; |
| reg-names = "basic", "pfconfig"; |
| clocks = <&ccm IMX_CCM_NETC_CLK 0x0 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| switch: dsa@60a00000 { |
| compatible = "nxp,netc-switch"; |
| reg = <0x60a00000 0x10000>, |
| <0x60002000 0x1000>; |
| reg-names = "base", "pfconfig"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| switch_port0: switch_port@0 { |
| compatible = "zephyr,dsa-port"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| switch_port1: switch_port@1 { |
| compatible = "zephyr,dsa-port"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| switch_port2: switch_port@2 { |
| compatible = "zephyr,dsa-port"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| switch_port3: switch_port@3 { |
| compatible = "zephyr,dsa-port"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| |
| /* Internal port */ |
| switch_port4: switch_port@4 { |
| compatible = "zephyr,dsa-port"; |
| reg = <4>; |
| ethernet = <&enetc_psi1>; |
| phy-connection-type = "internal"; |
| dsa-tag-protocol = <DSA_TAG_PROTO_NOTAG>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| flexcan1: can@43a0000 { |
| compatible = "nxp,flexcan-fd", "nxp,flexcan"; |
| reg = <0x43a0000 0x1000>; |
| interrupts = <8 0>, <9 0>; |
| interrupt-names = "common", "error"; |
| clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; |
| clk-source = <0>; |
| status = "disabled"; |
| }; |
| |
| flexcan2: can@25b0000 { |
| compatible = "nxp,flexcan-fd", "nxp,flexcan"; |
| reg = <0x25b0000 0x1000>; |
| interrupts = <51 0>, <52 0>; |
| interrupt-names = "common", "error"; |
| clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>; |
| clk-source = <0>; |
| status = "disabled"; |
| }; |
| |
| flexcan3: can@45b0000 { |
| compatible = "nxp,flexcan-fd", "nxp,flexcan"; |
| reg = <0x45b0000 0x1000>; |
| interrupts = <191 0>, <192 0>; |
| interrupt-names = "common", "error"; |
| clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>; |
| clk-source = <0>; |
| status = "disabled"; |
| }; |
| |
| lpit1: lpit@442f0000 { |
| compatible = "nxp,lpit"; |
| reg = <0x442f0000 0x1000>; |
| interrupts = <15 0>; |
| clocks = <&ccm IMX_CCM_LPIT1_CLK 0x0 0>; |
| status = "disabled"; |
| max-load-value = <0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lpit1_channel0: lpit_channel@0 { |
| compatible = "nxp,lpit-channel"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| lpit1_channel1: lpit_channel@1 { |
| compatible = "nxp,lpit-channel"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| lpit1_channel2: lpit_channel@2 { |
| compatible = "nxp,lpit-channel"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| lpit1_channel3: lpit_channel@3 { |
| compatible = "nxp,lpit-channel"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| lpit2: lpit@424c0000 { |
| compatible = "nxp,lpit"; |
| reg = <0x424c0000 0x1000>; |
| interrupts = <64 0>; |
| clocks = <&ccm IMX_CCM_LPIT2_CLK 0x0 0>; |
| status = "disabled"; |
| max-load-value = <0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lpit2_channel0: lpit_channel@0 { |
| compatible = "nxp,lpit-channel"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| lpit2_channel1: lpit_channel@1 { |
| compatible = "nxp,lpit-channel"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| lpit2_channel2: lpit_channel@2 { |
| compatible = "nxp,lpit-channel"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| lpit2_channel3: lpit_channel@3 { |
| compatible = "nxp,lpit-channel"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| lpit3: lpit@42cc0000 { |
| compatible = "nxp,lpit"; |
| reg = <0x42cc0000 0x1000>; |
| interrupts = <149 0>; |
| clocks = <&ccm IMX_CCM_LPIT3_CLK 0x0 0>; |
| status = "disabled"; |
| max-load-value = <0xffffffff>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| lpit3_channel0: lpit_channel@0 { |
| compatible = "nxp,lpit-channel"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| lpit3_channel1: lpit_channel@1 { |
| compatible = "nxp,lpit-channel"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| lpit3_channel2: lpit_channel@2 { |
| compatible = "nxp,lpit-channel"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| lpit3_channel3: lpit_channel@3 { |
| compatible = "nxp,lpit-channel"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| lptmr1: timer@4300000 { |
| compatible = "nxp,lptmr"; |
| reg = <0x4300000 0x1000>; |
| interrupts = <18 0>; |
| clock-frequency = <DT_FREQ_M(80)>; |
| prescaler = <1>; |
| clk-source = <0>; |
| resolution = <32>; |
| status = "disabled"; |
| }; |
| |
| lptmr2: timer@24d0000 { |
| compatible = "nxp,lptmr"; |
| reg = <0x24d0000 0x1000>; |
| interrupts = <67 0>; |
| clock-frequency = <DT_FREQ_M(80)>; |
| prescaler = <1>; |
| clk-source = <0>; |
| resolution = <32>; |
| status = "disabled"; |
| }; |
| |
| lptmr3: timer@2cd0000 { |
| compatible = "nxp,lptmr"; |
| reg = <0x2cd0000 0x1000>; |
| interrupts = <150 0>; |
| clock-frequency = <DT_FREQ_M(80)>; |
| prescaler = <1>; |
| clk-source = <0>; |
| resolution = <32>; |
| status = "disabled"; |
| }; |
| |
| flexio1: flexio@25c0000 { |
| compatible = "nxp,flexio"; |
| reg = <0x25c0000 0x4000>; |
| interrupts = <53 0>; |
| clocks = <&ccm IMX_CCM_FLEXIO1_CLK 0 0>; |
| status = "disabled"; |
| }; |
| |
| flexio2: flexio@25d0000 { |
| compatible = "nxp,flexio"; |
| reg = <0x25d0000 0x4000>; |
| interrupts = <54 0>; |
| clocks = <&ccm IMX_CCM_FLEXIO2_CLK 0 0>; |
| status = "disabled"; |
| }; |
| |
| flexpwm1: pwm@2650000 { |
| compatible = "nxp,flexpwm"; |
| reg = <0x2650000 0x4000>; |
| interrupts = <23 0>; |
| |
| flexpwm1_pwm0: flexpwm1_pwm0 { |
| compatible = "nxp,imx-pwm"; |
| index = <0>; |
| interrupts = <24 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm1_pwm1: flexpwm1_pwm1 { |
| compatible = "nxp,imx-pwm"; |
| index = <1>; |
| interrupts = <25 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm1_pwm2: flexpwm1_pwm2 { |
| compatible = "nxp,imx-pwm"; |
| index = <2>; |
| interrupts = <26 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm1_pwm3: flexpwm1_pwm3 { |
| compatible = "nxp,imx-pwm"; |
| index = <3>; |
| interrupts = <27 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flexpwm2: pwm@2660000 { |
| compatible = "nxp,flexpwm"; |
| reg = <0x2660000 0x4000>; |
| interrupts = <170 0>; |
| |
| flexpwm2_pwm0: flexpwm2_pwm0 { |
| compatible = "nxp,imx-pwm"; |
| index = <0>; |
| interrupts = <171 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm2_pwm1: flexpwm2_pwm1 { |
| compatible = "nxp,imx-pwm"; |
| index = <1>; |
| interrupts = <172 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm2_pwm2: flexpwm2_pwm2 { |
| compatible = "nxp,imx-pwm"; |
| index = <2>; |
| interrupts = <173 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm2_pwm3: flexpwm2_pwm3 { |
| compatible = "nxp,imx-pwm"; |
| index = <3>; |
| interrupts = <174 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flexpwm3: pwm@2670000 { |
| compatible = "nxp,flexpwm"; |
| reg = <0x2670000 0x4000>; |
| interrupts = <175 0>; |
| |
| flexpwm3_pwm0: flexpwm3_pwm0 { |
| compatible = "nxp,imx-pwm"; |
| index = <0>; |
| interrupts = <176 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm3_pwm1: flexpwm3_pwm1 { |
| compatible = "nxp,imx-pwm"; |
| index = <1>; |
| interrupts = <177 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm3_pwm2: flexpwm3_pwm2 { |
| compatible = "nxp,imx-pwm"; |
| index = <2>; |
| interrupts = <178 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm3_pwm3: flexpwm3_pwm3 { |
| compatible = "nxp,imx-pwm"; |
| index = <3>; |
| interrupts = <179 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flexpwm4: pwm@2680000 { |
| compatible = "nxp,flexpwm"; |
| reg = <0x2680000 0x4000>; |
| interrupts = <180 0>; |
| |
| flexpwm4_pwm0: flexpwm4_pwm0 { |
| compatible = "nxp,imx-pwm"; |
| index = <0>; |
| interrupts = <181 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm4_pwm1: flexpwm4_pwm1 { |
| compatible = "nxp,imx-pwm"; |
| index = <1>; |
| interrupts = <182 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm4_pwm2: flexpwm4_pwm2 { |
| compatible = "nxp,imx-pwm"; |
| index = <2>; |
| interrupts = <183 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| |
| flexpwm4_pwm3: flexpwm4_pwm3 { |
| compatible = "nxp,imx-pwm"; |
| index = <3>; |
| interrupts = <184 0>; |
| #pwm-cells = <3>; |
| clocks = <&ccm IMX_CCM_PWM_CLK 0 0>; |
| nxp,prescaler = <128>; |
| status = "disabled"; |
| }; |
| }; |
| |
| src: reset-controller@44460000 { |
| compatible = "nxp,imx-src-rev2"; |
| reg = <0x44460000 0xa4>; |
| status = "okay"; |
| }; |
| |
| tpm1: pwm@4310000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x4310000 0x88>; |
| interrupts = <36 0>; |
| clocks = <&ccm IMX_CCM_TPM1_CLK 0x3b 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| tpm2: pwm@4320000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x4320000 0x88>; |
| interrupts = <37 0>; |
| clocks = <&ccm IMX_CCM_TPM2_CLK 0x3c 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| tpm3: pwm@24E0000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x24E0000 0x88>; |
| interrupts = <75 0>; |
| clocks = <&ccm IMX_CCM_TPM3_CLK 0x3d 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| tpm4: pwm@24F0000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x24F0000 0x88>; |
| interrupts = <76 0>; |
| clocks = <&ccm IMX_CCM_TPM4_CLK 0x3e 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| tpm5: pwm@2500000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x2500000 0x88>; |
| interrupts = <77 0>; |
| clocks = <&ccm IMX_CCM_TPM5_CLK 0x3f 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| tpm6: pwm@42510000 { |
| compatible = "nxp,kinetis-tpm"; |
| reg = <0x42510000 0x88>; |
| interrupts = <78 0>; |
| clocks = <&ccm IMX_CCM_TPM6_CLK 0x40 0>; |
| prescaler = <16>; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| i3c1: i3c@4330000 { |
| compatible = "nxp,mcux-i3c"; |
| reg = <0x4330000 0x1000>; |
| interrupts = <12 0>; |
| clocks = <&ccm IMX_CCM_I3C1_CLK 0x67 0>; |
| clk-divider = <2>; |
| clk-divider-slow = <1>; |
| clk-divider-tc = <1>; |
| status = "disabled"; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| }; |
| |
| i3c2: i3c@2520000 { |
| compatible = "nxp,mcux-i3c"; |
| reg = <0x2520000 0x1000>; |
| interrupts = <61 0>; |
| clocks = <&ccm IMX_CCM_I3C2_CLK 0x68 0>; |
| clk-divider = <2>; |
| clk-divider-slow = <1>; |
| clk-divider-tc = <1>; |
| status = "disabled"; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| }; |
| |
| usdhc1: memory-controller@2850000 { |
| compatible = "nxp,imx-usdhc"; |
| reg = <0x2850000 0x4000>; |
| status = "disabled"; |
| interrupts = <86 0>; |
| clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>; |
| max-current-330 = <1020>; |
| max-current-180 = <1020>; |
| max-bus-freq = <DT_FREQ_M(208)>; |
| min-bus-freq = <DT_FREQ_K(400)>; |
| }; |
| |
| usdhc2: memory-controller@2860000 { |
| compatible = "nxp,imx-usdhc"; |
| reg = <0x2860000 0x4000>; |
| status = "disabled"; |
| interrupts = <87 0>; |
| clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>; |
| max-current-330 = <1020>; |
| max-current-180 = <1020>; |
| max-bus-freq = <DT_FREQ_M(208)>; |
| min-bus-freq = <DT_FREQ_K(400)>; |
| }; |
| |
| edma3: dma-controller@4000000 { |
| #dma-cells = <2>; |
| compatible = "nxp,mcux-edma"; |
| nxp,version = <4>; |
| reg = <0x4000000 0x210000>; |
| dma-channels = <32>; |
| dma-requests = <39>; |
| no-error-irq; |
| interrupts = <95 0>, <96 0>, <97 0>, |
| <98 0>, <99 0>, <100 0>, <101 0>, |
| <102 0>, <103 0>, <104 0>, <105 0>, |
| <106 0>, <107 0>, <108 0>, <109 0>, |
| <110 0>, <111 0>, <112 0>, <113 0>, |
| <114 0>, <115 0>, <116 0>, <117 0>, |
| <118 0>, <119 0>, <120 0>, <121 0>, |
| <122 0>, <123 0>, <124 0>, <125 0>, |
| <126 0>, <94 0>; |
| status = "disabled"; |
| }; |
| |
| edma4: dma-controller@2000000 { |
| #dma-cells = <2>; |
| compatible = "nxp,mcux-edma"; |
| nxp,version = <4>; |
| dma-channels = <64>; |
| dma-requests = <222>; |
| reg = <0x2000000 0x4000>; |
| no-error-irq; |
| interrupts = <128 0>, <129 0>, <130 0>, |
| <131 0>, <132 0>, <133 0>, <134 0>, |
| <135 0>, <136 0>, <137 0>, <138 0>, |
| <139 0>, <140 0>, <141 0>, <142 0>, |
| <143 0>, <127 0>; |
| channels-shared-irq-mask = <0x00000003 0x00000003 |
| 0x0000000C 0x0000000C 0x00000030 0x00000030 |
| 0x000000C0 0x000000C0 0x00000300 0x00000300 |
| 0x00000C00 0x00000C00 0x00003000 0x00003000 |
| 0x0000C000 0x0000C000 0x00030000 0x00030000 |
| 0x000C0000 0x000C0000 0x00300000 0x00300000 |
| 0x00C00000 0x00C00000 0x03000000 0x03000000 |
| 0x0C000000 0x0C000000 0x30000000 0x30000000 |
| 0xC0000000 0xC0000000>; |
| status = "disabled"; |
| }; |
| |
| ewm0: ewm@27b0000 { |
| compatible = "nxp,ewm"; |
| reg = <0x27b0000 0x6>; |
| status = "disabled"; |
| interrupts = <147 0>; |
| clk-sel = "lpo_clk[2]"; |
| clk-divider = <0x2>; |
| }; |
| |
| lpspi1: spi@4360000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x4360000 0x4000>; |
| interrupts = <16 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 0>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| kpp: kpp@2a00000 { |
| compatible = "nxp,mcux-kpp"; |
| reg = <0x2A00000 0x1000>; |
| interrupts = <211 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_KPP_CLK 0x0 0>; |
| }; |
| |
| lpspi2: spi@4370000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x4370000 0x4000>; |
| interrupts = <17 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 2>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| lpspi3: spi@2550000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x2550000 0x4000>; |
| interrupts = <65 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 4>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| lpspi4: spi@2560000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x2560000 0x4000>; |
| interrupts = <66 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 6>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| lpspi5: spi@2d50000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x2d50000 0x4000>; |
| interrupts = <194 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| lpspi6: spi@2d60000 { |
| compatible = "nxp,lpspi"; |
| reg = <0x2d60000 0x4000>; |
| interrupts = <195 3>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>; |
| tx-fifo-size = <16>; |
| rx-fifo-size = <16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| rtwdog0: wdog@42d0000 { |
| compatible = "nxp,rtwdog"; |
| reg = <0x42d0000 0x10>; |
| status = "okay"; |
| interrupts = <38 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <1>; |
| }; |
| |
| rtwdog1: watchdog@42e0000 { |
| compatible = "nxp,rtwdog"; |
| reg = <0x42e0000 0x10>; |
| status = "disabled"; |
| interrupts = <39 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <1>; |
| }; |
| |
| rtwdog2: watchdog@2490000 { |
| compatible = "nxp,rtwdog"; |
| reg = <0x2490000 0x10>; |
| status = "disabled"; |
| interrupts = <79 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <1>; |
| }; |
| |
| rtwdog3: wdog@24a0000 { |
| compatible = "nxp,rtwdog"; |
| reg = <0x24a0000 0x10>; |
| status = "disabled"; |
| interrupts = <80 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <1>; |
| }; |
| |
| rtwdog4: watchdog@24b0000 { |
| compatible = "nxp,rtwdog"; |
| reg = <0x24b0000 0x10>; |
| status = "disabled"; |
| interrupts = <81 0>; |
| clocks = <&lpo>; |
| clk-source = <1>; |
| clk-divider = <1>; |
| }; |
| |
| usb1: usbd@2c80000 { |
| compatible = "nxp,ehci"; |
| reg = <0x2c80000 0x1000>; |
| interrupts = <215 0>; |
| interrupt-names = "usb_otg"; |
| clocks = <&usbclk>; |
| num-bidir-endpoints = <8>; |
| status = "disabled"; |
| }; |
| |
| usb2: usb@2c90000 { |
| compatible = "nxp,ehci"; |
| reg = <0x2c90000 0x1000>; |
| interrupts = <214 0>; |
| interrupt-names = "usb_otg"; |
| clocks = <&usbclk>; |
| num-bidir-endpoints = <8>; |
| status = "disabled"; |
| }; |
| |
| usbphy1: usb-phy@2ca0000 { |
| compatible = "nxp,usbphy"; |
| reg = <0x2ca0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| usbphy2: usb-phy@2cb0000 { |
| compatible = "nxp,usbphy"; |
| reg = <0x2cb0000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| tmpsns: tmpsns@4484580 { |
| reg = <0x4484580 0x24>; |
| interrupts = <83 0>; |
| compatible = "nxp,tmpsns"; |
| status = "disabled"; |
| }; |
| |
| sai1: sai@43b0000 { |
| compatible = "nxp,mcux-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinmux-cells = <2>; |
| reg = <0x43b0000 0x4000>; |
| clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>; |
| /* Source from audio PLL */ |
| clock-mux = <2>; |
| pre-div = <0>; |
| podf = <12>; |
| pll-clocks = <&anatop 0 0 0>, |
| <&anatop 0 0 32>, |
| <&anatop 0 0 1>, |
| <&anatop 0 0 768>, |
| <&anatop 0 0 1000>; |
| pll-clock-names = "src", "lp", "pd", "num", "den"; |
| pinmuxes = <&blkctrl_ns_aon 0x20 0x100>; |
| interrupts = <45 0>; |
| nxp,tx-channel = <1>; |
| dmas = <&edma3 0 22>, <&edma3 0 21>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <0>; |
| nxp,rx-dma-channel = <1>; |
| status = "disabled"; |
| }; |
| |
| sai2: sai@2bb0000 { |
| compatible = "nxp,mcux-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinmux-cells = <2>; |
| reg = <0x2bb0000 0x4000>; |
| clocks = <&ccm IMX_CCM_SAI2_CLK 0x2084 4>; |
| /* Source from audio PLL */ |
| clock-mux = <2>; |
| pre-div = <0>; |
| podf = <12>; |
| pll-clocks = <&anatop 0 0 0>, |
| <&anatop 0 0 32>, |
| <&anatop 0 0 1>, |
| <&anatop 0 0 768>, |
| <&anatop 0 0 1000>; |
| pll-clock-names = "src", "lp", "pd", "num", "den"; |
| pinmuxes = <&blkctrl_wakeup 0x38 0x100>; |
| interrupts = <198 0>; |
| nxp,tx-channel = <1>; |
| dmas = <&edma4 0 181>, <&edma4 0 180>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <3>; |
| nxp,rx-dma-channel = <4>; |
| status = "disabled"; |
| }; |
| |
| sai3: sai@2bc0000 { |
| compatible = "nxp,mcux-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinmux-cells = <2>; |
| reg = <0x2bc0000 0x4000>; |
| clocks = <&ccm IMX_CCM_SAI3_CLK 0x2104 4>; |
| /* Source from audio PLL */ |
| clock-mux = <2>; |
| pre-div = <0>; |
| podf = <12>; |
| pll-clocks = <&anatop 0 0 0>, |
| <&anatop 0 0 32>, |
| <&anatop 0 0 1>, |
| <&anatop 0 0 768>, |
| <&anatop 0 0 1000>; |
| pll-clock-names = "src", "lp", "pd", "num", "den"; |
| pinmuxes = <&blkctrl_wakeup 0x3c 0x100>; |
| interrupts = <199 0>; |
| nxp,tx-channel = <1>; |
| dmas = <&edma4 0 183>, <&edma4 0 182>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <5>; |
| nxp,rx-dma-channel = <6>; |
| status = "disabled"; |
| }; |
| |
| sai4: sai@2bd0000 { |
| compatible = "nxp,mcux-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinmux-cells = <2>; |
| reg = <0x2bd0000 0x4000>; |
| clocks = <&ccm IMX_CCM_SAI4_CLK 0x2184 6>; |
| /* Source from audio PLL */ |
| clock-mux = <2>; |
| pre-div = <0>; |
| podf = <12>; |
| pll-clocks = <&anatop 0 0 0>, |
| <&anatop 0 0 32>, |
| <&anatop 0 0 1>, |
| <&anatop 0 0 768>, |
| <&anatop 0 0 1000>; |
| pll-clock-names = "src", "lp", "pd", "num", "den"; |
| pinmuxes = <&blkctrl_wakeup 0x40 0x100>; |
| interrupts = <154 0>; |
| nxp,tx-channel = <1>; |
| dmas = <&edma4 0 185>, <&edma4 0 184>; |
| dma-names = "rx", "tx"; |
| nxp,tx-dma-channel = <0>; |
| nxp,rx-dma-channel = <8>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &flexspi { |
| compatible = "nxp,imx-flexspi"; |
| interrupts = <55 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>; |
| }; |
| |
| &flexspi2 { |
| compatible = "nxp,imx-flexspi"; |
| interrupts = <56 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>; |
| }; |
| |
| &memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ocram1: memory@0 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "OCRAM1"; |
| reg = <0x0 DT_SIZE_K(512)>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ocram1_available: memory@4000 { |
| /* OCRAM1 first 16K access is blocked by TRDC */ |
| reg = <0x0 DT_SIZE_K(496)>; |
| }; |
| }; |
| |
| ocram2: memory@80000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "OCRAM2"; |
| reg = <0x80000 DT_SIZE_K(256)>; |
| }; |
| }; |
