dts/arm/xilinx/versalnet_r52.dtsi

/*
 * Copyright (c) 2025, Advanced Micro Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <mem.h>
#include <arm/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <amd/versalnet.dtsi>

/ {
	model = "Versal NET RPU";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <0>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		status = "okay";
	};
};

&soc {
	interrupt-parent = <&gic>;

	gic: interrupt-controller@e2000000 {
		compatible = "arm,gic-v3", "arm,gic";
		reg = <0xe2000000 0x10000>,
		      <0xe2100000 0x80000>;
		interrupt-controller;
		#interrupt-cells = <4>;
		status = "okay";
	};
};