|  | /* | 
|  | * | 
|  | * Copyright (c) 2017 Linaro Limited. | 
|  | * | 
|  | * SPDX-License-Identifier: Apache-2.0 | 
|  | */ | 
|  |  | 
|  |  | 
|  | #include <soc.h> | 
|  | #include <soc_registers.h> | 
|  | #include <clock_control.h> | 
|  | #include <misc/util.h> | 
|  | #include <clock_control/stm32_clock_control.h> | 
|  | #include "stm32_ll_clock.h" | 
|  |  | 
|  |  | 
|  | #ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL | 
|  |  | 
|  | /* Macros to fill up division factors values */ | 
|  | #define _pllm(v) LL_RCC_PLLM_DIV_ ## v | 
|  | #define pllm(v) _pllm(v) | 
|  |  | 
|  | #define _pllp(v) LL_RCC_PLLP_DIV_ ## v | 
|  | #define pllp(v) _pllp(v) | 
|  |  | 
|  | /** | 
|  | * @brief fill in pll configuration structure | 
|  | */ | 
|  | void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit) | 
|  | { | 
|  | pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR); | 
|  | pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER; | 
|  | pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR); | 
|  | } | 
|  | #endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */ | 
|  |  | 
|  | /** | 
|  | * @brief Activate default clocks | 
|  | */ | 
|  | void config_enable_default_clocks(void) | 
|  | { | 
|  | /* Power Interface clock enabled by default */ | 
|  | LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); | 
|  | } | 
|  |  | 
|  | /** | 
|  | * @brief Function kept for driver genericity | 
|  | */ | 
|  | void LL_RCC_MSI_Disable(void) | 
|  | { | 
|  | /* Do nothing */ | 
|  | } |