| # SPDX-License-Identifier: Apache-2.0 |
| |
| zephyr_library() |
| |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_adsp.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ARM_SCMI clock_control_arm_scmi.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK clock_control_fixed_rate.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM clock_control_mcux_ccm.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM_REV2 clock_control_mcux_ccm_rev2.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_MCG clock_control_mcux_mcg.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_PCC clock_control_mcux_pcc.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_control_mcux_scg.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_control_mcux_scg_k4.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SERIES clock_control_silabs_series.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_PLL clock_control_si32_pll.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_control_si32_ahb.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_control_si32_apb.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_control_smartbond.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c) |
| |
| if(CONFIG_CLOCK_CONTROL_NRF2) |
| zephyr_library_sources(clock_control_nrf2_common.c) |
| zephyr_library_sources(clock_control_nrf2_fll16m.c) |
| zephyr_library_sources(clock_control_nrf2_hfxo.c) |
| zephyr_library_sources(clock_control_nrf2_hsfll.c) |
| zephyr_library_sources(clock_control_nrf2_lfclk.c) |
| endif() |
| |
| if(CONFIG_CLOCK_CONTROL_STM32_CUBE) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MCO clock_stm32_mco.c) |
| if(CONFIG_SOC_SERIES_STM32MP1X) |
| zephyr_library_sources(clock_stm32_ll_mp1.c) |
| elseif(CONFIG_SOC_SERIES_STM32H7X) |
| zephyr_library_sources(clock_stm32_ll_h7.c) |
| elseif(CONFIG_SOC_SERIES_STM32H7RSX) |
| zephyr_library_sources(clock_stm32_ll_h7.c) |
| elseif(CONFIG_SOC_SERIES_STM32H5X) |
| zephyr_library_sources(clock_stm32_ll_h5.c) |
| elseif(CONFIG_SOC_SERIES_STM32U5X) |
| zephyr_library_sources(clock_stm32_ll_u5.c) |
| elseif(CONFIG_SOC_SERIES_STM32WB0X) |
| zephyr_library_sources(clock_stm32_ll_wb0.c) |
| elseif(CONFIG_SOC_SERIES_STM32WBAX) |
| zephyr_library_sources(clock_stm32_ll_wba.c) |
| else() |
| zephyr_library_sources(clock_stm32_ll_common.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32C0X clock_stm32c0.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F0X clock_stm32f0_f3.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X clock_stm32f1.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F2X clock_stm32f2_f4_f7.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f0_f3.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f2_f4_f7.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f2_f4_f7.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0_u0.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_l5_wb_wl.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X clock_stm32l4_l5_wb_wl.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32U0X clock_stm32g0_u0.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_l5_wb_wl.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_STM32WLX clock_stm32l4_l5_wb_wl.c) |
| endif() |
| endif() |
| |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex_ll.c) |
| zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AGILEX5 clock_control_agilex5_ll.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AGILEX5 clock_control_agilex5.c) |
| |
| if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR) |
| zephyr_library_sources(clock_control_renesas_cpg_mssr.c) |
| zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED clock_control_r8a7795_cpg_mssr.c) |
| zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A779F0_CPG_MSSR_ENABLED clock_control_r8a779f0_cpg_mssr.c) |
| endif() |
| |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MAX32 clock_control_max32.c) |
| zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_AUXPLL clock_control_nrf_auxpll.c) |