| # Copyright (c) 2024 Nuvoton Technology Corporation. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| description: | |
| Nuvoton I3C controller |
| |
| Representation: |
| |
| /* If CONFIG_I3C_NPCX is enabled, the suggested clock configuration is as follows: */ |
| &pcc { |
| clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */ |
| core-prescaler = <3>; /* CORE_CLK runs at 30MHz */ |
| apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ |
| apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ |
| apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ |
| apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */ |
| }; |
| |
| &rst { |
| status = "okay"; |
| }; |
| |
| &i3c0 { |
| status = "okay"; |
| |
| /* I3C clock frequency suggestion = <PP_SCL, OD_SCL> */ |
| * Full speed = <12500000, 4170000> |
| * Normal speed = <7500000, 1500000> |
| */ |
| i3c-scl-hz = <12500000>; |
| i3c-od-scl-hz = <4170000>; |
| }; |
| |
| compatible: "nuvoton,npcx-i3c" |
| |
| include: [i3c-controller.yaml, pinctrl-device.yaml, reset-device.yaml] |
| |
| properties: |
| reg: |
| required: true |
| |
| interrupts: |
| required: true |
| |
| resets: |
| required: true |
| |
| i3c-od-scl-hz: |
| type: int |
| description: | |
| Open Drain Frequency for the I3C controller. When undefined, use |
| the controller default or as specified by the I3C specification. |
