| /* |
| * Copyright (c) 2023 Google LLC. |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <xtensa/config/core-isa.h> |
| #include <zephyr/sys/util.h> |
| #include <zephyr/sw_isr_table.h> |
| |
| #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 1 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 2 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| #if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 3 |
| #error core-isa.h interrupt level does not match dispatcher! |
| #endif |
| |
| /* |
| * Interrupt masks for every level (RT595 ADSP): |
| * XCHAL_INTLEVEL1_MASK: 0x0000FFE0 |
| * XCHAL_INTLEVEL2_MASK: 0x00FF0006 |
| * XCHAL_INTLEVEL3_MASK: 0xFF000018 |
| * XCHAL_INTLEVEL4_MASK: 0x00000000 |
| * XCHAL_INTLEVEL5_MASK: 0x00000001 |
| */ |
| |
| static inline int _xtensa_handle_one_int1(unsigned int mask) |
| { |
| int irq; |
| |
| mask &= XCHAL_INTLEVEL1_MASK; |
| for (int i = 5; i <= 31; i++) { |
| if (mask & BIT(i)) { |
| mask = BIT(i); |
| irq = i; |
| goto handle_irq; |
| } |
| } |
| return 0; |
| handle_irq: |
| _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
| return mask; |
| } |
| |
| static inline int _xtensa_handle_one_int2(unsigned int mask) |
| { |
| int irq; |
| |
| mask &= XCHAL_INTLEVEL2_MASK; |
| for (int i = 1; i <= 31; i++) { |
| if (mask & BIT(i)) { |
| mask = BIT(i); |
| irq = i; |
| goto handle_irq; |
| } |
| } |
| return 0; |
| handle_irq: |
| _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
| return mask; |
| } |
| |
| static inline int _xtensa_handle_one_int3(unsigned int mask) |
| { |
| int irq; |
| |
| mask &= XCHAL_INTLEVEL3_MASK; |
| for (int i = 3; i <= 31; i++) { |
| if (mask & BIT(i)) { |
| mask = BIT(i); |
| irq = i; |
| goto handle_irq; |
| } |
| } |
| return 0; |
| handle_irq: |
| _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
| return mask; |
| } |
| |
| static inline int _xtensa_handle_one_int4(unsigned int mask) |
| { |
| return 0; |
| } |
| |
| static inline int _xtensa_handle_one_int5(unsigned int mask) |
| { |
| int irq; |
| |
| if (mask & BIT(0)) { |
| mask = BIT(0); |
| irq = 0; |
| goto handle_irq; |
| } |
| return 0; |
| handle_irq: |
| _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
| return mask; |
| } |