blob: 3f5f3075777fc8278c2d2e1273c7353c45f9c93a [file] [log] [blame]
# ARM architecture configuration options
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
menu "ARM Options"
depends on ARM
config ARCH
default "arm"
config CPU_CORTEX
bool
help
This option signifies the use of a CPU of the Cortex family.
config ARM_CUSTOM_INTERRUPT_CONTROLLER
bool
help
This option indicates that the ARM CPU is connected to a custom (i.e.
non-GIC or NVIC) interrupt controller.
A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
allow interfacing to a custom external interrupt controller and this
option must be selected when such cores are connected to an interrupt
controller that is not the ARM Generic Interrupt Controller (GIC) or
the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
When this option is selected, the architecture interrupt control
functions are mapped to the SoC interrupt control interface, which is
implemented at the SoC level.
N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
is assumed that the custom interrupt control interface implementation
assumes responsibility for handling the NVIC.
config CODE_DATA_RELOCATION_SRAM
bool "Relocate code/data sections to SRAM"
depends on CPU_CORTEX_M
select CODE_DATA_RELOCATION
help
When selected this will relocate .text, data and .bss sections from
the specified files and places it in SRAM. The files should be specified
in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This
config is used to create an MPU entry for the SRAM space used for code
relocation.
config ARM_ON_ENTER_CPU_IDLE_HOOK
bool
help
Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
If needed, this hook can be used to prevent the CPU from actually
entering sleep by skipping the WFE/WFI instruction.
config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
bool
help
Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when
the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
If needed, this hook can prepare data to upcoming call to
z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs
from z_arm_on_enter_cpu_idle because it is called before interrupts are
disabled.
config ARM_ON_EXIT_CPU_IDLE
bool
help
Enables a possibility to inject SoC-specific code just after WFI/WFE
instructions of the cpu idle implementation.
Enabling this option requires that the SoC provides a soc_cpu_idle.h
header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by
_ASMLANGUAGE.
The SOC_ON_EXIT_CPU_IDLE macro is expanded just after
WFI/WFE instructions before any memory access is performed. The purpose
of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues
observed on some SoCs caused by a memory access following WFI/WFE
instructions.
rsource "core/Kconfig"
rsource "core/Kconfig.vfp"
# General options signifying CPU capabilities of ARM SoCs
config CPU_HAS_ARM_MPU
bool
select CPU_HAS_MPU
help
This option is enabled when the CPU has a Memory Protection Unit (MPU)
in ARM flavor.
config CPU_HAS_NXP_MPU
bool
select CPU_HAS_MPU
help
This option is enabled when the CPU has a Memory Protection Unit (MPU)
in NXP flavor.
config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
bool "Custom fixed SoC MPU region definition"
help
If enabled, this option signifies that the SoC will
define and configure its own fixed MPU regions in the
SoC definition. These fixed MPU regions are currently
used to set Flash and SRAM default access policies and
they are programmed at boot time.
config CPU_HAS_ARM_SAU
bool
select CPU_HAS_TEE
help
MCU implements the ARM Security Attribution Unit (SAU).
config CPU_HAS_NRF_IDAU
bool
select CPU_HAS_TEE
help
MCU implements the nRF (vendor-specific) Security Attribution Unit.
(IDAU: "Implementation-Defined Attribution Unit", in accordance with
ARM terminology).
config HAS_SWO
bool
help
When enabled, indicates that SoC has an SWO output
endmenu