blob: ac61c7d351be3ac6b34ae47ad34e3f32ed4f8252 [file] [log] [blame]
/*
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f412.dtsi>
/ {
soc {
compatible = "st,stm32f413", "st,stm32f4", "simple-bus";
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1, 31U)>;
interrupts = <83 0>;
status = "disabled";
};
uart9: serial@40011800 {
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
resets = <&rctl STM32_RESET(APB2, 6U)>;
interrupts = <88 0>;
status = "disabled";
};
uart10: serial@40011c00 {
compatible = "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <89 0>;
status = "disabled";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
#io-channel-cells = <1>;
};
can3: can@40006c00 {
compatible = "st,stm32-bxcan";
reg = <0x40006c00 0x400>;
interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>;
status = "disabled";
sample-point = <875>;
};
};
};