boards/ezurio/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi

/*
 * Copyright (c) 2022 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	i2c0_default: i2c0_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
				<NRF_PSEL(TWIM_SCL, 0, 29)>;
		};
	};

	i2c0_sleep: i2c0_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
				<NRF_PSEL(TWIM_SCL, 0, 29)>;
			low-power-enable;
		};
	};

	spi0_default: spi0_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
				<NRF_PSEL(SPIM_MOSI, 0, 3)>,
				<NRF_PSEL(SPIM_MISO, 0, 17)>;
		};
	};

	spi0_sleep: spi0_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 0)>,
				<NRF_PSEL(SPIM_MOSI, 0, 3)>,
				<NRF_PSEL(SPIM_MISO, 0, 17)>;
			low-power-enable;
		};
	};

	spi1_default: spi1_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
				<NRF_PSEL(SPIM_MOSI, 0, 9)>,
				<NRF_PSEL(SPIM_MISO, 0, 10)>;
		};
	};

	spi1_sleep: spi1_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
				<NRF_PSEL(SPIM_MOSI, 0, 9)>,
				<NRF_PSEL(SPIM_MISO, 0, 10)>;
			low-power-enable;
		};
	};

	uart0_default: uart0_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 21)>,
				<NRF_PSEL(UART_RX, 0, 22)>,
				<NRF_PSEL(UART_RTS, 0, 23)>,
				<NRF_PSEL(UART_CTS, 0, 24)>;
		};
	};

	uart0_sleep: uart0_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 21)>,
				<NRF_PSEL(UART_RX, 0, 22)>,
				<NRF_PSEL(UART_RTS, 0, 23)>,
				<NRF_PSEL(UART_CTS, 0, 24)>;
			low-power-enable;
		};
	};

};