commit 70f541107420503841825c6fac72f6cdbfbb3424
author IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com> Mon Mar 25 10:52:51 2024 +0100
committer Fabio Baltieri <fabio.baltieri@gmail.com> Thu Mar 28 09:42:12 2024 +0000
tree adf2b70d03f36e891b84230e352a5a3fec032d7a
parent 12c69562cff8cc542819c156380b6c116c2ca46e

boards: stm32h573i_dk: Fix CAN core clock

Set the PLL1_Q divider to 6 give a can core clock of 80MHz to
resolve fdcan_clk reception problem because M_CAN requires that
the host clock "APB1" should be higher or equal to the CAN core
clock "PLL1_Q".

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>

boards/st/stm32h573i_dk/stm32h573i_dk.dts

diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
index a4d0b5b..30401d7 100644
--- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts
+++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
@@ -81,7 +81,7 @@
 	div-m = <5>;
 	mul-n = <96>;
 	div-p = <2>;
-	div-q = <2>;
+	div-q = <6>;
 	div-r = <2>;
 	clocks = <&clk_hse>;
 	status = "okay";