boards/st/stm32h750b_dk/stm32h750b_dk.dts

/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <st/h7/stm32h750Xb.dtsi>
#include <st/h7/stm32h750xbhx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>

/ {
	model = "STMicroelectronics STM32H750B DISCOVERY KIT";
	compatible = "st,stm32h750b-dk";

	chosen {
		zephyr,console = &usart3;
		zephyr,shell-uart = &usart3;
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
		zephyr,flash-controller = &mt25ql512ab1;
	};

	sdram2: sdram@d0000000 {
		compatible = "zephyr,memory-region", "mmio-sram";
		device_type = "memory";
		reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
		zephyr,memory-region = "SDRAM2";
		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
	};

	leds {
		compatible = "gpio-leds";
		red_led: led_1 {
			gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
			label = "USER1 LD6";
		};
		green_led: led_2 {
			gpios = <&gpioj 2 GPIO_ACTIVE_LOW>;
			label = "USER2 LD7";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		user_button: button {
			label = "User";
			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
			zephyr,code = <INPUT_KEY_0>;
		};
	};

	aliases {
		led0 = &green_led;
		led1 = &red_led;
		sw0 = &user_button;
		spi-flash0 = &mt25ql512ab1;
	};
};

&clk_hse {
	clock-frequency = <DT_FREQ_M(25)>;
	hse-bypass;
	status = "okay";
};

&pll {
	div-m = <5>;
	mul-n = <192>;
	div-p = <2>;
	div-q = <4>;
	div-r = <4>;
	clocks = <&clk_hse>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(480)>;
	d1cpre = <1>;
	hpre = <2>;
	d1ppre = <2>;
	d2ppre1 = <2>;
	d2ppre2 = <2>;
	d3ppre = <2>;
};

&usart3 {
	pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&quadspi {
	pinctrl-names = "default";
	pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
		     &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
		     &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
		     &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
	flash-id = <1>;
	status = "okay";

	mt25ql512ab1: qspi-nor-flash-1@90000000 {
		compatible = "st,stm32-qspi-nor";
		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
		qspi-max-frequency = <72000000>;
		spi-bus-width = <4>;
		status = "okay";

		partitions {
			   compatible = "fixed-partitions";
			   #address-cells = <1>;
			   #size-cells = <1>;

			   partition@0 {
			       reg = <0x0 DT_SIZE_M(64)>;
			   };
		};
	};

	mt25ql512ab2: qspi-nor-flash-2@90000000 {
		compatible = "st,stm32-qspi-nor";
		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
		qspi-max-frequency = <72000000>;
		status = "okay";
	};
};

&fmc {
	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
		&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
		&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
		&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
		&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
		&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
		&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
		&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
		&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
		&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
		&fmc_d15_pd10>;
	pinctrl-names = "default";
	status = "okay";

	sdram {
		status = "okay";
		power-up-delay = <100>;
		num-auto-refresh = <8>;
		mode-register = <0x220>;
		refresh-rate = <0x603>;
		bank@1 {
			reg = <1>;
			st,sdram-control = <STM32_FMC_SDRAM_NC_8
				STM32_FMC_SDRAM_NR_12
				STM32_FMC_SDRAM_MWID_16
				STM32_FMC_SDRAM_NB_4
				STM32_FMC_SDRAM_CAS_3
				STM32_FMC_SDRAM_SDCLK_PERIOD_2
				STM32_FMC_SDRAM_RBURST_ENABLE
				STM32_FMC_SDRAM_RPIPE_0>;
			st,sdram-timing = <2 7 4 7 2 2 2>;
		};
	};
};