/* | |
* Copyright 2024 NXP | |
* | |
* SPDX-License-Identifier: Apache-2.0 | |
*/ | |
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ | |
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ | |
#define PMU_RESET_CM33_SOFT_RESET 0x1 | |
#define PMU_RESET_CM33_LOCKUP 0x2 | |
#define PMU_RESET_WATCHDOG 0x4 | |
#define PMU_RESET_AP_RESET 0x8 | |
#define PMU_RESET_CODE_WATCHDOG 0x10 | |
#define PMU_RESET_ITRC 0x20 | |
#define PMU_RESET_RESETB 0x40 | |
#define PMU_RESET_ALL 0x7F | |
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ */ |