| common: |
| tags: |
| - kernel |
| - interrupt |
| - isr_table |
| tests: |
| arch.interrupt.gen_isr_table.arm_baseline: &arm-baseline |
| platform_allow: qemu_cortex_m3 |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| arch.interrupt.gen_isr_table.arm_baseline.linker_generator: &arm-baseline-linker-generator |
| platform_allow: qemu_cortex_m3 |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE |
| tags: |
| - linker_generator |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| - CONFIG_CMAKE_LINKER_GENERATOR=y |
| arch.interrupt.gen_isr_table.arm_mainline: &arm-mainline |
| platform_allow: qemu_cortex_m3 |
| platform_exclude: |
| - stmf103_mini |
| - nucleo_f103rb |
| - olimexino_stm32 |
| - stm32_min_dev@black |
| - stm32_min_dev@blue |
| - usb_kw24d512 |
| - v2m_beetle |
| - cc1352r1_launchxl |
| - cc26x2r1_launchxl |
| - olimex_stm32_h103 |
| - cc1352r_sensortag |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV7_M_ARMV8_M_MAINLINE |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| arch.interrupt.gen_isr_table.disabled: |
| platform_allow: qemu_cortex_m3 |
| extra_configs: |
| - CONFIG_GEN_ISR_TABLES=n |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| build_only: true |
| |
| arch.interrupt.gen_isr_table_local.arm_baseline: |
| <<: *arm-baseline |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE and not CONFIG_USERSPACE |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y |
| arch.interrupt.gen_isr_table_local.arm_baseline.linker_generator: |
| <<: *arm-baseline-linker-generator |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE and not CONFIG_USERSPACE |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| - CONFIG_CMAKE_LINKER_GENERATOR=y |
| - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y |
| arch.interrupt.gen_isr_table_local.arm_mainline: |
| <<: *arm-mainline |
| filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE and not CONFIG_USERSPACE |
| extra_configs: |
| - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y |
| - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y |
| |
| arch.interrupt.gen_isr_table.arc: |
| arch_allow: arc |
| filter: CONFIG_RGF_NUM_BANKS > 1 |
| extra_configs: |
| - CONFIG_ARC_FIRQ_STACK=y |
| - CONFIG_TEST_HW_STACK_PROTECTION=n |
| arch.interrupt.gen_isr_table.riscv_direct: |
| arch_allow: riscv |
| platform_exclude: |
| - m2gl025_miv |
| - adp_xc7k/ae350 |
| filter: CONFIG_RISCV_PRIVILEGED |
| extra_configs: |
| - CONFIG_GEN_IRQ_VECTOR_TABLE=y |
| arch.interrupt.gen_isr_table.riscv_no_direct: |
| platform_exclude: m2gl025_miv |
| arch_allow: riscv |
| filter: CONFIG_RISCV_PRIVILEGED |
| extra_configs: |
| - CONFIG_GEN_IRQ_VECTOR_TABLE=n |
| arch.interrupt.gen_isr_table.bit_shift_2nd_level: |
| platform_allow: qemu_riscv32 |
| filter: CONFIG_RISCV_PRIVILEGED |
| extra_configs: |
| - CONFIG_1ST_LEVEL_INTERRUPT_BITS=7 |
| - CONFIG_2ND_LEVEL_INTERRUPT_BITS=9 |
| arch.interrupt.gen_isr_table.bit_shift_3rd_level: |
| platform_allow: qemu_riscv32 |
| filter: CONFIG_RISCV_PRIVILEGED |
| extra_configs: |
| - CONFIG_MULTI_LEVEL_INTERRUPTS=y |
| - CONFIG_2ND_LEVEL_INTERRUPTS=y |
| - CONFIG_3RD_LEVEL_INTERRUPTS=y |
| - CONFIG_1ST_LEVEL_INTERRUPT_BITS=8 |
| - CONFIG_2ND_LEVEL_INTERRUPT_BITS=11 |
| - CONFIG_3RD_LEVEL_INTERRUPT_BITS=13 |
