| /* |
| ** ################################################################### |
| ** Processors: MCIMX6X_M4 |
| ** |
| ** Compilers: Keil ARM C/C++ Compiler |
| ** Freescale C/C++ for Embedded ARM |
| ** GNU C Compiler |
| ** GNU C Compiler - CodeSourcery Sourcery G++ |
| ** IAR ANSI C/C++ Compiler for ARM |
| ** |
| ** Reference manual: |
| ** Version: rev. 1.0, 2015-07-17 |
| ** Build: b150707 |
| ** |
| ** Abstract: |
| ** CMSIS Peripheral Access Layer for MCIMX6X_M4 |
| ** |
| ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. |
| ** All rights reserved. |
| ** |
| ** Redistribution and use in source and binary forms, with or without modification, |
| ** are permitted provided that the following conditions are met: |
| ** |
| ** o Redistributions of source code must retain the above copyright notice, this list |
| ** of conditions and the following disclaimer. |
| ** |
| ** o Redistributions in binary form must reproduce the above copyright notice, this |
| ** list of conditions and the following disclaimer in the documentation and/or |
| ** other materials provided with the distribution. |
| ** |
| ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| ** contributors may be used to endorse or promote products derived from this |
| ** software without specific prior written permission. |
| ** |
| ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ** |
| ** http: www.freescale.com |
| ** mail: support@freescale.com |
| ** |
| ** Revisions: |
| ** - rev. 1.0 (2015-07-17) |
| ** Initial version . |
| ** |
| ** ################################################################### |
| */ |
| |
| /*! |
| * @file MCIMX6X_M4.h |
| * @version 1.0 |
| * @date 2015-07-17 |
| * @brief CMSIS Peripheral Access Layer for MCIMX6X_M4 |
| * |
| * CMSIS Peripheral Access Layer for MCIMX6X_M4 |
| */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCU activation |
| ---------------------------------------------------------------------------- */ |
| |
| /* Prevention from multiple including the same memory map */ |
| #if !defined(MCIMX6X_M4_H_) /* Check if memory map has not been already included */ |
| #define MCIMX6X_M4_H_ |
| #define MCU_MCIMX6X_M4 |
| |
| /* Check if another memory map has not been also included */ |
| #if (defined(MCU_ACTIVE)) |
| #error MCIMX6X_M4 memory map: There is already included another memory map. Only one memory map can be included. |
| #endif /* (defined(MCU_ACTIVE)) */ |
| #define MCU_ACTIVE |
| |
| #include <stdint.h> |
| |
| /** Memory map major version (memory maps with equal major version number are |
| * compatible) */ |
| #define MCU_MEM_MAP_VERSION 0x0100u |
| /** Memory map minor version */ |
| #define MCU_MEM_MAP_VERSION_MINOR 0x0000u |
| |
| /* ---------------------------------------------------------------------------- |
| -- Interrupt vector numbers |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
| * @{ |
| */ |
| |
| /** Interrupt Number Definitions */ |
| #define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ |
| |
| typedef enum IRQn { |
| /* Auxiliary constants */ |
| NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
| |
| /* Core interrupts */ |
| NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ |
| MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ |
| BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ |
| UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ |
| SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ |
| DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ |
| PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ |
| |
| /* Device specific interrupts */ |
| Cortex_M4_IRQn = 0, /**< Cache Controller interrupt */ |
| DAP_IRQn = 1, /**< Debug Access Port interrupt request. */ |
| SDMA_IRQn = 2, /**< SDMA interrupt request from all channels. */ |
| Reserved0_IRQn = 3, /**< Reserved */ |
| SNVS_IRQn = 4, /**< PMIC power off request. */ |
| LCDIF1_IRQn = 5, /**< LCDIF1 Sync Interrupt */ |
| LCDIF2_IRQn = 6, /**< LCDIF2 Sync Interrupt */ |
| CSI1_IRQn = 7, /**< CMOS Sensor Interface interrupt request */ |
| PXP_IRQn = 8, /**< PXP interrupt */ |
| Reserved1_IRQn = 9, /**< Reserved */ |
| GPU_IRQn = 10, /**< GPU general interrupt request */ |
| WDOG3_IRQn = 11, /**< WDOG3 interrupt request */ |
| SEMA4_CP1_IRQn = 12, /**< SEMA4 CP1 interrupt request. */ |
| APBHDMA_IRQn = 13, /**< Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ |
| EIM_IRQn = 14, /**< EIM interrupt request. */ |
| BCH_IRQn = 15, /**< BCH operation complete interrupt. */ |
| GPMI_IRQn = 16, /**< GPMI operation timeout error interrupt. */ |
| UART6_IRQn = 17, /**< UART6 interrupt request. */ |
| eCSPI5_IRQn = 18, /**< eCSPI5 interrupt request. */ |
| SNVS_CONSOLIDATED_IRQn = 19, /**< SNVS consolidated interrupt. */ |
| SNVS_SECURITY_IRQn = 20, /**< SNVS security interrupt. */ |
| CSU_IRQn = 21, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ |
| USDHC1_IRQn = 22, /**< uSDHC1 (Enhanced SDHC) interrupt request */ |
| USDHC2_IRQn = 23, /**< uSDHC2 (Enhanced SDHC) interrupt request. */ |
| USDHC3_IRQn = 24, /**< uSDHC3 (Enhanced SDHC) interrupt request. */ |
| USDHC4_IRQn = 25, /**< uSDHC4 (Enhanced SDHC) interrupt request. */ |
| UART1_IRQn = 26, /**< UART1 interrupt request. */ |
| UART2_IRQn = 27, /**< UART2 interrupt request. */ |
| UART3_IRQn = 28, /**< UART3 interrupt request. */ |
| UART4_IRQn = 29, /**< UART4 interrupt request. */ |
| UART5_IRQn = 30, /**< UART5 interrupt request. */ |
| eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request. */ |
| eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request. */ |
| eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request. */ |
| eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request. */ |
| I2C4_IRQn = 35, /**< I2C4 interrupt request */ |
| I2C1_IRQn = 36, /**< I2C1 interrupt request. */ |
| I2C2_IRQn = 37, /**< I2C2 interrupt request. */ |
| I2C3_IRQn = 38, /**< I2C3 interrupt request. */ |
| RDC_IRQn = 39, /**< RDC interrupt request. */ |
| USB_IRQn = 40, /**< USB HISC Host interrupt request. */ |
| CSI2_IRQn = 41, /**< CSI interrupt */ |
| USB_OTG2_IRQn = 42, /**< USB OTG 2 interrupt request. */ |
| USB_OTG1_IRQn = 43, /**< USB OTG 1 interrupt request. */ |
| USB_PHY1_IRQn = 44, /**< UTMI0 interrupt request. */ |
| USB_PHY2_IRQn = 45, /**< UTMI1 interrupt request. */ |
| SSI1_IRQn = 46, /**< SSI1 interrupt request. */ |
| SSI2_IRQn = 47, /**< SSI2 interrupt request. */ |
| SSI3_IRQn = 48, /**< SSI3 interrupt request. */ |
| Temperature_Monitor_IRQn = 49, /**< Temperature Sensor (temp. greater than threshold) interrupt request. */ |
| ASRC_IRQn = 50, /**< ASRC interrupt request. */ |
| ESAI_IRQn = 51, /**< ESAI interrupt request */ |
| SPDIF_IRQn = 52, /**< SPDIF Rx/Tx interrupt. */ |
| MLB_ERROR_IRQn = 53, /**< MLB error interrupt request. */ |
| PMU1_IRQn = 54, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ |
| GPT_IRQn = 55, /**< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines. */ |
| EPIT1_IRQn = 56, /**< EPIT1 output compare interrupt. */ |
| EPIT2_IRQn = 57, /**< EPIT2 output compare interrupt. */ |
| GPIO1_INT7_IRQn = 58, /**< INT7 interrupt request. */ |
| GPIO1_INT6_IRQn = 59, /**< INT6 interrupt request. */ |
| GPIO1_INT5_IRQn = 60, /**< INT5 interrupt request. */ |
| GPIO1_INT4_IRQn = 61, /**< INT4 interrupt request. */ |
| GPIO1_INT3_IRQn = 62, /**< INT3 interrupt request. */ |
| GPIO1_INT2_IRQn = 63, /**< INT2 interrupt request. */ |
| GPIO1_INT1_IRQn = 64, /**< INT1 interrupt request. */ |
| GPIO1_INT0_IRQn = 65, /**< INT0 interrupt request. */ |
| GPIO1_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ |
| GPIO1_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ |
| GPIO2_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ |
| GPIO2_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ |
| GPIO3_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ |
| GPIO3_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ |
| GPIO4_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ |
| GPIO4_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ |
| GPIO5_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ |
| GPIO5_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ |
| GPIO6_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO6 signals 0 - 15. */ |
| GPIO6_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO6 signals 16 - 31. */ |
| GPIO7_INT15_0_IRQn = 78, /**< Combined interrupt indication for GPIO7 signals 0 - 15. */ |
| GPIO7_INT31_16_IRQn = 79, /**< Combined interrupt indication for GPIO7 signals 16 - 31. */ |
| WDOG1_IRQn = 80, /**< WDOG1 timer reset interrupt request. */ |
| WDOG2_IRQn = 81, /**< WDOG2 timer reset interrupt request. */ |
| KPP_IRQn = 82, /**< Key Pad interrupt request */ |
| PWM1_PWM5_IRQn = 83, /**< Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ |
| PWM2_PWM6_IRQn = 84, /**< Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ |
| PWM3_PWM7_IRQn = 85, /**< Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ |
| PWM4_PWM8_IRQn = 86, /**< Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ |
| CCM1_IRQn = 87, /**< CCM interrupt request 1. */ |
| CCM2_IRQn = 88, /**< CCM interrupt request 2. */ |
| GPC_IRQn = 89, /**< GPC interrupt request 1. */ |
| MU_A9_IRQn = 90, /**< Message unit interrupt to A9 core */ |
| SRC_IRQn = 91, /**< SRC interrupt request. */ |
| CPU_L2I_IRQn = 92, /**< L2 interrupt request. */ |
| CPU_PCEI_IRQn = 93, /**< Parity Check error interrupt request. */ |
| CPU_PUI_IRQn = 94, /**< Performance Unit interrupt. */ |
| CPU_CTI_IRQn = 95, /**< CTI trigger outputs interrupt. */ |
| SRC_CPU_WDOG_IRQn = 96, /**< Combined CPU wdog interrupts (4x) out of SRC. */ |
| SAI1_IRQn = 97, /**< SAI1 interrupt request. */ |
| SAI2_IRQn = 98, /**< SAI2 interrupt request. */ |
| MU_M4_IRQn = 99, /**< Message unit Interrupt to M4 core */ |
| ADC1_IRQn = 100, /**< ADC1 interrupt request. */ |
| ADC2_IRQn = 101, /**< ADC2 interrupt request. */ |
| ENET2_IRQn = 102, /**< ENET2 Interrupt Request. */ |
| ENET2_TI_IRQn = 103, /**< ENET2 1588 Timer interrupt [synchronous] request. */ |
| SJC_IRQn = 104, /**< SJC interrupt from General Purpose register. */ |
| CAAM1_IRQn = 105, /**< CAAM job ring 0 interrupt. */ |
| CAAM2_IRQn = 106, /**< CAAM job ring 1 interrupt. */ |
| QSPI1_IRQn = 107, /**< QSPI1 interrupt request. */ |
| TZASC_IRQn = 108, /**< TZASC (PL380) interrupt request. */ |
| QSPI2_IRQn = 109, /**< QSPI2 interrupt request. */ |
| FLEXCAN1_IRQn = 110, /**< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ |
| FLEXCAN2_IRQn = 111, /**< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ |
| Reserved2_IRQn = 112, /**< Reserved */ |
| Reserved3_IRQn = 113, /**< Reserved */ |
| Reserved4_IRQn = 114, /**< Reserved */ |
| Reserved5_IRQn = 115, /**< Reserved */ |
| SEMA4_CP0_IRQn = 116, /**< SEMA4 CP0 interrupt request */ |
| MLB_IRCI_IRQn = 117, /**< Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158. */ |
| ENET1_IRQn = 118, /**< ENET1 Interrupt Request. */ |
| ENET1_TI_IRQn = 119, /**< ENET1 1588 Timer interrupt [synchronous] request. */ |
| PCIe1_IRQn = 120, /**< PCIe interrupt request 1. */ |
| PCIe2_IRQn = 121, /**< PCIe interrupt request 2. */ |
| PCIe3_IRQn = 122, /**< PCIe interrupt request 3. */ |
| PCIe4_IRQn = 123, /**< PCIe interrupt request 4. */ |
| DCIC1_IRQn = 124, /**< DCIC1 interrupt request. */ |
| DCIC2_IRQn = 125, /**< DCIC2 interrupt request. */ |
| MLB_LOCI_IRQn = 126, /**< Logical OR of channel[63:32] interrupt requests. */ |
| PMU2_IRQn = 127, /**< Brown out of core, gpu, and chip digital regulators occurred. */ |
| } IRQn_Type; |
| |
| /*! |
| * @} |
| */ /* end of group Interrupt_vector_numbers */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- Cortex M4 Core Configuration |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration |
| * @{ |
| */ |
| |
| #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ |
| #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ |
| #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
| #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ |
| |
| #include "core_cm4.h" /* Core Peripheral Access Layer */ |
| |
| /*! |
| * @} |
| */ /* end of group Cortex_Core_Configuration */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- Device Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
| * @{ |
| */ |
| |
| /* |
| ** Start of section using anonymous unions |
| */ |
| |
| #if defined(__ARMCC_VERSION) |
| #pragma push |
| #pragma anon_unions |
| #elif defined(__GNUC__) |
| /* anonymous unions are enabled by default */ |
| #elif defined(__IAR_SYSTEMS_ICC__) |
| #pragma language=extended |
| #else |
| #error Not supported compiler type |
| #endif |
| |
| /* ---------------------------------------------------------------------------- |
| -- ADC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ADC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t HC0; /**< Control register for hardware triggers, offset: 0x0 */ |
| __IO uint32_t HC1; /**< Control register for hardware triggers, offset: 0x4 */ |
| __I uint32_t HS; /**< Status register for HW triggers, offset: 0x8 */ |
| __IO uint32_t R0; /**< Data result register for HW triggers, offset: 0xC */ |
| __IO uint32_t R1; /**< Data result register for HW triggers, offset: 0x10 */ |
| __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ |
| __IO uint32_t GC; /**< General control register, offset: 0x18 */ |
| __IO uint32_t GS; /**< General status register, offset: 0x1C */ |
| __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ |
| __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ |
| __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ |
| } ADC_Type, *ADC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ADC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ADC - Register accessors */ |
| #define ADC_HC0_REG(base) ((base)->HC0) |
| #define ADC_HC1_REG(base) ((base)->HC1) |
| #define ADC_HS_REG(base) ((base)->HS) |
| #define ADC_R0_REG(base) ((base)->R0) |
| #define ADC_R1_REG(base) ((base)->R1) |
| #define ADC_CFG_REG(base) ((base)->CFG) |
| #define ADC_GC_REG(base) ((base)->GC) |
| #define ADC_GS_REG(base) ((base)->GS) |
| #define ADC_CV_REG(base) ((base)->CV) |
| #define ADC_OFS_REG(base) ((base)->OFS) |
| #define ADC_CAL_REG(base) ((base)->CAL) |
| |
| /*! |
| * @} |
| */ /* end of group ADC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ADC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ADC_Register_Masks ADC Register Masks |
| * @{ |
| */ |
| |
| /* HC0 Bit Fields */ |
| #define ADC_HC0_ADCH_MASK 0x1Fu |
| #define ADC_HC0_ADCH_SHIFT 0 |
| #define ADC_HC0_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_HC0_ADCH_SHIFT))&ADC_HC0_ADCH_MASK) |
| #define ADC_HC0_AIEN_MASK 0x80u |
| #define ADC_HC0_AIEN_SHIFT 7 |
| /* HC1 Bit Fields */ |
| #define ADC_HC1_ADCH_MASK 0x1Fu |
| #define ADC_HC1_ADCH_SHIFT 0 |
| #define ADC_HC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_HC1_ADCH_SHIFT))&ADC_HC1_ADCH_MASK) |
| #define ADC_HC1_AIEN_MASK 0x80u |
| #define ADC_HC1_AIEN_SHIFT 7 |
| /* HS Bit Fields */ |
| #define ADC_HS_COCO0_MASK 0x1u |
| #define ADC_HS_COCO0_SHIFT 0 |
| #define ADC_HS_COCO1_MASK 0x2u |
| #define ADC_HS_COCO1_SHIFT 1 |
| /* R0 Bit Fields */ |
| #define ADC_R0_D_MASK 0xFFFu |
| #define ADC_R0_D_SHIFT 0 |
| #define ADC_R0_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R0_D_SHIFT))&ADC_R0_D_MASK) |
| /* R1 Bit Fields */ |
| #define ADC_R1_D_MASK 0xFFFu |
| #define ADC_R1_D_SHIFT 0 |
| #define ADC_R1_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R1_D_SHIFT))&ADC_R1_D_MASK) |
| /* CFG Bit Fields */ |
| #define ADC_CFG_ADICLK_MASK 0x3u |
| #define ADC_CFG_ADICLK_SHIFT 0 |
| #define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADICLK_SHIFT))&ADC_CFG_ADICLK_MASK) |
| #define ADC_CFG_MODE_MASK 0xCu |
| #define ADC_CFG_MODE_SHIFT 2 |
| #define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_MODE_SHIFT))&ADC_CFG_MODE_MASK) |
| #define ADC_CFG_ADLSMP_MASK 0x10u |
| #define ADC_CFG_ADLSMP_SHIFT 4 |
| #define ADC_CFG_ADIV_MASK 0x60u |
| #define ADC_CFG_ADIV_SHIFT 5 |
| #define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADIV_SHIFT))&ADC_CFG_ADIV_MASK) |
| #define ADC_CFG_ADLPC_MASK 0x80u |
| #define ADC_CFG_ADLPC_SHIFT 7 |
| #define ADC_CFG_ADSTS_MASK 0x300u |
| #define ADC_CFG_ADSTS_SHIFT 8 |
| #define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_ADSTS_SHIFT))&ADC_CFG_ADSTS_MASK) |
| #define ADC_CFG_ADHSC_MASK 0x400u |
| #define ADC_CFG_ADHSC_SHIFT 10 |
| #define ADC_CFG_REFSEL_MASK 0x1800u |
| #define ADC_CFG_REFSEL_SHIFT 11 |
| #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_REFSEL_SHIFT))&ADC_CFG_REFSEL_MASK) |
| #define ADC_CFG_ADTRG_MASK 0x2000u |
| #define ADC_CFG_ADTRG_SHIFT 13 |
| #define ADC_CFG_AVGS_MASK 0xC000u |
| #define ADC_CFG_AVGS_SHIFT 14 |
| #define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG_AVGS_SHIFT))&ADC_CFG_AVGS_MASK) |
| #define ADC_CFG_OVWREN_MASK 0x10000u |
| #define ADC_CFG_OVWREN_SHIFT 16 |
| /* GC Bit Fields */ |
| #define ADC_GC_ADACKEN_MASK 0x1u |
| #define ADC_GC_ADACKEN_SHIFT 0 |
| #define ADC_GC_DMAEN_MASK 0x2u |
| #define ADC_GC_DMAEN_SHIFT 1 |
| #define ADC_GC_ACREN_MASK 0x4u |
| #define ADC_GC_ACREN_SHIFT 2 |
| #define ADC_GC_ACFGT_MASK 0x8u |
| #define ADC_GC_ACFGT_SHIFT 3 |
| #define ADC_GC_ACFE_MASK 0x10u |
| #define ADC_GC_ACFE_SHIFT 4 |
| #define ADC_GC_AVGE_MASK 0x20u |
| #define ADC_GC_AVGE_SHIFT 5 |
| #define ADC_GC_ADCO_MASK 0x40u |
| #define ADC_GC_ADCO_SHIFT 6 |
| #define ADC_GC_CAL_MASK 0x80u |
| #define ADC_GC_CAL_SHIFT 7 |
| /* GS Bit Fields */ |
| #define ADC_GS_ADACT_MASK 0x1u |
| #define ADC_GS_ADACT_SHIFT 0 |
| #define ADC_GS_CALF_MASK 0x2u |
| #define ADC_GS_CALF_SHIFT 1 |
| #define ADC_GS_AWKST_MASK 0x4u |
| #define ADC_GS_AWKST_SHIFT 2 |
| /* CV Bit Fields */ |
| #define ADC_CV_CV1_MASK 0xFFFu |
| #define ADC_CV_CV1_SHIFT 0 |
| #define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV1_SHIFT))&ADC_CV_CV1_MASK) |
| #define ADC_CV_CV2_MASK 0xFFF0000u |
| #define ADC_CV_CV2_SHIFT 16 |
| #define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV2_SHIFT))&ADC_CV_CV2_MASK) |
| /* OFS Bit Fields */ |
| #define ADC_OFS_OFS_MASK 0xFFFu |
| #define ADC_OFS_OFS_SHIFT 0 |
| #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) |
| #define ADC_OFS_SIGN_MASK 0x1000u |
| #define ADC_OFS_SIGN_SHIFT 12 |
| /* CAL Bit Fields */ |
| #define ADC_CAL_CAL_CODE_MASK 0xFu |
| #define ADC_CAL_CAL_CODE_SHIFT 0 |
| #define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CAL_CAL_CODE_SHIFT))&ADC_CAL_CAL_CODE_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group ADC_Register_Masks */ |
| |
| /* ADC - Peripheral instance base addresses */ |
| /** Peripheral ADC1 base address */ |
| #define ADC1_BASE (0x42280000u) |
| /** Peripheral ADC1 base pointer */ |
| #define ADC1 ((ADC_Type *)ADC1_BASE) |
| #define ADC1_BASE_PTR (ADC1) |
| /** Peripheral ADC2 base address */ |
| #define ADC2_BASE (0x42284000u) |
| /** Peripheral ADC2 base pointer */ |
| #define ADC2 ((ADC_Type *)ADC2_BASE) |
| #define ADC2_BASE_PTR (ADC2) |
| /** Array initializer of ADC peripheral base addresses */ |
| #define ADC_BASE_ADDRS { ADC1_BASE, ADC2_BASE } |
| /** Array initializer of ADC peripheral base pointers */ |
| #define ADC_BASE_PTRS { ADC1, ADC2 } |
| /** Interrupt vectors for the ADC peripheral type */ |
| #define ADC_IRQS { ADC1_IRQn, ADC2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ADC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ADC - Register instance definitions */ |
| /* ADC1 */ |
| #define ADC1_HC0 ADC_HC0_REG(ADC1_BASE_PTR) |
| #define ADC1_HC1 ADC_HC1_REG(ADC1_BASE_PTR) |
| #define ADC1_HS ADC_HS_REG(ADC1_BASE_PTR) |
| #define ADC1_R0 ADC_R0_REG(ADC1_BASE_PTR) |
| #define ADC1_R1 ADC_R1_REG(ADC1_BASE_PTR) |
| #define ADC1_CFG ADC_CFG_REG(ADC1_BASE_PTR) |
| #define ADC1_GC ADC_GC_REG(ADC1_BASE_PTR) |
| #define ADC1_GS ADC_GS_REG(ADC1_BASE_PTR) |
| #define ADC1_CV ADC_CV_REG(ADC1_BASE_PTR) |
| #define ADC1_OFS ADC_OFS_REG(ADC1_BASE_PTR) |
| #define ADC1_CAL ADC_CAL_REG(ADC1_BASE_PTR) |
| /* ADC2 */ |
| #define ADC2_HC0 ADC_HC0_REG(ADC2_BASE_PTR) |
| #define ADC2_HC1 ADC_HC1_REG(ADC2_BASE_PTR) |
| #define ADC2_HS ADC_HS_REG(ADC2_BASE_PTR) |
| #define ADC2_R0 ADC_R0_REG(ADC2_BASE_PTR) |
| #define ADC2_R1 ADC_R1_REG(ADC2_BASE_PTR) |
| #define ADC2_CFG ADC_CFG_REG(ADC2_BASE_PTR) |
| #define ADC2_GC ADC_GC_REG(ADC2_BASE_PTR) |
| #define ADC2_GS ADC_GS_REG(ADC2_BASE_PTR) |
| #define ADC2_CV ADC_CV_REG(ADC2_BASE_PTR) |
| #define ADC2_OFS ADC_OFS_REG(ADC2_BASE_PTR) |
| #define ADC2_CAL ADC_CAL_REG(ADC2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group ADC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ADC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- AFE Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AFE_Peripheral_Access_Layer AFE Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** AFE - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t BLOCK_ID; /**< , offset: 0x0 */ |
| __IO uint32_t PDBUF; /**< Power Down Buffers, offset: 0x4 */ |
| __IO uint32_t SWRST; /**< Software Reset, offset: 0x8 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t BGREG; /**< Band Gap, offset: 0x18 */ |
| uint8_t RESERVED_1[996]; |
| __IO uint32_t ACCESSAR_ID; /**< Accessar ID, offset: 0x400 */ |
| __IO uint32_t PDADC; /**< Power Down ADC, offset: 0x404 */ |
| __IO uint32_t PDSARH; /**< Power Down SAR High, offset: 0x408 */ |
| __IO uint32_t PDSARL; /**< Power Down SAR Low, offset: 0x40C */ |
| __IO uint32_t PDADCRFH; /**< Power Down ADC Ref. High, offset: 0x410 */ |
| __IO uint32_t PDADCRFL; /**< Power Down ADC Ref. Low, offset: 0x414 */ |
| uint8_t RESERVED_2[4]; |
| __IO uint32_t ADCGN; /**< ADC Gain, offset: 0x41C */ |
| uint8_t RESERVED_3[20]; |
| __IO uint32_t REFTRIML; /**< ADC Ref Trim Low, offset: 0x434 */ |
| __IO uint32_t REFTRIMH; /**< ADC Ref Trim High, offset: 0x438 */ |
| uint8_t RESERVED_4[16]; |
| __IO uint32_t DACAMP; /**< Clamp DAC Trim, offset: 0x44C */ |
| uint8_t RESERVED_5[4]; |
| __IO uint32_t CLMPDAT; /**< Clamp DAC Data, offset: 0x454 */ |
| __IO uint32_t CLMPAMP; /**< Clamp DAC Control, offset: 0x458 */ |
| __IO uint32_t CLAMP; /**< Clamp Control, offset: 0x45C */ |
| __IO uint32_t INPBUF; /**< Input Buffer, offset: 0x460 */ |
| __IO uint32_t INPFLT; /**< Analog Input Filter, offset: 0x464 */ |
| __IO uint32_t ADCDGN; /**< ADC Digital Gain, offset: 0x468 */ |
| __IO uint32_t OFFDRV; /**< Off-Chip Drive, offset: 0x46C */ |
| __IO uint32_t INPCONFIG; /**< VADC INPUT CONFIG, offset: 0x470 */ |
| __IO uint32_t PROGDELAY; /**< VADC PROG DELAY, offset: 0x474 */ |
| __IO uint32_t ADCOMT; /**< ADC COMPARATOR TIMING, offset: 0x478 */ |
| __IO uint32_t ALGDELAY; /**< ALGORITHM DELAY, offset: 0x47C */ |
| uint8_t RESERVED_6[896]; |
| __I uint32_t ACC_ID; /**< Acc ID, offset: 0x800 */ |
| __IO uint32_t ACCSTA; /**< ACC STATUS, offset: 0x804 */ |
| __IO uint32_t ACCNOSLI; /**< ACC NUMBER OF SLICE, offset: 0x808 */ |
| __IO uint32_t ACCCALCON; /**< ACC CALIBRATE CONTROL, offset: 0x80C */ |
| __IO uint32_t BWEWRICTRL; /**< ACC BWE WRITE CONTROL, offset: 0x810 */ |
| __IO uint32_t SELSLI; /**< ACC SELECT SLICE, offset: 0x814 */ |
| __IO uint32_t SELBYT; /**< ACC SELECT BYTE, offset: 0x818 */ |
| uint8_t RESERVED_7[4]; |
| __IO uint32_t REDVAL; /**< ACC READ VALUE, offset: 0x820 */ |
| __IO uint32_t WRIBYT; /**< ACC WRITE BYTE, offset: 0x824 */ |
| } AFE_Type, *AFE_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- AFE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AFE_Register_Accessor_Macros AFE - Register accessor macros |
| * @{ |
| */ |
| |
| /* AFE - Register accessors */ |
| #define AFE_BLOCK_ID_REG(base) ((base)->BLOCK_ID) |
| #define AFE_PDBUF_REG(base) ((base)->PDBUF) |
| #define AFE_SWRST_REG(base) ((base)->SWRST) |
| #define AFE_BGREG_REG(base) ((base)->BGREG) |
| #define AFE_ACCESSAR_ID_REG(base) ((base)->ACCESSAR_ID) |
| #define AFE_PDADC_REG(base) ((base)->PDADC) |
| #define AFE_PDSARH_REG(base) ((base)->PDSARH) |
| #define AFE_PDSARL_REG(base) ((base)->PDSARL) |
| #define AFE_PDADCRFH_REG(base) ((base)->PDADCRFH) |
| #define AFE_PDADCRFL_REG(base) ((base)->PDADCRFL) |
| #define AFE_ADCGN_REG(base) ((base)->ADCGN) |
| #define AFE_REFTRIML_REG(base) ((base)->REFTRIML) |
| #define AFE_REFTRIMH_REG(base) ((base)->REFTRIMH) |
| #define AFE_DACAMP_REG(base) ((base)->DACAMP) |
| #define AFE_CLMPDAT_REG(base) ((base)->CLMPDAT) |
| #define AFE_CLMPAMP_REG(base) ((base)->CLMPAMP) |
| #define AFE_CLAMP_REG(base) ((base)->CLAMP) |
| #define AFE_INPBUF_REG(base) ((base)->INPBUF) |
| #define AFE_INPFLT_REG(base) ((base)->INPFLT) |
| #define AFE_ADCDGN_REG(base) ((base)->ADCDGN) |
| #define AFE_OFFDRV_REG(base) ((base)->OFFDRV) |
| #define AFE_INPCONFIG_REG(base) ((base)->INPCONFIG) |
| #define AFE_PROGDELAY_REG(base) ((base)->PROGDELAY) |
| #define AFE_ADCOMT_REG(base) ((base)->ADCOMT) |
| #define AFE_ALGDELAY_REG(base) ((base)->ALGDELAY) |
| #define AFE_ACC_ID_REG(base) ((base)->ACC_ID) |
| #define AFE_ACCSTA_REG(base) ((base)->ACCSTA) |
| #define AFE_ACCNOSLI_REG(base) ((base)->ACCNOSLI) |
| #define AFE_ACCCALCON_REG(base) ((base)->ACCCALCON) |
| #define AFE_BWEWRICTRL_REG(base) ((base)->BWEWRICTRL) |
| #define AFE_SELSLI_REG(base) ((base)->SELSLI) |
| #define AFE_SELBYT_REG(base) ((base)->SELBYT) |
| #define AFE_REDVAL_REG(base) ((base)->REDVAL) |
| #define AFE_WRIBYT_REG(base) ((base)->WRIBYT) |
| |
| /*! |
| * @} |
| */ /* end of group AFE_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- AFE Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AFE_Register_Masks AFE Register Masks |
| * @{ |
| */ |
| |
| /* BLOCK_ID Bit Fields */ |
| #define AFE_BLOCK_ID_BLOCK_ID_MASK 0xFFu |
| #define AFE_BLOCK_ID_BLOCK_ID_SHIFT 0 |
| #define AFE_BLOCK_ID_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x))<<AFE_BLOCK_ID_BLOCK_ID_SHIFT))&AFE_BLOCK_ID_BLOCK_ID_MASK) |
| /* PDBUF Bit Fields */ |
| #define AFE_PDBUF_ACAFE_PD_N_MASK 0x1u |
| #define AFE_PDBUF_ACAFE_PD_N_SHIFT 0 |
| #define AFE_PDBUF_BGR_BGR_PD_N_MASK 0x2u |
| #define AFE_PDBUF_BGR_BGR_PD_N_SHIFT 1 |
| #define AFE_PDBUF_BGR_PD_N_MASK 0x4u |
| #define AFE_PDBUF_BGR_PD_N_SHIFT 2 |
| #define AFE_PDBUF_TESTBUFFERS_PD_N_MASK 0x18u |
| #define AFE_PDBUF_TESTBUFFERS_PD_N_SHIFT 3 |
| #define AFE_PDBUF_TESTBUFFERS_PD_N(x) (((uint32_t)(((uint32_t)(x))<<AFE_PDBUF_TESTBUFFERS_PD_N_SHIFT))&AFE_PDBUF_TESTBUFFERS_PD_N_MASK) |
| /* SWRST Bit Fields */ |
| #define AFE_SWRST_SYSCLK_SW_RST_N_MASK 0x1u |
| #define AFE_SWRST_SYSCLK_SW_RST_N_SHIFT 0 |
| #define AFE_SWRST_ADC_PROC_CLK_SW_RST_N_MASK 0x2u |
| #define AFE_SWRST_ADC_PROC_CLK_SW_RST_N_SHIFT 1 |
| #define AFE_SWRST_ACAFE_SW_RST_N_MASK 0x4u |
| #define AFE_SWRST_ACAFE_SW_RST_N_SHIFT 2 |
| /* BGREG Bit Fields */ |
| #define AFE_BGREG_BGR_TRIMLEVEL_MASK 0xFu |
| #define AFE_BGREG_BGR_TRIMLEVEL_SHIFT 0 |
| #define AFE_BGREG_BGR_TRIMLEVEL(x) (((uint32_t)(((uint32_t)(x))<<AFE_BGREG_BGR_TRIMLEVEL_SHIFT))&AFE_BGREG_BGR_TRIMLEVEL_MASK) |
| #define AFE_BGREG_BGR_EN_EXT_CURRENT_MASK 0x10u |
| #define AFE_BGREG_BGR_EN_EXT_CURRENT_SHIFT 4 |
| /* ACCESSAR_ID Bit Fields */ |
| #define AFE_ACCESSAR_ID_ACCESSAR_ID_MASK 0xFFu |
| #define AFE_ACCESSAR_ID_ACCESSAR_ID_SHIFT 0 |
| #define AFE_ACCESSAR_ID_ACCESSAR_ID(x) (((uint32_t)(((uint32_t)(x))<<AFE_ACCESSAR_ID_ACCESSAR_ID_SHIFT))&AFE_ACCESSAR_ID_ACCESSAR_ID_MASK) |
| /* PDADC Bit Fields */ |
| #define AFE_PDADC_ACCESSAR_PD_N_MASK 0x1u |
| #define AFE_PDADC_ACCESSAR_PD_N_SHIFT 0 |
| #define AFE_PDADC_DLYLOOP_PD_N_MASK 0x2u |
| #define AFE_PDADC_DLYLOOP_PD_N_SHIFT 1 |
| #define AFE_PDADC_ADC_IREF_PD_N_MASK 0x4u |
| #define AFE_PDADC_ADC_IREF_PD_N_SHIFT 2 |
| #define AFE_PDADC_CLAMP_PD_N_MASK 0x8u |
| #define AFE_PDADC_CLAMP_PD_N_SHIFT 3 |
| /* PDSARH Bit Fields */ |
| #define AFE_PDSARH_ADC_PD_N_MASK 0x1u |
| #define AFE_PDSARH_ADC_PD_N_SHIFT 0 |
| /* PDSARL Bit Fields */ |
| #define AFE_PDSARL_ADC_PD_N_MASK 0xFFu |
| #define AFE_PDSARL_ADC_PD_N_SHIFT 0 |
| #define AFE_PDSARL_ADC_PD_N(x) (((uint32_t)(((uint32_t)(x))<<AFE_PDSARL_ADC_PD_N_SHIFT))&AFE_PDSARL_ADC_PD_N_MASK) |
| /* PDADCRFH Bit Fields */ |
| #define AFE_PDADCRFH_ADCREF_REFBUFSLICE_PD_N_MASK 0x1u |
| #define AFE_PDADCRFH_ADCREF_REFBUFSLICE_PD_N_SHIFT 0 |
| /* PDADCRFL Bit Fields */ |
| #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_MASK 0xFFu |
| #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_SHIFT 0 |
| #define AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N(x) (((uint32_t)(((uint32_t)(x))<<AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_SHIFT))&AFE_PDADCRFL_ADCREF_REFBUFSLICE_PD_N_MASK) |
| /* ADCGN Bit Fields */ |
| #define AFE_ADCGN_ADC_GAIN_MASK 0xFu |
| #define AFE_ADCGN_ADC_GAIN_SHIFT 0 |
| #define AFE_ADCGN_ADC_GAIN(x) (((uint32_t)(((uint32_t)(x))<<AFE_ADCGN_ADC_GAIN_SHIFT))&AFE_ADCGN_ADC_GAIN_MASK) |
| /* REFTRIML Bit Fields */ |
| #define AFE_REFTRIML_ADCREF_REFTRIM08_MASK 0x3u |
| #define AFE_REFTRIML_ADCREF_REFTRIM08_SHIFT 0 |
| #define AFE_REFTRIML_ADCREF_REFTRIM08(x) (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM08_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM08_MASK) |
| #define AFE_REFTRIML_ADCREF_REFTRIM04_MASK 0xCu |
| #define AFE_REFTRIML_ADCREF_REFTRIM04_SHIFT 2 |
| #define AFE_REFTRIML_ADCREF_REFTRIM04(x) (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM04_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM04_MASK) |
| #define AFE_REFTRIML_ADCREF_REFTRIM02_MASK 0x30u |
| #define AFE_REFTRIML_ADCREF_REFTRIM02_SHIFT 4 |
| #define AFE_REFTRIML_ADCREF_REFTRIM02(x) (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIM02_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIM02_MASK) |
| #define AFE_REFTRIML_ADCREF_REFTRIMOP_MASK 0xC0u |
| #define AFE_REFTRIML_ADCREF_REFTRIMOP_SHIFT 6 |
| #define AFE_REFTRIML_ADCREF_REFTRIMOP(x) (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIML_ADCREF_REFTRIMOP_SHIFT))&AFE_REFTRIML_ADCREF_REFTRIMOP_MASK) |
| /* REFTRIMH Bit Fields */ |
| #define AFE_REFTRIMH_ADCREF_REFTRIM_MASK 0xFu |
| #define AFE_REFTRIMH_ADCREF_REFTRIM_SHIFT 0 |
| #define AFE_REFTRIMH_ADCREF_REFTRIM(x) (((uint32_t)(((uint32_t)(x))<<AFE_REFTRIMH_ADCREF_REFTRIM_SHIFT))&AFE_REFTRIMH_ADCREF_REFTRIM_MASK) |
| /* DACAMP Bit Fields */ |
| #define AFE_DACAMP_CLAMPDAC_TRIM_MASK 0xFu |
| #define AFE_DACAMP_CLAMPDAC_TRIM_SHIFT 0 |
| #define AFE_DACAMP_CLAMPDAC_TRIM(x) (((uint32_t)(((uint32_t)(x))<<AFE_DACAMP_CLAMPDAC_TRIM_SHIFT))&AFE_DACAMP_CLAMPDAC_TRIM_MASK) |
| /* CLMPDAT Bit Fields */ |
| #define AFE_CLMPDAT_CLAMPDAC_DATA_MASK 0xFFu |
| #define AFE_CLMPDAT_CLAMPDAC_DATA_SHIFT 0 |
| #define AFE_CLMPDAT_CLAMPDAC_DATA(x) (((uint32_t)(((uint32_t)(x))<<AFE_CLMPDAT_CLAMPDAC_DATA_SHIFT))&AFE_CLMPDAT_CLAMPDAC_DATA_MASK) |
| /* CLMPAMP Bit Fields */ |
| #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_MASK 0x7u |
| #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_SHIFT 0 |
| #define AFE_CLMPAMP_CLAMP_DACDATA_EXTRA(x) (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_SHIFT))&AFE_CLMPAMP_CLAMP_DACDATA_EXTRA_MASK) |
| #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_MASK 0x18u |
| #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_SHIFT 3 |
| #define AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT(x) (((uint32_t)(((uint32_t)(x))<<AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_SHIFT))&AFE_CLMPAMP_CLAMP_DACDATA_WEIGHT_MASK) |
| #define AFE_CLMPAMP_CLAMP_UPDN_REG_OVERRIDE_MASK 0x20u |
| #define AFE_CLMPAMP_CLAMP_UPDN_REG_OVERRIDE_SHIFT 5 |
| #define AFE_CLMPAMP_CLAMP_CURRENT_REG_OVERRIDE_MASK 0x40u |
| #define AFE_CLMPAMP_CLAMP_CURRENT_REG_OVERRIDE_SHIFT 6 |
| /* CLAMP Bit Fields */ |
| #define AFE_CLAMP_NCLAMP_POWERSAVE_MASK 0x1u |
| #define AFE_CLAMP_NCLAMP_POWERSAVE_SHIFT 0 |
| #define AFE_CLAMP_CLAMP_VN_MASK 0x2u |
| #define AFE_CLAMP_CLAMP_VN_SHIFT 1 |
| #define AFE_CLAMP_CLAMP_IPEN_REG_MASK 0x4u |
| #define AFE_CLAMP_CLAMP_IPEN_REG_SHIFT 2 |
| #define AFE_CLAMP_CLAMP_INEN_REG_MASK 0x8u |
| #define AFE_CLAMP_CLAMP_INEN_REG_SHIFT 3 |
| #define AFE_CLAMP_CLAMP_LOWCURRMODE_MASK 0x10u |
| #define AFE_CLAMP_CLAMP_LOWCURRMODE_SHIFT 4 |
| #define AFE_CLAMP_DIV_PROC_CLK_MASK 0x20u |
| #define AFE_CLAMP_DIV_PROC_CLK_SHIFT 5 |
| #define AFE_CLAMP_CLAMP_UP_DOWN_POLARITY_MASK 0x40u |
| #define AFE_CLAMP_CLAMP_UP_DOWN_POLARITY_SHIFT 6 |
| #define AFE_CLAMP_CLAMP_PWN_MODE_MASK 0x80u |
| #define AFE_CLAMP_CLAMP_PWN_MODE_SHIFT 7 |
| /* INPBUF Bit Fields */ |
| #define AFE_INPBUF_BUFF_EN_RI_MASK 0x1u |
| #define AFE_INPBUF_BUFF_EN_RI_SHIFT 0 |
| #define AFE_INPBUF_BUFF_EN_DI_MASK 0x2u |
| #define AFE_INPBUF_BUFF_EN_DI_SHIFT 1 |
| #define AFE_INPBUF_BUFF_EN_CM_MASK 0x4u |
| #define AFE_INPBUF_BUFF_EN_CM_SHIFT 2 |
| #define AFE_INPBUF_MUX_BUFFER_BP_EN_MASK 0x8u |
| #define AFE_INPBUF_MUX_BUFFER_BP_EN_SHIFT 3 |
| #define AFE_INPBUF_MUX_BUFFER_15M_EN_MASK 0x10u |
| #define AFE_INPBUF_MUX_BUFFER_15M_EN_SHIFT 4 |
| #define AFE_INPBUF_MUX_CLAMPEN_MASK 0x20u |
| #define AFE_INPBUF_MUX_CLAMPEN_SHIFT 5 |
| /* INPFLT Bit Fields */ |
| #define AFE_INPFLT_MUX_PDCURRENTMIRROR_MASK 0x1u |
| #define AFE_INPFLT_MUX_PDCURRENTMIRROR_SHIFT 0 |
| #define AFE_INPFLT_MUX_FILTER_15M_EN_MASK 0x2u |
| #define AFE_INPFLT_MUX_FILTER_15M_EN_SHIFT 1 |
| #define AFE_INPFLT_MUX_FILTERBYPASS_MASK 0x4u |
| #define AFE_INPFLT_MUX_FILTERBYPASS_SHIFT 2 |
| /* ADCDGN Bit Fields */ |
| #define AFE_ADCDGN_ADC_DIGITAL_GAIN_MASK 0x3Fu |
| #define AFE_ADCDGN_ADC_DIGITAL_GAIN_SHIFT 0 |
| #define AFE_ADCDGN_ADC_DIGITAL_GAIN(x) (((uint32_t)(((uint32_t)(x))<<AFE_ADCDGN_ADC_DIGITAL_GAIN_SHIFT))&AFE_ADCDGN_ADC_DIGITAL_GAIN_MASK) |
| #define AFE_ADCDGN_ADC_DIGITAL_GAIN_BYPASS_MASK 0x40u |
| #define AFE_ADCDGN_ADC_DIGITAL_GAIN_BYPASS_SHIFT 6 |
| /* OFFDRV Bit Fields */ |
| #define AFE_OFFDRV_ENOFFCHIPDRIVE_MASK 0x3u |
| #define AFE_OFFDRV_ENOFFCHIPDRIVE_SHIFT 0 |
| #define AFE_OFFDRV_ENOFFCHIPDRIVE(x) (((uint32_t)(((uint32_t)(x))<<AFE_OFFDRV_ENOFFCHIPDRIVE_SHIFT))&AFE_OFFDRV_ENOFFCHIPDRIVE_MASK) |
| #define AFE_OFFDRV_SH_TRIM_MASK 0xCu |
| #define AFE_OFFDRV_SH_TRIM_SHIFT 2 |
| #define AFE_OFFDRV_SH_TRIM(x) (((uint32_t)(((uint32_t)(x))<<AFE_OFFDRV_SH_TRIM_SHIFT))&AFE_OFFDRV_SH_TRIM_MASK) |
| /* INPCONFIG Bit Fields */ |
| #define AFE_INPCONFIG_INPUT_PULLDOWN_EN_MASK 0xFu |
| #define AFE_INPCONFIG_INPUT_PULLDOWN_EN_SHIFT 0 |
| #define AFE_INPCONFIG_INPUT_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x))<<AFE_INPCONFIG_INPUT_PULLDOWN_EN_SHIFT))&AFE_INPCONFIG_INPUT_PULLDOWN_EN_MASK) |
| #define AFE_INPCONFIG_MUX_ENLF_MASK 0xF0u |
| #define AFE_INPCONFIG_MUX_ENLF_SHIFT 4 |
| #define AFE_INPCONFIG_MUX_ENLF(x) (((uint32_t)(((uint32_t)(x))<<AFE_INPCONFIG_MUX_ENLF_SHIFT))&AFE_INPCONFIG_MUX_ENLF_MASK) |
| /* PROGDELAY Bit Fields */ |
| #define AFE_PROGDELAY_PROG_DELAY_MASK 0xFFu |
| #define AFE_PROGDELAY_PROG_DELAY_SHIFT 0 |
| #define AFE_PROGDELAY_PROG_DELAY(x) (((uint32_t)(((uint32_t)(x))<<AFE_PROGDELAY_PROG_DELAY_SHIFT))&AFE_PROGDELAY_PROG_DELAY_MASK) |
| /* ADCOMT Bit Fields */ |
| #define AFE_ADCOMT_OVERRIDE_MASK 0x1u |
| #define AFE_ADCOMT_OVERRIDE_SHIFT 0 |
| #define AFE_ADCOMT_WAIT_TIME_MASK 0x3Eu |
| #define AFE_ADCOMT_WAIT_TIME_SHIFT 1 |
| #define AFE_ADCOMT_WAIT_TIME(x) (((uint32_t)(((uint32_t)(x))<<AFE_ADCOMT_WAIT_TIME_SHIFT))&AFE_ADCOMT_WAIT_TIME_MASK) |
| #define AFE_ADCOMT_MEASURE_TIMING_MASK 0xC0u |
| #define AFE_ADCOMT_MEASURE_TIMING_SHIFT 6 |
| #define AFE_ADCOMT_MEASURE_TIMING(x) (((uint32_t)(((uint32_t)(x))<<AFE_ADCOMT_MEASURE_TIMING_SHIFT))&AFE_ADCOMT_MEASURE_TIMING_MASK) |
| /* ALGDELAY Bit Fields */ |
| #define AFE_ALGDELAY_ALGORITHM_DELAY_MASK 0xFFu |
| #define AFE_ALGDELAY_ALGORITHM_DELAY_SHIFT 0 |
| #define AFE_ALGDELAY_ALGORITHM_DELAY(x) (((uint32_t)(((uint32_t)(x))<<AFE_ALGDELAY_ALGORITHM_DELAY_SHIFT))&AFE_ALGDELAY_ALGORITHM_DELAY_MASK) |
| /* ACC_ID Bit Fields */ |
| #define AFE_ACC_ID_BLOCK_ID_MASK 0xFFu |
| #define AFE_ACC_ID_BLOCK_ID_SHIFT 0 |
| #define AFE_ACC_ID_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x))<<AFE_ACC_ID_BLOCK_ID_SHIFT))&AFE_ACC_ID_BLOCK_ID_MASK) |
| /* ACCSTA Bit Fields */ |
| #define AFE_ACCSTA_STATUS_MASK 0x1Fu |
| #define AFE_ACCSTA_STATUS_SHIFT 0 |
| #define AFE_ACCSTA_STATUS(x) (((uint32_t)(((uint32_t)(x))<<AFE_ACCSTA_STATUS_SHIFT))&AFE_ACCSTA_STATUS_MASK) |
| /* ACCNOSLI Bit Fields */ |
| #define AFE_ACCNOSLI_NO_OF_SLICES_MASK 0x3Fu |
| #define AFE_ACCNOSLI_NO_OF_SLICES_SHIFT 0 |
| #define AFE_ACCNOSLI_NO_OF_SLICES(x) (((uint32_t)(((uint32_t)(x))<<AFE_ACCNOSLI_NO_OF_SLICES_SHIFT))&AFE_ACCNOSLI_NO_OF_SLICES_MASK) |
| /* ACCCALCON Bit Fields */ |
| #define AFE_ACCCALCON_CALIBRATE_START_MASK 0x1u |
| #define AFE_ACCCALCON_CALIBRATE_START_SHIFT 0 |
| #define AFE_ACCCALCON_BYPASS_MASK 0x2u |
| #define AFE_ACCCALCON_BYPASS_SHIFT 1 |
| #define AFE_ACCCALCON_BYPASS_CALIB_MASK 0x4u |
| #define AFE_ACCCALCON_BYPASS_CALIB_SHIFT 2 |
| #define AFE_ACCCALCON_OFFSET_COMP_EN_MASK 0x8u |
| #define AFE_ACCCALCON_OFFSET_COMP_EN_SHIFT 3 |
| #define AFE_ACCCALCON_ANA_OFFSET_COMP_EN_MASK 0x10u |
| #define AFE_ACCCALCON_ANA_OFFSET_COMP_EN_SHIFT 4 |
| /* BWEWRICTRL Bit Fields */ |
| #define AFE_BWEWRICTRL_BWE_CTRL_MASK 0x3u |
| #define AFE_BWEWRICTRL_BWE_CTRL_SHIFT 0 |
| #define AFE_BWEWRICTRL_BWE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<AFE_BWEWRICTRL_BWE_CTRL_SHIFT))&AFE_BWEWRICTRL_BWE_CTRL_MASK) |
| #define AFE_BWEWRICTRL_BWE_WRITE_CTRL_MASK 0x4u |
| #define AFE_BWEWRICTRL_BWE_WRITE_CTRL_SHIFT 2 |
| /* SELSLI Bit Fields */ |
| #define AFE_SELSLI_SELECT_SLICE_MASK 0xFFu |
| #define AFE_SELSLI_SELECT_SLICE_SHIFT 0 |
| #define AFE_SELSLI_SELECT_SLICE(x) (((uint32_t)(((uint32_t)(x))<<AFE_SELSLI_SELECT_SLICE_SHIFT))&AFE_SELSLI_SELECT_SLICE_MASK) |
| /* SELBYT Bit Fields */ |
| #define AFE_SELBYT_SELECT_BYTE_MASK 0xFFu |
| #define AFE_SELBYT_SELECT_BYTE_SHIFT 0 |
| #define AFE_SELBYT_SELECT_BYTE(x) (((uint32_t)(((uint32_t)(x))<<AFE_SELBYT_SELECT_BYTE_SHIFT))&AFE_SELBYT_SELECT_BYTE_MASK) |
| /* REDVAL Bit Fields */ |
| #define AFE_REDVAL_READ_VALUE_MASK 0xFFu |
| #define AFE_REDVAL_READ_VALUE_SHIFT 0 |
| #define AFE_REDVAL_READ_VALUE(x) (((uint32_t)(((uint32_t)(x))<<AFE_REDVAL_READ_VALUE_SHIFT))&AFE_REDVAL_READ_VALUE_MASK) |
| /* WRIBYT Bit Fields */ |
| #define AFE_WRIBYT_WRITE_BYTE_MASK 0xFFu |
| #define AFE_WRIBYT_WRITE_BYTE_SHIFT 0 |
| #define AFE_WRIBYT_WRITE_BYTE(x) (((uint32_t)(((uint32_t)(x))<<AFE_WRIBYT_WRITE_BYTE_SHIFT))&AFE_WRIBYT_WRITE_BYTE_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group AFE_Register_Masks */ |
| |
| /* AFE - Peripheral instance base addresses */ |
| /** Peripheral AFE base address */ |
| #define AFE_BASE (0x42228000u) |
| /** Peripheral AFE base pointer */ |
| #define AFE ((AFE_Type *)AFE_BASE) |
| #define AFE_BASE_PTR (AFE) |
| /** Array initializer of AFE peripheral base addresses */ |
| #define AFE_BASE_ADDRS { AFE_BASE } |
| /** Array initializer of AFE peripheral base pointers */ |
| #define AFE_BASE_PTRS { AFE } |
| |
| /* ---------------------------------------------------------------------------- |
| -- AFE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AFE_Register_Accessor_Macros AFE - Register accessor macros |
| * @{ |
| */ |
| |
| /* AFE - Register instance definitions */ |
| /* AFE */ |
| #define AFE_BLOCK_ID AFE_BLOCK_ID_REG(AFE_BASE_PTR) |
| #define AFE_PDBUF AFE_PDBUF_REG(AFE_BASE_PTR) |
| #define AFE_SWRST AFE_SWRST_REG(AFE_BASE_PTR) |
| #define AFE_BGREG AFE_BGREG_REG(AFE_BASE_PTR) |
| #define AFE_ACCESSAR_ID AFE_ACCESSAR_ID_REG(AFE_BASE_PTR) |
| #define AFE_PDADC AFE_PDADC_REG(AFE_BASE_PTR) |
| #define AFE_PDSARH AFE_PDSARH_REG(AFE_BASE_PTR) |
| #define AFE_PDSARL AFE_PDSARL_REG(AFE_BASE_PTR) |
| #define AFE_PDADCRFH AFE_PDADCRFH_REG(AFE_BASE_PTR) |
| #define AFE_PDADCRFL AFE_PDADCRFL_REG(AFE_BASE_PTR) |
| #define AFE_ADCGN AFE_ADCGN_REG(AFE_BASE_PTR) |
| #define AFE_REFTRIML AFE_REFTRIML_REG(AFE_BASE_PTR) |
| #define AFE_REFTRIMH AFE_REFTRIMH_REG(AFE_BASE_PTR) |
| #define AFE_DACAMP AFE_DACAMP_REG(AFE_BASE_PTR) |
| #define AFE_CLMPDAT AFE_CLMPDAT_REG(AFE_BASE_PTR) |
| #define AFE_CLMPAMP AFE_CLMPAMP_REG(AFE_BASE_PTR) |
| #define AFE_CLAMP AFE_CLAMP_REG(AFE_BASE_PTR) |
| #define AFE_INPBUF AFE_INPBUF_REG(AFE_BASE_PTR) |
| #define AFE_INPFLT AFE_INPFLT_REG(AFE_BASE_PTR) |
| #define AFE_ADCDGN AFE_ADCDGN_REG(AFE_BASE_PTR) |
| #define AFE_OFFDRV AFE_OFFDRV_REG(AFE_BASE_PTR) |
| #define AFE_INPCONFIG AFE_INPCONFIG_REG(AFE_BASE_PTR) |
| #define AFE_PROGDELAY AFE_PROGDELAY_REG(AFE_BASE_PTR) |
| #define AFE_ADCOMT AFE_ADCOMT_REG(AFE_BASE_PTR) |
| #define AFE_ALGDELAY AFE_ALGDELAY_REG(AFE_BASE_PTR) |
| #define AFE_ACC_ID AFE_ACC_ID_REG(AFE_BASE_PTR) |
| #define AFE_ACCSTA AFE_ACCSTA_REG(AFE_BASE_PTR) |
| #define AFE_ACCNOSLI AFE_ACCNOSLI_REG(AFE_BASE_PTR) |
| #define AFE_ACCCALCON AFE_ACCCALCON_REG(AFE_BASE_PTR) |
| #define AFE_BWEWRICTRL AFE_BWEWRICTRL_REG(AFE_BASE_PTR) |
| #define AFE_SELSLI AFE_SELSLI_REG(AFE_BASE_PTR) |
| #define AFE_SELBYT AFE_SELBYT_REG(AFE_BASE_PTR) |
| #define AFE_REDVAL AFE_REDVAL_REG(AFE_BASE_PTR) |
| #define AFE_WRIBYT AFE_WRIBYT_REG(AFE_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group AFE_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group AFE_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ASRC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ASRC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ |
| __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ |
| __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ |
| __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ |
| __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ |
| __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ |
| __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ |
| uint8_t RESERVED_1[28]; |
| __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ |
| __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ |
| uint8_t RESERVED_2[4]; |
| __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ |
| struct { /* offset: 0x60, array step: 0x-8 */ |
| __O uint32_t ASRDI; /**< ASRC Data Input Register for Pair , array offset: 0x60, array step: 0x-8 */ |
| __I uint32_t ASRDO; /**< ASRC Data Output Register for Pair , array offset: 0x64, array step: 0x-8 */ |
| } ASRD[3]; |
| uint8_t RESERVED_3[8]; |
| __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ |
| __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ |
| __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ |
| __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ |
| __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ |
| __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ |
| __IO uint32_t ASR76K; /**< ASRC 76kHz Period in terms of ASRC processing clock, offset: 0x98 */ |
| __IO uint32_t ASR56K; /**< ASRC 56kHz Period in terms of ASRC processing clock, offset: 0x9C */ |
| __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ |
| __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ |
| __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ |
| __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ |
| __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ |
| __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ |
| uint8_t RESERVED_4[8]; |
| __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x0 */ |
| } ASRC_Type, *ASRC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ASRC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ASRC_Register_Accessor_Macros ASRC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ASRC - Register accessors */ |
| #define ASRC_ASRCTR_REG(base) ((base)->ASRCTR) |
| #define ASRC_ASRIER_REG(base) ((base)->ASRIER) |
| #define ASRC_ASRCNCR_REG(base) ((base)->ASRCNCR) |
| #define ASRC_ASRCFG_REG(base) ((base)->ASRCFG) |
| #define ASRC_ASRCSR_REG(base) ((base)->ASRCSR) |
| #define ASRC_ASRCDR1_REG(base) ((base)->ASRCDR1) |
| #define ASRC_ASRCDR2_REG(base) ((base)->ASRCDR2) |
| #define ASRC_ASRSTR_REG(base) ((base)->ASRSTR) |
| #define ASRC_ASRPMn_REG(base,index) ((base)->ASRPMn[index]) |
| #define ASRC_ASRTFR1_REG(base) ((base)->ASRTFR1) |
| #define ASRC_ASRCCR_REG(base) ((base)->ASRCCR) |
| #define ASRC_ASRDI_REG(base,index) ((base)->ASRD[index].ASRDI) |
| #define ASRC_ASRDO_REG(base,index) ((base)->ASRD[index].ASRDO) |
| #define ASRC_ASRIDRHA_REG(base) ((base)->ASRIDRHA) |
| #define ASRC_ASRIDRLA_REG(base) ((base)->ASRIDRLA) |
| #define ASRC_ASRIDRHB_REG(base) ((base)->ASRIDRHB) |
| #define ASRC_ASRIDRLB_REG(base) ((base)->ASRIDRLB) |
| #define ASRC_ASRIDRHC_REG(base) ((base)->ASRIDRHC) |
| #define ASRC_ASRIDRLC_REG(base) ((base)->ASRIDRLC) |
| #define ASRC_ASR76K_REG(base) ((base)->ASR76K) |
| #define ASRC_ASR56K_REG(base) ((base)->ASR56K) |
| #define ASRC_ASRMCRA_REG(base) ((base)->ASRMCRA) |
| #define ASRC_ASRFSTA_REG(base) ((base)->ASRFSTA) |
| #define ASRC_ASRMCRB_REG(base) ((base)->ASRMCRB) |
| #define ASRC_ASRFSTB_REG(base) ((base)->ASRFSTB) |
| #define ASRC_ASRMCRC_REG(base) ((base)->ASRMCRC) |
| #define ASRC_ASRFSTC_REG(base) ((base)->ASRFSTC) |
| #define ASRC_ASRMCR1_REG(base,index) ((base)->ASRMCR1[index]) |
| |
| /*! |
| * @} |
| */ /* end of group ASRC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ASRC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ASRC_Register_Masks ASRC Register Masks |
| * @{ |
| */ |
| |
| /* ASRCTR Bit Fields */ |
| #define ASRC_ASRCTR_ASRCEN_MASK 0x1u |
| #define ASRC_ASRCTR_ASRCEN_SHIFT 0 |
| #define ASRC_ASRCTR_ASREA_MASK 0x2u |
| #define ASRC_ASRCTR_ASREA_SHIFT 1 |
| #define ASRC_ASRCTR_ASREB_MASK 0x4u |
| #define ASRC_ASRCTR_ASREB_SHIFT 2 |
| #define ASRC_ASRCTR_ASREC_MASK 0x8u |
| #define ASRC_ASRCTR_ASREC_SHIFT 3 |
| #define ASRC_ASRCTR_SRST_MASK 0x10u |
| #define ASRC_ASRCTR_SRST_SHIFT 4 |
| #define ASRC_ASRCTR_IDRA_MASK 0x2000u |
| #define ASRC_ASRCTR_IDRA_SHIFT 13 |
| #define ASRC_ASRCTR_USRA_MASK 0x4000u |
| #define ASRC_ASRCTR_USRA_SHIFT 14 |
| #define ASRC_ASRCTR_IDRB_MASK 0x8000u |
| #define ASRC_ASRCTR_IDRB_SHIFT 15 |
| #define ASRC_ASRCTR_USRB_MASK 0x10000u |
| #define ASRC_ASRCTR_USRB_SHIFT 16 |
| #define ASRC_ASRCTR_IDRC_MASK 0x20000u |
| #define ASRC_ASRCTR_IDRC_SHIFT 17 |
| #define ASRC_ASRCTR_USRC_MASK 0x40000u |
| #define ASRC_ASRCTR_USRC_SHIFT 18 |
| #define ASRC_ASRCTR_ATSA_MASK 0x100000u |
| #define ASRC_ASRCTR_ATSA_SHIFT 20 |
| #define ASRC_ASRCTR_ATSB_MASK 0x200000u |
| #define ASRC_ASRCTR_ATSB_SHIFT 21 |
| #define ASRC_ASRCTR_ATSC_MASK 0x400000u |
| #define ASRC_ASRCTR_ATSC_SHIFT 22 |
| /* ASRIER Bit Fields */ |
| #define ASRC_ASRIER_ADIEA_MASK 0x1u |
| #define ASRC_ASRIER_ADIEA_SHIFT 0 |
| #define ASRC_ASRIER_ADIEB_MASK 0x2u |
| #define ASRC_ASRIER_ADIEB_SHIFT 1 |
| #define ASRC_ASRIER_ADIEC_MASK 0x4u |
| #define ASRC_ASRIER_ADIEC_SHIFT 2 |
| #define ASRC_ASRIER_ADOEA_MASK 0x8u |
| #define ASRC_ASRIER_ADOEA_SHIFT 3 |
| #define ASRC_ASRIER_ADOEB_MASK 0x10u |
| #define ASRC_ASRIER_ADOEB_SHIFT 4 |
| #define ASRC_ASRIER_ADOEC_MASK 0x20u |
| #define ASRC_ASRIER_ADOEC_SHIFT 5 |
| #define ASRC_ASRIER_AOLIE_MASK 0x40u |
| #define ASRC_ASRIER_AOLIE_SHIFT 6 |
| #define ASRC_ASRIER_AFPWE_MASK 0x80u |
| #define ASRC_ASRIER_AFPWE_SHIFT 7 |
| /* ASRCNCR Bit Fields */ |
| #define ASRC_ASRCNCR_ANCA_MASK 0xFu |
| #define ASRC_ASRCNCR_ANCA_SHIFT 0 |
| #define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCA_SHIFT))&ASRC_ASRCNCR_ANCA_MASK) |
| #define ASRC_ASRCNCR_ANCB_MASK 0xF0u |
| #define ASRC_ASRCNCR_ANCB_SHIFT 4 |
| #define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCB_SHIFT))&ASRC_ASRCNCR_ANCB_MASK) |
| #define ASRC_ASRCNCR_ANCC_MASK 0xF00u |
| #define ASRC_ASRCNCR_ANCC_SHIFT 8 |
| #define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCNCR_ANCC_SHIFT))&ASRC_ASRCNCR_ANCC_MASK) |
| /* ASRCFG Bit Fields */ |
| #define ASRC_ASRCFG_PREMODA_MASK 0xC0u |
| #define ASRC_ASRCFG_PREMODA_SHIFT 6 |
| #define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODA_SHIFT))&ASRC_ASRCFG_PREMODA_MASK) |
| #define ASRC_ASRCFG_POSTMODA_MASK 0x300u |
| #define ASRC_ASRCFG_POSTMODA_SHIFT 8 |
| #define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODA_SHIFT))&ASRC_ASRCFG_POSTMODA_MASK) |
| #define ASRC_ASRCFG_PREMODB_MASK 0xC00u |
| #define ASRC_ASRCFG_PREMODB_SHIFT 10 |
| #define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODB_SHIFT))&ASRC_ASRCFG_PREMODB_MASK) |
| #define ASRC_ASRCFG_POSTMODB_MASK 0x3000u |
| #define ASRC_ASRCFG_POSTMODB_SHIFT 12 |
| #define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODB_SHIFT))&ASRC_ASRCFG_POSTMODB_MASK) |
| #define ASRC_ASRCFG_PREMODC_MASK 0xC000u |
| #define ASRC_ASRCFG_PREMODC_SHIFT 14 |
| #define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_PREMODC_SHIFT))&ASRC_ASRCFG_PREMODC_MASK) |
| #define ASRC_ASRCFG_POSTMODC_MASK 0x30000u |
| #define ASRC_ASRCFG_POSTMODC_SHIFT 16 |
| #define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCFG_POSTMODC_SHIFT))&ASRC_ASRCFG_POSTMODC_MASK) |
| #define ASRC_ASRCFG_NDPRA_MASK 0x40000u |
| #define ASRC_ASRCFG_NDPRA_SHIFT 18 |
| #define ASRC_ASRCFG_NDPRB_MASK 0x80000u |
| #define ASRC_ASRCFG_NDPRB_SHIFT 19 |
| #define ASRC_ASRCFG_NDPRC_MASK 0x100000u |
| #define ASRC_ASRCFG_NDPRC_SHIFT 20 |
| #define ASRC_ASRCFG_INIRQA_MASK 0x200000u |
| #define ASRC_ASRCFG_INIRQA_SHIFT 21 |
| #define ASRC_ASRCFG_INIRQB_MASK 0x400000u |
| #define ASRC_ASRCFG_INIRQB_SHIFT 22 |
| #define ASRC_ASRCFG_INIRQC_MASK 0x800000u |
| #define ASRC_ASRCFG_INIRQC_SHIFT 23 |
| /* ASRCSR Bit Fields */ |
| #define ASRC_ASRCSR_AICSA_MASK 0xFu |
| #define ASRC_ASRCSR_AICSA_SHIFT 0 |
| #define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSA_SHIFT))&ASRC_ASRCSR_AICSA_MASK) |
| #define ASRC_ASRCSR_AICSB_MASK 0xF0u |
| #define ASRC_ASRCSR_AICSB_SHIFT 4 |
| #define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSB_SHIFT))&ASRC_ASRCSR_AICSB_MASK) |
| #define ASRC_ASRCSR_AICSC_MASK 0xF00u |
| #define ASRC_ASRCSR_AICSC_SHIFT 8 |
| #define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AICSC_SHIFT))&ASRC_ASRCSR_AICSC_MASK) |
| #define ASRC_ASRCSR_AOCSA_MASK 0xF000u |
| #define ASRC_ASRCSR_AOCSA_SHIFT 12 |
| #define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSA_SHIFT))&ASRC_ASRCSR_AOCSA_MASK) |
| #define ASRC_ASRCSR_AOCSB_MASK 0xF0000u |
| #define ASRC_ASRCSR_AOCSB_SHIFT 16 |
| #define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSB_SHIFT))&ASRC_ASRCSR_AOCSB_MASK) |
| #define ASRC_ASRCSR_AOCSC_MASK 0xF00000u |
| #define ASRC_ASRCSR_AOCSC_SHIFT 20 |
| #define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCSR_AOCSC_SHIFT))&ASRC_ASRCSR_AOCSC_MASK) |
| /* ASRCDR1 Bit Fields */ |
| #define ASRC_ASRCDR1_AICPA_MASK 0x7u |
| #define ASRC_ASRCDR1_AICPA_SHIFT 0 |
| #define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPA_SHIFT))&ASRC_ASRCDR1_AICPA_MASK) |
| #define ASRC_ASRCDR1_AICDA_MASK 0x38u |
| #define ASRC_ASRCDR1_AICDA_SHIFT 3 |
| #define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDA_SHIFT))&ASRC_ASRCDR1_AICDA_MASK) |
| #define ASRC_ASRCDR1_AICPB_MASK 0x1C0u |
| #define ASRC_ASRCDR1_AICPB_SHIFT 6 |
| #define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICPB_SHIFT))&ASRC_ASRCDR1_AICPB_MASK) |
| #define ASRC_ASRCDR1_AICDB_MASK 0xE00u |
| #define ASRC_ASRCDR1_AICDB_SHIFT 9 |
| #define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AICDB_SHIFT))&ASRC_ASRCDR1_AICDB_MASK) |
| #define ASRC_ASRCDR1_AOCPA_MASK 0x7000u |
| #define ASRC_ASRCDR1_AOCPA_SHIFT 12 |
| #define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPA_SHIFT))&ASRC_ASRCDR1_AOCPA_MASK) |
| #define ASRC_ASRCDR1_AOCDA_MASK 0x38000u |
| #define ASRC_ASRCDR1_AOCDA_SHIFT 15 |
| #define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDA_SHIFT))&ASRC_ASRCDR1_AOCDA_MASK) |
| #define ASRC_ASRCDR1_AOCPB_MASK 0x1C0000u |
| #define ASRC_ASRCDR1_AOCPB_SHIFT 18 |
| #define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCPB_SHIFT))&ASRC_ASRCDR1_AOCPB_MASK) |
| #define ASRC_ASRCDR1_AOCDB_MASK 0xE00000u |
| #define ASRC_ASRCDR1_AOCDB_SHIFT 21 |
| #define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR1_AOCDB_SHIFT))&ASRC_ASRCDR1_AOCDB_MASK) |
| /* ASRCDR2 Bit Fields */ |
| #define ASRC_ASRCDR2_AICPC_MASK 0x7u |
| #define ASRC_ASRCDR2_AICPC_SHIFT 0 |
| #define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICPC_SHIFT))&ASRC_ASRCDR2_AICPC_MASK) |
| #define ASRC_ASRCDR2_AICDC_MASK 0x38u |
| #define ASRC_ASRCDR2_AICDC_SHIFT 3 |
| #define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AICDC_SHIFT))&ASRC_ASRCDR2_AICDC_MASK) |
| #define ASRC_ASRCDR2_AOCPC_MASK 0x1C0u |
| #define ASRC_ASRCDR2_AOCPC_SHIFT 6 |
| #define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCPC_SHIFT))&ASRC_ASRCDR2_AOCPC_MASK) |
| #define ASRC_ASRCDR2_AOCDC_MASK 0xE00u |
| #define ASRC_ASRCDR2_AOCDC_SHIFT 9 |
| #define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCDR2_AOCDC_SHIFT))&ASRC_ASRCDR2_AOCDC_MASK) |
| /* ASRSTR Bit Fields */ |
| #define ASRC_ASRSTR_AIDEA_MASK 0x1u |
| #define ASRC_ASRSTR_AIDEA_SHIFT 0 |
| #define ASRC_ASRSTR_AIDEB_MASK 0x2u |
| #define ASRC_ASRSTR_AIDEB_SHIFT 1 |
| #define ASRC_ASRSTR_AIDEC_MASK 0x4u |
| #define ASRC_ASRSTR_AIDEC_SHIFT 2 |
| #define ASRC_ASRSTR_AODFA_MASK 0x8u |
| #define ASRC_ASRSTR_AODFA_SHIFT 3 |
| #define ASRC_ASRSTR_AODFB_MASK 0x10u |
| #define ASRC_ASRSTR_AODFB_SHIFT 4 |
| #define ASRC_ASRSTR_AODFC_MASK 0x20u |
| #define ASRC_ASRSTR_AODFC_SHIFT 5 |
| #define ASRC_ASRSTR_AOLE_MASK 0x40u |
| #define ASRC_ASRSTR_AOLE_SHIFT 6 |
| #define ASRC_ASRSTR_FPWT_MASK 0x80u |
| #define ASRC_ASRSTR_FPWT_SHIFT 7 |
| #define ASRC_ASRSTR_AIDUA_MASK 0x100u |
| #define ASRC_ASRSTR_AIDUA_SHIFT 8 |
| #define ASRC_ASRSTR_AIDUB_MASK 0x200u |
| #define ASRC_ASRSTR_AIDUB_SHIFT 9 |
| #define ASRC_ASRSTR_AIDUC_MASK 0x400u |
| #define ASRC_ASRSTR_AIDUC_SHIFT 10 |
| #define ASRC_ASRSTR_AODOA_MASK 0x800u |
| #define ASRC_ASRSTR_AODOA_SHIFT 11 |
| #define ASRC_ASRSTR_AODOB_MASK 0x1000u |
| #define ASRC_ASRSTR_AODOB_SHIFT 12 |
| #define ASRC_ASRSTR_AODOC_MASK 0x2000u |
| #define ASRC_ASRSTR_AODOC_SHIFT 13 |
| #define ASRC_ASRSTR_AIOLA_MASK 0x4000u |
| #define ASRC_ASRSTR_AIOLA_SHIFT 14 |
| #define ASRC_ASRSTR_AIOLB_MASK 0x8000u |
| #define ASRC_ASRSTR_AIOLB_SHIFT 15 |
| #define ASRC_ASRSTR_AIOLC_MASK 0x10000u |
| #define ASRC_ASRSTR_AIOLC_SHIFT 16 |
| #define ASRC_ASRSTR_AOOLA_MASK 0x20000u |
| #define ASRC_ASRSTR_AOOLA_SHIFT 17 |
| #define ASRC_ASRSTR_AOOLB_MASK 0x40000u |
| #define ASRC_ASRSTR_AOOLB_SHIFT 18 |
| #define ASRC_ASRSTR_AOOLC_MASK 0x80000u |
| #define ASRC_ASRSTR_AOOLC_SHIFT 19 |
| #define ASRC_ASRSTR_ATQOL_MASK 0x100000u |
| #define ASRC_ASRSTR_ATQOL_SHIFT 20 |
| #define ASRC_ASRSTR_DSLCNT_MASK 0x200000u |
| #define ASRC_ASRSTR_DSLCNT_SHIFT 21 |
| /* ASRPMn Bit Fields */ |
| #define ASRC_ASRPMn_PARAMETER_VALUE_MASK 0xFFFFFFu |
| #define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT 0 |
| #define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRPMn_PARAMETER_VALUE_SHIFT))&ASRC_ASRPMn_PARAMETER_VALUE_MASK) |
| /* ASRTFR1 Bit Fields */ |
| #define ASRC_ASRTFR1_TF_BASE_MASK 0x1FC0u |
| #define ASRC_ASRTFR1_TF_BASE_SHIFT 6 |
| #define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_BASE_SHIFT))&ASRC_ASRTFR1_TF_BASE_MASK) |
| #define ASRC_ASRTFR1_TF_FILL_MASK 0xFE000u |
| #define ASRC_ASRTFR1_TF_FILL_SHIFT 13 |
| #define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRTFR1_TF_FILL_SHIFT))&ASRC_ASRTFR1_TF_FILL_MASK) |
| /* ASRCCR Bit Fields */ |
| #define ASRC_ASRCCR_ACIA_MASK 0xFu |
| #define ASRC_ASRCCR_ACIA_SHIFT 0 |
| #define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIA_SHIFT))&ASRC_ASRCCR_ACIA_MASK) |
| #define ASRC_ASRCCR_ACIB_MASK 0xF0u |
| #define ASRC_ASRCCR_ACIB_SHIFT 4 |
| #define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIB_SHIFT))&ASRC_ASRCCR_ACIB_MASK) |
| #define ASRC_ASRCCR_ACIC_MASK 0xF00u |
| #define ASRC_ASRCCR_ACIC_SHIFT 8 |
| #define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACIC_SHIFT))&ASRC_ASRCCR_ACIC_MASK) |
| #define ASRC_ASRCCR_ACOA_MASK 0xF000u |
| #define ASRC_ASRCCR_ACOA_SHIFT 12 |
| #define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOA_SHIFT))&ASRC_ASRCCR_ACOA_MASK) |
| #define ASRC_ASRCCR_ACOB_MASK 0xF0000u |
| #define ASRC_ASRCCR_ACOB_SHIFT 16 |
| #define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOB_SHIFT))&ASRC_ASRCCR_ACOB_MASK) |
| #define ASRC_ASRCCR_ACOC_MASK 0xF00000u |
| #define ASRC_ASRCCR_ACOC_SHIFT 20 |
| #define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRCCR_ACOC_SHIFT))&ASRC_ASRCCR_ACOC_MASK) |
| /* ASRDI Bit Fields */ |
| #define ASRC_ASRDI_DATA_MASK 0xFFFFFFu |
| #define ASRC_ASRDI_DATA_SHIFT 0 |
| #define ASRC_ASRDI_DATA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDI_DATA_SHIFT))&ASRC_ASRDI_DATA_MASK) |
| /* ASRDO Bit Fields */ |
| #define ASRC_ASRDO_DATA_MASK 0xFFFFFFu |
| #define ASRC_ASRDO_DATA_SHIFT 0 |
| #define ASRC_ASRDO_DATA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRDO_DATA_SHIFT))&ASRC_ASRDO_DATA_MASK) |
| /* ASRIDRHA Bit Fields */ |
| #define ASRC_ASRIDRHA_IDRATIOA_MASK 0xFFu |
| #define ASRC_ASRIDRHA_IDRATIOA_SHIFT 0 |
| #define ASRC_ASRIDRHA_IDRATIOA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHA_IDRATIOA_SHIFT))&ASRC_ASRIDRHA_IDRATIOA_MASK) |
| /* ASRIDRLA Bit Fields */ |
| #define ASRC_ASRIDRLA_IDRATIOA_MASK 0xFFFFFFu |
| #define ASRC_ASRIDRLA_IDRATIOA_SHIFT 0 |
| #define ASRC_ASRIDRLA_IDRATIOA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLA_IDRATIOA_SHIFT))&ASRC_ASRIDRLA_IDRATIOA_MASK) |
| /* ASRIDRHB Bit Fields */ |
| #define ASRC_ASRIDRHB_IDRATIOB_MASK 0xFFu |
| #define ASRC_ASRIDRHB_IDRATIOB_SHIFT 0 |
| #define ASRC_ASRIDRHB_IDRATIOB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHB_IDRATIOB_SHIFT))&ASRC_ASRIDRHB_IDRATIOB_MASK) |
| /* ASRIDRLB Bit Fields */ |
| #define ASRC_ASRIDRLB_IDRATIOB_MASK 0xFFFFFFu |
| #define ASRC_ASRIDRLB_IDRATIOB_SHIFT 0 |
| #define ASRC_ASRIDRLB_IDRATIOB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLB_IDRATIOB_SHIFT))&ASRC_ASRIDRLB_IDRATIOB_MASK) |
| /* ASRIDRHC Bit Fields */ |
| #define ASRC_ASRIDRHC_IDRATIOC_MASK 0xFFu |
| #define ASRC_ASRIDRHC_IDRATIOC_SHIFT 0 |
| #define ASRC_ASRIDRHC_IDRATIOC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRHC_IDRATIOC_SHIFT))&ASRC_ASRIDRHC_IDRATIOC_MASK) |
| /* ASRIDRLC Bit Fields */ |
| #define ASRC_ASRIDRLC_IDRATIOC_MASK 0xFFFFFFu |
| #define ASRC_ASRIDRLC_IDRATIOC_SHIFT 0 |
| #define ASRC_ASRIDRLC_IDRATIOC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRIDRLC_IDRATIOC_SHIFT))&ASRC_ASRIDRLC_IDRATIOC_MASK) |
| /* ASR76K Bit Fields */ |
| #define ASRC_ASR76K_ASR76K_MASK 0x1FFFFu |
| #define ASRC_ASR76K_ASR76K_SHIFT 0 |
| #define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASR76K_ASR76K_SHIFT))&ASRC_ASR76K_ASR76K_MASK) |
| /* ASR56K Bit Fields */ |
| #define ASRC_ASR56K_ASR56K_MASK 0x1FFFFu |
| #define ASRC_ASR56K_ASR56K_SHIFT 0 |
| #define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASR56K_ASR56K_SHIFT))&ASRC_ASR56K_ASR56K_MASK) |
| /* ASRMCRA Bit Fields */ |
| #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK 0x3Fu |
| #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT 0 |
| #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) |
| #define ASRC_ASRMCRA_RSYNOFA_MASK 0x400u |
| #define ASRC_ASRMCRA_RSYNOFA_SHIFT 10 |
| #define ASRC_ASRMCRA_RSYNIFA_MASK 0x800u |
| #define ASRC_ASRMCRA_RSYNIFA_SHIFT 11 |
| #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK 0x3F000u |
| #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT 12 |
| #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT))&ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) |
| #define ASRC_ASRMCRA_BYPASSPOLYA_MASK 0x100000u |
| #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT 20 |
| #define ASRC_ASRMCRA_BUFSTALLA_MASK 0x200000u |
| #define ASRC_ASRMCRA_BUFSTALLA_SHIFT 21 |
| #define ASRC_ASRMCRA_EXTTHRSHA_MASK 0x400000u |
| #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT 22 |
| #define ASRC_ASRMCRA_ZEROBUFA_MASK 0x800000u |
| #define ASRC_ASRMCRA_ZEROBUFA_SHIFT 23 |
| /* ASRFSTA Bit Fields */ |
| #define ASRC_ASRFSTA_INFIFO_FILLA_MASK 0x7Fu |
| #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT 0 |
| #define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_INFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_INFIFO_FILLA_MASK) |
| #define ASRC_ASRFSTA_IAEA_MASK 0x800u |
| #define ASRC_ASRFSTA_IAEA_SHIFT 11 |
| #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK 0x7F000u |
| #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT 12 |
| #define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT))&ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) |
| #define ASRC_ASRFSTA_OAFA_MASK 0x800000u |
| #define ASRC_ASRFSTA_OAFA_SHIFT 23 |
| /* ASRMCRB Bit Fields */ |
| #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK 0x3Fu |
| #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT 0 |
| #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) |
| #define ASRC_ASRMCRB_RSYNOFB_MASK 0x400u |
| #define ASRC_ASRMCRB_RSYNOFB_SHIFT 10 |
| #define ASRC_ASRMCRB_RSYNIFB_MASK 0x800u |
| #define ASRC_ASRMCRB_RSYNIFB_SHIFT 11 |
| #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK 0x3F000u |
| #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT 12 |
| #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT))&ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) |
| #define ASRC_ASRMCRB_BYPASSPOLYB_MASK 0x100000u |
| #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT 20 |
| #define ASRC_ASRMCRB_BUFSTALLB_MASK 0x200000u |
| #define ASRC_ASRMCRB_BUFSTALLB_SHIFT 21 |
| #define ASRC_ASRMCRB_EXTTHRSHB_MASK 0x400000u |
| #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT 22 |
| #define ASRC_ASRMCRB_ZEROBUFB_MASK 0x800000u |
| #define ASRC_ASRMCRB_ZEROBUFB_SHIFT 23 |
| /* ASRFSTB Bit Fields */ |
| #define ASRC_ASRFSTB_INFIFO_FILLB_MASK 0x7Fu |
| #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT 0 |
| #define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_INFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_INFIFO_FILLB_MASK) |
| #define ASRC_ASRFSTB_IAEB_MASK 0x800u |
| #define ASRC_ASRFSTB_IAEB_SHIFT 11 |
| #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK 0x7F000u |
| #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT 12 |
| #define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT))&ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) |
| #define ASRC_ASRFSTB_OAFB_MASK 0x800000u |
| #define ASRC_ASRFSTB_OAFB_SHIFT 23 |
| /* ASRMCRC Bit Fields */ |
| #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK 0x3Fu |
| #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT 0 |
| #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) |
| #define ASRC_ASRMCRC_RSYNOFC_MASK 0x400u |
| #define ASRC_ASRMCRC_RSYNOFC_SHIFT 10 |
| #define ASRC_ASRMCRC_RSYNIFC_MASK 0x800u |
| #define ASRC_ASRMCRC_RSYNIFC_SHIFT 11 |
| #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK 0x3F000u |
| #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT 12 |
| #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT))&ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) |
| #define ASRC_ASRMCRC_BYPASSPOLYC_MASK 0x100000u |
| #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT 20 |
| #define ASRC_ASRMCRC_BUFSTALLC_MASK 0x200000u |
| #define ASRC_ASRMCRC_BUFSTALLC_SHIFT 21 |
| #define ASRC_ASRMCRC_EXTTHRSHC_MASK 0x400000u |
| #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT 22 |
| #define ASRC_ASRMCRC_ZEROBUFC_MASK 0x800000u |
| #define ASRC_ASRMCRC_ZEROBUFC_SHIFT 23 |
| /* ASRFSTC Bit Fields */ |
| #define ASRC_ASRFSTC_INFIFO_FILLC_MASK 0x7Fu |
| #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT 0 |
| #define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_INFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_INFIFO_FILLC_MASK) |
| #define ASRC_ASRFSTC_IAEC_MASK 0x800u |
| #define ASRC_ASRFSTC_IAEC_SHIFT 11 |
| #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK 0x7F000u |
| #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT 12 |
| #define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT))&ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) |
| #define ASRC_ASRFSTC_OAFC_MASK 0x800000u |
| #define ASRC_ASRFSTC_OAFC_SHIFT 23 |
| /* ASRMCR1 Bit Fields */ |
| #define ASRC_ASRMCR1_OW16_MASK 0x1u |
| #define ASRC_ASRMCR1_OW16_SHIFT 0 |
| #define ASRC_ASRMCR1_OSGN_MASK 0x2u |
| #define ASRC_ASRMCR1_OSGN_SHIFT 1 |
| #define ASRC_ASRMCR1_OMSB_MASK 0x4u |
| #define ASRC_ASRMCR1_OMSB_SHIFT 2 |
| #define ASRC_ASRMCR1_IMSB_MASK 0x100u |
| #define ASRC_ASRMCR1_IMSB_SHIFT 8 |
| #define ASRC_ASRMCR1_IWD_MASK 0xE00u |
| #define ASRC_ASRMCR1_IWD_SHIFT 9 |
| #define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x))<<ASRC_ASRMCR1_IWD_SHIFT))&ASRC_ASRMCR1_IWD_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group ASRC_Register_Masks */ |
| |
| /* ASRC - Peripheral instance base addresses */ |
| /** Peripheral ASRC base address */ |
| #define ASRC_BASE (0x42034000u) |
| /** Peripheral ASRC base pointer */ |
| #define ASRC ((ASRC_Type *)ASRC_BASE) |
| #define ASRC_BASE_PTR (ASRC) |
| /** Array initializer of ASRC peripheral base addresses */ |
| #define ASRC_BASE_ADDRS { ASRC_BASE } |
| /** Array initializer of ASRC peripheral base pointers */ |
| #define ASRC_BASE_PTRS { ASRC } |
| /** Interrupt vectors for the ASRC peripheral type */ |
| #define ASRC_IRQS { ASRC_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ASRC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ASRC_Register_Accessor_Macros ASRC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ASRC - Register instance definitions */ |
| /* ASRC */ |
| #define ASRC_ASRCTR ASRC_ASRCTR_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIER ASRC_ASRIER_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCNCR ASRC_ASRCNCR_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCFG ASRC_ASRCFG_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCSR ASRC_ASRCSR_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCDR1 ASRC_ASRCDR1_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCDR2 ASRC_ASRCDR2_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRSTR ASRC_ASRSTR_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRPMn1 ASRC_ASRPMn_REG(ASRC_BASE_PTR,0) |
| #define ASRC_ASRPMn2 ASRC_ASRPMn_REG(ASRC_BASE_PTR,1) |
| #define ASRC_ASRPMn3 ASRC_ASRPMn_REG(ASRC_BASE_PTR,2) |
| #define ASRC_ASRPMn4 ASRC_ASRPMn_REG(ASRC_BASE_PTR,3) |
| #define ASRC_ASRPMn5 ASRC_ASRPMn_REG(ASRC_BASE_PTR,4) |
| #define ASRC_ASRTFR1 ASRC_ASRTFR1_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRCCR ASRC_ASRCCR_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRDIA ASRC_ASRDI_REG(ASRC_BASE_PTR,0) |
| #define ASRC_ASRDOA ASRC_ASRDO_REG(ASRC_BASE_PTR,0) |
| #define ASRC_ASRDIB ASRC_ASRDI_REG(ASRC_BASE_PTR,1) |
| #define ASRC_ASRDOB ASRC_ASRDO_REG(ASRC_BASE_PTR,1) |
| #define ASRC_ASRDIC ASRC_ASRDI_REG(ASRC_BASE_PTR,2) |
| #define ASRC_ASRDOC ASRC_ASRDO_REG(ASRC_BASE_PTR,2) |
| #define ASRC_ASRIDRHA ASRC_ASRIDRHA_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIDRLA ASRC_ASRIDRLA_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIDRHB ASRC_ASRIDRHB_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIDRLB ASRC_ASRIDRLB_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIDRHC ASRC_ASRIDRHC_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRIDRLC ASRC_ASRIDRLC_REG(ASRC_BASE_PTR) |
| #define ASRC_ASR76K ASRC_ASR76K_REG(ASRC_BASE_PTR) |
| #define ASRC_ASR56K ASRC_ASR56K_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRMCRA ASRC_ASRMCRA_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRFSTA ASRC_ASRFSTA_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRMCRB ASRC_ASRMCRB_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRFSTB ASRC_ASRFSTB_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRMCRC ASRC_ASRMCRC_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRFSTC ASRC_ASRFSTC_REG(ASRC_BASE_PTR) |
| #define ASRC_ASRMCR1A ASRC_ASRMCR1_REG(ASRC_BASE_PTR,0) |
| #define ASRC_ASRMCR1B ASRC_ASRMCR1_REG(ASRC_BASE_PTR,1) |
| #define ASRC_ASRMCR1C ASRC_ASRMCR1_REG(ASRC_BASE_PTR,2) |
| /* ASRC - Register array accessors */ |
| #define ASRC_ASRPMn(index) ASRC_ASRPMn_REG(ASRC_BASE_PTR,index) |
| #define ASRC_ASRDI(index) ASRC_ASRDI_REG(ASRC_BASE_PTR,index) |
| #define ASRC_ASRDO(index) ASRC_ASRDO_REG(ASRC_BASE_PTR,index) |
| #define ASRC_ASRMCR1(index) ASRC_ASRMCR1_REG(ASRC_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group ASRC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ASRC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- AUDMUX Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AUDMUX_Peripheral_Access_Layer AUDMUX Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** AUDMUX - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PTCR1; /**< Port Timing Control Register 1, offset: 0x0 */ |
| __IO uint32_t PDCR1; /**< Port Data Control Register 1, offset: 0x4 */ |
| __IO uint32_t PTCR2; /**< Port Timing Control Register 2, offset: 0x8 */ |
| __IO uint32_t PDCR2; /**< Port Data Control Register 2, offset: 0xC */ |
| __IO uint32_t PTCR3; /**< Port Timing Control Register 3, offset: 0x10 */ |
| __IO uint32_t PDCR3; /**< Port Data Control Register 3, offset: 0x14 */ |
| __IO uint32_t PTCR4; /**< Port Timing Control Register 4, offset: 0x18 */ |
| __IO uint32_t PDCR4; /**< Port Data Control Register 4, offset: 0x1C */ |
| __IO uint32_t PTCR5; /**< Port Timing Control Register 5, offset: 0x20 */ |
| __IO uint32_t PDCR5; /**< Port Data Control Register 5, offset: 0x24 */ |
| __IO uint32_t PTCR6; /**< Port Timing Control Register 6, offset: 0x28 */ |
| __IO uint32_t PDCR6; /**< Port Data Control Register 6, offset: 0x2C */ |
| __IO uint32_t PTCR7; /**< Port Timing Control Register 7, offset: 0x30 */ |
| __IO uint32_t PDCR7; /**< Port Data Control Register 7, offset: 0x34 */ |
| } AUDMUX_Type, *AUDMUX_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- AUDMUX - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AUDMUX_Register_Accessor_Macros AUDMUX - Register accessor macros |
| * @{ |
| */ |
| |
| /* AUDMUX - Register accessors */ |
| #define AUDMUX_PTCR1_REG(base) ((base)->PTCR1) |
| #define AUDMUX_PDCR1_REG(base) ((base)->PDCR1) |
| #define AUDMUX_PTCR2_REG(base) ((base)->PTCR2) |
| #define AUDMUX_PDCR2_REG(base) ((base)->PDCR2) |
| #define AUDMUX_PTCR3_REG(base) ((base)->PTCR3) |
| #define AUDMUX_PDCR3_REG(base) ((base)->PDCR3) |
| #define AUDMUX_PTCR4_REG(base) ((base)->PTCR4) |
| #define AUDMUX_PDCR4_REG(base) ((base)->PDCR4) |
| #define AUDMUX_PTCR5_REG(base) ((base)->PTCR5) |
| #define AUDMUX_PDCR5_REG(base) ((base)->PDCR5) |
| #define AUDMUX_PTCR6_REG(base) ((base)->PTCR6) |
| #define AUDMUX_PDCR6_REG(base) ((base)->PDCR6) |
| #define AUDMUX_PTCR7_REG(base) ((base)->PTCR7) |
| #define AUDMUX_PDCR7_REG(base) ((base)->PDCR7) |
| |
| /*! |
| * @} |
| */ /* end of group AUDMUX_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- AUDMUX Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AUDMUX_Register_Masks AUDMUX Register Masks |
| * @{ |
| */ |
| |
| /* PTCR1 Bit Fields */ |
| #define AUDMUX_PTCR1_SYN_MASK 0x800u |
| #define AUDMUX_PTCR1_SYN_SHIFT 11 |
| #define AUDMUX_PTCR1_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR1_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR1_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_RCSEL_SHIFT))&AUDMUX_PTCR1_RCSEL_MASK) |
| #define AUDMUX_PTCR1_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR1_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR1_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR1_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR1_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_RFSEL_SHIFT))&AUDMUX_PTCR1_RFSEL_MASK) |
| #define AUDMUX_PTCR1_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR1_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR1_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR1_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR1_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_TCSEL_SHIFT))&AUDMUX_PTCR1_TCSEL_MASK) |
| #define AUDMUX_PTCR1_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR1_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR1_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR1_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR1_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR1_TFSEL_SHIFT))&AUDMUX_PTCR1_TFSEL_MASK) |
| #define AUDMUX_PTCR1_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR1_TFS_DIR_SHIFT 31 |
| /* PDCR1 Bit Fields */ |
| #define AUDMUX_PDCR1_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR1_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR1_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR1_INMMASK_SHIFT))&AUDMUX_PDCR1_INMMASK_MASK) |
| #define AUDMUX_PDCR1_MODE_MASK 0x100u |
| #define AUDMUX_PDCR1_MODE_SHIFT 8 |
| #define AUDMUX_PDCR1_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR1_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR1_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR1_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR1_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR1_RXDSEL_SHIFT))&AUDMUX_PDCR1_RXDSEL_MASK) |
| /* PTCR2 Bit Fields */ |
| #define AUDMUX_PTCR2_SYN_MASK 0x800u |
| #define AUDMUX_PTCR2_SYN_SHIFT 11 |
| #define AUDMUX_PTCR2_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR2_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR2_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_RCSEL_SHIFT))&AUDMUX_PTCR2_RCSEL_MASK) |
| #define AUDMUX_PTCR2_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR2_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR2_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR2_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR2_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_RFSEL_SHIFT))&AUDMUX_PTCR2_RFSEL_MASK) |
| #define AUDMUX_PTCR2_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR2_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR2_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR2_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR2_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_TCSEL_SHIFT))&AUDMUX_PTCR2_TCSEL_MASK) |
| #define AUDMUX_PTCR2_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR2_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR2_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR2_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR2_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR2_TFSEL_SHIFT))&AUDMUX_PTCR2_TFSEL_MASK) |
| #define AUDMUX_PTCR2_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR2_TFS_DIR_SHIFT 31 |
| /* PDCR2 Bit Fields */ |
| #define AUDMUX_PDCR2_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR2_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR2_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR2_INMMASK_SHIFT))&AUDMUX_PDCR2_INMMASK_MASK) |
| #define AUDMUX_PDCR2_MODE_MASK 0x100u |
| #define AUDMUX_PDCR2_MODE_SHIFT 8 |
| #define AUDMUX_PDCR2_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR2_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR2_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR2_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR2_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR2_RXDSEL_SHIFT))&AUDMUX_PDCR2_RXDSEL_MASK) |
| /* PTCR3 Bit Fields */ |
| #define AUDMUX_PTCR3_SYN_MASK 0x800u |
| #define AUDMUX_PTCR3_SYN_SHIFT 11 |
| #define AUDMUX_PTCR3_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR3_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR3_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_RCSEL_SHIFT))&AUDMUX_PTCR3_RCSEL_MASK) |
| #define AUDMUX_PTCR3_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR3_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR3_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR3_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR3_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_RFSEL_SHIFT))&AUDMUX_PTCR3_RFSEL_MASK) |
| #define AUDMUX_PTCR3_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR3_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR3_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR3_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR3_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_TCSEL_SHIFT))&AUDMUX_PTCR3_TCSEL_MASK) |
| #define AUDMUX_PTCR3_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR3_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR3_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR3_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR3_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR3_TFSEL_SHIFT))&AUDMUX_PTCR3_TFSEL_MASK) |
| #define AUDMUX_PTCR3_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR3_TFS_DIR_SHIFT 31 |
| /* PDCR3 Bit Fields */ |
| #define AUDMUX_PDCR3_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR3_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR3_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR3_INMMASK_SHIFT))&AUDMUX_PDCR3_INMMASK_MASK) |
| #define AUDMUX_PDCR3_MODE_MASK 0x100u |
| #define AUDMUX_PDCR3_MODE_SHIFT 8 |
| #define AUDMUX_PDCR3_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR3_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR3_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR3_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR3_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR3_RXDSEL_SHIFT))&AUDMUX_PDCR3_RXDSEL_MASK) |
| /* PTCR4 Bit Fields */ |
| #define AUDMUX_PTCR4_SYN_MASK 0x800u |
| #define AUDMUX_PTCR4_SYN_SHIFT 11 |
| #define AUDMUX_PTCR4_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR4_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR4_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_RCSEL_SHIFT))&AUDMUX_PTCR4_RCSEL_MASK) |
| #define AUDMUX_PTCR4_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR4_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR4_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR4_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR4_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_RFSEL_SHIFT))&AUDMUX_PTCR4_RFSEL_MASK) |
| #define AUDMUX_PTCR4_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR4_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR4_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR4_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR4_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_TCSEL_SHIFT))&AUDMUX_PTCR4_TCSEL_MASK) |
| #define AUDMUX_PTCR4_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR4_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR4_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR4_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR4_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR4_TFSEL_SHIFT))&AUDMUX_PTCR4_TFSEL_MASK) |
| #define AUDMUX_PTCR4_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR4_TFS_DIR_SHIFT 31 |
| /* PDCR4 Bit Fields */ |
| #define AUDMUX_PDCR4_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR4_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR4_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR4_INMMASK_SHIFT))&AUDMUX_PDCR4_INMMASK_MASK) |
| #define AUDMUX_PDCR4_MODE_MASK 0x100u |
| #define AUDMUX_PDCR4_MODE_SHIFT 8 |
| #define AUDMUX_PDCR4_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR4_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR4_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR4_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR4_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR4_RXDSEL_SHIFT))&AUDMUX_PDCR4_RXDSEL_MASK) |
| /* PTCR5 Bit Fields */ |
| #define AUDMUX_PTCR5_SYN_MASK 0x800u |
| #define AUDMUX_PTCR5_SYN_SHIFT 11 |
| #define AUDMUX_PTCR5_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR5_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR5_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_RCSEL_SHIFT))&AUDMUX_PTCR5_RCSEL_MASK) |
| #define AUDMUX_PTCR5_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR5_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR5_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR5_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR5_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_RFSEL_SHIFT))&AUDMUX_PTCR5_RFSEL_MASK) |
| #define AUDMUX_PTCR5_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR5_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR5_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR5_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR5_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_TCSEL_SHIFT))&AUDMUX_PTCR5_TCSEL_MASK) |
| #define AUDMUX_PTCR5_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR5_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR5_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR5_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR5_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR5_TFSEL_SHIFT))&AUDMUX_PTCR5_TFSEL_MASK) |
| #define AUDMUX_PTCR5_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR5_TFS_DIR_SHIFT 31 |
| /* PDCR5 Bit Fields */ |
| #define AUDMUX_PDCR5_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR5_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR5_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR5_INMMASK_SHIFT))&AUDMUX_PDCR5_INMMASK_MASK) |
| #define AUDMUX_PDCR5_MODE_MASK 0x100u |
| #define AUDMUX_PDCR5_MODE_SHIFT 8 |
| #define AUDMUX_PDCR5_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR5_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR5_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR5_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR5_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR5_RXDSEL_SHIFT))&AUDMUX_PDCR5_RXDSEL_MASK) |
| /* PTCR6 Bit Fields */ |
| #define AUDMUX_PTCR6_SYN_MASK 0x800u |
| #define AUDMUX_PTCR6_SYN_SHIFT 11 |
| #define AUDMUX_PTCR6_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR6_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR6_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_RCSEL_SHIFT))&AUDMUX_PTCR6_RCSEL_MASK) |
| #define AUDMUX_PTCR6_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR6_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR6_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR6_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR6_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_RFSEL_SHIFT))&AUDMUX_PTCR6_RFSEL_MASK) |
| #define AUDMUX_PTCR6_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR6_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR6_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR6_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR6_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_TCSEL_SHIFT))&AUDMUX_PTCR6_TCSEL_MASK) |
| #define AUDMUX_PTCR6_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR6_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR6_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR6_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR6_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR6_TFSEL_SHIFT))&AUDMUX_PTCR6_TFSEL_MASK) |
| #define AUDMUX_PTCR6_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR6_TFS_DIR_SHIFT 31 |
| /* PDCR6 Bit Fields */ |
| #define AUDMUX_PDCR6_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR6_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR6_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR6_INMMASK_SHIFT))&AUDMUX_PDCR6_INMMASK_MASK) |
| #define AUDMUX_PDCR6_MODE_MASK 0x100u |
| #define AUDMUX_PDCR6_MODE_SHIFT 8 |
| #define AUDMUX_PDCR6_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR6_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR6_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR6_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR6_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR6_RXDSEL_SHIFT))&AUDMUX_PDCR6_RXDSEL_MASK) |
| /* PTCR7 Bit Fields */ |
| #define AUDMUX_PTCR7_SYN_MASK 0x800u |
| #define AUDMUX_PTCR7_SYN_SHIFT 11 |
| #define AUDMUX_PTCR7_RCSEL_MASK 0xF000u |
| #define AUDMUX_PTCR7_RCSEL_SHIFT 12 |
| #define AUDMUX_PTCR7_RCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_RCSEL_SHIFT))&AUDMUX_PTCR7_RCSEL_MASK) |
| #define AUDMUX_PTCR7_RCLKDIR_MASK 0x10000u |
| #define AUDMUX_PTCR7_RCLKDIR_SHIFT 16 |
| #define AUDMUX_PTCR7_RFSEL_MASK 0x1E0000u |
| #define AUDMUX_PTCR7_RFSEL_SHIFT 17 |
| #define AUDMUX_PTCR7_RFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_RFSEL_SHIFT))&AUDMUX_PTCR7_RFSEL_MASK) |
| #define AUDMUX_PTCR7_RFS_DIR_MASK 0x200000u |
| #define AUDMUX_PTCR7_RFS_DIR_SHIFT 21 |
| #define AUDMUX_PTCR7_TCSEL_MASK 0x3C00000u |
| #define AUDMUX_PTCR7_TCSEL_SHIFT 22 |
| #define AUDMUX_PTCR7_TCSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_TCSEL_SHIFT))&AUDMUX_PTCR7_TCSEL_MASK) |
| #define AUDMUX_PTCR7_TCLKDIR_MASK 0x4000000u |
| #define AUDMUX_PTCR7_TCLKDIR_SHIFT 26 |
| #define AUDMUX_PTCR7_TFSEL_MASK 0x78000000u |
| #define AUDMUX_PTCR7_TFSEL_SHIFT 27 |
| #define AUDMUX_PTCR7_TFSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PTCR7_TFSEL_SHIFT))&AUDMUX_PTCR7_TFSEL_MASK) |
| #define AUDMUX_PTCR7_TFS_DIR_MASK 0x80000000u |
| #define AUDMUX_PTCR7_TFS_DIR_SHIFT 31 |
| /* PDCR7 Bit Fields */ |
| #define AUDMUX_PDCR7_INMMASK_MASK 0xFFu |
| #define AUDMUX_PDCR7_INMMASK_SHIFT 0 |
| #define AUDMUX_PDCR7_INMMASK(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR7_INMMASK_SHIFT))&AUDMUX_PDCR7_INMMASK_MASK) |
| #define AUDMUX_PDCR7_MODE_MASK 0x100u |
| #define AUDMUX_PDCR7_MODE_SHIFT 8 |
| #define AUDMUX_PDCR7_TXRXEN_MASK 0x1000u |
| #define AUDMUX_PDCR7_TXRXEN_SHIFT 12 |
| #define AUDMUX_PDCR7_RXDSEL_MASK 0xE000u |
| #define AUDMUX_PDCR7_RXDSEL_SHIFT 13 |
| #define AUDMUX_PDCR7_RXDSEL(x) (((uint32_t)(((uint32_t)(x))<<AUDMUX_PDCR7_RXDSEL_SHIFT))&AUDMUX_PDCR7_RXDSEL_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group AUDMUX_Register_Masks */ |
| |
| /* AUDMUX - Peripheral instance base addresses */ |
| /** Peripheral AUDMUX base address */ |
| #define AUDMUX_BASE (0x421D8000u) |
| /** Peripheral AUDMUX base pointer */ |
| #define AUDMUX ((AUDMUX_Type *)AUDMUX_BASE) |
| #define AUDMUX_BASE_PTR (AUDMUX) |
| /** Array initializer of AUDMUX peripheral base addresses */ |
| #define AUDMUX_BASE_ADDRS { AUDMUX_BASE } |
| /** Array initializer of AUDMUX peripheral base pointers */ |
| #define AUDMUX_BASE_PTRS { AUDMUX } |
| |
| /* ---------------------------------------------------------------------------- |
| -- AUDMUX - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup AUDMUX_Register_Accessor_Macros AUDMUX - Register accessor macros |
| * @{ |
| */ |
| |
| /* AUDMUX - Register instance definitions */ |
| /* AUDMUX */ |
| #define AUDMUX_PTCR1 AUDMUX_PTCR1_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR1 AUDMUX_PDCR1_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR2 AUDMUX_PTCR2_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR2 AUDMUX_PDCR2_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR3 AUDMUX_PTCR3_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR3 AUDMUX_PDCR3_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR4 AUDMUX_PTCR4_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR4 AUDMUX_PDCR4_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR5 AUDMUX_PTCR5_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR5 AUDMUX_PDCR5_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR6 AUDMUX_PTCR6_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR6 AUDMUX_PDCR6_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PTCR7 AUDMUX_PTCR7_REG(AUDMUX_BASE_PTR) |
| #define AUDMUX_PDCR7 AUDMUX_PDCR7_REG(AUDMUX_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group AUDMUX_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group AUDMUX_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** BCH - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ |
| __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ |
| __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ |
| __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ |
| __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ |
| __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ |
| __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ |
| __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ |
| __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ |
| __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ |
| __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ |
| __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ |
| __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ |
| __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ |
| __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ |
| __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ |
| __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ |
| __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ |
| __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ |
| __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ |
| __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ |
| uint8_t RESERVED_0[16]; |
| __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ |
| __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ |
| __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ |
| __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ |
| __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ |
| __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ |
| __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ |
| __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ |
| __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ |
| __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ |
| __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ |
| __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ |
| __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ |
| __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ |
| __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ |
| __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ |
| __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ |
| __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ |
| __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ |
| __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ |
| __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ |
| __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ |
| __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ |
| __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ |
| __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ |
| __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ |
| __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ |
| __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ |
| __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ |
| __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ |
| __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ |
| __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ |
| __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ |
| __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ |
| __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ |
| __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ |
| __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ |
| __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ |
| __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ |
| __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ |
| __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ |
| __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ |
| __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ |
| __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ |
| __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ |
| __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ |
| __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ |
| __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ |
| __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ |
| __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ |
| __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ |
| __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ |
| __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ |
| __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ |
| __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ |
| __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ |
| __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ |
| __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ |
| __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ |
| __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ |
| __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ |
| __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ |
| __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ |
| __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ |
| __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1 , offset: 0x170 */ |
| __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1 , offset: 0x174 */ |
| __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1 , offset: 0x178 */ |
| __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1 , offset: 0x17C */ |
| } BCH_Type, *BCH_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros |
| * @{ |
| */ |
| |
| /* BCH - Register accessors */ |
| #define BCH_CTRL_REG(base) ((base)->CTRL) |
| #define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) |
| #define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) |
| #define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) |
| #define BCH_STATUS0_REG(base) ((base)->STATUS0) |
| #define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) |
| #define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) |
| #define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) |
| #define BCH_MODE_REG(base) ((base)->MODE) |
| #define BCH_MODE_SET_REG(base) ((base)->MODE_SET) |
| #define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) |
| #define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) |
| #define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) |
| #define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) |
| #define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) |
| #define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) |
| #define BCH_DATAPTR_REG(base) ((base)->DATAPTR) |
| #define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) |
| #define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) |
| #define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) |
| #define BCH_METAPTR_REG(base) ((base)->METAPTR) |
| #define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) |
| #define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) |
| #define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) |
| #define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) |
| #define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) |
| #define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) |
| #define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) |
| #define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) |
| #define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) |
| #define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) |
| #define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) |
| #define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) |
| #define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) |
| #define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) |
| #define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) |
| #define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) |
| #define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) |
| #define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) |
| #define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) |
| #define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) |
| #define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) |
| #define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) |
| #define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) |
| #define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) |
| #define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) |
| #define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) |
| #define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) |
| #define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) |
| #define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) |
| #define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) |
| #define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) |
| #define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) |
| #define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) |
| #define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) |
| #define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) |
| #define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) |
| #define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) |
| #define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) |
| #define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) |
| #define BCH_DEBUG0_REG(base) ((base)->DEBUG0) |
| #define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) |
| #define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) |
| #define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) |
| #define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) |
| #define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) |
| #define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) |
| #define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) |
| #define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) |
| #define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) |
| #define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) |
| #define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) |
| #define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) |
| #define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) |
| #define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) |
| #define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) |
| #define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) |
| #define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) |
| #define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) |
| #define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) |
| #define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) |
| #define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) |
| #define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) |
| #define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) |
| #define BCH_VERSION_REG(base) ((base)->VERSION) |
| #define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) |
| #define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) |
| #define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) |
| #define BCH_DEBUG1_REG(base) ((base)->DEBUG1) |
| #define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) |
| #define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) |
| #define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Register_Masks BCH Register Masks |
| * @{ |
| */ |
| |
| /* CTRL Bit Fields */ |
| #define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u |
| #define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 |
| #define BCH_CTRL_RSVD0_MASK 0x2u |
| #define BCH_CTRL_RSVD0_SHIFT 1 |
| #define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u |
| #define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 |
| #define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u |
| #define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 |
| #define BCH_CTRL_RSVD1_MASK 0xF0u |
| #define BCH_CTRL_RSVD1_SHIFT 4 |
| #define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD1_SHIFT))&BCH_CTRL_RSVD1_MASK) |
| #define BCH_CTRL_COMPLETE_IRQ_EN_MASK 0x100u |
| #define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT 8 |
| #define BCH_CTRL_RSVD2_MASK 0x200u |
| #define BCH_CTRL_RSVD2_SHIFT 9 |
| #define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK 0x400u |
| #define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT 10 |
| #define BCH_CTRL_RSVD3_MASK 0xF800u |
| #define BCH_CTRL_RSVD3_SHIFT 11 |
| #define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD3_SHIFT))&BCH_CTRL_RSVD3_MASK) |
| #define BCH_CTRL_M2M_ENABLE_MASK 0x10000u |
| #define BCH_CTRL_M2M_ENABLE_SHIFT 16 |
| #define BCH_CTRL_M2M_ENCODE_MASK 0x20000u |
| #define BCH_CTRL_M2M_ENCODE_SHIFT 17 |
| #define BCH_CTRL_M2M_LAYOUT_MASK 0xC0000u |
| #define BCH_CTRL_M2M_LAYOUT_SHIFT 18 |
| #define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_M2M_LAYOUT_SHIFT))&BCH_CTRL_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_RSVD4_MASK 0x300000u |
| #define BCH_CTRL_RSVD4_SHIFT 20 |
| #define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD4_SHIFT))&BCH_CTRL_RSVD4_MASK) |
| #define BCH_CTRL_DEBUGSYNDROME_MASK 0x400000u |
| #define BCH_CTRL_DEBUGSYNDROME_SHIFT 22 |
| #define BCH_CTRL_RSVD5_MASK 0x3F800000u |
| #define BCH_CTRL_RSVD5_SHIFT 23 |
| #define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD5_SHIFT))&BCH_CTRL_RSVD5_MASK) |
| #define BCH_CTRL_CLKGATE_MASK 0x40000000u |
| #define BCH_CTRL_CLKGATE_SHIFT 30 |
| #define BCH_CTRL_SFTRST_MASK 0x80000000u |
| #define BCH_CTRL_SFTRST_SHIFT 31 |
| /* CTRL_SET Bit Fields */ |
| #define BCH_CTRL_SET_COMPLETE_IRQ_MASK 0x1u |
| #define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT 0 |
| #define BCH_CTRL_SET_RSVD0_MASK 0x2u |
| #define BCH_CTRL_SET_RSVD0_SHIFT 1 |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK 0x4u |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT 2 |
| #define BCH_CTRL_SET_BM_ERROR_IRQ_MASK 0x8u |
| #define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT 3 |
| #define BCH_CTRL_SET_RSVD1_MASK 0xF0u |
| #define BCH_CTRL_SET_RSVD1_SHIFT 4 |
| #define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD1_SHIFT))&BCH_CTRL_SET_RSVD1_MASK) |
| #define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK 0x100u |
| #define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT 8 |
| #define BCH_CTRL_SET_RSVD2_MASK 0x200u |
| #define BCH_CTRL_SET_RSVD2_SHIFT 9 |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK 0x400u |
| #define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT 10 |
| #define BCH_CTRL_SET_RSVD3_MASK 0xF800u |
| #define BCH_CTRL_SET_RSVD3_SHIFT 11 |
| #define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD3_SHIFT))&BCH_CTRL_SET_RSVD3_MASK) |
| #define BCH_CTRL_SET_M2M_ENABLE_MASK 0x10000u |
| #define BCH_CTRL_SET_M2M_ENABLE_SHIFT 16 |
| #define BCH_CTRL_SET_M2M_ENCODE_MASK 0x20000u |
| #define BCH_CTRL_SET_M2M_ENCODE_SHIFT 17 |
| #define BCH_CTRL_SET_M2M_LAYOUT_MASK 0xC0000u |
| #define BCH_CTRL_SET_M2M_LAYOUT_SHIFT 18 |
| #define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_M2M_LAYOUT_SHIFT))&BCH_CTRL_SET_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_SET_RSVD4_MASK 0x300000u |
| #define BCH_CTRL_SET_RSVD4_SHIFT 20 |
| #define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD4_SHIFT))&BCH_CTRL_SET_RSVD4_MASK) |
| #define BCH_CTRL_SET_DEBUGSYNDROME_MASK 0x400000u |
| #define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT 22 |
| #define BCH_CTRL_SET_RSVD5_MASK 0x3F800000u |
| #define BCH_CTRL_SET_RSVD5_SHIFT 23 |
| #define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD5_SHIFT))&BCH_CTRL_SET_RSVD5_MASK) |
| #define BCH_CTRL_SET_CLKGATE_MASK 0x40000000u |
| #define BCH_CTRL_SET_CLKGATE_SHIFT 30 |
| #define BCH_CTRL_SET_SFTRST_MASK 0x80000000u |
| #define BCH_CTRL_SET_SFTRST_SHIFT 31 |
| /* CTRL_CLR Bit Fields */ |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_MASK 0x1u |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT 0 |
| #define BCH_CTRL_CLR_RSVD0_MASK 0x2u |
| #define BCH_CTRL_CLR_RSVD0_SHIFT 1 |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK 0x4u |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT 2 |
| #define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK 0x8u |
| #define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT 3 |
| #define BCH_CTRL_CLR_RSVD1_MASK 0xF0u |
| #define BCH_CTRL_CLR_RSVD1_SHIFT 4 |
| #define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD1_SHIFT))&BCH_CTRL_CLR_RSVD1_MASK) |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK 0x100u |
| #define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT 8 |
| #define BCH_CTRL_CLR_RSVD2_MASK 0x200u |
| #define BCH_CTRL_CLR_RSVD2_SHIFT 9 |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK 0x400u |
| #define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT 10 |
| #define BCH_CTRL_CLR_RSVD3_MASK 0xF800u |
| #define BCH_CTRL_CLR_RSVD3_SHIFT 11 |
| #define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD3_SHIFT))&BCH_CTRL_CLR_RSVD3_MASK) |
| #define BCH_CTRL_CLR_M2M_ENABLE_MASK 0x10000u |
| #define BCH_CTRL_CLR_M2M_ENABLE_SHIFT 16 |
| #define BCH_CTRL_CLR_M2M_ENCODE_MASK 0x20000u |
| #define BCH_CTRL_CLR_M2M_ENCODE_SHIFT 17 |
| #define BCH_CTRL_CLR_M2M_LAYOUT_MASK 0xC0000u |
| #define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT 18 |
| #define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_M2M_LAYOUT_SHIFT))&BCH_CTRL_CLR_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_CLR_RSVD4_MASK 0x300000u |
| #define BCH_CTRL_CLR_RSVD4_SHIFT 20 |
| #define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD4_SHIFT))&BCH_CTRL_CLR_RSVD4_MASK) |
| #define BCH_CTRL_CLR_DEBUGSYNDROME_MASK 0x400000u |
| #define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT 22 |
| #define BCH_CTRL_CLR_RSVD5_MASK 0x3F800000u |
| #define BCH_CTRL_CLR_RSVD5_SHIFT 23 |
| #define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD5_SHIFT))&BCH_CTRL_CLR_RSVD5_MASK) |
| #define BCH_CTRL_CLR_CLKGATE_MASK 0x40000000u |
| #define BCH_CTRL_CLR_CLKGATE_SHIFT 30 |
| #define BCH_CTRL_CLR_SFTRST_MASK 0x80000000u |
| #define BCH_CTRL_CLR_SFTRST_SHIFT 31 |
| /* CTRL_TOG Bit Fields */ |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_MASK 0x1u |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT 0 |
| #define BCH_CTRL_TOG_RSVD0_MASK 0x2u |
| #define BCH_CTRL_TOG_RSVD0_SHIFT 1 |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK 0x4u |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT 2 |
| #define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK 0x8u |
| #define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT 3 |
| #define BCH_CTRL_TOG_RSVD1_MASK 0xF0u |
| #define BCH_CTRL_TOG_RSVD1_SHIFT 4 |
| #define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD1_SHIFT))&BCH_CTRL_TOG_RSVD1_MASK) |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK 0x100u |
| #define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT 8 |
| #define BCH_CTRL_TOG_RSVD2_MASK 0x200u |
| #define BCH_CTRL_TOG_RSVD2_SHIFT 9 |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK 0x400u |
| #define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT 10 |
| #define BCH_CTRL_TOG_RSVD3_MASK 0xF800u |
| #define BCH_CTRL_TOG_RSVD3_SHIFT 11 |
| #define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD3_SHIFT))&BCH_CTRL_TOG_RSVD3_MASK) |
| #define BCH_CTRL_TOG_M2M_ENABLE_MASK 0x10000u |
| #define BCH_CTRL_TOG_M2M_ENABLE_SHIFT 16 |
| #define BCH_CTRL_TOG_M2M_ENCODE_MASK 0x20000u |
| #define BCH_CTRL_TOG_M2M_ENCODE_SHIFT 17 |
| #define BCH_CTRL_TOG_M2M_LAYOUT_MASK 0xC0000u |
| #define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT 18 |
| #define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_M2M_LAYOUT_SHIFT))&BCH_CTRL_TOG_M2M_LAYOUT_MASK) |
| #define BCH_CTRL_TOG_RSVD4_MASK 0x300000u |
| #define BCH_CTRL_TOG_RSVD4_SHIFT 20 |
| #define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD4_SHIFT))&BCH_CTRL_TOG_RSVD4_MASK) |
| #define BCH_CTRL_TOG_DEBUGSYNDROME_MASK 0x400000u |
| #define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT 22 |
| #define BCH_CTRL_TOG_RSVD5_MASK 0x3F800000u |
| #define BCH_CTRL_TOG_RSVD5_SHIFT 23 |
| #define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD5_SHIFT))&BCH_CTRL_TOG_RSVD5_MASK) |
| #define BCH_CTRL_TOG_CLKGATE_MASK 0x40000000u |
| #define BCH_CTRL_TOG_CLKGATE_SHIFT 30 |
| #define BCH_CTRL_TOG_SFTRST_MASK 0x80000000u |
| #define BCH_CTRL_TOG_SFTRST_SHIFT 31 |
| /* STATUS0 Bit Fields */ |
| #define BCH_STATUS0_RSVD0_MASK 0x3u |
| #define BCH_STATUS0_RSVD0_SHIFT 0 |
| #define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD0_SHIFT))&BCH_STATUS0_RSVD0_MASK) |
| #define BCH_STATUS0_UNCORRECTABLE_MASK 0x4u |
| #define BCH_STATUS0_UNCORRECTABLE_SHIFT 2 |
| #define BCH_STATUS0_CORRECTED_MASK 0x8u |
| #define BCH_STATUS0_CORRECTED_SHIFT 3 |
| #define BCH_STATUS0_ALLONES_MASK 0x10u |
| #define BCH_STATUS0_ALLONES_SHIFT 4 |
| #define BCH_STATUS0_RSVD1_MASK 0xE0u |
| #define BCH_STATUS0_RSVD1_SHIFT 5 |
| #define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD1_SHIFT))&BCH_STATUS0_RSVD1_MASK) |
| #define BCH_STATUS0_STATUS_BLK0_MASK 0xFF00u |
| #define BCH_STATUS0_STATUS_BLK0_SHIFT 8 |
| #define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_STATUS_BLK0_SHIFT))&BCH_STATUS0_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_COMPLETED_CE_MASK 0xF0000u |
| #define BCH_STATUS0_COMPLETED_CE_SHIFT 16 |
| #define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_COMPLETED_CE_SHIFT))&BCH_STATUS0_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_HANDLE_MASK 0xFFF00000u |
| #define BCH_STATUS0_HANDLE_SHIFT 20 |
| #define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_HANDLE_SHIFT))&BCH_STATUS0_HANDLE_MASK) |
| /* STATUS0_SET Bit Fields */ |
| #define BCH_STATUS0_SET_RSVD0_MASK 0x3u |
| #define BCH_STATUS0_SET_RSVD0_SHIFT 0 |
| #define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD0_SHIFT))&BCH_STATUS0_SET_RSVD0_MASK) |
| #define BCH_STATUS0_SET_UNCORRECTABLE_MASK 0x4u |
| #define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT 2 |
| #define BCH_STATUS0_SET_CORRECTED_MASK 0x8u |
| #define BCH_STATUS0_SET_CORRECTED_SHIFT 3 |
| #define BCH_STATUS0_SET_ALLONES_MASK 0x10u |
| #define BCH_STATUS0_SET_ALLONES_SHIFT 4 |
| #define BCH_STATUS0_SET_RSVD1_MASK 0xE0u |
| #define BCH_STATUS0_SET_RSVD1_SHIFT 5 |
| #define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD1_SHIFT))&BCH_STATUS0_SET_RSVD1_MASK) |
| #define BCH_STATUS0_SET_STATUS_BLK0_MASK 0xFF00u |
| #define BCH_STATUS0_SET_STATUS_BLK0_SHIFT 8 |
| #define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_STATUS_BLK0_SHIFT))&BCH_STATUS0_SET_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_SET_COMPLETED_CE_MASK 0xF0000u |
| #define BCH_STATUS0_SET_COMPLETED_CE_SHIFT 16 |
| #define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_COMPLETED_CE_SHIFT))&BCH_STATUS0_SET_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_SET_HANDLE_MASK 0xFFF00000u |
| #define BCH_STATUS0_SET_HANDLE_SHIFT 20 |
| #define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_HANDLE_SHIFT))&BCH_STATUS0_SET_HANDLE_MASK) |
| /* STATUS0_CLR Bit Fields */ |
| #define BCH_STATUS0_CLR_RSVD0_MASK 0x3u |
| #define BCH_STATUS0_CLR_RSVD0_SHIFT 0 |
| #define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK) |
| #define BCH_STATUS0_CLR_UNCORRECTABLE_MASK 0x4u |
| #define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT 2 |
| #define BCH_STATUS0_CLR_CORRECTED_MASK 0x8u |
| #define BCH_STATUS0_CLR_CORRECTED_SHIFT 3 |
| #define BCH_STATUS0_CLR_ALLONES_MASK 0x10u |
| #define BCH_STATUS0_CLR_ALLONES_SHIFT 4 |
| #define BCH_STATUS0_CLR_RSVD1_MASK 0xE0u |
| #define BCH_STATUS0_CLR_RSVD1_SHIFT 5 |
| #define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD1_SHIFT))&BCH_STATUS0_CLR_RSVD1_MASK) |
| #define BCH_STATUS0_CLR_STATUS_BLK0_MASK 0xFF00u |
| #define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT 8 |
| #define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_STATUS_BLK0_SHIFT))&BCH_STATUS0_CLR_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_CLR_COMPLETED_CE_MASK 0xF0000u |
| #define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT 16 |
| #define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_COMPLETED_CE_SHIFT))&BCH_STATUS0_CLR_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_CLR_HANDLE_MASK 0xFFF00000u |
| #define BCH_STATUS0_CLR_HANDLE_SHIFT 20 |
| #define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_HANDLE_SHIFT))&BCH_STATUS0_CLR_HANDLE_MASK) |
| /* STATUS0_TOG Bit Fields */ |
| #define BCH_STATUS0_TOG_RSVD0_MASK 0x3u |
| #define BCH_STATUS0_TOG_RSVD0_SHIFT 0 |
| #define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD0_SHIFT))&BCH_STATUS0_TOG_RSVD0_MASK) |
| #define BCH_STATUS0_TOG_UNCORRECTABLE_MASK 0x4u |
| #define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT 2 |
| #define BCH_STATUS0_TOG_CORRECTED_MASK 0x8u |
| #define BCH_STATUS0_TOG_CORRECTED_SHIFT 3 |
| #define BCH_STATUS0_TOG_ALLONES_MASK 0x10u |
| #define BCH_STATUS0_TOG_ALLONES_SHIFT 4 |
| #define BCH_STATUS0_TOG_RSVD1_MASK 0xE0u |
| #define BCH_STATUS0_TOG_RSVD1_SHIFT 5 |
| #define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD1_SHIFT))&BCH_STATUS0_TOG_RSVD1_MASK) |
| #define BCH_STATUS0_TOG_STATUS_BLK0_MASK 0xFF00u |
| #define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT 8 |
| #define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_STATUS_BLK0_SHIFT))&BCH_STATUS0_TOG_STATUS_BLK0_MASK) |
| #define BCH_STATUS0_TOG_COMPLETED_CE_MASK 0xF0000u |
| #define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT 16 |
| #define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_COMPLETED_CE_SHIFT))&BCH_STATUS0_TOG_COMPLETED_CE_MASK) |
| #define BCH_STATUS0_TOG_HANDLE_MASK 0xFFF00000u |
| #define BCH_STATUS0_TOG_HANDLE_SHIFT 20 |
| #define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_HANDLE_SHIFT))&BCH_STATUS0_TOG_HANDLE_MASK) |
| /* MODE Bit Fields */ |
| #define BCH_MODE_ERASE_THRESHOLD_MASK 0xFFu |
| #define BCH_MODE_ERASE_THRESHOLD_SHIFT 0 |
| #define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_ERASE_THRESHOLD_SHIFT))&BCH_MODE_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_RSVD_MASK 0xFFFFFF00u |
| #define BCH_MODE_RSVD_SHIFT 8 |
| #define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_RSVD_SHIFT))&BCH_MODE_RSVD_MASK) |
| /* MODE_SET Bit Fields */ |
| #define BCH_MODE_SET_ERASE_THRESHOLD_MASK 0xFFu |
| #define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT 0 |
| #define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_ERASE_THRESHOLD_SHIFT))&BCH_MODE_SET_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_SET_RSVD_MASK 0xFFFFFF00u |
| #define BCH_MODE_SET_RSVD_SHIFT 8 |
| #define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_RSVD_SHIFT))&BCH_MODE_SET_RSVD_MASK) |
| /* MODE_CLR Bit Fields */ |
| #define BCH_MODE_CLR_ERASE_THRESHOLD_MASK 0xFFu |
| #define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT 0 |
| #define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT))&BCH_MODE_CLR_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_CLR_RSVD_MASK 0xFFFFFF00u |
| #define BCH_MODE_CLR_RSVD_SHIFT 8 |
| #define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_RSVD_SHIFT))&BCH_MODE_CLR_RSVD_MASK) |
| /* MODE_TOG Bit Fields */ |
| #define BCH_MODE_TOG_ERASE_THRESHOLD_MASK 0xFFu |
| #define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT 0 |
| #define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT))&BCH_MODE_TOG_ERASE_THRESHOLD_MASK) |
| #define BCH_MODE_TOG_RSVD_MASK 0xFFFFFF00u |
| #define BCH_MODE_TOG_RSVD_SHIFT 8 |
| #define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_RSVD_SHIFT))&BCH_MODE_TOG_RSVD_MASK) |
| /* ENCODEPTR Bit Fields */ |
| #define BCH_ENCODEPTR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_ENCODEPTR_ADDR_SHIFT 0 |
| #define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_ADDR_SHIFT))&BCH_ENCODEPTR_ADDR_MASK) |
| /* ENCODEPTR_SET Bit Fields */ |
| #define BCH_ENCODEPTR_SET_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_ENCODEPTR_SET_ADDR_SHIFT 0 |
| #define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_SET_ADDR_SHIFT))&BCH_ENCODEPTR_SET_ADDR_MASK) |
| /* ENCODEPTR_CLR Bit Fields */ |
| #define BCH_ENCODEPTR_CLR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_ENCODEPTR_CLR_ADDR_SHIFT 0 |
| #define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_CLR_ADDR_SHIFT))&BCH_ENCODEPTR_CLR_ADDR_MASK) |
| /* ENCODEPTR_TOG Bit Fields */ |
| #define BCH_ENCODEPTR_TOG_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_ENCODEPTR_TOG_ADDR_SHIFT 0 |
| #define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_TOG_ADDR_SHIFT))&BCH_ENCODEPTR_TOG_ADDR_MASK) |
| /* DATAPTR Bit Fields */ |
| #define BCH_DATAPTR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_DATAPTR_ADDR_SHIFT 0 |
| #define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_ADDR_SHIFT))&BCH_DATAPTR_ADDR_MASK) |
| /* DATAPTR_SET Bit Fields */ |
| #define BCH_DATAPTR_SET_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_DATAPTR_SET_ADDR_SHIFT 0 |
| #define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_SET_ADDR_SHIFT))&BCH_DATAPTR_SET_ADDR_MASK) |
| /* DATAPTR_CLR Bit Fields */ |
| #define BCH_DATAPTR_CLR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_DATAPTR_CLR_ADDR_SHIFT 0 |
| #define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_CLR_ADDR_SHIFT))&BCH_DATAPTR_CLR_ADDR_MASK) |
| /* DATAPTR_TOG Bit Fields */ |
| #define BCH_DATAPTR_TOG_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_DATAPTR_TOG_ADDR_SHIFT 0 |
| #define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_TOG_ADDR_SHIFT))&BCH_DATAPTR_TOG_ADDR_MASK) |
| /* METAPTR Bit Fields */ |
| #define BCH_METAPTR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_METAPTR_ADDR_SHIFT 0 |
| #define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_ADDR_SHIFT))&BCH_METAPTR_ADDR_MASK) |
| /* METAPTR_SET Bit Fields */ |
| #define BCH_METAPTR_SET_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_METAPTR_SET_ADDR_SHIFT 0 |
| #define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_SET_ADDR_SHIFT))&BCH_METAPTR_SET_ADDR_MASK) |
| /* METAPTR_CLR Bit Fields */ |
| #define BCH_METAPTR_CLR_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_METAPTR_CLR_ADDR_SHIFT 0 |
| #define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_CLR_ADDR_SHIFT))&BCH_METAPTR_CLR_ADDR_MASK) |
| /* METAPTR_TOG Bit Fields */ |
| #define BCH_METAPTR_TOG_ADDR_MASK 0xFFFFFFFFu |
| #define BCH_METAPTR_TOG_ADDR_SHIFT 0 |
| #define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_TOG_ADDR_SHIFT))&BCH_METAPTR_TOG_ADDR_MASK) |
| /* LAYOUTSELECT Bit Fields */ |
| #define BCH_LAYOUTSELECT_CS0_SELECT_MASK 0x3u |
| #define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT 0 |
| #define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS1_SELECT_MASK 0xCu |
| #define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT 2 |
| #define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS2_SELECT_MASK 0x30u |
| #define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT 4 |
| #define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS3_SELECT_MASK 0xC0u |
| #define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT 6 |
| #define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS4_SELECT_MASK 0x300u |
| #define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT 8 |
| #define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS5_SELECT_MASK 0xC00u |
| #define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT 10 |
| #define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS6_SELECT_MASK 0x3000u |
| #define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT 12 |
| #define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS7_SELECT_MASK 0xC000u |
| #define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT 14 |
| #define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS8_SELECT_MASK 0x30000u |
| #define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT 16 |
| #define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS9_SELECT_MASK 0xC0000u |
| #define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT 18 |
| #define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS10_SELECT_MASK 0x300000u |
| #define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT 20 |
| #define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS11_SELECT_MASK 0xC00000u |
| #define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT 22 |
| #define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS12_SELECT_MASK 0x3000000u |
| #define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT 24 |
| #define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS13_SELECT_MASK 0xC000000u |
| #define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT 26 |
| #define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS14_SELECT_MASK 0x30000000u |
| #define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT 28 |
| #define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CS15_SELECT_MASK 0xC0000000u |
| #define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT 30 |
| #define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS15_SELECT_MASK) |
| /* LAYOUTSELECT_SET Bit Fields */ |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK 0x3u |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT 0 |
| #define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK 0xCu |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT 2 |
| #define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK 0x30u |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT 4 |
| #define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK 0xC0u |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT 6 |
| #define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK 0x300u |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT 8 |
| #define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK 0xC00u |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT 10 |
| #define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK 0x3000u |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT 12 |
| #define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK 0xC000u |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT 14 |
| #define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK 0x30000u |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT 16 |
| #define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK 0xC0000u |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT 18 |
| #define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK 0x300000u |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT 20 |
| #define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK 0xC00000u |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT 22 |
| #define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK 0x3000000u |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT 24 |
| #define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK 0xC000000u |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT 26 |
| #define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK 0x30000000u |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT 28 |
| #define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK 0xC0000000u |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT 30 |
| #define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) |
| /* LAYOUTSELECT_CLR Bit Fields */ |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK 0x3u |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT 0 |
| #define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK 0xCu |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT 2 |
| #define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK 0x30u |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT 4 |
| #define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK 0xC0u |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT 6 |
| #define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK 0x300u |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT 8 |
| #define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK 0xC00u |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT 10 |
| #define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK 0x3000u |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT 12 |
| #define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK 0xC000u |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT 14 |
| #define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK 0x30000u |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT 16 |
| #define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK 0xC0000u |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT 18 |
| #define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK 0x300000u |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT 20 |
| #define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK 0xC00000u |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT 22 |
| #define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK 0x3000000u |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT 24 |
| #define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK 0xC000000u |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT 26 |
| #define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK 0x30000000u |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT 28 |
| #define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK 0xC0000000u |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT 30 |
| #define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) |
| /* LAYOUTSELECT_TOG Bit Fields */ |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK 0x3u |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT 0 |
| #define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK 0xCu |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT 2 |
| #define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK 0x30u |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT 4 |
| #define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK 0xC0u |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT 6 |
| #define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK 0x300u |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT 8 |
| #define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK 0xC00u |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT 10 |
| #define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK 0x3000u |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT 12 |
| #define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK 0xC000u |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT 14 |
| #define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK 0x30000u |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT 16 |
| #define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK 0xC0000u |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT 18 |
| #define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK 0x300000u |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT 20 |
| #define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK 0xC00000u |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT 22 |
| #define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK 0x3000000u |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT 24 |
| #define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK 0xC000000u |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT 26 |
| #define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK 0x30000000u |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT 28 |
| #define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK 0xC0000000u |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT 30 |
| #define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) |
| /* FLASH0LAYOUT0 Bit Fields */ |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT0_ECC0_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT0_ECC0_SHIFT 11 |
| #define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_NBLOCKS_MASK) |
| /* FLASH0LAYOUT0_SET Bit Fields */ |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT0_SET_ECC0_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT 11 |
| #define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) |
| /* FLASH0LAYOUT0_CLR Bit Fields */ |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT 11 |
| #define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) |
| /* FLASH0LAYOUT0_TOG Bit Fields */ |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT 11 |
| #define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) |
| /* FLASH0LAYOUT1 Bit Fields */ |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT1_ECCN_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT1_ECCN_SHIFT 11 |
| #define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) |
| /* FLASH0LAYOUT1_SET Bit Fields */ |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT1_SET_ECCN_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT 11 |
| #define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) |
| /* FLASH0LAYOUT1_CLR Bit Fields */ |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT 11 |
| #define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /* FLASH0LAYOUT1_TOG Bit Fields */ |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK 0xF800u |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT 11 |
| #define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /* FLASH1LAYOUT0 Bit Fields */ |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT0_ECC0_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT0_ECC0_SHIFT 11 |
| #define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_NBLOCKS_MASK) |
| /* FLASH1LAYOUT0_SET Bit Fields */ |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT0_SET_ECC0_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT 11 |
| #define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) |
| /* FLASH1LAYOUT0_CLR Bit Fields */ |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT 11 |
| #define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) |
| /* FLASH1LAYOUT0_TOG Bit Fields */ |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT 11 |
| #define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) |
| /* FLASH1LAYOUT1 Bit Fields */ |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT1_ECCN_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT1_ECCN_SHIFT 11 |
| #define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) |
| /* FLASH1LAYOUT1_SET Bit Fields */ |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT1_SET_ECCN_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT 11 |
| #define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) |
| /* FLASH1LAYOUT1_CLR Bit Fields */ |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT 11 |
| #define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /* FLASH1LAYOUT1_TOG Bit Fields */ |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK 0xF800u |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT 11 |
| #define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /* FLASH2LAYOUT0 Bit Fields */ |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT0_ECC0_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT0_ECC0_SHIFT 11 |
| #define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_NBLOCKS_MASK) |
| /* FLASH2LAYOUT0_SET Bit Fields */ |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT0_SET_ECC0_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT 11 |
| #define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) |
| /* FLASH2LAYOUT0_CLR Bit Fields */ |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT 11 |
| #define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) |
| /* FLASH2LAYOUT0_TOG Bit Fields */ |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT 11 |
| #define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) |
| /* FLASH2LAYOUT1 Bit Fields */ |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT1_ECCN_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT1_ECCN_SHIFT 11 |
| #define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) |
| /* FLASH2LAYOUT1_SET Bit Fields */ |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT1_SET_ECCN_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT 11 |
| #define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) |
| /* FLASH2LAYOUT1_CLR Bit Fields */ |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT 11 |
| #define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /* FLASH2LAYOUT1_TOG Bit Fields */ |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK 0xF800u |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT 11 |
| #define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /* FLASH3LAYOUT0 Bit Fields */ |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT0_ECC0_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT0_ECC0_SHIFT 11 |
| #define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_NBLOCKS_MASK) |
| /* FLASH3LAYOUT0_SET Bit Fields */ |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT0_SET_ECC0_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT 11 |
| #define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_SET_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) |
| /* FLASH3LAYOUT0_CLR Bit Fields */ |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT 11 |
| #define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) |
| /* FLASH3LAYOUT0_TOG Bit Fields */ |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT 11 |
| #define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT 24 |
| #define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) |
| /* FLASH3LAYOUT1 Bit Fields */ |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT1_ECCN_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT1_ECCN_SHIFT 11 |
| #define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) |
| /* FLASH3LAYOUT1_SET Bit Fields */ |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT1_SET_ECCN_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT 11 |
| #define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_SET_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) |
| /* FLASH3LAYOUT1_CLR Bit Fields */ |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT 11 |
| #define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) |
| /* FLASH3LAYOUT1_TOG Bit Fields */ |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 |
| #define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) |
| #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u |
| #define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK 0xF800u |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT 11 |
| #define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 |
| #define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) |
| /* DEBUG0 Bit Fields */ |
| #define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3Fu |
| #define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT 0 |
| #define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_RSVD0_MASK 0xC0u |
| #define BCH_DEBUG0_RSVD0_SHIFT 6 |
| #define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD0_SHIFT))&BCH_DEBUG0_RSVD0_MASK) |
| #define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK 0x100u |
| #define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT 8 |
| #define BCH_DEBUG0_KES_DEBUG_STALL_MASK 0x200u |
| #define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT 9 |
| #define BCH_DEBUG0_KES_DEBUG_STEP_MASK 0x400u |
| #define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT 10 |
| #define BCH_DEBUG0_KES_STANDALONE_MASK 0x800u |
| #define BCH_DEBUG0_KES_STANDALONE_SHIFT 11 |
| #define BCH_DEBUG0_KES_DEBUG_KICK_MASK 0x1000u |
| #define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT 12 |
| #define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK 0x2000u |
| #define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT 13 |
| #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u |
| #define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 |
| #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK 0x8000u |
| #define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT 15 |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 |
| #define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_RSVD1_MASK 0xFE000000u |
| #define BCH_DEBUG0_RSVD1_SHIFT 25 |
| #define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD1_SHIFT))&BCH_DEBUG0_RSVD1_MASK) |
| /* DEBUG0_SET Bit Fields */ |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK 0x3Fu |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT 0 |
| #define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_SET_RSVD0_MASK 0xC0u |
| #define BCH_DEBUG0_SET_RSVD0_SHIFT 6 |
| #define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD0_SHIFT))&BCH_DEBUG0_SET_RSVD0_MASK) |
| #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK 0x100u |
| #define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT 8 |
| #define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK 0x200u |
| #define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT 9 |
| #define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK 0x400u |
| #define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT 10 |
| #define BCH_DEBUG0_SET_KES_STANDALONE_MASK 0x800u |
| #define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT 11 |
| #define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK 0x1000u |
| #define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT 12 |
| #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK 0x2000u |
| #define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT 13 |
| #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u |
| #define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 |
| #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK 0x8000u |
| #define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT 15 |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 |
| #define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_SET_RSVD1_MASK 0xFE000000u |
| #define BCH_DEBUG0_SET_RSVD1_SHIFT 25 |
| #define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD1_SHIFT))&BCH_DEBUG0_SET_RSVD1_MASK) |
| /* DEBUG0_CLR Bit Fields */ |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK 0x3Fu |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT 0 |
| #define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_CLR_RSVD0_MASK 0xC0u |
| #define BCH_DEBUG0_CLR_RSVD0_SHIFT 6 |
| #define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD0_SHIFT))&BCH_DEBUG0_CLR_RSVD0_MASK) |
| #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK 0x100u |
| #define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT 8 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK 0x200u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT 9 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK 0x400u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT 10 |
| #define BCH_DEBUG0_CLR_KES_STANDALONE_MASK 0x800u |
| #define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT 11 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK 0x1000u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT 12 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK 0x2000u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT 13 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK 0x8000u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT 15 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 |
| #define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_CLR_RSVD1_MASK 0xFE000000u |
| #define BCH_DEBUG0_CLR_RSVD1_SHIFT 25 |
| #define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD1_SHIFT))&BCH_DEBUG0_CLR_RSVD1_MASK) |
| /* DEBUG0_TOG Bit Fields */ |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK 0x3Fu |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT 0 |
| #define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) |
| #define BCH_DEBUG0_TOG_RSVD0_MASK 0xC0u |
| #define BCH_DEBUG0_TOG_RSVD0_SHIFT 6 |
| #define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD0_SHIFT))&BCH_DEBUG0_TOG_RSVD0_MASK) |
| #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK 0x100u |
| #define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT 8 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK 0x200u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT 9 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK 0x400u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT 10 |
| #define BCH_DEBUG0_TOG_KES_STANDALONE_MASK 0x800u |
| #define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT 11 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK 0x1000u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT 12 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK 0x2000u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT 13 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK 0x8000u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT 15 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 |
| #define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) |
| #define BCH_DEBUG0_TOG_RSVD1_MASK 0xFE000000u |
| #define BCH_DEBUG0_TOG_RSVD1_SHIFT 25 |
| #define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD1_SHIFT))&BCH_DEBUG0_TOG_RSVD1_MASK) |
| /* DBGKESREAD Bit Fields */ |
| #define BCH_DBGKESREAD_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGKESREAD_VALUES_SHIFT 0 |
| #define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_VALUES_SHIFT))&BCH_DBGKESREAD_VALUES_MASK) |
| /* DBGKESREAD_SET Bit Fields */ |
| #define BCH_DBGKESREAD_SET_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGKESREAD_SET_VALUES_SHIFT 0 |
| #define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_SET_VALUES_SHIFT))&BCH_DBGKESREAD_SET_VALUES_MASK) |
| /* DBGKESREAD_CLR Bit Fields */ |
| #define BCH_DBGKESREAD_CLR_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGKESREAD_CLR_VALUES_SHIFT 0 |
| #define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_CLR_VALUES_SHIFT))&BCH_DBGKESREAD_CLR_VALUES_MASK) |
| /* DBGKESREAD_TOG Bit Fields */ |
| #define BCH_DBGKESREAD_TOG_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGKESREAD_TOG_VALUES_SHIFT 0 |
| #define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_TOG_VALUES_SHIFT))&BCH_DBGKESREAD_TOG_VALUES_MASK) |
| /* DBGCSFEREAD Bit Fields */ |
| #define BCH_DBGCSFEREAD_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGCSFEREAD_VALUES_SHIFT 0 |
| #define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_VALUES_SHIFT))&BCH_DBGCSFEREAD_VALUES_MASK) |
| /* DBGCSFEREAD_SET Bit Fields */ |
| #define BCH_DBGCSFEREAD_SET_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGCSFEREAD_SET_VALUES_SHIFT 0 |
| #define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_SET_VALUES_SHIFT))&BCH_DBGCSFEREAD_SET_VALUES_MASK) |
| /* DBGCSFEREAD_CLR Bit Fields */ |
| #define BCH_DBGCSFEREAD_CLR_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT 0 |
| #define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_CLR_VALUES_SHIFT))&BCH_DBGCSFEREAD_CLR_VALUES_MASK) |
| /* DBGCSFEREAD_TOG Bit Fields */ |
| #define BCH_DBGCSFEREAD_TOG_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT 0 |
| #define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_TOG_VALUES_SHIFT))&BCH_DBGCSFEREAD_TOG_VALUES_MASK) |
| /* DBGSYNDGENREAD Bit Fields */ |
| #define BCH_DBGSYNDGENREAD_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGSYNDGENREAD_VALUES_SHIFT 0 |
| #define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_VALUES_MASK) |
| /* DBGSYNDGENREAD_SET Bit Fields */ |
| #define BCH_DBGSYNDGENREAD_SET_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT 0 |
| #define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_SET_VALUES_MASK) |
| /* DBGSYNDGENREAD_CLR Bit Fields */ |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT 0 |
| #define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) |
| /* DBGSYNDGENREAD_TOG Bit Fields */ |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT 0 |
| #define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) |
| /* DBGAHBMREAD Bit Fields */ |
| #define BCH_DBGAHBMREAD_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGAHBMREAD_VALUES_SHIFT 0 |
| #define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_VALUES_SHIFT))&BCH_DBGAHBMREAD_VALUES_MASK) |
| /* DBGAHBMREAD_SET Bit Fields */ |
| #define BCH_DBGAHBMREAD_SET_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGAHBMREAD_SET_VALUES_SHIFT 0 |
| #define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_SET_VALUES_SHIFT))&BCH_DBGAHBMREAD_SET_VALUES_MASK) |
| /* DBGAHBMREAD_CLR Bit Fields */ |
| #define BCH_DBGAHBMREAD_CLR_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT 0 |
| #define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_CLR_VALUES_SHIFT))&BCH_DBGAHBMREAD_CLR_VALUES_MASK) |
| /* DBGAHBMREAD_TOG Bit Fields */ |
| #define BCH_DBGAHBMREAD_TOG_VALUES_MASK 0xFFFFFFFFu |
| #define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT 0 |
| #define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_TOG_VALUES_SHIFT))&BCH_DBGAHBMREAD_TOG_VALUES_MASK) |
| /* BLOCKNAME Bit Fields */ |
| #define BCH_BLOCKNAME_NAME_MASK 0xFFFFFFFFu |
| #define BCH_BLOCKNAME_NAME_SHIFT 0 |
| #define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_NAME_SHIFT))&BCH_BLOCKNAME_NAME_MASK) |
| /* BLOCKNAME_SET Bit Fields */ |
| #define BCH_BLOCKNAME_SET_NAME_MASK 0xFFFFFFFFu |
| #define BCH_BLOCKNAME_SET_NAME_SHIFT 0 |
| #define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_SET_NAME_SHIFT))&BCH_BLOCKNAME_SET_NAME_MASK) |
| /* BLOCKNAME_CLR Bit Fields */ |
| #define BCH_BLOCKNAME_CLR_NAME_MASK 0xFFFFFFFFu |
| #define BCH_BLOCKNAME_CLR_NAME_SHIFT 0 |
| #define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_CLR_NAME_SHIFT))&BCH_BLOCKNAME_CLR_NAME_MASK) |
| /* BLOCKNAME_TOG Bit Fields */ |
| #define BCH_BLOCKNAME_TOG_NAME_MASK 0xFFFFFFFFu |
| #define BCH_BLOCKNAME_TOG_NAME_SHIFT 0 |
| #define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_TOG_NAME_SHIFT))&BCH_BLOCKNAME_TOG_NAME_MASK) |
| /* VERSION Bit Fields */ |
| #define BCH_VERSION_STEP_MASK 0xFFFFu |
| #define BCH_VERSION_STEP_SHIFT 0 |
| #define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_STEP_SHIFT))&BCH_VERSION_STEP_MASK) |
| #define BCH_VERSION_MINOR_MASK 0xFF0000u |
| #define BCH_VERSION_MINOR_SHIFT 16 |
| #define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MINOR_SHIFT))&BCH_VERSION_MINOR_MASK) |
| #define BCH_VERSION_MAJOR_MASK 0xFF000000u |
| #define BCH_VERSION_MAJOR_SHIFT 24 |
| #define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MAJOR_SHIFT))&BCH_VERSION_MAJOR_MASK) |
| /* VERSION_SET Bit Fields */ |
| #define BCH_VERSION_SET_STEP_MASK 0xFFFFu |
| #define BCH_VERSION_SET_STEP_SHIFT 0 |
| #define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_STEP_SHIFT))&BCH_VERSION_SET_STEP_MASK) |
| #define BCH_VERSION_SET_MINOR_MASK 0xFF0000u |
| #define BCH_VERSION_SET_MINOR_SHIFT 16 |
| #define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MINOR_SHIFT))&BCH_VERSION_SET_MINOR_MASK) |
| #define BCH_VERSION_SET_MAJOR_MASK 0xFF000000u |
| #define BCH_VERSION_SET_MAJOR_SHIFT 24 |
| #define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MAJOR_SHIFT))&BCH_VERSION_SET_MAJOR_MASK) |
| /* VERSION_CLR Bit Fields */ |
| #define BCH_VERSION_CLR_STEP_MASK 0xFFFFu |
| #define BCH_VERSION_CLR_STEP_SHIFT 0 |
| #define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_STEP_SHIFT))&BCH_VERSION_CLR_STEP_MASK) |
| #define BCH_VERSION_CLR_MINOR_MASK 0xFF0000u |
| #define BCH_VERSION_CLR_MINOR_SHIFT 16 |
| #define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MINOR_SHIFT))&BCH_VERSION_CLR_MINOR_MASK) |
| #define BCH_VERSION_CLR_MAJOR_MASK 0xFF000000u |
| #define BCH_VERSION_CLR_MAJOR_SHIFT 24 |
| #define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MAJOR_SHIFT))&BCH_VERSION_CLR_MAJOR_MASK) |
| /* VERSION_TOG Bit Fields */ |
| #define BCH_VERSION_TOG_STEP_MASK 0xFFFFu |
| #define BCH_VERSION_TOG_STEP_SHIFT 0 |
| #define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_STEP_SHIFT))&BCH_VERSION_TOG_STEP_MASK) |
| #define BCH_VERSION_TOG_MINOR_MASK 0xFF0000u |
| #define BCH_VERSION_TOG_MINOR_SHIFT 16 |
| #define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MINOR_SHIFT))&BCH_VERSION_TOG_MINOR_MASK) |
| #define BCH_VERSION_TOG_MAJOR_MASK 0xFF000000u |
| #define BCH_VERSION_TOG_MAJOR_SHIFT 24 |
| #define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MAJOR_SHIFT))&BCH_VERSION_TOG_MAJOR_MASK) |
| /* DEBUG1 Bit Fields */ |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK 0x1FFu |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT 0 |
| #define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_RSVD_MASK 0x7FFFFE00u |
| #define BCH_DEBUG1_RSVD_SHIFT 9 |
| #define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_RSVD_SHIFT))&BCH_DEBUG1_RSVD_MASK) |
| #define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK 0x80000000u |
| #define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT 31 |
| /* DEBUG1_SET Bit Fields */ |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK 0x1FFu |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT 0 |
| #define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_SET_RSVD_MASK 0x7FFFFE00u |
| #define BCH_DEBUG1_SET_RSVD_SHIFT 9 |
| #define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_RSVD_SHIFT))&BCH_DEBUG1_SET_RSVD_MASK) |
| #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK 0x80000000u |
| #define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT 31 |
| /* DEBUG1_CLR Bit Fields */ |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK 0x1FFu |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT 0 |
| #define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_CLR_RSVD_MASK 0x7FFFFE00u |
| #define BCH_DEBUG1_CLR_RSVD_SHIFT 9 |
| #define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_RSVD_SHIFT))&BCH_DEBUG1_CLR_RSVD_MASK) |
| #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK 0x80000000u |
| #define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT 31 |
| /* DEBUG1_TOG Bit Fields */ |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK 0x1FFu |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT 0 |
| #define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) |
| #define BCH_DEBUG1_TOG_RSVD_MASK 0x7FFFFE00u |
| #define BCH_DEBUG1_TOG_RSVD_SHIFT 9 |
| #define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_RSVD_SHIFT))&BCH_DEBUG1_TOG_RSVD_MASK) |
| #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK 0x80000000u |
| #define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT 31 |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Register_Masks */ |
| |
| /* BCH - Peripheral instance base addresses */ |
| /** Peripheral BCH base address */ |
| #define BCH_BASE (0x41808000u) |
| /** Peripheral BCH base pointer */ |
| #define BCH ((BCH_Type *)BCH_BASE) |
| #define BCH_BASE_PTR (BCH) |
| /** Array initializer of BCH peripheral base addresses */ |
| #define BCH_BASE_ADDRS { BCH_BASE } |
| /** Array initializer of BCH peripheral base pointers */ |
| #define BCH_BASE_PTRS { BCH } |
| /** Interrupt vectors for the BCH peripheral type */ |
| #define BCH_IRQS { BCH_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- BCH - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros |
| * @{ |
| */ |
| |
| /* BCH - Register instance definitions */ |
| /* BCH */ |
| #define BCH_CTRL BCH_CTRL_REG(BCH_BASE_PTR) |
| #define BCH_CTRL_SET BCH_CTRL_SET_REG(BCH_BASE_PTR) |
| #define BCH_CTRL_CLR BCH_CTRL_CLR_REG(BCH_BASE_PTR) |
| #define BCH_CTRL_TOG BCH_CTRL_TOG_REG(BCH_BASE_PTR) |
| #define BCH_STATUS0 BCH_STATUS0_REG(BCH_BASE_PTR) |
| #define BCH_STATUS0_SET BCH_STATUS0_SET_REG(BCH_BASE_PTR) |
| #define BCH_STATUS0_CLR BCH_STATUS0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_STATUS0_TOG BCH_STATUS0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_MODE BCH_MODE_REG(BCH_BASE_PTR) |
| #define BCH_MODE_SET BCH_MODE_SET_REG(BCH_BASE_PTR) |
| #define BCH_MODE_CLR BCH_MODE_CLR_REG(BCH_BASE_PTR) |
| #define BCH_MODE_TOG BCH_MODE_TOG_REG(BCH_BASE_PTR) |
| #define BCH_ENCODEPTR BCH_ENCODEPTR_REG(BCH_BASE_PTR) |
| #define BCH_ENCODEPTR_SET BCH_ENCODEPTR_SET_REG(BCH_BASE_PTR) |
| #define BCH_ENCODEPTR_CLR BCH_ENCODEPTR_CLR_REG(BCH_BASE_PTR) |
| #define BCH_ENCODEPTR_TOG BCH_ENCODEPTR_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DATAPTR BCH_DATAPTR_REG(BCH_BASE_PTR) |
| #define BCH_DATAPTR_SET BCH_DATAPTR_SET_REG(BCH_BASE_PTR) |
| #define BCH_DATAPTR_CLR BCH_DATAPTR_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DATAPTR_TOG BCH_DATAPTR_TOG_REG(BCH_BASE_PTR) |
| #define BCH_METAPTR BCH_METAPTR_REG(BCH_BASE_PTR) |
| #define BCH_METAPTR_SET BCH_METAPTR_SET_REG(BCH_BASE_PTR) |
| #define BCH_METAPTR_CLR BCH_METAPTR_CLR_REG(BCH_BASE_PTR) |
| #define BCH_METAPTR_TOG BCH_METAPTR_TOG_REG(BCH_BASE_PTR) |
| #define BCH_LAYOUTSELECT BCH_LAYOUTSELECT_REG(BCH_BASE_PTR) |
| #define BCH_LAYOUTSELECT_SET BCH_LAYOUTSELECT_SET_REG(BCH_BASE_PTR) |
| #define BCH_LAYOUTSELECT_CLR BCH_LAYOUTSELECT_CLR_REG(BCH_BASE_PTR) |
| #define BCH_LAYOUTSELECT_TOG BCH_LAYOUTSELECT_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT0 BCH_FLASH0LAYOUT0_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT0_SET BCH_FLASH0LAYOUT0_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT0_CLR BCH_FLASH0LAYOUT0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT0_TOG BCH_FLASH0LAYOUT0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT1 BCH_FLASH0LAYOUT1_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT1_SET BCH_FLASH0LAYOUT1_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT1_CLR BCH_FLASH0LAYOUT1_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH0LAYOUT1_TOG BCH_FLASH0LAYOUT1_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT0 BCH_FLASH1LAYOUT0_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT0_SET BCH_FLASH1LAYOUT0_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT0_CLR BCH_FLASH1LAYOUT0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT0_TOG BCH_FLASH1LAYOUT0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT1 BCH_FLASH1LAYOUT1_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT1_SET BCH_FLASH1LAYOUT1_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT1_CLR BCH_FLASH1LAYOUT1_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH1LAYOUT1_TOG BCH_FLASH1LAYOUT1_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT0 BCH_FLASH2LAYOUT0_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT0_SET BCH_FLASH2LAYOUT0_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT0_CLR BCH_FLASH2LAYOUT0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT0_TOG BCH_FLASH2LAYOUT0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT1 BCH_FLASH2LAYOUT1_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT1_SET BCH_FLASH2LAYOUT1_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT1_CLR BCH_FLASH2LAYOUT1_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH2LAYOUT1_TOG BCH_FLASH2LAYOUT1_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT0 BCH_FLASH3LAYOUT0_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT0_SET BCH_FLASH3LAYOUT0_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT0_CLR BCH_FLASH3LAYOUT0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT0_TOG BCH_FLASH3LAYOUT0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT1 BCH_FLASH3LAYOUT1_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT1_SET BCH_FLASH3LAYOUT1_SET_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT1_CLR BCH_FLASH3LAYOUT1_CLR_REG(BCH_BASE_PTR) |
| #define BCH_FLASH3LAYOUT1_TOG BCH_FLASH3LAYOUT1_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG0 BCH_DEBUG0_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG0_SET BCH_DEBUG0_SET_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG0_CLR BCH_DEBUG0_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG0_TOG BCH_DEBUG0_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DBGKESREAD BCH_DBGKESREAD_REG(BCH_BASE_PTR) |
| #define BCH_DBGKESREAD_SET BCH_DBGKESREAD_SET_REG(BCH_BASE_PTR) |
| #define BCH_DBGKESREAD_CLR BCH_DBGKESREAD_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DBGKESREAD_TOG BCH_DBGKESREAD_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DBGCSFEREAD BCH_DBGCSFEREAD_REG(BCH_BASE_PTR) |
| #define BCH_DBGCSFEREAD_SET BCH_DBGCSFEREAD_SET_REG(BCH_BASE_PTR) |
| #define BCH_DBGCSFEREAD_CLR BCH_DBGCSFEREAD_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DBGCSFEREAD_TOG BCH_DBGCSFEREAD_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DBGSYNDGENREAD BCH_DBGSYNDGENREAD_REG(BCH_BASE_PTR) |
| #define BCH_DBGSYNDGENREAD_SET BCH_DBGSYNDGENREAD_SET_REG(BCH_BASE_PTR) |
| #define BCH_DBGSYNDGENREAD_CLR BCH_DBGSYNDGENREAD_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DBGSYNDGENREAD_TOG BCH_DBGSYNDGENREAD_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DBGAHBMREAD BCH_DBGAHBMREAD_REG(BCH_BASE_PTR) |
| #define BCH_DBGAHBMREAD_SET BCH_DBGAHBMREAD_SET_REG(BCH_BASE_PTR) |
| #define BCH_DBGAHBMREAD_CLR BCH_DBGAHBMREAD_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DBGAHBMREAD_TOG BCH_DBGAHBMREAD_TOG_REG(BCH_BASE_PTR) |
| #define BCH_BLOCKNAME BCH_BLOCKNAME_REG(BCH_BASE_PTR) |
| #define BCH_BLOCKNAME_SET BCH_BLOCKNAME_SET_REG(BCH_BASE_PTR) |
| #define BCH_BLOCKNAME_CLR BCH_BLOCKNAME_CLR_REG(BCH_BASE_PTR) |
| #define BCH_BLOCKNAME_TOG BCH_BLOCKNAME_TOG_REG(BCH_BASE_PTR) |
| #define BCH_VERSION BCH_VERSION_REG(BCH_BASE_PTR) |
| #define BCH_VERSION_SET BCH_VERSION_SET_REG(BCH_BASE_PTR) |
| #define BCH_VERSION_CLR BCH_VERSION_CLR_REG(BCH_BASE_PTR) |
| #define BCH_VERSION_TOG BCH_VERSION_TOG_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG1 BCH_DEBUG1_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG1_SET BCH_DEBUG1_SET_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG1_CLR BCH_DEBUG1_CLR_REG(BCH_BASE_PTR) |
| #define BCH_DEBUG1_TOG BCH_DEBUG1_TOG_REG(BCH_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group BCH_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CAN Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CAN - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
| __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ |
| __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ |
| __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ |
| __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ |
| __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ |
| __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ |
| __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ |
| __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ |
| __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ |
| __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ |
| __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ |
| __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ |
| uint8_t RESERVED_1[8]; |
| __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ |
| __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ |
| __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ |
| uint8_t RESERVED_2[48]; |
| struct { /* offset: 0x80, array step: 0x10 */ |
| __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ |
| __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ |
| __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ |
| __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ |
| } MB[64]; |
| uint8_t RESERVED_3[1024]; |
| __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ |
| uint8_t RESERVED_4[96]; |
| __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ |
| } CAN_Type, *CAN_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CAN - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros |
| * @{ |
| */ |
| |
| /* CAN - Register accessors */ |
| #define CAN_MCR_REG(base) ((base)->MCR) |
| #define CAN_CTRL1_REG(base) ((base)->CTRL1) |
| #define CAN_TIMER_REG(base) ((base)->TIMER) |
| #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) |
| #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) |
| #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) |
| #define CAN_ECR_REG(base) ((base)->ECR) |
| #define CAN_ESR1_REG(base) ((base)->ESR1) |
| #define CAN_IMASK2_REG(base) ((base)->IMASK2) |
| #define CAN_IMASK1_REG(base) ((base)->IMASK1) |
| #define CAN_IFLAG2_REG(base) ((base)->IFLAG2) |
| #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) |
| #define CAN_CTRL2_REG(base) ((base)->CTRL2) |
| #define CAN_ESR2_REG(base) ((base)->ESR2) |
| #define CAN_CRCR_REG(base) ((base)->CRCR) |
| #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) |
| #define CAN_RXFIR_REG(base) ((base)->RXFIR) |
| #define CAN_CS_REG(base,index) ((base)->MB[index].CS) |
| #define CAN_CS_COUNT 64 |
| #define CAN_ID_REG(base,index) ((base)->MB[index].ID) |
| #define CAN_ID_COUNT 64 |
| #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) |
| #define CAN_WORD0_COUNT 64 |
| #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) |
| #define CAN_WORD1_COUNT 64 |
| #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) |
| #define CAN_RXIMR_COUNT 64 |
| #define CAN_GFWR_REG(base) ((base)->GFWR) |
| |
| /*! |
| * @} |
| */ /* end of group CAN_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CAN Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CAN_Register_Masks CAN Register Masks |
| * @{ |
| */ |
| |
| /* MCR Bit Fields */ |
| #define CAN_MCR_MAXMB_MASK 0x7Fu |
| #define CAN_MCR_MAXMB_SHIFT 0 |
| #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK) |
| #define CAN_MCR_IDAM_MASK 0x300u |
| #define CAN_MCR_IDAM_SHIFT 8 |
| #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK) |
| #define CAN_MCR_AEN_MASK 0x1000u |
| #define CAN_MCR_AEN_SHIFT 12 |
| #define CAN_MCR_LPRIO_EN_MASK 0x2000u |
| #define CAN_MCR_LPRIO_EN_SHIFT 13 |
| #define CAN_MCR_IRMQ_MASK 0x10000u |
| #define CAN_MCR_IRMQ_SHIFT 16 |
| #define CAN_MCR_SRX_DIS_MASK 0x20000u |
| #define CAN_MCR_SRX_DIS_SHIFT 17 |
| #define CAN_MCR_WAK_SRC_MASK 0x80000u |
| #define CAN_MCR_WAK_SRC_SHIFT 19 |
| #define CAN_MCR_LPM_ACK_MASK 0x100000u |
| #define CAN_MCR_LPM_ACK_SHIFT 20 |
| #define CAN_MCR_WRN_EN_MASK 0x200000u |
| #define CAN_MCR_WRN_EN_SHIFT 21 |
| #define CAN_MCR_SLF_WAK_MASK 0x400000u |
| #define CAN_MCR_SLF_WAK_SHIFT 22 |
| #define CAN_MCR_SUPV_MASK 0x800000u |
| #define CAN_MCR_SUPV_SHIFT 23 |
| #define CAN_MCR_FRZ_ACK_MASK 0x1000000u |
| #define CAN_MCR_FRZ_ACK_SHIFT 24 |
| #define CAN_MCR_SOFT_RST_MASK 0x2000000u |
| #define CAN_MCR_SOFT_RST_SHIFT 25 |
| #define CAN_MCR_WAK_MSK_MASK 0x4000000u |
| #define CAN_MCR_WAK_MSK_SHIFT 26 |
| #define CAN_MCR_NOT_RDY_MASK 0x8000000u |
| #define CAN_MCR_NOT_RDY_SHIFT 27 |
| #define CAN_MCR_HALT_MASK 0x10000000u |
| #define CAN_MCR_HALT_SHIFT 28 |
| #define CAN_MCR_RFEN_MASK 0x20000000u |
| #define CAN_MCR_RFEN_SHIFT 29 |
| #define CAN_MCR_FRZ_MASK 0x40000000u |
| #define CAN_MCR_FRZ_SHIFT 30 |
| #define CAN_MCR_MDIS_MASK 0x80000000u |
| #define CAN_MCR_MDIS_SHIFT 31 |
| /* CTRL1 Bit Fields */ |
| #define CAN_CTRL1_PROP_SEG_MASK 0x7u |
| #define CAN_CTRL1_PROP_SEG_SHIFT 0 |
| #define CAN_CTRL1_PROP_SEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROP_SEG_SHIFT))&CAN_CTRL1_PROP_SEG_MASK) |
| #define CAN_CTRL1_LOM_MASK 0x8u |
| #define CAN_CTRL1_LOM_SHIFT 3 |
| #define CAN_CTRL1_LBUF_MASK 0x10u |
| #define CAN_CTRL1_LBUF_SHIFT 4 |
| #define CAN_CTRL1_TSYN_MASK 0x20u |
| #define CAN_CTRL1_TSYN_SHIFT 5 |
| #define CAN_CTRL1_BOFF_REC_MASK 0x40u |
| #define CAN_CTRL1_BOFF_REC_SHIFT 6 |
| #define CAN_CTRL1_SMP_MASK 0x80u |
| #define CAN_CTRL1_SMP_SHIFT 7 |
| #define CAN_CTRL1_RWRN_MSK_MASK 0x400u |
| #define CAN_CTRL1_RWRN_MSK_SHIFT 10 |
| #define CAN_CTRL1_TWRN_MSK_MASK 0x800u |
| #define CAN_CTRL1_TWRN_MSK_SHIFT 11 |
| #define CAN_CTRL1_LPB_MASK 0x1000u |
| #define CAN_CTRL1_LPB_SHIFT 12 |
| #define CAN_CTRL1_ERR_MSK_MASK 0x4000u |
| #define CAN_CTRL1_ERR_MSK_SHIFT 14 |
| #define CAN_CTRL1_BOFF_MSK_MASK 0x8000u |
| #define CAN_CTRL1_BOFF_MSK_SHIFT 15 |
| #define CAN_CTRL1_PSEG2_MASK 0x70000u |
| #define CAN_CTRL1_PSEG2_SHIFT 16 |
| #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK) |
| #define CAN_CTRL1_PSEG1_MASK 0x380000u |
| #define CAN_CTRL1_PSEG1_SHIFT 19 |
| #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK) |
| #define CAN_CTRL1_RJW_MASK 0xC00000u |
| #define CAN_CTRL1_RJW_SHIFT 22 |
| #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK) |
| #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u |
| #define CAN_CTRL1_PRESDIV_SHIFT 24 |
| #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK) |
| /* TIMER Bit Fields */ |
| #define CAN_TIMER_TIMER_MASK 0xFFFFu |
| #define CAN_TIMER_TIMER_SHIFT 0 |
| #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK) |
| /* RXMGMASK Bit Fields */ |
| #define CAN_RXMGMASK_MG31_MG0_MASK 0xFFFFFFFFu |
| #define CAN_RXMGMASK_MG31_MG0_SHIFT 0 |
| #define CAN_RXMGMASK_MG31_MG0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG31_MG0_SHIFT))&CAN_RXMGMASK_MG31_MG0_MASK) |
| /* RX14MASK Bit Fields */ |
| #define CAN_RX14MASK_RX14M31_RX14M0_MASK 0xFFFFFFFFu |
| #define CAN_RX14MASK_RX14M31_RX14M0_SHIFT 0 |
| #define CAN_RX14MASK_RX14M31_RX14M0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M31_RX14M0_SHIFT))&CAN_RX14MASK_RX14M31_RX14M0_MASK) |
| /* RX15MASK Bit Fields */ |
| #define CAN_RX15MASK_RX15M31_RX15M0_MASK 0xFFFFFFFFu |
| #define CAN_RX15MASK_RX15M31_RX15M0_SHIFT 0 |
| #define CAN_RX15MASK_RX15M31_RX15M0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M31_RX15M0_SHIFT))&CAN_RX15MASK_RX15M31_RX15M0_MASK) |
| /* ECR Bit Fields */ |
| #define CAN_ECR_Tx_Err_Counter_MASK 0xFFu |
| #define CAN_ECR_Tx_Err_Counter_SHIFT 0 |
| #define CAN_ECR_Tx_Err_Counter(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Tx_Err_Counter_SHIFT))&CAN_ECR_Tx_Err_Counter_MASK) |
| #define CAN_ECR_Rx_Err_Counter_MASK 0xFF00u |
| #define CAN_ECR_Rx_Err_Counter_SHIFT 8 |
| #define CAN_ECR_Rx_Err_Counter(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Rx_Err_Counter_SHIFT))&CAN_ECR_Rx_Err_Counter_MASK) |
| /* ESR1 Bit Fields */ |
| #define CAN_ESR1_WAK_INT_MASK 0x1u |
| #define CAN_ESR1_WAK_INT_SHIFT 0 |
| #define CAN_ESR1_ERR_INT_MASK 0x2u |
| #define CAN_ESR1_ERR_INT_SHIFT 1 |
| #define CAN_ESR1_BOFF_INT_MASK 0x4u |
| #define CAN_ESR1_BOFF_INT_SHIFT 2 |
| #define CAN_ESR1_RX_MASK 0x8u |
| #define CAN_ESR1_RX_SHIFT 3 |
| #define CAN_ESR1_FLT_CONF_MASK 0x30u |
| #define CAN_ESR1_FLT_CONF_SHIFT 4 |
| #define CAN_ESR1_FLT_CONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLT_CONF_SHIFT))&CAN_ESR1_FLT_CONF_MASK) |
| #define CAN_ESR1_TX_MASK 0x40u |
| #define CAN_ESR1_TX_SHIFT 6 |
| #define CAN_ESR1_IDLE_MASK 0x80u |
| #define CAN_ESR1_IDLE_SHIFT 7 |
| #define CAN_ESR1_RX_WRN_MASK 0x100u |
| #define CAN_ESR1_RX_WRN_SHIFT 8 |
| #define CAN_ESR1_TX_WRN_MASK 0x200u |
| #define CAN_ESR1_TX_WRN_SHIFT 9 |
| #define CAN_ESR1_STF_ERR_MASK 0x400u |
| #define CAN_ESR1_STF_ERR_SHIFT 10 |
| #define CAN_ESR1_FRM_ERR_MASK 0x800u |
| #define CAN_ESR1_FRM_ERR_SHIFT 11 |
| #define CAN_ESR1_CRC_ERR_MASK 0x1000u |
| #define CAN_ESR1_CRC_ERR_SHIFT 12 |
| #define CAN_ESR1_ACK_ERR_MASK 0x2000u |
| #define CAN_ESR1_ACK_ERR_SHIFT 13 |
| #define CAN_ESR1_BIT0_ERR_MASK 0x4000u |
| #define CAN_ESR1_BIT0_ERR_SHIFT 14 |
| #define CAN_ESR1_BIT1_ERR_MASK 0x8000u |
| #define CAN_ESR1_BIT1_ERR_SHIFT 15 |
| #define CAN_ESR1_RWRN_INT_MASK 0x10000u |
| #define CAN_ESR1_RWRN_INT_SHIFT 16 |
| #define CAN_ESR1_TWRN_INT_MASK 0x20000u |
| #define CAN_ESR1_TWRN_INT_SHIFT 17 |
| #define CAN_ESR1_SYNCH_MASK 0x40000u |
| #define CAN_ESR1_SYNCH_SHIFT 18 |
| /* IMASK2 Bit Fields */ |
| #define CAN_IMASK2_BUF63M_BUF32M_MASK 0xFFFFFFFFu |
| #define CAN_IMASK2_BUF63M_BUF32M_SHIFT 0 |
| #define CAN_IMASK2_BUF63M_BUF32M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUF63M_BUF32M_SHIFT))&CAN_IMASK2_BUF63M_BUF32M_MASK) |
| /* IMASK1 Bit Fields */ |
| #define CAN_IMASK1_BUF31M_BUF0M_MASK 0xFFFFFFFFu |
| #define CAN_IMASK1_BUF31M_BUF0M_SHIFT 0 |
| #define CAN_IMASK1_BUF31M_BUF0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31M_BUF0M_SHIFT))&CAN_IMASK1_BUF31M_BUF0M_MASK) |
| /* IFLAG2 Bit Fields */ |
| #define CAN_IFLAG2_BUF63I_BUF32I_MASK 0xFFFFFFFFu |
| #define CAN_IFLAG2_BUF63I_BUF32I_SHIFT 0 |
| #define CAN_IFLAG2_BUF63I_BUF32I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUF63I_BUF32I_SHIFT))&CAN_IFLAG2_BUF63I_BUF32I_MASK) |
| /* IFLAG1 Bit Fields */ |
| #define CAN_IFLAG1_BUF4I_BUF0I_MASK 0x1Fu |
| #define CAN_IFLAG1_BUF4I_BUF0I_SHIFT 0 |
| #define CAN_IFLAG1_BUF4I_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4I_BUF0I_SHIFT))&CAN_IFLAG1_BUF4I_BUF0I_MASK) |
| #define CAN_IFLAG1_BUF5I_MASK 0x20u |
| #define CAN_IFLAG1_BUF5I_SHIFT 5 |
| #define CAN_IFLAG1_BUF6I_MASK 0x40u |
| #define CAN_IFLAG1_BUF6I_SHIFT 6 |
| #define CAN_IFLAG1_BUF7I_MASK 0x80u |
| #define CAN_IFLAG1_BUF7I_SHIFT 7 |
| #define CAN_IFLAG1_BUF31I_BUF8I_MASK 0xFFFFFF00u |
| #define CAN_IFLAG1_BUF31I_BUF8I_SHIFT 8 |
| #define CAN_IFLAG1_BUF31I_BUF8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31I_BUF8I_SHIFT))&CAN_IFLAG1_BUF31I_BUF8I_MASK) |
| /* CTRL2 Bit Fields */ |
| #define CAN_CTRL2_EACEN_MASK 0x10000u |
| #define CAN_CTRL2_EACEN_SHIFT 16 |
| #define CAN_CTRL2_RRS_MASK 0x20000u |
| #define CAN_CTRL2_RRS_SHIFT 17 |
| #define CAN_CTRL2_MRP_MASK 0x40000u |
| #define CAN_CTRL2_MRP_SHIFT 18 |
| #define CAN_CTRL2_TASD_MASK 0xF80000u |
| #define CAN_CTRL2_TASD_SHIFT 19 |
| #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK) |
| #define CAN_CTRL2_RFFN_MASK 0xF000000u |
| #define CAN_CTRL2_RFFN_SHIFT 24 |
| #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK) |
| #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u |
| #define CAN_CTRL2_WRMFRZ_SHIFT 28 |
| /* ESR2 Bit Fields */ |
| #define CAN_ESR2_IMB_MASK 0x2000u |
| #define CAN_ESR2_IMB_SHIFT 13 |
| #define CAN_ESR2_VPS_MASK 0x4000u |
| #define CAN_ESR2_VPS_SHIFT 14 |
| #define CAN_ESR2_LPTM_MASK 0x7F0000u |
| #define CAN_ESR2_LPTM_SHIFT 16 |
| #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK) |
| /* CRCR Bit Fields */ |
| #define CAN_CRCR_TXCRC_MASK 0x7FFFu |
| #define CAN_CRCR_TXCRC_SHIFT 0 |
| #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK) |
| #define CAN_CRCR_MBCRC_MASK 0x7F0000u |
| #define CAN_CRCR_MBCRC_SHIFT 16 |
| #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK) |
| /* RXFGMASK Bit Fields */ |
| #define CAN_RXFGMASK_FGM31_FGM0_MASK 0xFFFFFFFFu |
| #define CAN_RXFGMASK_FGM31_FGM0_SHIFT 0 |
| #define CAN_RXFGMASK_FGM31_FGM0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM31_FGM0_SHIFT))&CAN_RXFGMASK_FGM31_FGM0_MASK) |
| /* RXFIR Bit Fields */ |
| #define CAN_RXFIR_IDHIT_MASK 0x1FFu |
| #define CAN_RXFIR_IDHIT_SHIFT 0 |
| #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK) |
| /* CS Bit Fields */ |
| #define CAN_CS_TIME_STAMP_MASK 0xFFFFu |
| #define CAN_CS_TIME_STAMP_SHIFT 0 |
| #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK) |
| #define CAN_CS_DLC_MASK 0xF0000u |
| #define CAN_CS_DLC_SHIFT 16 |
| #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK) |
| #define CAN_CS_RTR_MASK 0x100000u |
| #define CAN_CS_RTR_SHIFT 20 |
| #define CAN_CS_IDE_MASK 0x200000u |
| #define CAN_CS_IDE_SHIFT 21 |
| #define CAN_CS_SRR_MASK 0x400000u |
| #define CAN_CS_SRR_SHIFT 22 |
| #define CAN_CS_CODE_MASK 0xF000000u |
| #define CAN_CS_CODE_SHIFT 24 |
| #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK) |
| /* ID Bit Fields */ |
| #define CAN_ID_EXT_MASK 0x3FFFFu |
| #define CAN_ID_EXT_SHIFT 0 |
| #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK) |
| #define CAN_ID_STD_MASK 0x1FFC0000u |
| #define CAN_ID_STD_SHIFT 18 |
| #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK) |
| #define CAN_ID_PRIO_MASK 0xE0000000u |
| #define CAN_ID_PRIO_SHIFT 29 |
| #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK) |
| /* WORD0 Bit Fields */ |
| #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu |
| #define CAN_WORD0_DATA_BYTE_3_SHIFT 0 |
| #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK) |
| #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u |
| #define CAN_WORD0_DATA_BYTE_2_SHIFT 8 |
| #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK) |
| #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u |
| #define CAN_WORD0_DATA_BYTE_1_SHIFT 16 |
| #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK) |
| #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u |
| #define CAN_WORD0_DATA_BYTE_0_SHIFT 24 |
| #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK) |
| /* WORD1 Bit Fields */ |
| #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu |
| #define CAN_WORD1_DATA_BYTE_7_SHIFT 0 |
| #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK) |
| #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u |
| #define CAN_WORD1_DATA_BYTE_6_SHIFT 8 |
| #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK) |
| #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u |
| #define CAN_WORD1_DATA_BYTE_5_SHIFT 16 |
| #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK) |
| #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u |
| #define CAN_WORD1_DATA_BYTE_4_SHIFT 24 |
| #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK) |
| /* RXIMR Bit Fields */ |
| #define CAN_RXIMR0_RXIMR63_MI31_MI0_MASK 0xFFFFFFFFu |
| #define CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT 0 |
| #define CAN_RXIMR0_RXIMR63_MI31_MI0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT))&CAN_RXIMR0_RXIMR63_MI31_MI0_MASK) |
| /* GFWR Bit Fields */ |
| #define CAN_GFWR_GFWR_MASK 0xFFu |
| #define CAN_GFWR_GFWR_SHIFT 0 |
| #define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x))<<CAN_GFWR_GFWR_SHIFT))&CAN_GFWR_GFWR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group CAN_Register_Masks */ |
| |
| /* CAN - Peripheral instance base addresses */ |
| /** Peripheral CAN1 base address */ |
| #define CAN1_BASE (0x42090000u) |
| /** Peripheral CAN1 base pointer */ |
| #define CAN1 ((CAN_Type *)CAN1_BASE) |
| #define CAN1_BASE_PTR (CAN1) |
| /** Peripheral CAN2 base address */ |
| #define CAN2_BASE (0x42094000u) |
| /** Peripheral CAN2 base pointer */ |
| #define CAN2 ((CAN_Type *)CAN2_BASE) |
| #define CAN2_BASE_PTR (CAN2) |
| /** Array initializer of CAN peripheral base addresses */ |
| #define CAN_BASE_ADDRS { CAN1_BASE, CAN2_BASE } |
| /** Array initializer of CAN peripheral base pointers */ |
| #define CAN_BASE_PTRS { CAN1, CAN2 } |
| /** Interrupt vectors for the CAN peripheral type */ |
| #define CAN_IRQS { FLEXCAN1_IRQn, FLEXCAN2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- CAN - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros |
| * @{ |
| */ |
| |
| /* CAN - Register instance definitions */ |
| /* CAN1 */ |
| #define CAN1_MCR CAN_MCR_REG(CAN1_BASE_PTR) |
| #define CAN1_CTRL1 CAN_CTRL1_REG(CAN1_BASE_PTR) |
| #define CAN1_TIMER CAN_TIMER_REG(CAN1_BASE_PTR) |
| #define CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1_BASE_PTR) |
| #define CAN1_RX14MASK CAN_RX14MASK_REG(CAN1_BASE_PTR) |
| #define CAN1_RX15MASK CAN_RX15MASK_REG(CAN1_BASE_PTR) |
| #define CAN1_ECR CAN_ECR_REG(CAN1_BASE_PTR) |
| #define CAN1_ESR1 CAN_ESR1_REG(CAN1_BASE_PTR) |
| #define CAN1_IMASK2 CAN_IMASK2_REG(CAN1_BASE_PTR) |
| #define CAN1_IMASK1 CAN_IMASK1_REG(CAN1_BASE_PTR) |
| #define CAN1_IFLAG2 CAN_IFLAG2_REG(CAN1_BASE_PTR) |
| #define CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1_BASE_PTR) |
| #define CAN1_CTRL2 CAN_CTRL2_REG(CAN1_BASE_PTR) |
| #define CAN1_ESR2 CAN_ESR2_REG(CAN1_BASE_PTR) |
| #define CAN1_CRCR CAN_CRCR_REG(CAN1_BASE_PTR) |
| #define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1_BASE_PTR) |
| #define CAN1_RXFIR CAN_RXFIR_REG(CAN1_BASE_PTR) |
| #define CAN1_CS0 CAN_CS_REG(CAN1_BASE_PTR,0) |
| #define CAN1_ID0 CAN_ID_REG(CAN1_BASE_PTR,0) |
| #define CAN1_WORD00 CAN_WORD0_REG(CAN1_BASE_PTR,0) |
| #define CAN1_WORD10 CAN_WORD1_REG(CAN1_BASE_PTR,0) |
| #define CAN1_CS1 CAN_CS_REG(CAN1_BASE_PTR,1) |
| #define CAN1_ID1 CAN_ID_REG(CAN1_BASE_PTR,1) |
| #define CAN1_WORD01 CAN_WORD0_REG(CAN1_BASE_PTR,1) |
| #define CAN1_WORD11 CAN_WORD1_REG(CAN1_BASE_PTR,1) |
| #define CAN1_CS2 CAN_CS_REG(CAN1_BASE_PTR,2) |
| #define CAN1_ID2 CAN_ID_REG(CAN1_BASE_PTR,2) |
| #define CAN1_WORD02 CAN_WORD0_REG(CAN1_BASE_PTR,2) |
| #define CAN1_WORD12 CAN_WORD1_REG(CAN1_BASE_PTR,2) |
| #define CAN1_CS3 CAN_CS_REG(CAN1_BASE_PTR,3) |
| #define CAN1_ID3 CAN_ID_REG(CAN1_BASE_PTR,3) |
| #define CAN1_WORD03 CAN_WORD0_REG(CAN1_BASE_PTR,3) |
| #define CAN1_WORD13 CAN_WORD1_REG(CAN1_BASE_PTR,3) |
| #define CAN1_CS4 CAN_CS_REG(CAN1_BASE_PTR,4) |
| #define CAN1_ID4 CAN_ID_REG(CAN1_BASE_PTR,4) |
| #define CAN1_WORD04 CAN_WORD0_REG(CAN1_BASE_PTR,4) |
| #define CAN1_WORD14 CAN_WORD1_REG(CAN1_BASE_PTR,4) |
| #define CAN1_CS5 CAN_CS_REG(CAN1_BASE_PTR,5) |
| #define CAN1_ID5 CAN_ID_REG(CAN1_BASE_PTR,5) |
| #define CAN1_WORD05 CAN_WORD0_REG(CAN1_BASE_PTR,5) |
| #define CAN1_WORD15 CAN_WORD1_REG(CAN1_BASE_PTR,5) |
| #define CAN1_CS6 CAN_CS_REG(CAN1_BASE_PTR,6) |
| #define CAN1_ID6 CAN_ID_REG(CAN1_BASE_PTR,6) |
| #define CAN1_WORD06 CAN_WORD0_REG(CAN1_BASE_PTR,6) |
| #define CAN1_WORD16 CAN_WORD1_REG(CAN1_BASE_PTR,6) |
| #define CAN1_CS7 CAN_CS_REG(CAN1_BASE_PTR,7) |
| #define CAN1_ID7 CAN_ID_REG(CAN1_BASE_PTR,7) |
| #define CAN1_WORD07 CAN_WORD0_REG(CAN1_BASE_PTR,7) |
| #define CAN1_WORD17 CAN_WORD1_REG(CAN1_BASE_PTR,7) |
| #define CAN1_CS8 CAN_CS_REG(CAN1_BASE_PTR,8) |
| #define CAN1_ID8 CAN_ID_REG(CAN1_BASE_PTR,8) |
| #define CAN1_WORD08 CAN_WORD0_REG(CAN1_BASE_PTR,8) |
| #define CAN1_WORD18 CAN_WORD1_REG(CAN1_BASE_PTR,8) |
| #define CAN1_CS9 CAN_CS_REG(CAN1_BASE_PTR,9) |
| #define CAN1_ID9 CAN_ID_REG(CAN1_BASE_PTR,9) |
| #define CAN1_WORD09 CAN_WORD0_REG(CAN1_BASE_PTR,9) |
| #define CAN1_WORD19 CAN_WORD1_REG(CAN1_BASE_PTR,9) |
| #define CAN1_CS10 CAN_CS_REG(CAN1_BASE_PTR,10) |
| #define CAN1_ID10 CAN_ID_REG(CAN1_BASE_PTR,10) |
| #define CAN1_WORD010 CAN_WORD0_REG(CAN1_BASE_PTR,10) |
| #define CAN1_WORD110 CAN_WORD1_REG(CAN1_BASE_PTR,10) |
| #define CAN1_CS11 CAN_CS_REG(CAN1_BASE_PTR,11) |
| #define CAN1_ID11 CAN_ID_REG(CAN1_BASE_PTR,11) |
| #define CAN1_WORD011 CAN_WORD0_REG(CAN1_BASE_PTR,11) |
| #define CAN1_WORD111 CAN_WORD1_REG(CAN1_BASE_PTR,11) |
| #define CAN1_CS12 CAN_CS_REG(CAN1_BASE_PTR,12) |
| #define CAN1_ID12 CAN_ID_REG(CAN1_BASE_PTR,12) |
| #define CAN1_WORD012 CAN_WORD0_REG(CAN1_BASE_PTR,12) |
| #define CAN1_WORD112 CAN_WORD1_REG(CAN1_BASE_PTR,12) |
| #define CAN1_CS13 CAN_CS_REG(CAN1_BASE_PTR,13) |
| #define CAN1_ID13 CAN_ID_REG(CAN1_BASE_PTR,13) |
| #define CAN1_WORD013 CAN_WORD0_REG(CAN1_BASE_PTR,13) |
| #define CAN1_WORD113 CAN_WORD1_REG(CAN1_BASE_PTR,13) |
| #define CAN1_CS14 CAN_CS_REG(CAN1_BASE_PTR,14) |
| #define CAN1_ID14 CAN_ID_REG(CAN1_BASE_PTR,14) |
| #define CAN1_WORD014 CAN_WORD0_REG(CAN1_BASE_PTR,14) |
| #define CAN1_WORD114 CAN_WORD1_REG(CAN1_BASE_PTR,14) |
| #define CAN1_CS15 CAN_CS_REG(CAN1_BASE_PTR,15) |
| #define CAN1_ID15 CAN_ID_REG(CAN1_BASE_PTR,15) |
| #define CAN1_WORD015 CAN_WORD0_REG(CAN1_BASE_PTR,15) |
| #define CAN1_WORD115 CAN_WORD1_REG(CAN1_BASE_PTR,15) |
| #define CAN1_CS16 CAN_CS_REG(CAN1_BASE_PTR,16) |
| #define CAN1_ID16 CAN_ID_REG(CAN1_BASE_PTR,16) |
| #define CAN1_WORD016 CAN_WORD0_REG(CAN1_BASE_PTR,16) |
| #define CAN1_WORD116 CAN_WORD1_REG(CAN1_BASE_PTR,16) |
| #define CAN1_CS17 CAN_CS_REG(CAN1_BASE_PTR,17) |
| #define CAN1_ID17 CAN_ID_REG(CAN1_BASE_PTR,17) |
| #define CAN1_WORD017 CAN_WORD0_REG(CAN1_BASE_PTR,17) |
| #define CAN1_WORD117 CAN_WORD1_REG(CAN1_BASE_PTR,17) |
| #define CAN1_CS18 CAN_CS_REG(CAN1_BASE_PTR,18) |
| #define CAN1_ID18 CAN_ID_REG(CAN1_BASE_PTR,18) |
| #define CAN1_WORD018 CAN_WORD0_REG(CAN1_BASE_PTR,18) |
| #define CAN1_WORD118 CAN_WORD1_REG(CAN1_BASE_PTR,18) |
| #define CAN1_CS19 CAN_CS_REG(CAN1_BASE_PTR,19) |
| #define CAN1_ID19 CAN_ID_REG(CAN1_BASE_PTR,19) |
| #define CAN1_WORD019 CAN_WORD0_REG(CAN1_BASE_PTR,19) |
| #define CAN1_WORD119 CAN_WORD1_REG(CAN1_BASE_PTR,19) |
| #define CAN1_CS20 CAN_CS_REG(CAN1_BASE_PTR,20) |
| #define CAN1_ID20 CAN_ID_REG(CAN1_BASE_PTR,20) |
| #define CAN1_WORD020 CAN_WORD0_REG(CAN1_BASE_PTR,20) |
| #define CAN1_WORD120 CAN_WORD1_REG(CAN1_BASE_PTR,20) |
| #define CAN1_CS21 CAN_CS_REG(CAN1_BASE_PTR,21) |
| #define CAN1_ID21 CAN_ID_REG(CAN1_BASE_PTR,21) |
| #define CAN1_WORD021 CAN_WORD0_REG(CAN1_BASE_PTR,21) |
| #define CAN1_WORD121 CAN_WORD1_REG(CAN1_BASE_PTR,21) |
| #define CAN1_CS22 CAN_CS_REG(CAN1_BASE_PTR,22) |
| #define CAN1_ID22 CAN_ID_REG(CAN1_BASE_PTR,22) |
| #define CAN1_WORD022 CAN_WORD0_REG(CAN1_BASE_PTR,22) |
| #define CAN1_WORD122 CAN_WORD1_REG(CAN1_BASE_PTR,22) |
| #define CAN1_CS23 CAN_CS_REG(CAN1_BASE_PTR,23) |
| #define CAN1_ID23 CAN_ID_REG(CAN1_BASE_PTR,23) |
| #define CAN1_WORD023 CAN_WORD0_REG(CAN1_BASE_PTR,23) |
| #define CAN1_WORD123 CAN_WORD1_REG(CAN1_BASE_PTR,23) |
| #define CAN1_CS24 CAN_CS_REG(CAN1_BASE_PTR,24) |
| #define CAN1_ID24 CAN_ID_REG(CAN1_BASE_PTR,24) |
| #define CAN1_WORD024 CAN_WORD0_REG(CAN1_BASE_PTR,24) |
| #define CAN1_WORD124 CAN_WORD1_REG(CAN1_BASE_PTR,24) |
| #define CAN1_CS25 CAN_CS_REG(CAN1_BASE_PTR,25) |
| #define CAN1_ID25 CAN_ID_REG(CAN1_BASE_PTR,25) |
| #define CAN1_WORD025 CAN_WORD0_REG(CAN1_BASE_PTR,25) |
| #define CAN1_WORD125 CAN_WORD1_REG(CAN1_BASE_PTR,25) |
| #define CAN1_CS26 CAN_CS_REG(CAN1_BASE_PTR,26) |
| #define CAN1_ID26 CAN_ID_REG(CAN1_BASE_PTR,26) |
| #define CAN1_WORD026 CAN_WORD0_REG(CAN1_BASE_PTR,26) |
| #define CAN1_WORD126 CAN_WORD1_REG(CAN1_BASE_PTR,26) |
| #define CAN1_CS27 CAN_CS_REG(CAN1_BASE_PTR,27) |
| #define CAN1_ID27 CAN_ID_REG(CAN1_BASE_PTR,27) |
| #define CAN1_WORD027 CAN_WORD0_REG(CAN1_BASE_PTR,27) |
| #define CAN1_WORD127 CAN_WORD1_REG(CAN1_BASE_PTR,27) |
| #define CAN1_CS28 CAN_CS_REG(CAN1_BASE_PTR,28) |
| #define CAN1_ID28 CAN_ID_REG(CAN1_BASE_PTR,28) |
| #define CAN1_WORD028 CAN_WORD0_REG(CAN1_BASE_PTR,28) |
| #define CAN1_WORD128 CAN_WORD1_REG(CAN1_BASE_PTR,28) |
| #define CAN1_CS29 CAN_CS_REG(CAN1_BASE_PTR,29) |
| #define CAN1_ID29 CAN_ID_REG(CAN1_BASE_PTR,29) |
| #define CAN1_WORD029 CAN_WORD0_REG(CAN1_BASE_PTR,29) |
| #define CAN1_WORD129 CAN_WORD1_REG(CAN1_BASE_PTR,29) |
| #define CAN1_CS30 CAN_CS_REG(CAN1_BASE_PTR,30) |
| #define CAN1_ID30 CAN_ID_REG(CAN1_BASE_PTR,30) |
| #define CAN1_WORD030 CAN_WORD0_REG(CAN1_BASE_PTR,30) |
| #define CAN1_WORD130 CAN_WORD1_REG(CAN1_BASE_PTR,30) |
| #define CAN1_CS31 CAN_CS_REG(CAN1_BASE_PTR,31) |
| #define CAN1_ID31 CAN_ID_REG(CAN1_BASE_PTR,31) |
| #define CAN1_WORD031 CAN_WORD0_REG(CAN1_BASE_PTR,31) |
| #define CAN1_WORD131 CAN_WORD1_REG(CAN1_BASE_PTR,31) |
| #define CAN1_CS32 CAN_CS_REG(CAN1_BASE_PTR,32) |
| #define CAN1_ID32 CAN_ID_REG(CAN1_BASE_PTR,32) |
| #define CAN1_WORD032 CAN_WORD0_REG(CAN1_BASE_PTR,32) |
| #define CAN1_WORD132 CAN_WORD1_REG(CAN1_BASE_PTR,32) |
| #define CAN1_CS33 CAN_CS_REG(CAN1_BASE_PTR,33) |
| #define CAN1_ID33 CAN_ID_REG(CAN1_BASE_PTR,33) |
| #define CAN1_WORD033 CAN_WORD0_REG(CAN1_BASE_PTR,33) |
| #define CAN1_WORD133 CAN_WORD1_REG(CAN1_BASE_PTR,33) |
| #define CAN1_CS34 CAN_CS_REG(CAN1_BASE_PTR,34) |
| #define CAN1_ID34 CAN_ID_REG(CAN1_BASE_PTR,34) |
| #define CAN1_WORD034 CAN_WORD0_REG(CAN1_BASE_PTR,34) |
| #define CAN1_WORD134 CAN_WORD1_REG(CAN1_BASE_PTR,34) |
| #define CAN1_CS35 CAN_CS_REG(CAN1_BASE_PTR,35) |
| #define CAN1_ID35 CAN_ID_REG(CAN1_BASE_PTR,35) |
| #define CAN1_WORD035 CAN_WORD0_REG(CAN1_BASE_PTR,35) |
| #define CAN1_WORD135 CAN_WORD1_REG(CAN1_BASE_PTR,35) |
| #define CAN1_CS36 CAN_CS_REG(CAN1_BASE_PTR,36) |
| #define CAN1_ID36 CAN_ID_REG(CAN1_BASE_PTR,36) |
| #define CAN1_WORD036 CAN_WORD0_REG(CAN1_BASE_PTR,36) |
| #define CAN1_WORD136 CAN_WORD1_REG(CAN1_BASE_PTR,36) |
| #define CAN1_CS37 CAN_CS_REG(CAN1_BASE_PTR,37) |
| #define CAN1_ID37 CAN_ID_REG(CAN1_BASE_PTR,37) |
| #define CAN1_WORD037 CAN_WORD0_REG(CAN1_BASE_PTR,37) |
| #define CAN1_WORD137 CAN_WORD1_REG(CAN1_BASE_PTR,37) |
| #define CAN1_CS38 CAN_CS_REG(CAN1_BASE_PTR,38) |
| #define CAN1_ID38 CAN_ID_REG(CAN1_BASE_PTR,38) |
| #define CAN1_WORD038 CAN_WORD0_REG(CAN1_BASE_PTR,38) |
| #define CAN1_WORD138 CAN_WORD1_REG(CAN1_BASE_PTR,38) |
| #define CAN1_CS39 CAN_CS_REG(CAN1_BASE_PTR,39) |
| #define CAN1_ID39 CAN_ID_REG(CAN1_BASE_PTR,39) |
| #define CAN1_WORD039 CAN_WORD0_REG(CAN1_BASE_PTR,39) |
| #define CAN1_WORD139 CAN_WORD1_REG(CAN1_BASE_PTR,39) |
| #define CAN1_CS40 CAN_CS_REG(CAN1_BASE_PTR,40) |
| #define CAN1_ID40 CAN_ID_REG(CAN1_BASE_PTR,40) |
| #define CAN1_WORD040 CAN_WORD0_REG(CAN1_BASE_PTR,40) |
| #define CAN1_WORD140 CAN_WORD1_REG(CAN1_BASE_PTR,40) |
| #define CAN1_CS41 CAN_CS_REG(CAN1_BASE_PTR,41) |
| #define CAN1_ID41 CAN_ID_REG(CAN1_BASE_PTR,41) |
| #define CAN1_WORD041 CAN_WORD0_REG(CAN1_BASE_PTR,41) |
| #define CAN1_WORD141 CAN_WORD1_REG(CAN1_BASE_PTR,41) |
| #define CAN1_CS42 CAN_CS_REG(CAN1_BASE_PTR,42) |
| #define CAN1_ID42 CAN_ID_REG(CAN1_BASE_PTR,42) |
| #define CAN1_WORD042 CAN_WORD0_REG(CAN1_BASE_PTR,42) |
| #define CAN1_WORD142 CAN_WORD1_REG(CAN1_BASE_PTR,42) |
| #define CAN1_CS43 CAN_CS_REG(CAN1_BASE_PTR,43) |
| #define CAN1_ID43 CAN_ID_REG(CAN1_BASE_PTR,43) |
| #define CAN1_WORD043 CAN_WORD0_REG(CAN1_BASE_PTR,43) |
| #define CAN1_WORD143 CAN_WORD1_REG(CAN1_BASE_PTR,43) |
| #define CAN1_CS44 CAN_CS_REG(CAN1_BASE_PTR,44) |
| #define CAN1_ID44 CAN_ID_REG(CAN1_BASE_PTR,44) |
| #define CAN1_WORD044 CAN_WORD0_REG(CAN1_BASE_PTR,44) |
| #define CAN1_WORD144 CAN_WORD1_REG(CAN1_BASE_PTR,44) |
| #define CAN1_CS45 CAN_CS_REG(CAN1_BASE_PTR,45) |
| #define CAN1_ID45 CAN_ID_REG(CAN1_BASE_PTR,45) |
| #define CAN1_WORD045 CAN_WORD0_REG(CAN1_BASE_PTR,45) |
| #define CAN1_WORD145 CAN_WORD1_REG(CAN1_BASE_PTR,45) |
| #define CAN1_CS46 CAN_CS_REG(CAN1_BASE_PTR,46) |
| #define CAN1_ID46 CAN_ID_REG(CAN1_BASE_PTR,46) |
| #define CAN1_WORD046 CAN_WORD0_REG(CAN1_BASE_PTR,46) |
| #define CAN1_WORD146 CAN_WORD1_REG(CAN1_BASE_PTR,46) |
| #define CAN1_CS47 CAN_CS_REG(CAN1_BASE_PTR,47) |
| #define CAN1_ID47 CAN_ID_REG(CAN1_BASE_PTR,47) |
| #define CAN1_WORD047 CAN_WORD0_REG(CAN1_BASE_PTR,47) |
| #define CAN1_WORD147 CAN_WORD1_REG(CAN1_BASE_PTR,47) |
| #define CAN1_CS48 CAN_CS_REG(CAN1_BASE_PTR,48) |
| #define CAN1_ID48 CAN_ID_REG(CAN1_BASE_PTR,48) |
| #define CAN1_WORD048 CAN_WORD0_REG(CAN1_BASE_PTR,48) |
| #define CAN1_WORD148 CAN_WORD1_REG(CAN1_BASE_PTR,48) |
| #define CAN1_CS49 CAN_CS_REG(CAN1_BASE_PTR,49) |
| #define CAN1_ID49 CAN_ID_REG(CAN1_BASE_PTR,49) |
| #define CAN1_WORD049 CAN_WORD0_REG(CAN1_BASE_PTR,49) |
| #define CAN1_WORD149 CAN_WORD1_REG(CAN1_BASE_PTR,49) |
| #define CAN1_CS50 CAN_CS_REG(CAN1_BASE_PTR,50) |
| #define CAN1_ID50 CAN_ID_REG(CAN1_BASE_PTR,50) |
| #define CAN1_WORD050 CAN_WORD0_REG(CAN1_BASE_PTR,50) |
| #define CAN1_WORD150 CAN_WORD1_REG(CAN1_BASE_PTR,50) |
| #define CAN1_CS51 CAN_CS_REG(CAN1_BASE_PTR,51) |
| #define CAN1_ID51 CAN_ID_REG(CAN1_BASE_PTR,51) |
| #define CAN1_WORD051 CAN_WORD0_REG(CAN1_BASE_PTR,51) |
| #define CAN1_WORD151 CAN_WORD1_REG(CAN1_BASE_PTR,51) |
| #define CAN1_CS52 CAN_CS_REG(CAN1_BASE_PTR,52) |
| #define CAN1_ID52 CAN_ID_REG(CAN1_BASE_PTR,52) |
| #define CAN1_WORD052 CAN_WORD0_REG(CAN1_BASE_PTR,52) |
| #define CAN1_WORD152 CAN_WORD1_REG(CAN1_BASE_PTR,52) |
| #define CAN1_CS53 CAN_CS_REG(CAN1_BASE_PTR,53) |
| #define CAN1_ID53 CAN_ID_REG(CAN1_BASE_PTR,53) |
| #define CAN1_WORD053 CAN_WORD0_REG(CAN1_BASE_PTR,53) |
| #define CAN1_WORD153 CAN_WORD1_REG(CAN1_BASE_PTR,53) |
| #define CAN1_CS54 CAN_CS_REG(CAN1_BASE_PTR,54) |
| #define CAN1_ID54 CAN_ID_REG(CAN1_BASE_PTR,54) |
| #define CAN1_WORD054 CAN_WORD0_REG(CAN1_BASE_PTR,54) |
| #define CAN1_WORD154 CAN_WORD1_REG(CAN1_BASE_PTR,54) |
| #define CAN1_CS55 CAN_CS_REG(CAN1_BASE_PTR,55) |
| #define CAN1_ID55 CAN_ID_REG(CAN1_BASE_PTR,55) |
| #define CAN1_WORD055 CAN_WORD0_REG(CAN1_BASE_PTR,55) |
| #define CAN1_WORD155 CAN_WORD1_REG(CAN1_BASE_PTR,55) |
| #define CAN1_CS56 CAN_CS_REG(CAN1_BASE_PTR,56) |
| #define CAN1_ID56 CAN_ID_REG(CAN1_BASE_PTR,56) |
| #define CAN1_WORD056 CAN_WORD0_REG(CAN1_BASE_PTR,56) |
| #define CAN1_WORD156 CAN_WORD1_REG(CAN1_BASE_PTR,56) |
| #define CAN1_CS57 CAN_CS_REG(CAN1_BASE_PTR,57) |
| #define CAN1_ID57 CAN_ID_REG(CAN1_BASE_PTR,57) |
| #define CAN1_WORD057 CAN_WORD0_REG(CAN1_BASE_PTR,57) |
| #define CAN1_WORD157 CAN_WORD1_REG(CAN1_BASE_PTR,57) |
| #define CAN1_CS58 CAN_CS_REG(CAN1_BASE_PTR,58) |
| #define CAN1_ID58 CAN_ID_REG(CAN1_BASE_PTR,58) |
| #define CAN1_WORD058 CAN_WORD0_REG(CAN1_BASE_PTR,58) |
| #define CAN1_WORD158 CAN_WORD1_REG(CAN1_BASE_PTR,58) |
| #define CAN1_CS59 CAN_CS_REG(CAN1_BASE_PTR,59) |
| #define CAN1_ID59 CAN_ID_REG(CAN1_BASE_PTR,59) |
| #define CAN1_WORD059 CAN_WORD0_REG(CAN1_BASE_PTR,59) |
| #define CAN1_WORD159 CAN_WORD1_REG(CAN1_BASE_PTR,59) |
| #define CAN1_CS60 CAN_CS_REG(CAN1_BASE_PTR,60) |
| #define CAN1_ID60 CAN_ID_REG(CAN1_BASE_PTR,60) |
| #define CAN1_WORD060 CAN_WORD0_REG(CAN1_BASE_PTR,60) |
| #define CAN1_WORD160 CAN_WORD1_REG(CAN1_BASE_PTR,60) |
| #define CAN1_CS61 CAN_CS_REG(CAN1_BASE_PTR,61) |
| #define CAN1_ID61 CAN_ID_REG(CAN1_BASE_PTR,61) |
| #define CAN1_WORD061 CAN_WORD0_REG(CAN1_BASE_PTR,61) |
| #define CAN1_WORD161 CAN_WORD1_REG(CAN1_BASE_PTR,61) |
| #define CAN1_CS62 CAN_CS_REG(CAN1_BASE_PTR,62) |
| #define CAN1_ID62 CAN_ID_REG(CAN1_BASE_PTR,62) |
| #define CAN1_WORD062 CAN_WORD0_REG(CAN1_BASE_PTR,62) |
| #define CAN1_WORD162 CAN_WORD1_REG(CAN1_BASE_PTR,62) |
| #define CAN1_CS63 CAN_CS_REG(CAN1_BASE_PTR,63) |
| #define CAN1_ID63 CAN_ID_REG(CAN1_BASE_PTR,63) |
| #define CAN1_WORD063 CAN_WORD0_REG(CAN1_BASE_PTR,63) |
| #define CAN1_WORD163 CAN_WORD1_REG(CAN1_BASE_PTR,63) |
| #define CAN1_RXIMR0 CAN_RXIMR_REG(CAN1_BASE_PTR,0) |
| #define CAN1_RXIMR1 CAN_RXIMR_REG(CAN1_BASE_PTR,1) |
| #define CAN1_RXIMR2 CAN_RXIMR_REG(CAN1_BASE_PTR,2) |
| #define CAN1_RXIMR3 CAN_RXIMR_REG(CAN1_BASE_PTR,3) |
| #define CAN1_RXIMR4 CAN_RXIMR_REG(CAN1_BASE_PTR,4) |
| #define CAN1_RXIMR5 CAN_RXIMR_REG(CAN1_BASE_PTR,5) |
| #define CAN1_RXIMR6 CAN_RXIMR_REG(CAN1_BASE_PTR,6) |
| #define CAN1_RXIMR7 CAN_RXIMR_REG(CAN1_BASE_PTR,7) |
| #define CAN1_RXIMR8 CAN_RXIMR_REG(CAN1_BASE_PTR,8) |
| #define CAN1_RXIMR9 CAN_RXIMR_REG(CAN1_BASE_PTR,9) |
| #define CAN1_RXIMR10 CAN_RXIMR_REG(CAN1_BASE_PTR,10) |
| #define CAN1_RXIMR11 CAN_RXIMR_REG(CAN1_BASE_PTR,11) |
| #define CAN1_RXIMR12 CAN_RXIMR_REG(CAN1_BASE_PTR,12) |
| #define CAN1_RXIMR13 CAN_RXIMR_REG(CAN1_BASE_PTR,13) |
| #define CAN1_RXIMR14 CAN_RXIMR_REG(CAN1_BASE_PTR,14) |
| #define CAN1_RXIMR15 CAN_RXIMR_REG(CAN1_BASE_PTR,15) |
| #define CAN1_RXIMR16 CAN_RXIMR_REG(CAN1_BASE_PTR,16) |
| #define CAN1_RXIMR17 CAN_RXIMR_REG(CAN1_BASE_PTR,17) |
| #define CAN1_RXIMR18 CAN_RXIMR_REG(CAN1_BASE_PTR,18) |
| #define CAN1_RXIMR19 CAN_RXIMR_REG(CAN1_BASE_PTR,19) |
| #define CAN1_RXIMR20 CAN_RXIMR_REG(CAN1_BASE_PTR,20) |
| #define CAN1_RXIMR21 CAN_RXIMR_REG(CAN1_BASE_PTR,21) |
| #define CAN1_RXIMR22 CAN_RXIMR_REG(CAN1_BASE_PTR,22) |
| #define CAN1_RXIMR23 CAN_RXIMR_REG(CAN1_BASE_PTR,23) |
| #define CAN1_RXIMR24 CAN_RXIMR_REG(CAN1_BASE_PTR,24) |
| #define CAN1_RXIMR25 CAN_RXIMR_REG(CAN1_BASE_PTR,25) |
| #define CAN1_RXIMR26 CAN_RXIMR_REG(CAN1_BASE_PTR,26) |
| #define CAN1_RXIMR27 CAN_RXIMR_REG(CAN1_BASE_PTR,27) |
| #define CAN1_RXIMR28 CAN_RXIMR_REG(CAN1_BASE_PTR,28) |
| #define CAN1_RXIMR29 CAN_RXIMR_REG(CAN1_BASE_PTR,29) |
| #define CAN1_RXIMR30 CAN_RXIMR_REG(CAN1_BASE_PTR,30) |
| #define CAN1_RXIMR31 CAN_RXIMR_REG(CAN1_BASE_PTR,31) |
| #define CAN1_RXIMR32 CAN_RXIMR_REG(CAN1_BASE_PTR,32) |
| #define CAN1_RXIMR33 CAN_RXIMR_REG(CAN1_BASE_PTR,33) |
| #define CAN1_RXIMR34 CAN_RXIMR_REG(CAN1_BASE_PTR,34) |
| #define CAN1_RXIMR35 CAN_RXIMR_REG(CAN1_BASE_PTR,35) |
| #define CAN1_RXIMR36 CAN_RXIMR_REG(CAN1_BASE_PTR,36) |
| #define CAN1_RXIMR37 CAN_RXIMR_REG(CAN1_BASE_PTR,37) |
| #define CAN1_RXIMR38 CAN_RXIMR_REG(CAN1_BASE_PTR,38) |
| #define CAN1_RXIMR39 CAN_RXIMR_REG(CAN1_BASE_PTR,39) |
| #define CAN1_RXIMR40 CAN_RXIMR_REG(CAN1_BASE_PTR,40) |
| #define CAN1_RXIMR41 CAN_RXIMR_REG(CAN1_BASE_PTR,41) |
| #define CAN1_RXIMR42 CAN_RXIMR_REG(CAN1_BASE_PTR,42) |
| #define CAN1_RXIMR43 CAN_RXIMR_REG(CAN1_BASE_PTR,43) |
| #define CAN1_RXIMR44 CAN_RXIMR_REG(CAN1_BASE_PTR,44) |
| #define CAN1_RXIMR45 CAN_RXIMR_REG(CAN1_BASE_PTR,45) |
| #define CAN1_RXIMR46 CAN_RXIMR_REG(CAN1_BASE_PTR,46) |
| #define CAN1_RXIMR47 CAN_RXIMR_REG(CAN1_BASE_PTR,47) |
| #define CAN1_RXIMR48 CAN_RXIMR_REG(CAN1_BASE_PTR,48) |
| #define CAN1_RXIMR49 CAN_RXIMR_REG(CAN1_BASE_PTR,49) |
| #define CAN1_RXIMR50 CAN_RXIMR_REG(CAN1_BASE_PTR,50) |
| #define CAN1_RXIMR51 CAN_RXIMR_REG(CAN1_BASE_PTR,51) |
| #define CAN1_RXIMR52 CAN_RXIMR_REG(CAN1_BASE_PTR,52) |
| #define CAN1_RXIMR53 CAN_RXIMR_REG(CAN1_BASE_PTR,53) |
| #define CAN1_RXIMR54 CAN_RXIMR_REG(CAN1_BASE_PTR,54) |
| #define CAN1_RXIMR55 CAN_RXIMR_REG(CAN1_BASE_PTR,55) |
| #define CAN1_RXIMR56 CAN_RXIMR_REG(CAN1_BASE_PTR,56) |
| #define CAN1_RXIMR57 CAN_RXIMR_REG(CAN1_BASE_PTR,57) |
| #define CAN1_RXIMR58 CAN_RXIMR_REG(CAN1_BASE_PTR,58) |
| #define CAN1_RXIMR59 CAN_RXIMR_REG(CAN1_BASE_PTR,59) |
| #define CAN1_RXIMR60 CAN_RXIMR_REG(CAN1_BASE_PTR,60) |
| #define CAN1_RXIMR61 CAN_RXIMR_REG(CAN1_BASE_PTR,61) |
| #define CAN1_RXIMR62 CAN_RXIMR_REG(CAN1_BASE_PTR,62) |
| #define CAN1_RXIMR63 CAN_RXIMR_REG(CAN1_BASE_PTR,63) |
| #define CAN1_GFWR CAN_GFWR_REG(CAN1_BASE_PTR) |
| /* CAN2 */ |
| #define CAN2_MCR CAN_MCR_REG(CAN2_BASE_PTR) |
| #define CAN2_CTRL1 CAN_CTRL1_REG(CAN2_BASE_PTR) |
| #define CAN2_TIMER CAN_TIMER_REG(CAN2_BASE_PTR) |
| #define CAN2_RXMGMASK CAN_RXMGMASK_REG(CAN2_BASE_PTR) |
| #define CAN2_RX14MASK CAN_RX14MASK_REG(CAN2_BASE_PTR) |
| #define CAN2_RX15MASK CAN_RX15MASK_REG(CAN2_BASE_PTR) |
| #define CAN2_ECR CAN_ECR_REG(CAN2_BASE_PTR) |
| #define CAN2_ESR1 CAN_ESR1_REG(CAN2_BASE_PTR) |
| #define CAN2_IMASK2 CAN_IMASK2_REG(CAN2_BASE_PTR) |
| #define CAN2_IMASK1 CAN_IMASK1_REG(CAN2_BASE_PTR) |
| #define CAN2_IFLAG2 CAN_IFLAG2_REG(CAN2_BASE_PTR) |
| #define CAN2_IFLAG1 CAN_IFLAG1_REG(CAN2_BASE_PTR) |
| #define CAN2_CTRL2 CAN_CTRL2_REG(CAN2_BASE_PTR) |
| #define CAN2_ESR2 CAN_ESR2_REG(CAN2_BASE_PTR) |
| #define CAN2_CRCR CAN_CRCR_REG(CAN2_BASE_PTR) |
| #define CAN2_RXFGMASK CAN_RXFGMASK_REG(CAN2_BASE_PTR) |
| #define CAN2_RXFIR CAN_RXFIR_REG(CAN2_BASE_PTR) |
| #define CAN2_CS0 CAN_CS_REG(CAN2_BASE_PTR,0) |
| #define CAN2_ID0 CAN_ID_REG(CAN2_BASE_PTR,0) |
| #define CAN2_WORD00 CAN_WORD0_REG(CAN2_BASE_PTR,0) |
| #define CAN2_WORD10 CAN_WORD1_REG(CAN2_BASE_PTR,0) |
| #define CAN2_CS1 CAN_CS_REG(CAN2_BASE_PTR,1) |
| #define CAN2_ID1 CAN_ID_REG(CAN2_BASE_PTR,1) |
| #define CAN2_WORD01 CAN_WORD0_REG(CAN2_BASE_PTR,1) |
| #define CAN2_WORD11 CAN_WORD1_REG(CAN2_BASE_PTR,1) |
| #define CAN2_CS2 CAN_CS_REG(CAN2_BASE_PTR,2) |
| #define CAN2_ID2 CAN_ID_REG(CAN2_BASE_PTR,2) |
| #define CAN2_WORD02 CAN_WORD0_REG(CAN2_BASE_PTR,2) |
| #define CAN2_WORD12 CAN_WORD1_REG(CAN2_BASE_PTR,2) |
| #define CAN2_CS3 CAN_CS_REG(CAN2_BASE_PTR,3) |
| #define CAN2_ID3 CAN_ID_REG(CAN2_BASE_PTR,3) |
| #define CAN2_WORD03 CAN_WORD0_REG(CAN2_BASE_PTR,3) |
| #define CAN2_WORD13 CAN_WORD1_REG(CAN2_BASE_PTR,3) |
| #define CAN2_CS4 CAN_CS_REG(CAN2_BASE_PTR,4) |
| #define CAN2_ID4 CAN_ID_REG(CAN2_BASE_PTR,4) |
| #define CAN2_WORD04 CAN_WORD0_REG(CAN2_BASE_PTR,4) |
| #define CAN2_WORD14 CAN_WORD1_REG(CAN2_BASE_PTR,4) |
| #define CAN2_CS5 CAN_CS_REG(CAN2_BASE_PTR,5) |
| #define CAN2_ID5 CAN_ID_REG(CAN2_BASE_PTR,5) |
| #define CAN2_WORD05 CAN_WORD0_REG(CAN2_BASE_PTR,5) |
| #define CAN2_WORD15 CAN_WORD1_REG(CAN2_BASE_PTR,5) |
| #define CAN2_CS6 CAN_CS_REG(CAN2_BASE_PTR,6) |
| #define CAN2_ID6 CAN_ID_REG(CAN2_BASE_PTR,6) |
| #define CAN2_WORD06 CAN_WORD0_REG(CAN2_BASE_PTR,6) |
| #define CAN2_WORD16 CAN_WORD1_REG(CAN2_BASE_PTR,6) |
| #define CAN2_CS7 CAN_CS_REG(CAN2_BASE_PTR,7) |
| #define CAN2_ID7 CAN_ID_REG(CAN2_BASE_PTR,7) |
| #define CAN2_WORD07 CAN_WORD0_REG(CAN2_BASE_PTR,7) |
| #define CAN2_WORD17 CAN_WORD1_REG(CAN2_BASE_PTR,7) |
| #define CAN2_CS8 CAN_CS_REG(CAN2_BASE_PTR,8) |
| #define CAN2_ID8 CAN_ID_REG(CAN2_BASE_PTR,8) |
| #define CAN2_WORD08 CAN_WORD0_REG(CAN2_BASE_PTR,8) |
| #define CAN2_WORD18 CAN_WORD1_REG(CAN2_BASE_PTR,8) |
| #define CAN2_CS9 CAN_CS_REG(CAN2_BASE_PTR,9) |
| #define CAN2_ID9 CAN_ID_REG(CAN2_BASE_PTR,9) |
| #define CAN2_WORD09 CAN_WORD0_REG(CAN2_BASE_PTR,9) |
| #define CAN2_WORD19 CAN_WORD1_REG(CAN2_BASE_PTR,9) |
| #define CAN2_CS10 CAN_CS_REG(CAN2_BASE_PTR,10) |
| #define CAN2_ID10 CAN_ID_REG(CAN2_BASE_PTR,10) |
| #define CAN2_WORD010 CAN_WORD0_REG(CAN2_BASE_PTR,10) |
| #define CAN2_WORD110 CAN_WORD1_REG(CAN2_BASE_PTR,10) |
| #define CAN2_CS11 CAN_CS_REG(CAN2_BASE_PTR,11) |
| #define CAN2_ID11 CAN_ID_REG(CAN2_BASE_PTR,11) |
| #define CAN2_WORD011 CAN_WORD0_REG(CAN2_BASE_PTR,11) |
| #define CAN2_WORD111 CAN_WORD1_REG(CAN2_BASE_PTR,11) |
| #define CAN2_CS12 CAN_CS_REG(CAN2_BASE_PTR,12) |
| #define CAN2_ID12 CAN_ID_REG(CAN2_BASE_PTR,12) |
| #define CAN2_WORD012 CAN_WORD0_REG(CAN2_BASE_PTR,12) |
| #define CAN2_WORD112 CAN_WORD1_REG(CAN2_BASE_PTR,12) |
| #define CAN2_CS13 CAN_CS_REG(CAN2_BASE_PTR,13) |
| #define CAN2_ID13 CAN_ID_REG(CAN2_BASE_PTR,13) |
| #define CAN2_WORD013 CAN_WORD0_REG(CAN2_BASE_PTR,13) |
| #define CAN2_WORD113 CAN_WORD1_REG(CAN2_BASE_PTR,13) |
| #define CAN2_CS14 CAN_CS_REG(CAN2_BASE_PTR,14) |
| #define CAN2_ID14 CAN_ID_REG(CAN2_BASE_PTR,14) |
| #define CAN2_WORD014 CAN_WORD0_REG(CAN2_BASE_PTR,14) |
| #define CAN2_WORD114 CAN_WORD1_REG(CAN2_BASE_PTR,14) |
| #define CAN2_CS15 CAN_CS_REG(CAN2_BASE_PTR,15) |
| #define CAN2_ID15 CAN_ID_REG(CAN2_BASE_PTR,15) |
| #define CAN2_WORD015 CAN_WORD0_REG(CAN2_BASE_PTR,15) |
| #define CAN2_WORD115 CAN_WORD1_REG(CAN2_BASE_PTR,15) |
| #define CAN2_CS16 CAN_CS_REG(CAN2_BASE_PTR,16) |
| #define CAN2_ID16 CAN_ID_REG(CAN2_BASE_PTR,16) |
| #define CAN2_WORD016 CAN_WORD0_REG(CAN2_BASE_PTR,16) |
| #define CAN2_WORD116 CAN_WORD1_REG(CAN2_BASE_PTR,16) |
| #define CAN2_CS17 CAN_CS_REG(CAN2_BASE_PTR,17) |
| #define CAN2_ID17 CAN_ID_REG(CAN2_BASE_PTR,17) |
| #define CAN2_WORD017 CAN_WORD0_REG(CAN2_BASE_PTR,17) |
| #define CAN2_WORD117 CAN_WORD1_REG(CAN2_BASE_PTR,17) |
| #define CAN2_CS18 CAN_CS_REG(CAN2_BASE_PTR,18) |
| #define CAN2_ID18 CAN_ID_REG(CAN2_BASE_PTR,18) |
| #define CAN2_WORD018 CAN_WORD0_REG(CAN2_BASE_PTR,18) |
| #define CAN2_WORD118 CAN_WORD1_REG(CAN2_BASE_PTR,18) |
| #define CAN2_CS19 CAN_CS_REG(CAN2_BASE_PTR,19) |
| #define CAN2_ID19 CAN_ID_REG(CAN2_BASE_PTR,19) |
| #define CAN2_WORD019 CAN_WORD0_REG(CAN2_BASE_PTR,19) |
| #define CAN2_WORD119 CAN_WORD1_REG(CAN2_BASE_PTR,19) |
| #define CAN2_CS20 CAN_CS_REG(CAN2_BASE_PTR,20) |
| #define CAN2_ID20 CAN_ID_REG(CAN2_BASE_PTR,20) |
| #define CAN2_WORD020 CAN_WORD0_REG(CAN2_BASE_PTR,20) |
| #define CAN2_WORD120 CAN_WORD1_REG(CAN2_BASE_PTR,20) |
| #define CAN2_CS21 CAN_CS_REG(CAN2_BASE_PTR,21) |
| #define CAN2_ID21 CAN_ID_REG(CAN2_BASE_PTR,21) |
| #define CAN2_WORD021 CAN_WORD0_REG(CAN2_BASE_PTR,21) |
| #define CAN2_WORD121 CAN_WORD1_REG(CAN2_BASE_PTR,21) |
| #define CAN2_CS22 CAN_CS_REG(CAN2_BASE_PTR,22) |
| #define CAN2_ID22 CAN_ID_REG(CAN2_BASE_PTR,22) |
| #define CAN2_WORD022 CAN_WORD0_REG(CAN2_BASE_PTR,22) |
| #define CAN2_WORD122 CAN_WORD1_REG(CAN2_BASE_PTR,22) |
| #define CAN2_CS23 CAN_CS_REG(CAN2_BASE_PTR,23) |
| #define CAN2_ID23 CAN_ID_REG(CAN2_BASE_PTR,23) |
| #define CAN2_WORD023 CAN_WORD0_REG(CAN2_BASE_PTR,23) |
| #define CAN2_WORD123 CAN_WORD1_REG(CAN2_BASE_PTR,23) |
| #define CAN2_CS24 CAN_CS_REG(CAN2_BASE_PTR,24) |
| #define CAN2_ID24 CAN_ID_REG(CAN2_BASE_PTR,24) |
| #define CAN2_WORD024 CAN_WORD0_REG(CAN2_BASE_PTR,24) |
| #define CAN2_WORD124 CAN_WORD1_REG(CAN2_BASE_PTR,24) |
| #define CAN2_CS25 CAN_CS_REG(CAN2_BASE_PTR,25) |
| #define CAN2_ID25 CAN_ID_REG(CAN2_BASE_PTR,25) |
| #define CAN2_WORD025 CAN_WORD0_REG(CAN2_BASE_PTR,25) |
| #define CAN2_WORD125 CAN_WORD1_REG(CAN2_BASE_PTR,25) |
| #define CAN2_CS26 CAN_CS_REG(CAN2_BASE_PTR,26) |
| #define CAN2_ID26 CAN_ID_REG(CAN2_BASE_PTR,26) |
| #define CAN2_WORD026 CAN_WORD0_REG(CAN2_BASE_PTR,26) |
| #define CAN2_WORD126 CAN_WORD1_REG(CAN2_BASE_PTR,26) |
| #define CAN2_CS27 CAN_CS_REG(CAN2_BASE_PTR,27) |
| #define CAN2_ID27 CAN_ID_REG(CAN2_BASE_PTR,27) |
| #define CAN2_WORD027 CAN_WORD0_REG(CAN2_BASE_PTR,27) |
| #define CAN2_WORD127 CAN_WORD1_REG(CAN2_BASE_PTR,27) |
| #define CAN2_CS28 CAN_CS_REG(CAN2_BASE_PTR,28) |
| #define CAN2_ID28 CAN_ID_REG(CAN2_BASE_PTR,28) |
| #define CAN2_WORD028 CAN_WORD0_REG(CAN2_BASE_PTR,28) |
| #define CAN2_WORD128 CAN_WORD1_REG(CAN2_BASE_PTR,28) |
| #define CAN2_CS29 CAN_CS_REG(CAN2_BASE_PTR,29) |
| #define CAN2_ID29 CAN_ID_REG(CAN2_BASE_PTR,29) |
| #define CAN2_WORD029 CAN_WORD0_REG(CAN2_BASE_PTR,29) |
| #define CAN2_WORD129 CAN_WORD1_REG(CAN2_BASE_PTR,29) |
| #define CAN2_CS30 CAN_CS_REG(CAN2_BASE_PTR,30) |
| #define CAN2_ID30 CAN_ID_REG(CAN2_BASE_PTR,30) |
| #define CAN2_WORD030 CAN_WORD0_REG(CAN2_BASE_PTR,30) |
| #define CAN2_WORD130 CAN_WORD1_REG(CAN2_BASE_PTR,30) |
| #define CAN2_CS31 CAN_CS_REG(CAN2_BASE_PTR,31) |
| #define CAN2_ID31 CAN_ID_REG(CAN2_BASE_PTR,31) |
| #define CAN2_WORD031 CAN_WORD0_REG(CAN2_BASE_PTR,31) |
| #define CAN2_WORD131 CAN_WORD1_REG(CAN2_BASE_PTR,31) |
| #define CAN2_CS32 CAN_CS_REG(CAN2_BASE_PTR,32) |
| #define CAN2_ID32 CAN_ID_REG(CAN2_BASE_PTR,32) |
| #define CAN2_WORD032 CAN_WORD0_REG(CAN2_BASE_PTR,32) |
| #define CAN2_WORD132 CAN_WORD1_REG(CAN2_BASE_PTR,32) |
| #define CAN2_CS33 CAN_CS_REG(CAN2_BASE_PTR,33) |
| #define CAN2_ID33 CAN_ID_REG(CAN2_BASE_PTR,33) |
| #define CAN2_WORD033 CAN_WORD0_REG(CAN2_BASE_PTR,33) |
| #define CAN2_WORD133 CAN_WORD1_REG(CAN2_BASE_PTR,33) |
| #define CAN2_CS34 CAN_CS_REG(CAN2_BASE_PTR,34) |
| #define CAN2_ID34 CAN_ID_REG(CAN2_BASE_PTR,34) |
| #define CAN2_WORD034 CAN_WORD0_REG(CAN2_BASE_PTR,34) |
| #define CAN2_WORD134 CAN_WORD1_REG(CAN2_BASE_PTR,34) |
| #define CAN2_CS35 CAN_CS_REG(CAN2_BASE_PTR,35) |
| #define CAN2_ID35 CAN_ID_REG(CAN2_BASE_PTR,35) |
| #define CAN2_WORD035 CAN_WORD0_REG(CAN2_BASE_PTR,35) |
| #define CAN2_WORD135 CAN_WORD1_REG(CAN2_BASE_PTR,35) |
| #define CAN2_CS36 CAN_CS_REG(CAN2_BASE_PTR,36) |
| #define CAN2_ID36 CAN_ID_REG(CAN2_BASE_PTR,36) |
| #define CAN2_WORD036 CAN_WORD0_REG(CAN2_BASE_PTR,36) |
| #define CAN2_WORD136 CAN_WORD1_REG(CAN2_BASE_PTR,36) |
| #define CAN2_CS37 CAN_CS_REG(CAN2_BASE_PTR,37) |
| #define CAN2_ID37 CAN_ID_REG(CAN2_BASE_PTR,37) |
| #define CAN2_WORD037 CAN_WORD0_REG(CAN2_BASE_PTR,37) |
| #define CAN2_WORD137 CAN_WORD1_REG(CAN2_BASE_PTR,37) |
| #define CAN2_CS38 CAN_CS_REG(CAN2_BASE_PTR,38) |
| #define CAN2_ID38 CAN_ID_REG(CAN2_BASE_PTR,38) |
| #define CAN2_WORD038 CAN_WORD0_REG(CAN2_BASE_PTR,38) |
| #define CAN2_WORD138 CAN_WORD1_REG(CAN2_BASE_PTR,38) |
| #define CAN2_CS39 CAN_CS_REG(CAN2_BASE_PTR,39) |
| #define CAN2_ID39 CAN_ID_REG(CAN2_BASE_PTR,39) |
| #define CAN2_WORD039 CAN_WORD0_REG(CAN2_BASE_PTR,39) |
| #define CAN2_WORD139 CAN_WORD1_REG(CAN2_BASE_PTR,39) |
| #define CAN2_CS40 CAN_CS_REG(CAN2_BASE_PTR,40) |
| #define CAN2_ID40 CAN_ID_REG(CAN2_BASE_PTR,40) |
| #define CAN2_WORD040 CAN_WORD0_REG(CAN2_BASE_PTR,40) |
| #define CAN2_WORD140 CAN_WORD1_REG(CAN2_BASE_PTR,40) |
| #define CAN2_CS41 CAN_CS_REG(CAN2_BASE_PTR,41) |
| #define CAN2_ID41 CAN_ID_REG(CAN2_BASE_PTR,41) |
| #define CAN2_WORD041 CAN_WORD0_REG(CAN2_BASE_PTR,41) |
| #define CAN2_WORD141 CAN_WORD1_REG(CAN2_BASE_PTR,41) |
| #define CAN2_CS42 CAN_CS_REG(CAN2_BASE_PTR,42) |
| #define CAN2_ID42 CAN_ID_REG(CAN2_BASE_PTR,42) |
| #define CAN2_WORD042 CAN_WORD0_REG(CAN2_BASE_PTR,42) |
| #define CAN2_WORD142 CAN_WORD1_REG(CAN2_BASE_PTR,42) |
| #define CAN2_CS43 CAN_CS_REG(CAN2_BASE_PTR,43) |
| #define CAN2_ID43 CAN_ID_REG(CAN2_BASE_PTR,43) |
| #define CAN2_WORD043 CAN_WORD0_REG(CAN2_BASE_PTR,43) |
| #define CAN2_WORD143 CAN_WORD1_REG(CAN2_BASE_PTR,43) |
| #define CAN2_CS44 CAN_CS_REG(CAN2_BASE_PTR,44) |
| #define CAN2_ID44 CAN_ID_REG(CAN2_BASE_PTR,44) |
| #define CAN2_WORD044 CAN_WORD0_REG(CAN2_BASE_PTR,44) |
| #define CAN2_WORD144 CAN_WORD1_REG(CAN2_BASE_PTR,44) |
| #define CAN2_CS45 CAN_CS_REG(CAN2_BASE_PTR,45) |
| #define CAN2_ID45 CAN_ID_REG(CAN2_BASE_PTR,45) |
| #define CAN2_WORD045 CAN_WORD0_REG(CAN2_BASE_PTR,45) |
| #define CAN2_WORD145 CAN_WORD1_REG(CAN2_BASE_PTR,45) |
| #define CAN2_CS46 CAN_CS_REG(CAN2_BASE_PTR,46) |
| #define CAN2_ID46 CAN_ID_REG(CAN2_BASE_PTR,46) |
| #define CAN2_WORD046 CAN_WORD0_REG(CAN2_BASE_PTR,46) |
| #define CAN2_WORD146 CAN_WORD1_REG(CAN2_BASE_PTR,46) |
| #define CAN2_CS47 CAN_CS_REG(CAN2_BASE_PTR,47) |
| #define CAN2_ID47 CAN_ID_REG(CAN2_BASE_PTR,47) |
| #define CAN2_WORD047 CAN_WORD0_REG(CAN2_BASE_PTR,47) |
| #define CAN2_WORD147 CAN_WORD1_REG(CAN2_BASE_PTR,47) |
| #define CAN2_CS48 CAN_CS_REG(CAN2_BASE_PTR,48) |
| #define CAN2_ID48 CAN_ID_REG(CAN2_BASE_PTR,48) |
| #define CAN2_WORD048 CAN_WORD0_REG(CAN2_BASE_PTR,48) |
| #define CAN2_WORD148 CAN_WORD1_REG(CAN2_BASE_PTR,48) |
| #define CAN2_CS49 CAN_CS_REG(CAN2_BASE_PTR,49) |
| #define CAN2_ID49 CAN_ID_REG(CAN2_BASE_PTR,49) |
| #define CAN2_WORD049 CAN_WORD0_REG(CAN2_BASE_PTR,49) |
| #define CAN2_WORD149 CAN_WORD1_REG(CAN2_BASE_PTR,49) |
| #define CAN2_CS50 CAN_CS_REG(CAN2_BASE_PTR,50) |
| #define CAN2_ID50 CAN_ID_REG(CAN2_BASE_PTR,50) |
| #define CAN2_WORD050 CAN_WORD0_REG(CAN2_BASE_PTR,50) |
| #define CAN2_WORD150 CAN_WORD1_REG(CAN2_BASE_PTR,50) |
| #define CAN2_CS51 CAN_CS_REG(CAN2_BASE_PTR,51) |
| #define CAN2_ID51 CAN_ID_REG(CAN2_BASE_PTR,51) |
| #define CAN2_WORD051 CAN_WORD0_REG(CAN2_BASE_PTR,51) |
| #define CAN2_WORD151 CAN_WORD1_REG(CAN2_BASE_PTR,51) |
| #define CAN2_CS52 CAN_CS_REG(CAN2_BASE_PTR,52) |
| #define CAN2_ID52 CAN_ID_REG(CAN2_BASE_PTR,52) |
| #define CAN2_WORD052 CAN_WORD0_REG(CAN2_BASE_PTR,52) |
| #define CAN2_WORD152 CAN_WORD1_REG(CAN2_BASE_PTR,52) |
| #define CAN2_CS53 CAN_CS_REG(CAN2_BASE_PTR,53) |
| #define CAN2_ID53 CAN_ID_REG(CAN2_BASE_PTR,53) |
| #define CAN2_WORD053 CAN_WORD0_REG(CAN2_BASE_PTR,53) |
| #define CAN2_WORD153 CAN_WORD1_REG(CAN2_BASE_PTR,53) |
| #define CAN2_CS54 CAN_CS_REG(CAN2_BASE_PTR,54) |
| #define CAN2_ID54 CAN_ID_REG(CAN2_BASE_PTR,54) |
| #define CAN2_WORD054 CAN_WORD0_REG(CAN2_BASE_PTR,54) |
| #define CAN2_WORD154 CAN_WORD1_REG(CAN2_BASE_PTR,54) |
| #define CAN2_CS55 CAN_CS_REG(CAN2_BASE_PTR,55) |
| #define CAN2_ID55 CAN_ID_REG(CAN2_BASE_PTR,55) |
| #define CAN2_WORD055 CAN_WORD0_REG(CAN2_BASE_PTR,55) |
| #define CAN2_WORD155 CAN_WORD1_REG(CAN2_BASE_PTR,55) |
| #define CAN2_CS56 CAN_CS_REG(CAN2_BASE_PTR,56) |
| #define CAN2_ID56 CAN_ID_REG(CAN2_BASE_PTR,56) |
| #define CAN2_WORD056 CAN_WORD0_REG(CAN2_BASE_PTR,56) |
| #define CAN2_WORD156 CAN_WORD1_REG(CAN2_BASE_PTR,56) |
| #define CAN2_CS57 CAN_CS_REG(CAN2_BASE_PTR,57) |
| #define CAN2_ID57 CAN_ID_REG(CAN2_BASE_PTR,57) |
| #define CAN2_WORD057 CAN_WORD0_REG(CAN2_BASE_PTR,57) |
| #define CAN2_WORD157 CAN_WORD1_REG(CAN2_BASE_PTR,57) |
| #define CAN2_CS58 CAN_CS_REG(CAN2_BASE_PTR,58) |
| #define CAN2_ID58 CAN_ID_REG(CAN2_BASE_PTR,58) |
| #define CAN2_WORD058 CAN_WORD0_REG(CAN2_BASE_PTR,58) |
| #define CAN2_WORD158 CAN_WORD1_REG(CAN2_BASE_PTR,58) |
| #define CAN2_CS59 CAN_CS_REG(CAN2_BASE_PTR,59) |
| #define CAN2_ID59 CAN_ID_REG(CAN2_BASE_PTR,59) |
| #define CAN2_WORD059 CAN_WORD0_REG(CAN2_BASE_PTR,59) |
| #define CAN2_WORD159 CAN_WORD1_REG(CAN2_BASE_PTR,59) |
| #define CAN2_CS60 CAN_CS_REG(CAN2_BASE_PTR,60) |
| #define CAN2_ID60 CAN_ID_REG(CAN2_BASE_PTR,60) |
| #define CAN2_WORD060 CAN_WORD0_REG(CAN2_BASE_PTR,60) |
| #define CAN2_WORD160 CAN_WORD1_REG(CAN2_BASE_PTR,60) |
| #define CAN2_CS61 CAN_CS_REG(CAN2_BASE_PTR,61) |
| #define CAN2_ID61 CAN_ID_REG(CAN2_BASE_PTR,61) |
| #define CAN2_WORD061 CAN_WORD0_REG(CAN2_BASE_PTR,61) |
| #define CAN2_WORD161 CAN_WORD1_REG(CAN2_BASE_PTR,61) |
| #define CAN2_CS62 CAN_CS_REG(CAN2_BASE_PTR,62) |
| #define CAN2_ID62 CAN_ID_REG(CAN2_BASE_PTR,62) |
| #define CAN2_WORD062 CAN_WORD0_REG(CAN2_BASE_PTR,62) |
| #define CAN2_WORD162 CAN_WORD1_REG(CAN2_BASE_PTR,62) |
| #define CAN2_CS63 CAN_CS_REG(CAN2_BASE_PTR,63) |
| #define CAN2_ID63 CAN_ID_REG(CAN2_BASE_PTR,63) |
| #define CAN2_WORD063 CAN_WORD0_REG(CAN2_BASE_PTR,63) |
| #define CAN2_WORD163 CAN_WORD1_REG(CAN2_BASE_PTR,63) |
| #define CAN2_RXIMR0 CAN_RXIMR_REG(CAN2_BASE_PTR,0) |
| #define CAN2_RXIMR1 CAN_RXIMR_REG(CAN2_BASE_PTR,1) |
| #define CAN2_RXIMR2 CAN_RXIMR_REG(CAN2_BASE_PTR,2) |
| #define CAN2_RXIMR3 CAN_RXIMR_REG(CAN2_BASE_PTR,3) |
| #define CAN2_RXIMR4 CAN_RXIMR_REG(CAN2_BASE_PTR,4) |
| #define CAN2_RXIMR5 CAN_RXIMR_REG(CAN2_BASE_PTR,5) |
| #define CAN2_RXIMR6 CAN_RXIMR_REG(CAN2_BASE_PTR,6) |
| #define CAN2_RXIMR7 CAN_RXIMR_REG(CAN2_BASE_PTR,7) |
| #define CAN2_RXIMR8 CAN_RXIMR_REG(CAN2_BASE_PTR,8) |
| #define CAN2_RXIMR9 CAN_RXIMR_REG(CAN2_BASE_PTR,9) |
| #define CAN2_RXIMR10 CAN_RXIMR_REG(CAN2_BASE_PTR,10) |
| #define CAN2_RXIMR11 CAN_RXIMR_REG(CAN2_BASE_PTR,11) |
| #define CAN2_RXIMR12 CAN_RXIMR_REG(CAN2_BASE_PTR,12) |
| #define CAN2_RXIMR13 CAN_RXIMR_REG(CAN2_BASE_PTR,13) |
| #define CAN2_RXIMR14 CAN_RXIMR_REG(CAN2_BASE_PTR,14) |
| #define CAN2_RXIMR15 CAN_RXIMR_REG(CAN2_BASE_PTR,15) |
| #define CAN2_RXIMR16 CAN_RXIMR_REG(CAN2_BASE_PTR,16) |
| #define CAN2_RXIMR17 CAN_RXIMR_REG(CAN2_BASE_PTR,17) |
| #define CAN2_RXIMR18 CAN_RXIMR_REG(CAN2_BASE_PTR,18) |
| #define CAN2_RXIMR19 CAN_RXIMR_REG(CAN2_BASE_PTR,19) |
| #define CAN2_RXIMR20 CAN_RXIMR_REG(CAN2_BASE_PTR,20) |
| #define CAN2_RXIMR21 CAN_RXIMR_REG(CAN2_BASE_PTR,21) |
| #define CAN2_RXIMR22 CAN_RXIMR_REG(CAN2_BASE_PTR,22) |
| #define CAN2_RXIMR23 CAN_RXIMR_REG(CAN2_BASE_PTR,23) |
| #define CAN2_RXIMR24 CAN_RXIMR_REG(CAN2_BASE_PTR,24) |
| #define CAN2_RXIMR25 CAN_RXIMR_REG(CAN2_BASE_PTR,25) |
| #define CAN2_RXIMR26 CAN_RXIMR_REG(CAN2_BASE_PTR,26) |
| #define CAN2_RXIMR27 CAN_RXIMR_REG(CAN2_BASE_PTR,27) |
| #define CAN2_RXIMR28 CAN_RXIMR_REG(CAN2_BASE_PTR,28) |
| #define CAN2_RXIMR29 CAN_RXIMR_REG(CAN2_BASE_PTR,29) |
| #define CAN2_RXIMR30 CAN_RXIMR_REG(CAN2_BASE_PTR,30) |
| #define CAN2_RXIMR31 CAN_RXIMR_REG(CAN2_BASE_PTR,31) |
| #define CAN2_RXIMR32 CAN_RXIMR_REG(CAN2_BASE_PTR,32) |
| #define CAN2_RXIMR33 CAN_RXIMR_REG(CAN2_BASE_PTR,33) |
| #define CAN2_RXIMR34 CAN_RXIMR_REG(CAN2_BASE_PTR,34) |
| #define CAN2_RXIMR35 CAN_RXIMR_REG(CAN2_BASE_PTR,35) |
| #define CAN2_RXIMR36 CAN_RXIMR_REG(CAN2_BASE_PTR,36) |
| #define CAN2_RXIMR37 CAN_RXIMR_REG(CAN2_BASE_PTR,37) |
| #define CAN2_RXIMR38 CAN_RXIMR_REG(CAN2_BASE_PTR,38) |
| #define CAN2_RXIMR39 CAN_RXIMR_REG(CAN2_BASE_PTR,39) |
| #define CAN2_RXIMR40 CAN_RXIMR_REG(CAN2_BASE_PTR,40) |
| #define CAN2_RXIMR41 CAN_RXIMR_REG(CAN2_BASE_PTR,41) |
| #define CAN2_RXIMR42 CAN_RXIMR_REG(CAN2_BASE_PTR,42) |
| #define CAN2_RXIMR43 CAN_RXIMR_REG(CAN2_BASE_PTR,43) |
| #define CAN2_RXIMR44 CAN_RXIMR_REG(CAN2_BASE_PTR,44) |
| #define CAN2_RXIMR45 CAN_RXIMR_REG(CAN2_BASE_PTR,45) |
| #define CAN2_RXIMR46 CAN_RXIMR_REG(CAN2_BASE_PTR,46) |
| #define CAN2_RXIMR47 CAN_RXIMR_REG(CAN2_BASE_PTR,47) |
| #define CAN2_RXIMR48 CAN_RXIMR_REG(CAN2_BASE_PTR,48) |
| #define CAN2_RXIMR49 CAN_RXIMR_REG(CAN2_BASE_PTR,49) |
| #define CAN2_RXIMR50 CAN_RXIMR_REG(CAN2_BASE_PTR,50) |
| #define CAN2_RXIMR51 CAN_RXIMR_REG(CAN2_BASE_PTR,51) |
| #define CAN2_RXIMR52 CAN_RXIMR_REG(CAN2_BASE_PTR,52) |
| #define CAN2_RXIMR53 CAN_RXIMR_REG(CAN2_BASE_PTR,53) |
| #define CAN2_RXIMR54 CAN_RXIMR_REG(CAN2_BASE_PTR,54) |
| #define CAN2_RXIMR55 CAN_RXIMR_REG(CAN2_BASE_PTR,55) |
| #define CAN2_RXIMR56 CAN_RXIMR_REG(CAN2_BASE_PTR,56) |
| #define CAN2_RXIMR57 CAN_RXIMR_REG(CAN2_BASE_PTR,57) |
| #define CAN2_RXIMR58 CAN_RXIMR_REG(CAN2_BASE_PTR,58) |
| #define CAN2_RXIMR59 CAN_RXIMR_REG(CAN2_BASE_PTR,59) |
| #define CAN2_RXIMR60 CAN_RXIMR_REG(CAN2_BASE_PTR,60) |
| #define CAN2_RXIMR61 CAN_RXIMR_REG(CAN2_BASE_PTR,61) |
| #define CAN2_RXIMR62 CAN_RXIMR_REG(CAN2_BASE_PTR,62) |
| #define CAN2_RXIMR63 CAN_RXIMR_REG(CAN2_BASE_PTR,63) |
| #define CAN2_GFWR CAN_GFWR_REG(CAN2_BASE_PTR) |
| /* CAN - Register array accessors */ |
| #define CAN1_CS(index) CAN_CS_REG(CAN1_BASE_PTR,index) |
| #define CAN2_CS(index) CAN_CS_REG(CAN2_BASE_PTR,index) |
| #define CAN1_ID(index) CAN_ID_REG(CAN1_BASE_PTR,index) |
| #define CAN2_ID(index) CAN_ID_REG(CAN2_BASE_PTR,index) |
| #define CAN1_WORD0(index) CAN_WORD0_REG(CAN1_BASE_PTR,index) |
| #define CAN2_WORD0(index) CAN_WORD0_REG(CAN2_BASE_PTR,index) |
| #define CAN1_WORD1(index) CAN_WORD1_REG(CAN1_BASE_PTR,index) |
| #define CAN2_WORD1(index) CAN_WORD1_REG(CAN2_BASE_PTR,index) |
| #define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1_BASE_PTR,index) |
| #define CAN2_RXIMR(index) CAN_RXIMR_REG(CAN2_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group CAN_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group CAN_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CCM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ |
| __IO uint32_t CCDR; /**< CCM Control Divider Register, offset: 0x4 */ |
| __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ |
| __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ |
| __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ |
| __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ |
| __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ |
| __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ |
| __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ |
| __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ |
| __IO uint32_t CS1CDR; /**< CCM SSI1 Clock Divider Register, offset: 0x28 */ |
| __IO uint32_t CS2CDR; /**< CCM SSI2 Clock Divider Register, offset: 0x2C */ |
| __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ |
| __IO uint32_t CHSCCDR; /**< CCM HSC Clock Divider Register, offset: 0x34 */ |
| __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ |
| __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t CWDR; /**< CCM Wakeup Detector Register, offset: 0x44 */ |
| __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ |
| __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ |
| __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ |
| __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ |
| __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ |
| __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ |
| __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ |
| __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ |
| __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ |
| __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ |
| __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ |
| __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ |
| uint8_t RESERVED_2[4]; |
| __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ |
| } CCM_Type, *CCM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros |
| * @{ |
| */ |
| |
| /* CCM - Register accessors */ |
| #define CCM_CCR_REG(base) ((base)->CCR) |
| #define CCM_CCDR_REG(base) ((base)->CCDR) |
| #define CCM_CSR_REG(base) ((base)->CSR) |
| #define CCM_CCSR_REG(base) ((base)->CCSR) |
| #define CCM_CACRR_REG(base) ((base)->CACRR) |
| #define CCM_CBCDR_REG(base) ((base)->CBCDR) |
| #define CCM_CBCMR_REG(base) ((base)->CBCMR) |
| #define CCM_CSCMR1_REG(base) ((base)->CSCMR1) |
| #define CCM_CSCMR2_REG(base) ((base)->CSCMR2) |
| #define CCM_CSCDR1_REG(base) ((base)->CSCDR1) |
| #define CCM_CS1CDR_REG(base) ((base)->CS1CDR) |
| #define CCM_CS2CDR_REG(base) ((base)->CS2CDR) |
| #define CCM_CDCDR_REG(base) ((base)->CDCDR) |
| #define CCM_CHSCCDR_REG(base) ((base)->CHSCCDR) |
| #define CCM_CSCDR2_REG(base) ((base)->CSCDR2) |
| #define CCM_CSCDR3_REG(base) ((base)->CSCDR3) |
| #define CCM_CWDR_REG(base) ((base)->CWDR) |
| #define CCM_CDHIPR_REG(base) ((base)->CDHIPR) |
| #define CCM_CLPCR_REG(base) ((base)->CLPCR) |
| #define CCM_CISR_REG(base) ((base)->CISR) |
| #define CCM_CIMR_REG(base) ((base)->CIMR) |
| #define CCM_CCOSR_REG(base) ((base)->CCOSR) |
| #define CCM_CGPR_REG(base) ((base)->CGPR) |
| #define CCM_CCGR0_REG(base) ((base)->CCGR0) |
| #define CCM_CCGR1_REG(base) ((base)->CCGR1) |
| #define CCM_CCGR2_REG(base) ((base)->CCGR2) |
| #define CCM_CCGR3_REG(base) ((base)->CCGR3) |
| #define CCM_CCGR4_REG(base) ((base)->CCGR4) |
| #define CCM_CCGR5_REG(base) ((base)->CCGR5) |
| #define CCM_CCGR6_REG(base) ((base)->CCGR6) |
| #define CCM_CMEOR_REG(base) ((base)->CMEOR) |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Register_Masks CCM Register Masks |
| * @{ |
| */ |
| |
| /* CCR Bit Fields */ |
| #define CCM_CCR_OSCNT_MASK 0x7Fu |
| #define CCM_CCR_OSCNT_SHIFT 0 |
| #define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCR_OSCNT_SHIFT))&CCM_CCR_OSCNT_MASK) |
| #define CCM_CCR_COSC_EN_MASK 0x1000u |
| #define CCM_CCR_COSC_EN_SHIFT 12 |
| #define CCM_CCR_REG_BYPASS_COUNT_MASK 0x7E00000u |
| #define CCM_CCR_REG_BYPASS_COUNT_SHIFT 21 |
| #define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCR_REG_BYPASS_COUNT_SHIFT))&CCM_CCR_REG_BYPASS_COUNT_MASK) |
| #define CCM_CCR_RBC_EN_MASK 0x8000000u |
| #define CCM_CCR_RBC_EN_SHIFT 27 |
| /* CCDR Bit Fields */ |
| #define CCM_CCDR_mmdc_mask_MASK 0x10000u |
| #define CCM_CCDR_mmdc_mask_SHIFT 16 |
| /* CSR Bit Fields */ |
| #define CCM_CSR_REF_EN_B_MASK 0x1u |
| #define CCM_CSR_REF_EN_B_SHIFT 0 |
| #define CCM_CSR_cosc_ready_MASK 0x20u |
| #define CCM_CSR_cosc_ready_SHIFT 5 |
| /* CCSR Bit Fields */ |
| #define CCM_CCSR_pll3_sw_clk_sel_MASK 0x1u |
| #define CCM_CCSR_pll3_sw_clk_sel_SHIFT 0 |
| #define CCM_CCSR_pll1_sw_clk_sel_MASK 0x4u |
| #define CCM_CCSR_pll1_sw_clk_sel_SHIFT 2 |
| #define CCM_CCSR_step_sel_MASK 0x100u |
| #define CCM_CCSR_step_sel_SHIFT 8 |
| /* CACRR Bit Fields */ |
| #define CCM_CACRR_arm_podf_MASK 0x7u |
| #define CCM_CACRR_arm_podf_SHIFT 0 |
| #define CCM_CACRR_arm_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CACRR_arm_podf_SHIFT))&CCM_CACRR_arm_podf_MASK) |
| /* CBCDR Bit Fields */ |
| #define CCM_CBCDR_periph2_clk2_podf_MASK 0x7u |
| #define CCM_CBCDR_periph2_clk2_podf_SHIFT 0 |
| #define CCM_CBCDR_periph2_clk2_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_periph2_clk2_podf_SHIFT))&CCM_CBCDR_periph2_clk2_podf_MASK) |
| #define CCM_CBCDR_fabric_mmdc_podf_MASK 0x38u |
| #define CCM_CBCDR_fabric_mmdc_podf_SHIFT 3 |
| #define CCM_CBCDR_fabric_mmdc_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_fabric_mmdc_podf_SHIFT))&CCM_CBCDR_fabric_mmdc_podf_MASK) |
| #define CCM_CBCDR_ocram_clk_sel_MASK 0x40u |
| #define CCM_CBCDR_ocram_clk_sel_SHIFT 6 |
| #define CCM_CBCDR_ocram_alt_clk_sel_MASK 0x80u |
| #define CCM_CBCDR_ocram_alt_clk_sel_SHIFT 7 |
| #define CCM_CBCDR_ipg_podf_MASK 0x300u |
| #define CCM_CBCDR_ipg_podf_SHIFT 8 |
| #define CCM_CBCDR_ipg_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ipg_podf_SHIFT))&CCM_CBCDR_ipg_podf_MASK) |
| #define CCM_CBCDR_ahb_podf_MASK 0x1C00u |
| #define CCM_CBCDR_ahb_podf_SHIFT 10 |
| #define CCM_CBCDR_ahb_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ahb_podf_SHIFT))&CCM_CBCDR_ahb_podf_MASK) |
| #define CCM_CBCDR_ocram_podf_MASK 0x70000u |
| #define CCM_CBCDR_ocram_podf_SHIFT 16 |
| #define CCM_CBCDR_ocram_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_ocram_podf_SHIFT))&CCM_CBCDR_ocram_podf_MASK) |
| #define CCM_CBCDR_periph_clk_sel_MASK 0x2000000u |
| #define CCM_CBCDR_periph_clk_sel_SHIFT 25 |
| #define CCM_CBCDR_periph2_clk_sel_MASK 0x4000000u |
| #define CCM_CBCDR_periph2_clk_sel_SHIFT 26 |
| #define CCM_CBCDR_periph_clk2_podf_MASK 0x38000000u |
| #define CCM_CBCDR_periph_clk2_podf_SHIFT 27 |
| #define CCM_CBCDR_periph_clk2_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCDR_periph_clk2_podf_SHIFT))&CCM_CBCDR_periph_clk2_podf_MASK) |
| /* CBCMR Bit Fields */ |
| #define CCM_CBCMR_gpu_core_sel_MASK 0x30u |
| #define CCM_CBCMR_gpu_core_sel_SHIFT 4 |
| #define CCM_CBCMR_gpu_core_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_core_sel_SHIFT))&CCM_CBCMR_gpu_core_sel_MASK) |
| #define CCM_CBCMR_gpu_axi_sel_MASK 0x300u |
| #define CCM_CBCMR_gpu_axi_sel_SHIFT 8 |
| #define CCM_CBCMR_gpu_axi_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_axi_sel_SHIFT))&CCM_CBCMR_gpu_axi_sel_MASK) |
| #define CCM_CBCMR_pcie_axi_clk_sel_MASK 0x400u |
| #define CCM_CBCMR_pcie_axi_clk_sel_SHIFT 10 |
| #define CCM_CBCMR_periph_clk2_sel_MASK 0x3000u |
| #define CCM_CBCMR_periph_clk2_sel_SHIFT 12 |
| #define CCM_CBCMR_periph_clk2_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_periph_clk2_sel_SHIFT))&CCM_CBCMR_periph_clk2_sel_MASK) |
| #define CCM_CBCMR_pre_periph_clk_sel_MASK 0xC0000u |
| #define CCM_CBCMR_pre_periph_clk_sel_SHIFT 18 |
| #define CCM_CBCMR_pre_periph_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_pre_periph_clk_sel_SHIFT))&CCM_CBCMR_pre_periph_clk_sel_MASK) |
| #define CCM_CBCMR_periph2_clk2_sel_MASK 0x100000u |
| #define CCM_CBCMR_periph2_clk2_sel_SHIFT 20 |
| #define CCM_CBCMR_pre_periph2_clk_sel_MASK 0x600000u |
| #define CCM_CBCMR_pre_periph2_clk_sel_SHIFT 21 |
| #define CCM_CBCMR_pre_periph2_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_pre_periph2_clk_sel_SHIFT))&CCM_CBCMR_pre_periph2_clk_sel_MASK) |
| #define CCM_CBCMR_lcdif1_podf_MASK 0x3800000u |
| #define CCM_CBCMR_lcdif1_podf_SHIFT 23 |
| #define CCM_CBCMR_lcdif1_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_lcdif1_podf_SHIFT))&CCM_CBCMR_lcdif1_podf_MASK) |
| #define CCM_CBCMR_gpu_axi_podf_MASK 0x1C000000u |
| #define CCM_CBCMR_gpu_axi_podf_SHIFT 26 |
| #define CCM_CBCMR_gpu_axi_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_axi_podf_SHIFT))&CCM_CBCMR_gpu_axi_podf_MASK) |
| #define CCM_CBCMR_gpu_core_podf_MASK 0xE0000000u |
| #define CCM_CBCMR_gpu_core_podf_SHIFT 29 |
| #define CCM_CBCMR_gpu_core_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CBCMR_gpu_core_podf_SHIFT))&CCM_CBCMR_gpu_core_podf_MASK) |
| /* CSCMR1 Bit Fields */ |
| #define CCM_CSCMR1_perclk_podf_MASK 0x3Fu |
| #define CCM_CSCMR1_perclk_podf_SHIFT 0 |
| #define CCM_CSCMR1_perclk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_perclk_podf_SHIFT))&CCM_CSCMR1_perclk_podf_MASK) |
| #define CCM_CSCMR1_perclk_clk_sel_MASK 0x40u |
| #define CCM_CSCMR1_perclk_clk_sel_SHIFT 6 |
| #define CCM_CSCMR1_qspi1_sel_MASK 0x380u |
| #define CCM_CSCMR1_qspi1_sel_SHIFT 7 |
| #define CCM_CSCMR1_qspi1_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_qspi1_sel_SHIFT))&CCM_CSCMR1_qspi1_sel_MASK) |
| #define CCM_CSCMR1_ssi1_clk_sel_MASK 0xC00u |
| #define CCM_CSCMR1_ssi1_clk_sel_SHIFT 10 |
| #define CCM_CSCMR1_ssi1_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi1_clk_sel_SHIFT))&CCM_CSCMR1_ssi1_clk_sel_MASK) |
| #define CCM_CSCMR1_ssi2_clk_sel_MASK 0x3000u |
| #define CCM_CSCMR1_ssi2_clk_sel_SHIFT 12 |
| #define CCM_CSCMR1_ssi2_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi2_clk_sel_SHIFT))&CCM_CSCMR1_ssi2_clk_sel_MASK) |
| #define CCM_CSCMR1_ssi3_clk_sel_MASK 0xC000u |
| #define CCM_CSCMR1_ssi3_clk_sel_SHIFT 14 |
| #define CCM_CSCMR1_ssi3_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_ssi3_clk_sel_SHIFT))&CCM_CSCMR1_ssi3_clk_sel_MASK) |
| #define CCM_CSCMR1_usdhc1_clk_sel_MASK 0x10000u |
| #define CCM_CSCMR1_usdhc1_clk_sel_SHIFT 16 |
| #define CCM_CSCMR1_usdhc2_clk_sel_MASK 0x20000u |
| #define CCM_CSCMR1_usdhc2_clk_sel_SHIFT 17 |
| #define CCM_CSCMR1_usdhc3_clk_sel_MASK 0x40000u |
| #define CCM_CSCMR1_usdhc3_clk_sel_SHIFT 18 |
| #define CCM_CSCMR1_usdhc4_clk_sel_MASK 0x80000u |
| #define CCM_CSCMR1_usdhc4_clk_sel_SHIFT 19 |
| #define CCM_CSCMR1_lcdif2_podf_MASK 0x700000u |
| #define CCM_CSCMR1_lcdif2_podf_SHIFT 20 |
| #define CCM_CSCMR1_lcdif2_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_lcdif2_podf_SHIFT))&CCM_CSCMR1_lcdif2_podf_MASK) |
| #define CCM_CSCMR1_aclk_eim_slow_podf_MASK 0x3800000u |
| #define CCM_CSCMR1_aclk_eim_slow_podf_SHIFT 23 |
| #define CCM_CSCMR1_aclk_eim_slow_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_aclk_eim_slow_podf_SHIFT))&CCM_CSCMR1_aclk_eim_slow_podf_MASK) |
| #define CCM_CSCMR1_qspi1_podf_MASK 0x1C000000u |
| #define CCM_CSCMR1_qspi1_podf_SHIFT 26 |
| #define CCM_CSCMR1_qspi1_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_qspi1_podf_SHIFT))&CCM_CSCMR1_qspi1_podf_MASK) |
| #define CCM_CSCMR1_aclk_eim_slow_sel_MASK 0x60000000u |
| #define CCM_CSCMR1_aclk_eim_slow_sel_SHIFT 29 |
| #define CCM_CSCMR1_aclk_eim_slow_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR1_aclk_eim_slow_sel_SHIFT))&CCM_CSCMR1_aclk_eim_slow_sel_MASK) |
| /* CSCMR2 Bit Fields */ |
| #define CCM_CSCMR2_can_clk_podf_MASK 0xFCu |
| #define CCM_CSCMR2_can_clk_podf_SHIFT 2 |
| #define CCM_CSCMR2_can_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_can_clk_podf_SHIFT))&CCM_CSCMR2_can_clk_podf_MASK) |
| #define CCM_CSCMR2_can_clk_sel_MASK 0x300u |
| #define CCM_CSCMR2_can_clk_sel_SHIFT 8 |
| #define CCM_CSCMR2_can_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_can_clk_sel_SHIFT))&CCM_CSCMR2_can_clk_sel_MASK) |
| #define CCM_CSCMR2_ldb_di0_div_MASK 0x400u |
| #define CCM_CSCMR2_ldb_di0_div_SHIFT 10 |
| #define CCM_CSCMR2_ldb_di1_div_MASK 0x800u |
| #define CCM_CSCMR2_ldb_di1_div_SHIFT 11 |
| #define CCM_CSCMR2_esai_clk_sel_MASK 0x180000u |
| #define CCM_CSCMR2_esai_clk_sel_SHIFT 19 |
| #define CCM_CSCMR2_esai_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_esai_clk_sel_SHIFT))&CCM_CSCMR2_esai_clk_sel_MASK) |
| #define CCM_CSCMR2_vid_clk_sel_MASK 0xE00000u |
| #define CCM_CSCMR2_vid_clk_sel_SHIFT 21 |
| #define CCM_CSCMR2_vid_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_sel_SHIFT))&CCM_CSCMR2_vid_clk_sel_MASK) |
| #define CCM_CSCMR2_vid_clk_pre_podf_MASK 0x3000000u |
| #define CCM_CSCMR2_vid_clk_pre_podf_SHIFT 24 |
| #define CCM_CSCMR2_vid_clk_pre_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_pre_podf_SHIFT))&CCM_CSCMR2_vid_clk_pre_podf_MASK) |
| #define CCM_CSCMR2_vid_clk_podf_MASK 0x1C000000u |
| #define CCM_CSCMR2_vid_clk_podf_SHIFT 26 |
| #define CCM_CSCMR2_vid_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCMR2_vid_clk_podf_SHIFT))&CCM_CSCMR2_vid_clk_podf_MASK) |
| /* CSCDR1 Bit Fields */ |
| #define CCM_CSCDR1_uart_clk_podf_MASK 0x3Fu |
| #define CCM_CSCDR1_uart_clk_podf_SHIFT 0 |
| #define CCM_CSCDR1_uart_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_uart_clk_podf_SHIFT))&CCM_CSCDR1_uart_clk_podf_MASK) |
| #define CCM_CSCDR1_uart_clk_sel_MASK 0x40u |
| #define CCM_CSCDR1_uart_clk_sel_SHIFT 6 |
| #define CCM_CSCDR1_usdhc1_podf_MASK 0x3800u |
| #define CCM_CSCDR1_usdhc1_podf_SHIFT 11 |
| #define CCM_CSCDR1_usdhc1_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc1_podf_SHIFT))&CCM_CSCDR1_usdhc1_podf_MASK) |
| #define CCM_CSCDR1_usdhc2_podf_MASK 0x70000u |
| #define CCM_CSCDR1_usdhc2_podf_SHIFT 16 |
| #define CCM_CSCDR1_usdhc2_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc2_podf_SHIFT))&CCM_CSCDR1_usdhc2_podf_MASK) |
| #define CCM_CSCDR1_usdhc3_podf_MASK 0x380000u |
| #define CCM_CSCDR1_usdhc3_podf_SHIFT 19 |
| #define CCM_CSCDR1_usdhc3_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc3_podf_SHIFT))&CCM_CSCDR1_usdhc3_podf_MASK) |
| #define CCM_CSCDR1_usdhc4_podf_MASK 0x1C00000u |
| #define CCM_CSCDR1_usdhc4_podf_SHIFT 22 |
| #define CCM_CSCDR1_usdhc4_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR1_usdhc4_podf_SHIFT))&CCM_CSCDR1_usdhc4_podf_MASK) |
| /* CS1CDR Bit Fields */ |
| #define CCM_CS1CDR_ssi1_clk_podf_MASK 0x3Fu |
| #define CCM_CS1CDR_ssi1_clk_podf_SHIFT 0 |
| #define CCM_CS1CDR_ssi1_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi1_clk_podf_SHIFT))&CCM_CS1CDR_ssi1_clk_podf_MASK) |
| #define CCM_CS1CDR_ssi1_clk_pred_MASK 0x1C0u |
| #define CCM_CS1CDR_ssi1_clk_pred_SHIFT 6 |
| #define CCM_CS1CDR_ssi1_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi1_clk_pred_SHIFT))&CCM_CS1CDR_ssi1_clk_pred_MASK) |
| #define CCM_CS1CDR_esai_clk_pred_MASK 0xE00u |
| #define CCM_CS1CDR_esai_clk_pred_SHIFT 9 |
| #define CCM_CS1CDR_esai_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_esai_clk_pred_SHIFT))&CCM_CS1CDR_esai_clk_pred_MASK) |
| #define CCM_CS1CDR_ssi3_clk_podf_MASK 0x3F0000u |
| #define CCM_CS1CDR_ssi3_clk_podf_SHIFT 16 |
| #define CCM_CS1CDR_ssi3_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi3_clk_podf_SHIFT))&CCM_CS1CDR_ssi3_clk_podf_MASK) |
| #define CCM_CS1CDR_ssi3_clk_pred_MASK 0x1C00000u |
| #define CCM_CS1CDR_ssi3_clk_pred_SHIFT 22 |
| #define CCM_CS1CDR_ssi3_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_ssi3_clk_pred_SHIFT))&CCM_CS1CDR_ssi3_clk_pred_MASK) |
| #define CCM_CS1CDR_esai_clk_podf_MASK 0xE000000u |
| #define CCM_CS1CDR_esai_clk_podf_SHIFT 25 |
| #define CCM_CS1CDR_esai_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS1CDR_esai_clk_podf_SHIFT))&CCM_CS1CDR_esai_clk_podf_MASK) |
| /* CS2CDR Bit Fields */ |
| #define CCM_CS2CDR_ssi2_clk_podf_MASK 0x3Fu |
| #define CCM_CS2CDR_ssi2_clk_podf_SHIFT 0 |
| #define CCM_CS2CDR_ssi2_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ssi2_clk_podf_SHIFT))&CCM_CS2CDR_ssi2_clk_podf_MASK) |
| #define CCM_CS2CDR_ssi2_clk_pred_MASK 0x1C0u |
| #define CCM_CS2CDR_ssi2_clk_pred_SHIFT 6 |
| #define CCM_CS2CDR_ssi2_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ssi2_clk_pred_SHIFT))&CCM_CS2CDR_ssi2_clk_pred_MASK) |
| #define CCM_CS2CDR_ldb_di0_clk_sel_MASK 0xE00u |
| #define CCM_CS2CDR_ldb_di0_clk_sel_SHIFT 9 |
| #define CCM_CS2CDR_ldb_di0_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ldb_di0_clk_sel_SHIFT))&CCM_CS2CDR_ldb_di0_clk_sel_MASK) |
| #define CCM_CS2CDR_ldb_di1_clk_sel_MASK 0x7000u |
| #define CCM_CS2CDR_ldb_di1_clk_sel_SHIFT 12 |
| #define CCM_CS2CDR_ldb_di1_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_ldb_di1_clk_sel_SHIFT))&CCM_CS2CDR_ldb_di1_clk_sel_MASK) |
| #define CCM_CS2CDR_qspi2_clk_sel_MASK 0x38000u |
| #define CCM_CS2CDR_qspi2_clk_sel_SHIFT 15 |
| #define CCM_CS2CDR_qspi2_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_sel_SHIFT))&CCM_CS2CDR_qspi2_clk_sel_MASK) |
| #define CCM_CS2CDR_qspi2_clk_pred_MASK 0x1C0000u |
| #define CCM_CS2CDR_qspi2_clk_pred_SHIFT 18 |
| #define CCM_CS2CDR_qspi2_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_pred_SHIFT))&CCM_CS2CDR_qspi2_clk_pred_MASK) |
| #define CCM_CS2CDR_qspi2_clk_podf_MASK 0x7E00000u |
| #define CCM_CS2CDR_qspi2_clk_podf_SHIFT 21 |
| #define CCM_CS2CDR_qspi2_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CS2CDR_qspi2_clk_podf_SHIFT))&CCM_CS2CDR_qspi2_clk_podf_MASK) |
| /* CDCDR Bit Fields */ |
| #define CCM_CDCDR_audio_clk_sel_MASK 0x180u |
| #define CCM_CDCDR_audio_clk_sel_SHIFT 7 |
| #define CCM_CDCDR_audio_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_sel_SHIFT))&CCM_CDCDR_audio_clk_sel_MASK) |
| #define CCM_CDCDR_audio_clk_podf_MASK 0xE00u |
| #define CCM_CDCDR_audio_clk_podf_SHIFT 9 |
| #define CCM_CDCDR_audio_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_podf_SHIFT))&CCM_CDCDR_audio_clk_podf_MASK) |
| #define CCM_CDCDR_audio_clk_pred_MASK 0x7000u |
| #define CCM_CDCDR_audio_clk_pred_SHIFT 12 |
| #define CCM_CDCDR_audio_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_audio_clk_pred_SHIFT))&CCM_CDCDR_audio_clk_pred_MASK) |
| #define CCM_CDCDR_spdif0_clk_sel_MASK 0x300000u |
| #define CCM_CDCDR_spdif0_clk_sel_SHIFT 20 |
| #define CCM_CDCDR_spdif0_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_sel_SHIFT))&CCM_CDCDR_spdif0_clk_sel_MASK) |
| #define CCM_CDCDR_spdif0_clk_podf_MASK 0x1C00000u |
| #define CCM_CDCDR_spdif0_clk_podf_SHIFT 22 |
| #define CCM_CDCDR_spdif0_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_podf_SHIFT))&CCM_CDCDR_spdif0_clk_podf_MASK) |
| #define CCM_CDCDR_spdif0_clk_pred_MASK 0xE000000u |
| #define CCM_CDCDR_spdif0_clk_pred_SHIFT 25 |
| #define CCM_CDCDR_spdif0_clk_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CDCDR_spdif0_clk_pred_SHIFT))&CCM_CDCDR_spdif0_clk_pred_MASK) |
| /* CHSCCDR Bit Fields */ |
| #define CCM_CHSCCDR_m4_clk_sel_MASK 0x7u |
| #define CCM_CHSCCDR_m4_clk_sel_SHIFT 0 |
| #define CCM_CHSCCDR_m4_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_clk_sel_SHIFT))&CCM_CHSCCDR_m4_clk_sel_MASK) |
| #define CCM_CHSCCDR_m4_podf_MASK 0x38u |
| #define CCM_CHSCCDR_m4_podf_SHIFT 3 |
| #define CCM_CHSCCDR_m4_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_podf_SHIFT))&CCM_CHSCCDR_m4_podf_MASK) |
| #define CCM_CHSCCDR_m4_pre_clk_sel_MASK 0x1C0u |
| #define CCM_CHSCCDR_m4_pre_clk_sel_SHIFT 6 |
| #define CCM_CHSCCDR_m4_pre_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_m4_pre_clk_sel_SHIFT))&CCM_CHSCCDR_m4_pre_clk_sel_MASK) |
| #define CCM_CHSCCDR_enet_clk_sel_MASK 0xE00u |
| #define CCM_CHSCCDR_enet_clk_sel_SHIFT 9 |
| #define CCM_CHSCCDR_enet_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_clk_sel_SHIFT))&CCM_CHSCCDR_enet_clk_sel_MASK) |
| #define CCM_CHSCCDR_enet_podf_MASK 0x7000u |
| #define CCM_CHSCCDR_enet_podf_SHIFT 12 |
| #define CCM_CHSCCDR_enet_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_podf_SHIFT))&CCM_CHSCCDR_enet_podf_MASK) |
| #define CCM_CHSCCDR_enet_pre_clk_sel_MASK 0x38000u |
| #define CCM_CHSCCDR_enet_pre_clk_sel_SHIFT 15 |
| #define CCM_CHSCCDR_enet_pre_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CHSCCDR_enet_pre_clk_sel_SHIFT))&CCM_CHSCCDR_enet_pre_clk_sel_MASK) |
| /* CSCDR2 Bit Fields */ |
| #define CCM_CSCDR2_lcdif2_clk_sel_MASK 0x7u |
| #define CCM_CSCDR2_lcdif2_clk_sel_SHIFT 0 |
| #define CCM_CSCDR2_lcdif2_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_clk_sel_SHIFT))&CCM_CSCDR2_lcdif2_clk_sel_MASK) |
| #define CCM_CSCDR2_lcdif2_pred_MASK 0x38u |
| #define CCM_CSCDR2_lcdif2_pred_SHIFT 3 |
| #define CCM_CSCDR2_lcdif2_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_pred_SHIFT))&CCM_CSCDR2_lcdif2_pred_MASK) |
| #define CCM_CSCDR2_lcdif2_pre_clk_sel_MASK 0x1C0u |
| #define CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT 6 |
| #define CCM_CSCDR2_lcdif2_pre_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT))&CCM_CSCDR2_lcdif2_pre_clk_sel_MASK) |
| #define CCM_CSCDR2_lcdif1_clk_sel_MASK 0xE00u |
| #define CCM_CSCDR2_lcdif1_clk_sel_SHIFT 9 |
| #define CCM_CSCDR2_lcdif1_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_clk_sel_SHIFT))&CCM_CSCDR2_lcdif1_clk_sel_MASK) |
| #define CCM_CSCDR2_lcdif1_pred_MASK 0x7000u |
| #define CCM_CSCDR2_lcdif1_pred_SHIFT 12 |
| #define CCM_CSCDR2_lcdif1_pred(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_pred_SHIFT))&CCM_CSCDR2_lcdif1_pred_MASK) |
| #define CCM_CSCDR2_lcdif1_pre_clk_sel_MASK 0x38000u |
| #define CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT 15 |
| #define CCM_CSCDR2_lcdif1_pre_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT))&CCM_CSCDR2_lcdif1_pre_clk_sel_MASK) |
| #define CCM_CSCDR2_ecspi_clk_sel_MASK 0x40000u |
| #define CCM_CSCDR2_ecspi_clk_sel_SHIFT 18 |
| #define CCM_CSCDR2_ecspi_clk_podf_MASK 0x1F80000u |
| #define CCM_CSCDR2_ecspi_clk_podf_SHIFT 19 |
| #define CCM_CSCDR2_ecspi_clk_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR2_ecspi_clk_podf_SHIFT))&CCM_CSCDR2_ecspi_clk_podf_MASK) |
| /* CSCDR3 Bit Fields */ |
| #define CCM_CSCDR3_csi_clk_sel_MASK 0x600u |
| #define CCM_CSCDR3_csi_clk_sel_SHIFT 9 |
| #define CCM_CSCDR3_csi_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_csi_clk_sel_SHIFT))&CCM_CSCDR3_csi_clk_sel_MASK) |
| #define CCM_CSCDR3_csi_podf_MASK 0x3800u |
| #define CCM_CSCDR3_csi_podf_SHIFT 11 |
| #define CCM_CSCDR3_csi_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_csi_podf_SHIFT))&CCM_CSCDR3_csi_podf_MASK) |
| #define CCM_CSCDR3_display_clk_sel_MASK 0xC000u |
| #define CCM_CSCDR3_display_clk_sel_SHIFT 14 |
| #define CCM_CSCDR3_display_clk_sel(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_display_clk_sel_SHIFT))&CCM_CSCDR3_display_clk_sel_MASK) |
| #define CCM_CSCDR3_display_podf_MASK 0x70000u |
| #define CCM_CSCDR3_display_podf_SHIFT 16 |
| #define CCM_CSCDR3_display_podf(x) (((uint32_t)(((uint32_t)(x))<<CCM_CSCDR3_display_podf_SHIFT))&CCM_CSCDR3_display_podf_MASK) |
| /* CWDR Bit Fields */ |
| /* CDHIPR Bit Fields */ |
| #define CCM_CDHIPR_ocram_podf_busy_MASK 0x1u |
| #define CCM_CDHIPR_ocram_podf_busy_SHIFT 0 |
| #define CCM_CDHIPR_ahb_podf_busy_MASK 0x2u |
| #define CCM_CDHIPR_ahb_podf_busy_SHIFT 1 |
| #define CCM_CDHIPR_mmdc_podf_busy_MASK 0x4u |
| #define CCM_CDHIPR_mmdc_podf_busy_SHIFT 2 |
| #define CCM_CDHIPR_periph2_clk_sel_busy_MASK 0x8u |
| #define CCM_CDHIPR_periph2_clk_sel_busy_SHIFT 3 |
| #define CCM_CDHIPR_periph_clk_sel_busy_MASK 0x20u |
| #define CCM_CDHIPR_periph_clk_sel_busy_SHIFT 5 |
| #define CCM_CDHIPR_arm_podf_busy_MASK 0x10000u |
| #define CCM_CDHIPR_arm_podf_busy_SHIFT 16 |
| /* CLPCR Bit Fields */ |
| #define CCM_CLPCR_LPM_MASK 0x3u |
| #define CCM_CLPCR_LPM_SHIFT 0 |
| #define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x))<<CCM_CLPCR_LPM_SHIFT))&CCM_CLPCR_LPM_MASK) |
| #define CCM_CLPCR_ARM_clk_dis_on_lpm_MASK 0x20u |
| #define CCM_CLPCR_ARM_clk_dis_on_lpm_SHIFT 5 |
| #define CCM_CLPCR_SBYOS_MASK 0x40u |
| #define CCM_CLPCR_SBYOS_SHIFT 6 |
| #define CCM_CLPCR_dis_ref_osc_MASK 0x80u |
| #define CCM_CLPCR_dis_ref_osc_SHIFT 7 |
| #define CCM_CLPCR_VSTBY_MASK 0x100u |
| #define CCM_CLPCR_VSTBY_SHIFT 8 |
| #define CCM_CLPCR_stby_count_MASK 0x600u |
| #define CCM_CLPCR_stby_count_SHIFT 9 |
| #define CCM_CLPCR_stby_count(x) (((uint32_t)(((uint32_t)(x))<<CCM_CLPCR_stby_count_SHIFT))&CCM_CLPCR_stby_count_MASK) |
| #define CCM_CLPCR_cosc_pwrdown_MASK 0x800u |
| #define CCM_CLPCR_cosc_pwrdown_SHIFT 11 |
| #define CCM_CLPCR_bypass_mmdc_lpm_hs_MASK 0x200000u |
| #define CCM_CLPCR_bypass_mmdc_lpm_hs_SHIFT 21 |
| #define CCM_CLPCR_mask_core0_wfi_MASK 0x400000u |
| #define CCM_CLPCR_mask_core0_wfi_SHIFT 22 |
| #define CCM_CLPCR_mask_scu_idle_MASK 0x4000000u |
| #define CCM_CLPCR_mask_scu_idle_SHIFT 26 |
| #define CCM_CLPCR_mask_l2cc_idle_MASK 0x8000000u |
| #define CCM_CLPCR_mask_l2cc_idle_SHIFT 27 |
| /* CISR Bit Fields */ |
| #define CCM_CISR_lrf_pll_MASK 0x1u |
| #define CCM_CISR_lrf_pll_SHIFT 0 |
| #define CCM_CISR_cosc_ready_MASK 0x40u |
| #define CCM_CISR_cosc_ready_SHIFT 6 |
| #define CCM_CISR_ocram_podf_loaded_MASK 0x20000u |
| #define CCM_CISR_ocram_podf_loaded_SHIFT 17 |
| #define CCM_CISR_periph2_clk_sel_loaded_MASK 0x80000u |
| #define CCM_CISR_periph2_clk_sel_loaded_SHIFT 19 |
| #define CCM_CISR_ahb_podf_loaded_MASK 0x100000u |
| #define CCM_CISR_ahb_podf_loaded_SHIFT 20 |
| #define CCM_CISR_mmdc_podf_loaded_MASK 0x200000u |
| #define CCM_CISR_mmdc_podf_loaded_SHIFT 21 |
| #define CCM_CISR_periph_clk_sel_loaded_MASK 0x400000u |
| #define CCM_CISR_periph_clk_sel_loaded_SHIFT 22 |
| #define CCM_CISR_arm_podf_loaded_MASK 0x4000000u |
| #define CCM_CISR_arm_podf_loaded_SHIFT 26 |
| /* CIMR Bit Fields */ |
| #define CCM_CIMR_mask_lrf_pll_MASK 0x1u |
| #define CCM_CIMR_mask_lrf_pll_SHIFT 0 |
| #define CCM_CIMR_mask_cosc_ready_MASK 0x40u |
| #define CCM_CIMR_mask_cosc_ready_SHIFT 6 |
| #define CCM_CIMR_mask_ocram_podf_loaded_MASK 0x20000u |
| #define CCM_CIMR_mask_ocram_podf_loaded_SHIFT 17 |
| #define CCM_CIMR_mask_periph2_clk_sel_loaded_MASK 0x80000u |
| #define CCM_CIMR_mask_periph2_clk_sel_loaded_SHIFT 19 |
| #define CCM_CIMR_mask_ahb_podf_loaded_MASK 0x100000u |
| #define CCM_CIMR_mask_ahb_podf_loaded_SHIFT 20 |
| #define CCM_CIMR_mask_mmdc_podf_loaded_MASK 0x200000u |
| #define CCM_CIMR_mask_mmdc_podf_loaded_SHIFT 21 |
| #define CCM_CIMR_mask_periph_clk_sel_loaded_MASK 0x400000u |
| #define CCM_CIMR_mask_periph_clk_sel_loaded_SHIFT 22 |
| #define CCM_CIMR_arm_podf_loaded_MASK 0x4000000u |
| #define CCM_CIMR_arm_podf_loaded_SHIFT 26 |
| /* CCOSR Bit Fields */ |
| #define CCM_CCOSR_CLKO_SEL_MASK 0xFu |
| #define CCM_CCOSR_CLKO_SEL_SHIFT 0 |
| #define CCM_CCOSR_CLKO_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO_SEL_SHIFT))&CCM_CCOSR_CLKO_SEL_MASK) |
| #define CCM_CCOSR_CLKO1_DIV_MASK 0x70u |
| #define CCM_CCOSR_CLKO1_DIV_SHIFT 4 |
| #define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO1_DIV_SHIFT))&CCM_CCOSR_CLKO1_DIV_MASK) |
| #define CCM_CCOSR_CLKO1_EN_MASK 0x80u |
| #define CCM_CCOSR_CLKO1_EN_SHIFT 7 |
| #define CCM_CCOSR_CLK_OUT_SEL_MASK 0x100u |
| #define CCM_CCOSR_CLK_OUT_SEL_SHIFT 8 |
| #define CCM_CCOSR_CLKO2_SEL_MASK 0x1F0000u |
| #define CCM_CCOSR_CLKO2_SEL_SHIFT 16 |
| #define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO2_SEL_SHIFT))&CCM_CCOSR_CLKO2_SEL_MASK) |
| #define CCM_CCOSR_CLKO2_DIV_MASK 0xE00000u |
| #define CCM_CCOSR_CLKO2_DIV_SHIFT 21 |
| #define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCOSR_CLKO2_DIV_SHIFT))&CCM_CCOSR_CLKO2_DIV_MASK) |
| #define CCM_CCOSR_CLKO2_EN_MASK 0x1000000u |
| #define CCM_CCOSR_CLKO2_EN_SHIFT 24 |
| /* CGPR Bit Fields */ |
| #define CCM_CGPR_pmic_delay_scaler_MASK 0x1u |
| #define CCM_CGPR_pmic_delay_scaler_SHIFT 0 |
| #define CCM_CGPR_mmdc_ext_clk_dis_MASK 0x4u |
| #define CCM_CGPR_mmdc_ext_clk_dis_SHIFT 2 |
| #define CCM_CGPR_efuse_prog_supply_gate_MASK 0x10u |
| #define CCM_CGPR_efuse_prog_supply_gate_SHIFT 4 |
| #define CCM_CGPR_FPL_MASK 0x10000u |
| #define CCM_CGPR_FPL_SHIFT 16 |
| #define CCM_CGPR_INT_MEM_CLK_LPM_MASK 0x20000u |
| #define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT 17 |
| /* CCGR0 Bit Fields */ |
| #define CCM_CCGR0_CG0_MASK 0x3u |
| #define CCM_CCGR0_CG0_SHIFT 0 |
| #define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG0_SHIFT))&CCM_CCGR0_CG0_MASK) |
| #define CCM_CCGR0_CG1_MASK 0xCu |
| #define CCM_CCGR0_CG1_SHIFT 2 |
| #define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG1_SHIFT))&CCM_CCGR0_CG1_MASK) |
| #define CCM_CCGR0_CG2_MASK 0x30u |
| #define CCM_CCGR0_CG2_SHIFT 4 |
| #define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG2_SHIFT))&CCM_CCGR0_CG2_MASK) |
| #define CCM_CCGR0_CG3_MASK 0xC0u |
| #define CCM_CCGR0_CG3_SHIFT 6 |
| #define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG3_SHIFT))&CCM_CCGR0_CG3_MASK) |
| #define CCM_CCGR0_CG4_MASK 0x300u |
| #define CCM_CCGR0_CG4_SHIFT 8 |
| #define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG4_SHIFT))&CCM_CCGR0_CG4_MASK) |
| #define CCM_CCGR0_CG5_MASK 0xC00u |
| #define CCM_CCGR0_CG5_SHIFT 10 |
| #define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG5_SHIFT))&CCM_CCGR0_CG5_MASK) |
| #define CCM_CCGR0_CG6_MASK 0x3000u |
| #define CCM_CCGR0_CG6_SHIFT 12 |
| #define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG6_SHIFT))&CCM_CCGR0_CG6_MASK) |
| #define CCM_CCGR0_CG7_MASK 0xC000u |
| #define CCM_CCGR0_CG7_SHIFT 14 |
| #define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG7_SHIFT))&CCM_CCGR0_CG7_MASK) |
| #define CCM_CCGR0_CG8_MASK 0x30000u |
| #define CCM_CCGR0_CG8_SHIFT 16 |
| #define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG8_SHIFT))&CCM_CCGR0_CG8_MASK) |
| #define CCM_CCGR0_CG9_MASK 0xC0000u |
| #define CCM_CCGR0_CG9_SHIFT 18 |
| #define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG9_SHIFT))&CCM_CCGR0_CG9_MASK) |
| #define CCM_CCGR0_CG10_MASK 0x300000u |
| #define CCM_CCGR0_CG10_SHIFT 20 |
| #define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG10_SHIFT))&CCM_CCGR0_CG10_MASK) |
| #define CCM_CCGR0_CG11_MASK 0xC00000u |
| #define CCM_CCGR0_CG11_SHIFT 22 |
| #define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG11_SHIFT))&CCM_CCGR0_CG11_MASK) |
| #define CCM_CCGR0_CG12_MASK 0x3000000u |
| #define CCM_CCGR0_CG12_SHIFT 24 |
| #define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG12_SHIFT))&CCM_CCGR0_CG12_MASK) |
| #define CCM_CCGR0_CG13_MASK 0xC000000u |
| #define CCM_CCGR0_CG13_SHIFT 26 |
| #define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG13_SHIFT))&CCM_CCGR0_CG13_MASK) |
| #define CCM_CCGR0_CG14_MASK 0x30000000u |
| #define CCM_CCGR0_CG14_SHIFT 28 |
| #define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG14_SHIFT))&CCM_CCGR0_CG14_MASK) |
| #define CCM_CCGR0_CG15_MASK 0xC0000000u |
| #define CCM_CCGR0_CG15_SHIFT 30 |
| #define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG15_SHIFT))&CCM_CCGR0_CG15_MASK) |
| /* CCGR1 Bit Fields */ |
| #define CCM_CCGR1_CG0_MASK 0x3u |
| #define CCM_CCGR1_CG0_SHIFT 0 |
| #define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG0_SHIFT))&CCM_CCGR1_CG0_MASK) |
| #define CCM_CCGR1_CG1_MASK 0xCu |
| #define CCM_CCGR1_CG1_SHIFT 2 |
| #define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG1_SHIFT))&CCM_CCGR1_CG1_MASK) |
| #define CCM_CCGR1_CG2_MASK 0x30u |
| #define CCM_CCGR1_CG2_SHIFT 4 |
| #define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG2_SHIFT))&CCM_CCGR1_CG2_MASK) |
| #define CCM_CCGR1_CG3_MASK 0xC0u |
| #define CCM_CCGR1_CG3_SHIFT 6 |
| #define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG3_SHIFT))&CCM_CCGR1_CG3_MASK) |
| #define CCM_CCGR1_CG4_MASK 0x300u |
| #define CCM_CCGR1_CG4_SHIFT 8 |
| #define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG4_SHIFT))&CCM_CCGR1_CG4_MASK) |
| #define CCM_CCGR1_CG5_MASK 0xC00u |
| #define CCM_CCGR1_CG5_SHIFT 10 |
| #define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG5_SHIFT))&CCM_CCGR1_CG5_MASK) |
| #define CCM_CCGR1_CG6_MASK 0x3000u |
| #define CCM_CCGR1_CG6_SHIFT 12 |
| #define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG6_SHIFT))&CCM_CCGR1_CG6_MASK) |
| #define CCM_CCGR1_CG7_MASK 0xC000u |
| #define CCM_CCGR1_CG7_SHIFT 14 |
| #define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG7_SHIFT))&CCM_CCGR1_CG7_MASK) |
| #define CCM_CCGR1_CG8_MASK 0x30000u |
| #define CCM_CCGR1_CG8_SHIFT 16 |
| #define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG8_SHIFT))&CCM_CCGR1_CG8_MASK) |
| #define CCM_CCGR1_CG9_MASK 0xC0000u |
| #define CCM_CCGR1_CG9_SHIFT 18 |
| #define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG9_SHIFT))&CCM_CCGR1_CG9_MASK) |
| #define CCM_CCGR1_CG10_MASK 0x300000u |
| #define CCM_CCGR1_CG10_SHIFT 20 |
| #define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG10_SHIFT))&CCM_CCGR1_CG10_MASK) |
| #define CCM_CCGR1_CG11_MASK 0xC00000u |
| #define CCM_CCGR1_CG11_SHIFT 22 |
| #define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG11_SHIFT))&CCM_CCGR1_CG11_MASK) |
| #define CCM_CCGR1_CG12_MASK 0x3000000u |
| #define CCM_CCGR1_CG12_SHIFT 24 |
| #define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG12_SHIFT))&CCM_CCGR1_CG12_MASK) |
| #define CCM_CCGR1_CG13_MASK 0xC000000u |
| #define CCM_CCGR1_CG13_SHIFT 26 |
| #define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG13_SHIFT))&CCM_CCGR1_CG13_MASK) |
| #define CCM_CCGR1_CG14_MASK 0x30000000u |
| #define CCM_CCGR1_CG14_SHIFT 28 |
| #define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG14_SHIFT))&CCM_CCGR1_CG14_MASK) |
| #define CCM_CCGR1_CG15_MASK 0xC0000000u |
| #define CCM_CCGR1_CG15_SHIFT 30 |
| #define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG15_SHIFT))&CCM_CCGR1_CG15_MASK) |
| /* CCGR2 Bit Fields */ |
| #define CCM_CCGR2_CG0_MASK 0x3u |
| #define CCM_CCGR2_CG0_SHIFT 0 |
| #define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG0_SHIFT))&CCM_CCGR2_CG0_MASK) |
| #define CCM_CCGR2_CG1_MASK 0xCu |
| #define CCM_CCGR2_CG1_SHIFT 2 |
| #define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG1_SHIFT))&CCM_CCGR2_CG1_MASK) |
| #define CCM_CCGR2_CG2_MASK 0x30u |
| #define CCM_CCGR2_CG2_SHIFT 4 |
| #define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG2_SHIFT))&CCM_CCGR2_CG2_MASK) |
| #define CCM_CCGR2_CG3_MASK 0xC0u |
| #define CCM_CCGR2_CG3_SHIFT 6 |
| #define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG3_SHIFT))&CCM_CCGR2_CG3_MASK) |
| #define CCM_CCGR2_CG4_MASK 0x300u |
| #define CCM_CCGR2_CG4_SHIFT 8 |
| #define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG4_SHIFT))&CCM_CCGR2_CG4_MASK) |
| #define CCM_CCGR2_CG5_MASK 0xC00u |
| #define CCM_CCGR2_CG5_SHIFT 10 |
| #define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG5_SHIFT))&CCM_CCGR2_CG5_MASK) |
| #define CCM_CCGR2_CG6_MASK 0x3000u |
| #define CCM_CCGR2_CG6_SHIFT 12 |
| #define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG6_SHIFT))&CCM_CCGR2_CG6_MASK) |
| #define CCM_CCGR2_CG7_MASK 0xC000u |
| #define CCM_CCGR2_CG7_SHIFT 14 |
| #define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG7_SHIFT))&CCM_CCGR2_CG7_MASK) |
| #define CCM_CCGR2_CG8_MASK 0x30000u |
| #define CCM_CCGR2_CG8_SHIFT 16 |
| #define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG8_SHIFT))&CCM_CCGR2_CG8_MASK) |
| #define CCM_CCGR2_CG9_MASK 0xC0000u |
| #define CCM_CCGR2_CG9_SHIFT 18 |
| #define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG9_SHIFT))&CCM_CCGR2_CG9_MASK) |
| #define CCM_CCGR2_CG10_MASK 0x300000u |
| #define CCM_CCGR2_CG10_SHIFT 20 |
| #define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG10_SHIFT))&CCM_CCGR2_CG10_MASK) |
| #define CCM_CCGR2_CG11_MASK 0xC00000u |
| #define CCM_CCGR2_CG11_SHIFT 22 |
| #define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG11_SHIFT))&CCM_CCGR2_CG11_MASK) |
| #define CCM_CCGR2_CG12_MASK 0x3000000u |
| #define CCM_CCGR2_CG12_SHIFT 24 |
| #define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG12_SHIFT))&CCM_CCGR2_CG12_MASK) |
| #define CCM_CCGR2_CG13_MASK 0xC000000u |
| #define CCM_CCGR2_CG13_SHIFT 26 |
| #define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG13_SHIFT))&CCM_CCGR2_CG13_MASK) |
| #define CCM_CCGR2_CG14_MASK 0x30000000u |
| #define CCM_CCGR2_CG14_SHIFT 28 |
| #define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG14_SHIFT))&CCM_CCGR2_CG14_MASK) |
| #define CCM_CCGR2_CG15_MASK 0xC0000000u |
| #define CCM_CCGR2_CG15_SHIFT 30 |
| #define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG15_SHIFT))&CCM_CCGR2_CG15_MASK) |
| /* CCGR3 Bit Fields */ |
| #define CCM_CCGR3_CG0_MASK 0x3u |
| #define CCM_CCGR3_CG0_SHIFT 0 |
| #define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG0_SHIFT))&CCM_CCGR3_CG0_MASK) |
| #define CCM_CCGR3_CG1_MASK 0xCu |
| #define CCM_CCGR3_CG1_SHIFT 2 |
| #define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG1_SHIFT))&CCM_CCGR3_CG1_MASK) |
| #define CCM_CCGR3_CG2_MASK 0x30u |
| #define CCM_CCGR3_CG2_SHIFT 4 |
| #define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG2_SHIFT))&CCM_CCGR3_CG2_MASK) |
| #define CCM_CCGR3_CG3_MASK 0xC0u |
| #define CCM_CCGR3_CG3_SHIFT 6 |
| #define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG3_SHIFT))&CCM_CCGR3_CG3_MASK) |
| #define CCM_CCGR3_CG4_MASK 0x300u |
| #define CCM_CCGR3_CG4_SHIFT 8 |
| #define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG4_SHIFT))&CCM_CCGR3_CG4_MASK) |
| #define CCM_CCGR3_CG5_MASK 0xC00u |
| #define CCM_CCGR3_CG5_SHIFT 10 |
| #define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG5_SHIFT))&CCM_CCGR3_CG5_MASK) |
| #define CCM_CCGR3_CG6_MASK 0x3000u |
| #define CCM_CCGR3_CG6_SHIFT 12 |
| #define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG6_SHIFT))&CCM_CCGR3_CG6_MASK) |
| #define CCM_CCGR3_CG7_MASK 0xC000u |
| #define CCM_CCGR3_CG7_SHIFT 14 |
| #define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG7_SHIFT))&CCM_CCGR3_CG7_MASK) |
| #define CCM_CCGR3_CG8_MASK 0x30000u |
| #define CCM_CCGR3_CG8_SHIFT 16 |
| #define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG8_SHIFT))&CCM_CCGR3_CG8_MASK) |
| #define CCM_CCGR3_CG9_MASK 0xC0000u |
| #define CCM_CCGR3_CG9_SHIFT 18 |
| #define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG9_SHIFT))&CCM_CCGR3_CG9_MASK) |
| #define CCM_CCGR3_CG10_MASK 0x300000u |
| #define CCM_CCGR3_CG10_SHIFT 20 |
| #define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG10_SHIFT))&CCM_CCGR3_CG10_MASK) |
| #define CCM_CCGR3_CG11_MASK 0xC00000u |
| #define CCM_CCGR3_CG11_SHIFT 22 |
| #define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG11_SHIFT))&CCM_CCGR3_CG11_MASK) |
| #define CCM_CCGR3_CG12_MASK 0x3000000u |
| #define CCM_CCGR3_CG12_SHIFT 24 |
| #define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG12_SHIFT))&CCM_CCGR3_CG12_MASK) |
| #define CCM_CCGR3_CG13_MASK 0xC000000u |
| #define CCM_CCGR3_CG13_SHIFT 26 |
| #define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG13_SHIFT))&CCM_CCGR3_CG13_MASK) |
| #define CCM_CCGR3_CG14_MASK 0x30000000u |
| #define CCM_CCGR3_CG14_SHIFT 28 |
| #define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG14_SHIFT))&CCM_CCGR3_CG14_MASK) |
| #define CCM_CCGR3_CG15_MASK 0xC0000000u |
| #define CCM_CCGR3_CG15_SHIFT 30 |
| #define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG15_SHIFT))&CCM_CCGR3_CG15_MASK) |
| /* CCGR4 Bit Fields */ |
| #define CCM_CCGR4_CG0_MASK 0x3u |
| #define CCM_CCGR4_CG0_SHIFT 0 |
| #define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG0_SHIFT))&CCM_CCGR4_CG0_MASK) |
| #define CCM_CCGR4_CG1_MASK 0xCu |
| #define CCM_CCGR4_CG1_SHIFT 2 |
| #define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG1_SHIFT))&CCM_CCGR4_CG1_MASK) |
| #define CCM_CCGR4_CG2_MASK 0x30u |
| #define CCM_CCGR4_CG2_SHIFT 4 |
| #define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG2_SHIFT))&CCM_CCGR4_CG2_MASK) |
| #define CCM_CCGR4_CG3_MASK 0xC0u |
| #define CCM_CCGR4_CG3_SHIFT 6 |
| #define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG3_SHIFT))&CCM_CCGR4_CG3_MASK) |
| #define CCM_CCGR4_CG4_MASK 0x300u |
| #define CCM_CCGR4_CG4_SHIFT 8 |
| #define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG4_SHIFT))&CCM_CCGR4_CG4_MASK) |
| #define CCM_CCGR4_CG5_MASK 0xC00u |
| #define CCM_CCGR4_CG5_SHIFT 10 |
| #define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG5_SHIFT))&CCM_CCGR4_CG5_MASK) |
| #define CCM_CCGR4_CG6_MASK 0x3000u |
| #define CCM_CCGR4_CG6_SHIFT 12 |
| #define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG6_SHIFT))&CCM_CCGR4_CG6_MASK) |
| #define CCM_CCGR4_CG7_MASK 0xC000u |
| #define CCM_CCGR4_CG7_SHIFT 14 |
| #define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG7_SHIFT))&CCM_CCGR4_CG7_MASK) |
| #define CCM_CCGR4_CG8_MASK 0x30000u |
| #define CCM_CCGR4_CG8_SHIFT 16 |
| #define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG8_SHIFT))&CCM_CCGR4_CG8_MASK) |
| #define CCM_CCGR4_CG9_MASK 0xC0000u |
| #define CCM_CCGR4_CG9_SHIFT 18 |
| #define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG9_SHIFT))&CCM_CCGR4_CG9_MASK) |
| #define CCM_CCGR4_CG10_MASK 0x300000u |
| #define CCM_CCGR4_CG10_SHIFT 20 |
| #define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG10_SHIFT))&CCM_CCGR4_CG10_MASK) |
| #define CCM_CCGR4_CG11_MASK 0xC00000u |
| #define CCM_CCGR4_CG11_SHIFT 22 |
| #define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG11_SHIFT))&CCM_CCGR4_CG11_MASK) |
| #define CCM_CCGR4_CG12_MASK 0x3000000u |
| #define CCM_CCGR4_CG12_SHIFT 24 |
| #define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG12_SHIFT))&CCM_CCGR4_CG12_MASK) |
| #define CCM_CCGR4_CG13_MASK 0xC000000u |
| #define CCM_CCGR4_CG13_SHIFT 26 |
| #define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG13_SHIFT))&CCM_CCGR4_CG13_MASK) |
| #define CCM_CCGR4_CG14_MASK 0x30000000u |
| #define CCM_CCGR4_CG14_SHIFT 28 |
| #define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG14_SHIFT))&CCM_CCGR4_CG14_MASK) |
| #define CCM_CCGR4_CG15_MASK 0xC0000000u |
| #define CCM_CCGR4_CG15_SHIFT 30 |
| #define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG15_SHIFT))&CCM_CCGR4_CG15_MASK) |
| /* CCGR5 Bit Fields */ |
| #define CCM_CCGR5_CG0_MASK 0x3u |
| #define CCM_CCGR5_CG0_SHIFT 0 |
| #define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG0_SHIFT))&CCM_CCGR5_CG0_MASK) |
| #define CCM_CCGR5_CG1_MASK 0xCu |
| #define CCM_CCGR5_CG1_SHIFT 2 |
| #define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG1_SHIFT))&CCM_CCGR5_CG1_MASK) |
| #define CCM_CCGR5_CG2_MASK 0x30u |
| #define CCM_CCGR5_CG2_SHIFT 4 |
| #define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG2_SHIFT))&CCM_CCGR5_CG2_MASK) |
| #define CCM_CCGR5_CG3_MASK 0xC0u |
| #define CCM_CCGR5_CG3_SHIFT 6 |
| #define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG3_SHIFT))&CCM_CCGR5_CG3_MASK) |
| #define CCM_CCGR5_CG4_MASK 0x300u |
| #define CCM_CCGR5_CG4_SHIFT 8 |
| #define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG4_SHIFT))&CCM_CCGR5_CG4_MASK) |
| #define CCM_CCGR5_CG5_MASK 0xC00u |
| #define CCM_CCGR5_CG5_SHIFT 10 |
| #define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG5_SHIFT))&CCM_CCGR5_CG5_MASK) |
| #define CCM_CCGR5_CG6_MASK 0x3000u |
| #define CCM_CCGR5_CG6_SHIFT 12 |
| #define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG6_SHIFT))&CCM_CCGR5_CG6_MASK) |
| #define CCM_CCGR5_CG7_MASK 0xC000u |
| #define CCM_CCGR5_CG7_SHIFT 14 |
| #define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG7_SHIFT))&CCM_CCGR5_CG7_MASK) |
| #define CCM_CCGR5_CG8_MASK 0x30000u |
| #define CCM_CCGR5_CG8_SHIFT 16 |
| #define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG8_SHIFT))&CCM_CCGR5_CG8_MASK) |
| #define CCM_CCGR5_CG9_MASK 0xC0000u |
| #define CCM_CCGR5_CG9_SHIFT 18 |
| #define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG9_SHIFT))&CCM_CCGR5_CG9_MASK) |
| #define CCM_CCGR5_CG10_MASK 0x300000u |
| #define CCM_CCGR5_CG10_SHIFT 20 |
| #define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG10_SHIFT))&CCM_CCGR5_CG10_MASK) |
| #define CCM_CCGR5_CG11_MASK 0xC00000u |
| #define CCM_CCGR5_CG11_SHIFT 22 |
| #define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG11_SHIFT))&CCM_CCGR5_CG11_MASK) |
| #define CCM_CCGR5_CG12_MASK 0x3000000u |
| #define CCM_CCGR5_CG12_SHIFT 24 |
| #define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG12_SHIFT))&CCM_CCGR5_CG12_MASK) |
| #define CCM_CCGR5_CG13_MASK 0xC000000u |
| #define CCM_CCGR5_CG13_SHIFT 26 |
| #define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG13_SHIFT))&CCM_CCGR5_CG13_MASK) |
| #define CCM_CCGR5_CG14_MASK 0x30000000u |
| #define CCM_CCGR5_CG14_SHIFT 28 |
| #define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG14_SHIFT))&CCM_CCGR5_CG14_MASK) |
| #define CCM_CCGR5_CG15_MASK 0xC0000000u |
| #define CCM_CCGR5_CG15_SHIFT 30 |
| #define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG15_SHIFT))&CCM_CCGR5_CG15_MASK) |
| /* CCGR6 Bit Fields */ |
| #define CCM_CCGR6_CG0_MASK 0x3u |
| #define CCM_CCGR6_CG0_SHIFT 0 |
| #define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG0_SHIFT))&CCM_CCGR6_CG0_MASK) |
| #define CCM_CCGR6_CG1_MASK 0xCu |
| #define CCM_CCGR6_CG1_SHIFT 2 |
| #define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG1_SHIFT))&CCM_CCGR6_CG1_MASK) |
| #define CCM_CCGR6_CG2_MASK 0x30u |
| #define CCM_CCGR6_CG2_SHIFT 4 |
| #define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG2_SHIFT))&CCM_CCGR6_CG2_MASK) |
| #define CCM_CCGR6_CG3_MASK 0xC0u |
| #define CCM_CCGR6_CG3_SHIFT 6 |
| #define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG3_SHIFT))&CCM_CCGR6_CG3_MASK) |
| #define CCM_CCGR6_CG4_MASK 0x300u |
| #define CCM_CCGR6_CG4_SHIFT 8 |
| #define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG4_SHIFT))&CCM_CCGR6_CG4_MASK) |
| #define CCM_CCGR6_CG5_MASK 0xC00u |
| #define CCM_CCGR6_CG5_SHIFT 10 |
| #define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG5_SHIFT))&CCM_CCGR6_CG5_MASK) |
| #define CCM_CCGR6_CG6_MASK 0x3000u |
| #define CCM_CCGR6_CG6_SHIFT 12 |
| #define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG6_SHIFT))&CCM_CCGR6_CG6_MASK) |
| #define CCM_CCGR6_CG7_MASK 0xC000u |
| #define CCM_CCGR6_CG7_SHIFT 14 |
| #define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG7_SHIFT))&CCM_CCGR6_CG7_MASK) |
| #define CCM_CCGR6_CG8_MASK 0x30000u |
| #define CCM_CCGR6_CG8_SHIFT 16 |
| #define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG8_SHIFT))&CCM_CCGR6_CG8_MASK) |
| #define CCM_CCGR6_CG9_MASK 0xC0000u |
| #define CCM_CCGR6_CG9_SHIFT 18 |
| #define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG9_SHIFT))&CCM_CCGR6_CG9_MASK) |
| #define CCM_CCGR6_CG10_MASK 0x300000u |
| #define CCM_CCGR6_CG10_SHIFT 20 |
| #define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG10_SHIFT))&CCM_CCGR6_CG10_MASK) |
| #define CCM_CCGR6_CG11_MASK 0xC00000u |
| #define CCM_CCGR6_CG11_SHIFT 22 |
| #define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG11_SHIFT))&CCM_CCGR6_CG11_MASK) |
| #define CCM_CCGR6_CG12_MASK 0x3000000u |
| #define CCM_CCGR6_CG12_SHIFT 24 |
| #define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG12_SHIFT))&CCM_CCGR6_CG12_MASK) |
| #define CCM_CCGR6_CG13_MASK 0xC000000u |
| #define CCM_CCGR6_CG13_SHIFT 26 |
| #define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG13_SHIFT))&CCM_CCGR6_CG13_MASK) |
| #define CCM_CCGR6_CG14_MASK 0x30000000u |
| #define CCM_CCGR6_CG14_SHIFT 28 |
| #define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG14_SHIFT))&CCM_CCGR6_CG14_MASK) |
| #define CCM_CCGR6_CG15_MASK 0xC0000000u |
| #define CCM_CCGR6_CG15_SHIFT 30 |
| #define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG15_SHIFT))&CCM_CCGR6_CG15_MASK) |
| /* CMEOR Bit Fields */ |
| #define CCM_CMEOR_mod_en_ov_gpt_MASK 0x20u |
| #define CCM_CMEOR_mod_en_ov_gpt_SHIFT 5 |
| #define CCM_CMEOR_mod_en_ov_epit_MASK 0x40u |
| #define CCM_CMEOR_mod_en_ov_epit_SHIFT 6 |
| #define CCM_CMEOR_mod_en_usdhc_MASK 0x80u |
| #define CCM_CMEOR_mod_en_usdhc_SHIFT 7 |
| #define CCM_CMEOR_mod_en_ov_gpu_MASK 0x400u |
| #define CCM_CMEOR_mod_en_ov_gpu_SHIFT 10 |
| #define CCM_CMEOR_mod_en_ov_can2_cpi_MASK 0x10000000u |
| #define CCM_CMEOR_mod_en_ov_can2_cpi_SHIFT 28 |
| #define CCM_CMEOR_mod_en_ov_can1_cpi_MASK 0x40000000u |
| #define CCM_CMEOR_mod_en_ov_can1_cpi_SHIFT 30 |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Register_Masks */ |
| |
| /* CCM - Peripheral instance base addresses */ |
| /** Peripheral CCM base address */ |
| #define CCM_BASE (0x420C4000u) |
| /** Peripheral CCM base pointer */ |
| #define CCM ((CCM_Type *)CCM_BASE) |
| #define CCM_BASE_PTR (CCM) |
| /** Array initializer of CCM peripheral base addresses */ |
| #define CCM_BASE_ADDRS { CCM_BASE } |
| /** Array initializer of CCM peripheral base pointers */ |
| #define CCM_BASE_PTRS { CCM } |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros |
| * @{ |
| */ |
| |
| /* CCM - Register instance definitions */ |
| /* CCM */ |
| #define CCM_CCR CCM_CCR_REG(CCM_BASE_PTR) |
| #define CCM_CCDR CCM_CCDR_REG(CCM_BASE_PTR) |
| #define CCM_CSR CCM_CSR_REG(CCM_BASE_PTR) |
| #define CCM_CCSR CCM_CCSR_REG(CCM_BASE_PTR) |
| #define CCM_CACRR CCM_CACRR_REG(CCM_BASE_PTR) |
| #define CCM_CBCDR CCM_CBCDR_REG(CCM_BASE_PTR) |
| #define CCM_CBCMR CCM_CBCMR_REG(CCM_BASE_PTR) |
| #define CCM_CSCMR1 CCM_CSCMR1_REG(CCM_BASE_PTR) |
| #define CCM_CSCMR2 CCM_CSCMR2_REG(CCM_BASE_PTR) |
| #define CCM_CSCDR1 CCM_CSCDR1_REG(CCM_BASE_PTR) |
| #define CCM_CS1CDR CCM_CS1CDR_REG(CCM_BASE_PTR) |
| #define CCM_CS2CDR CCM_CS2CDR_REG(CCM_BASE_PTR) |
| #define CCM_CDCDR CCM_CDCDR_REG(CCM_BASE_PTR) |
| #define CCM_CHSCCDR CCM_CHSCCDR_REG(CCM_BASE_PTR) |
| #define CCM_CSCDR2 CCM_CSCDR2_REG(CCM_BASE_PTR) |
| #define CCM_CSCDR3 CCM_CSCDR3_REG(CCM_BASE_PTR) |
| #define CCM_CWDR CCM_CWDR_REG(CCM_BASE_PTR) |
| #define CCM_CDHIPR CCM_CDHIPR_REG(CCM_BASE_PTR) |
| #define CCM_CLPCR CCM_CLPCR_REG(CCM_BASE_PTR) |
| #define CCM_CISR CCM_CISR_REG(CCM_BASE_PTR) |
| #define CCM_CIMR CCM_CIMR_REG(CCM_BASE_PTR) |
| #define CCM_CCOSR CCM_CCOSR_REG(CCM_BASE_PTR) |
| #define CCM_CGPR CCM_CGPR_REG(CCM_BASE_PTR) |
| #define CCM_CCGR0 CCM_CCGR0_REG(CCM_BASE_PTR) |
| #define CCM_CCGR1 CCM_CCGR1_REG(CCM_BASE_PTR) |
| #define CCM_CCGR2 CCM_CCGR2_REG(CCM_BASE_PTR) |
| #define CCM_CCGR3 CCM_CCGR3_REG(CCM_BASE_PTR) |
| #define CCM_CCGR4 CCM_CCGR4_REG(CCM_BASE_PTR) |
| #define CCM_CCGR5 CCM_CCGR5_REG(CCM_BASE_PTR) |
| #define CCM_CCGR6 CCM_CCGR6_REG(CCM_BASE_PTR) |
| #define CCM_CMEOR CCM_CMEOR_REG(CCM_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group CCM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CCM_ANALOG - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ |
| __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ |
| __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ |
| __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ |
| __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ |
| __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ |
| __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ |
| __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ |
| __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ |
| __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ |
| __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ |
| __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ |
| __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ |
| __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ |
| __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ |
| __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ |
| __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ |
| uint8_t RESERVED_0[44]; |
| __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ |
| __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ |
| __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ |
| __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ |
| __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ |
| __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ |
| __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ |
| __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ |
| __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ |
| uint8_t RESERVED_4[28]; |
| __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ |
| __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ |
| __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ |
| __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ |
| __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ |
| __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ |
| __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ |
| __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ |
| __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ |
| __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ |
| __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ |
| __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ |
| uint8_t RESERVED_5[64]; |
| __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ |
| __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ |
| __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ |
| __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ |
| __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ |
| __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ |
| __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ |
| __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ |
| __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ |
| __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ |
| __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ |
| __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ |
| } CCM_ANALOG_Type, *CCM_ANALOG_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* CCM_ANALOG - Register accessors */ |
| #define CCM_ANALOG_PLL_ARM_REG(base) ((base)->PLL_ARM) |
| #define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) |
| #define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) |
| #define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) |
| #define CCM_ANALOG_PLL_USB1_REG(base) ((base)->PLL_USB1) |
| #define CCM_ANALOG_PLL_USB1_SET_REG(base) ((base)->PLL_USB1_SET) |
| #define CCM_ANALOG_PLL_USB1_CLR_REG(base) ((base)->PLL_USB1_CLR) |
| #define CCM_ANALOG_PLL_USB1_TOG_REG(base) ((base)->PLL_USB1_TOG) |
| #define CCM_ANALOG_PLL_USB2_REG(base) ((base)->PLL_USB2) |
| #define CCM_ANALOG_PLL_USB2_SET_REG(base) ((base)->PLL_USB2_SET) |
| #define CCM_ANALOG_PLL_USB2_CLR_REG(base) ((base)->PLL_USB2_CLR) |
| #define CCM_ANALOG_PLL_USB2_TOG_REG(base) ((base)->PLL_USB2_TOG) |
| #define CCM_ANALOG_PLL_SYS_REG(base) ((base)->PLL_SYS) |
| #define CCM_ANALOG_PLL_SYS_SET_REG(base) ((base)->PLL_SYS_SET) |
| #define CCM_ANALOG_PLL_SYS_CLR_REG(base) ((base)->PLL_SYS_CLR) |
| #define CCM_ANALOG_PLL_SYS_TOG_REG(base) ((base)->PLL_SYS_TOG) |
| #define CCM_ANALOG_PLL_SYS_SS_REG(base) ((base)->PLL_SYS_SS) |
| #define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) |
| #define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) |
| #define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) |
| #define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) |
| #define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) |
| #define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) |
| #define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) |
| #define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) |
| #define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) |
| #define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) |
| #define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) |
| #define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) |
| #define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) |
| #define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) |
| #define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) |
| #define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) |
| #define CCM_ANALOG_PFD_480_REG(base) ((base)->PFD_480) |
| #define CCM_ANALOG_PFD_480_SET_REG(base) ((base)->PFD_480_SET) |
| #define CCM_ANALOG_PFD_480_CLR_REG(base) ((base)->PFD_480_CLR) |
| #define CCM_ANALOG_PFD_480_TOG_REG(base) ((base)->PFD_480_TOG) |
| #define CCM_ANALOG_PFD_528_REG(base) ((base)->PFD_528) |
| #define CCM_ANALOG_PFD_528_SET_REG(base) ((base)->PFD_528_SET) |
| #define CCM_ANALOG_PFD_528_CLR_REG(base) ((base)->PFD_528_CLR) |
| #define CCM_ANALOG_PFD_528_TOG_REG(base) ((base)->PFD_528_TOG) |
| #define CCM_ANALOG_MISC0_REG(base) ((base)->MISC0) |
| #define CCM_ANALOG_MISC0_SET_REG(base) ((base)->MISC0_SET) |
| #define CCM_ANALOG_MISC0_CLR_REG(base) ((base)->MISC0_CLR) |
| #define CCM_ANALOG_MISC0_TOG_REG(base) ((base)->MISC0_TOG) |
| #define CCM_ANALOG_MISC1_REG(base) ((base)->MISC1) |
| #define CCM_ANALOG_MISC1_SET_REG(base) ((base)->MISC1_SET) |
| #define CCM_ANALOG_MISC1_CLR_REG(base) ((base)->MISC1_CLR) |
| #define CCM_ANALOG_MISC1_TOG_REG(base) ((base)->MISC1_TOG) |
| #define CCM_ANALOG_MISC2_REG(base) ((base)->MISC2) |
| #define CCM_ANALOG_MISC2_SET_REG(base) ((base)->MISC2_SET) |
| #define CCM_ANALOG_MISC2_CLR_REG(base) ((base)->MISC2_CLR) |
| #define CCM_ANALOG_MISC2_TOG_REG(base) ((base)->MISC2_TOG) |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks |
| * @{ |
| */ |
| |
| /* PLL_ARM Bit Fields */ |
| #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ARM_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000u |
| #define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 |
| #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 |
| #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 |
| #define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 |
| /* PLL_ARM_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_MASK 0x20000u |
| #define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_SHIFT 17 |
| #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_SHIFT 18 |
| #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT 19 |
| #define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT 31 |
| /* PLL_ARM_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_MASK 0x20000u |
| #define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_SHIFT 17 |
| #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_SHIFT 18 |
| #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT 19 |
| #define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT 31 |
| /* PLL_ARM_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_MASK 0x20000u |
| #define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_SHIFT 17 |
| #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_SHIFT 18 |
| #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT 19 |
| #define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT 31 |
| /* PLL_USB1 Bit Fields */ |
| #define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB1_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB1_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB1_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB1_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB1_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB1_LOCK_SHIFT 31 |
| /* PLL_USB1_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB1_SET_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT 31 |
| /* PLL_USB1_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT 31 |
| /* PLL_USB1_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT 31 |
| /* PLL_USB2 Bit Fields */ |
| #define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB2_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB2_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB2_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB2_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB2_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB2_LOCK_SHIFT 31 |
| /* PLL_USB2_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB2_SET_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT 31 |
| /* PLL_USB2_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT 31 |
| /* PLL_USB2_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK 0x40u |
| #define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT 6 |
| #define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK 0x1000u |
| #define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT 12 |
| #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT 31 |
| /* PLL_SYS Bit Fields */ |
| #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK 0x1u |
| #define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_SYS_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_SYS_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_SYS_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_SYS_LOCK_SHIFT 31 |
| /* PLL_SYS_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK 0x1u |
| #define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT 31 |
| /* PLL_SYS_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK 0x1u |
| #define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT 31 |
| /* PLL_SYS_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK 0x1u |
| #define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT 31 |
| /* PLL_SYS_SS Bit Fields */ |
| #define CCM_ANALOG_PLL_SYS_SS_STEP_MASK 0x7FFFu |
| #define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT 0 |
| #define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT))&CCM_ANALOG_PLL_SYS_SS_STEP_MASK) |
| #define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK 0x8000u |
| #define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT 15 |
| #define CCM_ANALOG_PLL_SYS_SS_STOP_MASK 0xFFFF0000u |
| #define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT 16 |
| #define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT))&CCM_ANALOG_PLL_SYS_SS_STOP_MASK) |
| /* PLL_AUDIO Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 |
| /* PLL_AUDIO_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 |
| /* PLL_AUDIO_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 |
| /* PLL_AUDIO_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 |
| /* PLL_AUDIO_NUM Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu |
| #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) |
| /* PLL_AUDIO_DENOM Bit Fields */ |
| #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu |
| #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 |
| #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) |
| /* PLL_VIDEO Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 |
| /* PLL_VIDEO_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 |
| /* PLL_VIDEO_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 |
| /* PLL_VIDEO_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu |
| #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK 0x2000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT 13 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK 0x180000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT 19 |
| #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 |
| /* PLL_VIDEO_NUM Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu |
| #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) |
| /* PLL_VIDEO_DENOM Bit Fields */ |
| #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu |
| #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 |
| #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) |
| /* PLL_ENET Bit Fields */ |
| #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK 0xCu |
| #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT 2 |
| #define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT 13 |
| #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT 19 |
| #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK 0x100000u |
| #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT 20 |
| #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK 0x200000u |
| #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT 21 |
| #define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 |
| /* PLL_ENET_SET Bit Fields */ |
| #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK 0xCu |
| #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT 2 |
| #define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT 13 |
| #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT 19 |
| #define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK 0x100000u |
| #define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT 20 |
| #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK 0x200000u |
| #define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT 21 |
| #define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT 31 |
| /* PLL_ENET_CLR Bit Fields */ |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK 0xCu |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT 2 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT 13 |
| #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT 19 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK 0x100000u |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT 20 |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK 0x200000u |
| #define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT 21 |
| #define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT 31 |
| /* PLL_ENET_TOG Bit Fields */ |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK 0x3u |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT 0 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK 0xCu |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT 2 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) |
| #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK 0x1000u |
| #define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT 12 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK 0x2000u |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT 13 |
| #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK 0xC000u |
| #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT 14 |
| #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) |
| #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK 0x10000u |
| #define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT 16 |
| #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK 0x40000u |
| #define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT 18 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK 0x80000u |
| #define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT 19 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK 0x100000u |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT 20 |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK 0x200000u |
| #define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT 21 |
| #define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK 0x80000000u |
| #define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT 31 |
| /* PFD_480 Bit Fields */ |
| #define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_480_SET Bit Fields */ |
| #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_480_CLR Bit Fields */ |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_480_TOG Bit Fields */ |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_528 Bit Fields */ |
| #define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_528_SET Bit Fields */ |
| #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_528_CLR Bit Fields */ |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT 31 |
| /* PFD_528_TOG Bit Fields */ |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK 0x3Fu |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT 0 |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK 0x40u |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT 6 |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK 0x80u |
| #define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT 7 |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK 0x3F00u |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT 8 |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK 0x4000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT 14 |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK 0x8000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT 15 |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK 0x3F0000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT 16 |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK 0x400000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT 22 |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK 0x800000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT 23 |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK 0x3F000000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT 24 |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK 0x40000000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT 30 |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK 0x80000000u |
| #define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT 31 |
| /* MISC0 Bit Fields */ |
| #define CCM_ANALOG_MISC0_REFTOP_PWD_MASK 0x1u |
| #define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT 0 |
| #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK 0x70u |
| #define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT 4 |
| #define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) |
| #define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK 0x80u |
| #define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT 7 |
| #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK 0xC00u |
| #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT 10 |
| #define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) |
| #define CCM_ANALOG_MISC0_RTC_RINGOSC_EN_MASK 0x1000u |
| #define CCM_ANALOG_MISC0_RTC_RINGOSC_EN_SHIFT 12 |
| #define CCM_ANALOG_MISC0_OSC_I_MASK 0x6000u |
| #define CCM_ANALOG_MISC0_OSC_I_SHIFT 13 |
| #define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_OSC_I_SHIFT))&CCM_ANALOG_MISC0_OSC_I_MASK) |
| #define CCM_ANALOG_MISC0_OSC_XTALOK_MASK 0x8000u |
| #define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT 15 |
| #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK 0x2000000u |
| #define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT 25 |
| #define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK 0x1C000000u |
| #define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT 26 |
| #define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) |
| #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT 29 |
| #define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK 0x40000000u |
| #define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT 30 |
| #define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK 0x80000000u |
| #define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT 31 |
| /* MISC0_SET Bit Fields */ |
| #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK 0x1u |
| #define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT 0 |
| #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK 0x70u |
| #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT 4 |
| #define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) |
| #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK 0x80u |
| #define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT 7 |
| #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK 0xC00u |
| #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT 10 |
| #define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) |
| #define CCM_ANALOG_MISC0_SET_RTC_RINGOSC_EN_MASK 0x1000u |
| #define CCM_ANALOG_MISC0_SET_RTC_RINGOSC_EN_SHIFT 12 |
| #define CCM_ANALOG_MISC0_SET_OSC_I_MASK 0x6000u |
| #define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT 13 |
| #define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_OSC_I_SHIFT))&CCM_ANALOG_MISC0_SET_OSC_I_MASK) |
| #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK 0x8000u |
| #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT 15 |
| #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK 0x2000000u |
| #define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT 25 |
| #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK 0x1C000000u |
| #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT 26 |
| #define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) |
| #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT 29 |
| #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK 0x40000000u |
| #define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT 30 |
| #define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK 0x80000000u |
| #define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT 31 |
| /* MISC0_CLR Bit Fields */ |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK 0x1u |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT 0 |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK 0x70u |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT 4 |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK 0x80u |
| #define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT 7 |
| #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK 0xC00u |
| #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT 10 |
| #define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) |
| #define CCM_ANALOG_MISC0_CLR_RTC_RINGOSC_EN_MASK 0x1000u |
| #define CCM_ANALOG_MISC0_CLR_RTC_RINGOSC_EN_SHIFT 12 |
| #define CCM_ANALOG_MISC0_CLR_OSC_I_MASK 0x6000u |
| #define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT 13 |
| #define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT))&CCM_ANALOG_MISC0_CLR_OSC_I_MASK) |
| #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK 0x8000u |
| #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT 15 |
| #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK 0x2000000u |
| #define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT 25 |
| #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK 0x1C000000u |
| #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT 26 |
| #define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) |
| #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT 29 |
| #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK 0x40000000u |
| #define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT 30 |
| #define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK 0x80000000u |
| #define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT 31 |
| /* MISC0_TOG Bit Fields */ |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK 0x1u |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT 0 |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK 0x70u |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT 4 |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT))&CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK 0x80u |
| #define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT 7 |
| #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK 0xC00u |
| #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT 10 |
| #define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT))&CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) |
| #define CCM_ANALOG_MISC0_TOG_RTC_RINGOSC_EN_MASK 0x1000u |
| #define CCM_ANALOG_MISC0_TOG_RTC_RINGOSC_EN_SHIFT 12 |
| #define CCM_ANALOG_MISC0_TOG_OSC_I_MASK 0x6000u |
| #define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT 13 |
| #define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT))&CCM_ANALOG_MISC0_TOG_OSC_I_MASK) |
| #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK 0x8000u |
| #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT 15 |
| #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK 0x2000000u |
| #define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT 25 |
| #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK 0x1C000000u |
| #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT 26 |
| #define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT))&CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) |
| #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT 29 |
| #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK 0x40000000u |
| #define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT 30 |
| #define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK 0x80000000u |
| #define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT 31 |
| /* MISC1 Bit Fields */ |
| #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT 0 |
| #define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL_SHIFT 5 |
| #define CCM_ANALOG_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_LVDS2_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK 0x400u |
| #define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT 10 |
| #define CCM_ANALOG_MISC1_LVDSCLK2_OBEN_MASK 0x800u |
| #define CCM_ANALOG_MISC1_LVDSCLK2_OBEN_SHIFT 11 |
| #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK 0x1000u |
| #define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT 12 |
| #define CCM_ANALOG_MISC1_LVDSCLK2_IBEN_MASK 0x2000u |
| #define CCM_ANALOG_MISC1_LVDSCLK2_IBEN_SHIFT 13 |
| #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT 27 |
| #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK 0x10000000u |
| #define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT 28 |
| #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT 29 |
| #define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK 0x40000000u |
| #define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT 30 |
| #define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK 0x80000000u |
| #define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_SET Bit Fields */ |
| #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT 0 |
| #define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_SHIFT 5 |
| #define CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_SET_LVDS2_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK 0x400u |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT 10 |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK2_OBEN_MASK 0x800u |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK2_OBEN_SHIFT 11 |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK 0x1000u |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT 12 |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK2_IBEN_MASK 0x2000u |
| #define CCM_ANALOG_MISC1_SET_LVDSCLK2_IBEN_SHIFT 13 |
| #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT 27 |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK 0x10000000u |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT 28 |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT 29 |
| #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK 0x40000000u |
| #define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT 30 |
| #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK 0x80000000u |
| #define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_CLR Bit Fields */ |
| #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT 0 |
| #define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_SHIFT 5 |
| #define CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_CLR_LVDS2_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK 0x400u |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT 10 |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_OBEN_MASK 0x800u |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_OBEN_SHIFT 11 |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK 0x1000u |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT 12 |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_IBEN_MASK 0x2000u |
| #define CCM_ANALOG_MISC1_CLR_LVDSCLK2_IBEN_SHIFT 13 |
| #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT 27 |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK 0x10000000u |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT 28 |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT 29 |
| #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK 0x40000000u |
| #define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT 30 |
| #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK 0x80000000u |
| #define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_TOG Bit Fields */ |
| #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT 0 |
| #define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_SHIFT 5 |
| #define CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_SHIFT))&CCM_ANALOG_MISC1_TOG_LVDS2_CLK_SEL_MASK) |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK 0x400u |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT 10 |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_OBEN_MASK 0x800u |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_OBEN_SHIFT 11 |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK 0x1000u |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT 12 |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_IBEN_MASK 0x2000u |
| #define CCM_ANALOG_MISC1_TOG_LVDSCLK2_IBEN_SHIFT 13 |
| #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT 27 |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK 0x10000000u |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT 28 |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT 29 |
| #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK 0x40000000u |
| #define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT 30 |
| #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK 0x80000000u |
| #define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT 31 |
| /* MISC2 Bit Fields */ |
| #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK 0x7u |
| #define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT 0 |
| #define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK 0x8u |
| #define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT 3 |
| #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK 0x20u |
| #define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT 5 |
| #define CCM_ANALOG_MISC2_PLL3_disable_MASK 0x80u |
| #define CCM_ANALOG_MISC2_PLL3_disable_SHIFT 7 |
| #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK 0x700u |
| #define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT 8 |
| #define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK 0x800u |
| #define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT 11 |
| #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK 0x2000u |
| #define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT 13 |
| #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK 0x8000u |
| #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT 15 |
| #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK 0x70000u |
| #define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT 16 |
| #define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK 0x80000u |
| #define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT 19 |
| #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK 0x200000u |
| #define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT 21 |
| #define CCM_ANALOG_MISC2_REG2_OK_MASK 0x400000u |
| #define CCM_ANALOG_MISC2_REG2_OK_SHIFT 22 |
| #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK 0x800000u |
| #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT 23 |
| #define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK 0x3000000u |
| #define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT 24 |
| #define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK 0xC000000u |
| #define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT 26 |
| #define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK 0x30000000u |
| #define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT 28 |
| #define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK 0xC0000000u |
| #define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT 30 |
| #define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_VIDEO_DIV_MASK) |
| /* MISC2_SET Bit Fields */ |
| #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK 0x7u |
| #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT 0 |
| #define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK 0x8u |
| #define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT 3 |
| #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK 0x20u |
| #define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT 5 |
| #define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK 0x80u |
| #define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT 7 |
| #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK 0x700u |
| #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT 8 |
| #define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK 0x800u |
| #define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT 11 |
| #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK 0x2000u |
| #define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT 13 |
| #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK 0x8000u |
| #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT 15 |
| #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK 0x70000u |
| #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT 16 |
| #define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK 0x80000u |
| #define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT 19 |
| #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK 0x200000u |
| #define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT 21 |
| #define CCM_ANALOG_MISC2_SET_REG2_OK_MASK 0x400000u |
| #define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT 22 |
| #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK 0x800000u |
| #define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT 23 |
| #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK 0x3000000u |
| #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT 24 |
| #define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK 0xC000000u |
| #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT 26 |
| #define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK 0x30000000u |
| #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT 28 |
| #define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK 0xC0000000u |
| #define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT 30 |
| #define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) |
| /* MISC2_CLR Bit Fields */ |
| #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK 0x7u |
| #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT 0 |
| #define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK 0x8u |
| #define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT 3 |
| #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK 0x20u |
| #define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT 5 |
| #define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK 0x80u |
| #define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT 7 |
| #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK 0x700u |
| #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT 8 |
| #define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK 0x800u |
| #define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT 11 |
| #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK 0x2000u |
| #define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT 13 |
| #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK 0x8000u |
| #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT 15 |
| #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK 0x70000u |
| #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT 16 |
| #define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK 0x80000u |
| #define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT 19 |
| #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK 0x200000u |
| #define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT 21 |
| #define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK 0x400000u |
| #define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT 22 |
| #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK 0x800000u |
| #define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT 23 |
| #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK 0x3000000u |
| #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT 24 |
| #define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK 0xC000000u |
| #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT 26 |
| #define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK 0x30000000u |
| #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT 28 |
| #define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK 0xC0000000u |
| #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT 30 |
| #define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) |
| /* MISC2_TOG Bit Fields */ |
| #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK 0x7u |
| #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT 0 |
| #define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK 0x8u |
| #define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT 3 |
| #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK 0x20u |
| #define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT 5 |
| #define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK 0x80u |
| #define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT 7 |
| #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK 0x700u |
| #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT 8 |
| #define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK 0x800u |
| #define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT 11 |
| #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK 0x2000u |
| #define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT 13 |
| #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK 0x8000u |
| #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT 15 |
| #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK 0x70000u |
| #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT 16 |
| #define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT))&CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) |
| #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK 0x80000u |
| #define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT 19 |
| #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK 0x200000u |
| #define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT 21 |
| #define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK 0x400000u |
| #define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT 22 |
| #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK 0x800000u |
| #define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT 23 |
| #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK 0x3000000u |
| #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT 24 |
| #define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK 0xC000000u |
| #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT 26 |
| #define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK 0x30000000u |
| #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT 28 |
| #define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT))&CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) |
| #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK 0xC0000000u |
| #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT 30 |
| #define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT))&CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Register_Masks */ |
| |
| /* CCM_ANALOG - Peripheral instance base addresses */ |
| /** Peripheral CCM_ANALOG base address */ |
| #define CCM_ANALOG_BASE (0x420C8000u) |
| /** Peripheral CCM_ANALOG base pointer */ |
| #define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) |
| #define CCM_ANALOG_BASE_PTR (CCM_ANALOG) |
| /** Array initializer of CCM_ANALOG peripheral base addresses */ |
| #define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } |
| /** Array initializer of CCM_ANALOG peripheral base pointers */ |
| #define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } |
| |
| /* ---------------------------------------------------------------------------- |
| -- CCM_ANALOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* CCM_ANALOG - Register instance definitions */ |
| /* CCM_ANALOG */ |
| #define CCM_ANALOG_PLL_ARM CCM_ANALOG_PLL_ARM_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ARM_SET CCM_ANALOG_PLL_ARM_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ARM_CLR CCM_ANALOG_PLL_ARM_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ARM_TOG CCM_ANALOG_PLL_ARM_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB1 CCM_ANALOG_PLL_USB1_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB1_SET CCM_ANALOG_PLL_USB1_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB1_CLR CCM_ANALOG_PLL_USB1_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB1_TOG CCM_ANALOG_PLL_USB1_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB2 CCM_ANALOG_PLL_USB2_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB2_SET CCM_ANALOG_PLL_USB2_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB2_CLR CCM_ANALOG_PLL_USB2_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_USB2_TOG CCM_ANALOG_PLL_USB2_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_SYS CCM_ANALOG_PLL_SYS_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_SYS_SET CCM_ANALOG_PLL_SYS_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_SYS_CLR CCM_ANALOG_PLL_SYS_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_SYS_TOG CCM_ANALOG_PLL_SYS_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_SYS_SS CCM_ANALOG_PLL_SYS_SS_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO_SET CCM_ANALOG_PLL_AUDIO_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO_CLR CCM_ANALOG_PLL_AUDIO_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO_TOG CCM_ANALOG_PLL_AUDIO_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO_NUM CCM_ANALOG_PLL_AUDIO_NUM_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_AUDIO_DENOM CCM_ANALOG_PLL_AUDIO_DENOM_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO_SET CCM_ANALOG_PLL_VIDEO_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO_CLR CCM_ANALOG_PLL_VIDEO_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO_TOG CCM_ANALOG_PLL_VIDEO_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO_NUM CCM_ANALOG_PLL_VIDEO_NUM_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_VIDEO_DENOM CCM_ANALOG_PLL_VIDEO_DENOM_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ENET CCM_ANALOG_PLL_ENET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ENET_SET CCM_ANALOG_PLL_ENET_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ENET_CLR CCM_ANALOG_PLL_ENET_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PLL_ENET_TOG CCM_ANALOG_PLL_ENET_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_480 CCM_ANALOG_PFD_480_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_480_SET CCM_ANALOG_PFD_480_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_480_CLR CCM_ANALOG_PFD_480_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_480_TOG CCM_ANALOG_PFD_480_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_528 CCM_ANALOG_PFD_528_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_528_SET CCM_ANALOG_PFD_528_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_528_CLR CCM_ANALOG_PFD_528_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_PFD_528_TOG CCM_ANALOG_PFD_528_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC0 CCM_ANALOG_MISC0_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC0_SET CCM_ANALOG_MISC0_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC0_CLR CCM_ANALOG_MISC0_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC0_TOG CCM_ANALOG_MISC0_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC1 CCM_ANALOG_MISC1_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC1_SET CCM_ANALOG_MISC1_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC1_CLR CCM_ANALOG_MISC1_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC1_TOG CCM_ANALOG_MISC1_TOG_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC2 CCM_ANALOG_MISC2_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC2_SET CCM_ANALOG_MISC2_SET_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC2_CLR CCM_ANALOG_MISC2_CLR_REG(CCM_ANALOG_BASE_PTR) |
| #define CCM_ANALOG_MISC2_TOG CCM_ANALOG_MISC2_TOG_REG(CCM_ANALOG_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group CCM_ANALOG_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CSI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** CSI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ |
| __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ |
| __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ |
| __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ |
| __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ |
| __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ |
| __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ |
| __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ |
| __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ |
| __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ |
| __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ |
| __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ |
| uint8_t RESERVED_1[16]; |
| __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ |
| __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ |
| } CSI_Type, *CSI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- CSI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros |
| * @{ |
| */ |
| |
| /* CSI - Register accessors */ |
| #define CSI_CSICR1_REG(base) ((base)->CSICR1) |
| #define CSI_CSICR2_REG(base) ((base)->CSICR2) |
| #define CSI_CSICR3_REG(base) ((base)->CSICR3) |
| #define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) |
| #define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) |
| #define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) |
| #define CSI_CSISR_REG(base) ((base)->CSISR) |
| #define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) |
| #define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) |
| #define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) |
| #define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) |
| #define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) |
| #define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) |
| #define CSI_CSICR18_REG(base) ((base)->CSICR18) |
| #define CSI_CSICR19_REG(base) ((base)->CSICR19) |
| |
| /*! |
| * @} |
| */ /* end of group CSI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- CSI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CSI_Register_Masks CSI Register Masks |
| * @{ |
| */ |
| |
| /* CSICR1 Bit Fields */ |
| #define CSI_CSICR1_PIXEL_BIT_MASK 0x1u |
| #define CSI_CSICR1_PIXEL_BIT_SHIFT 0 |
| #define CSI_CSICR1_REDGE_MASK 0x2u |
| #define CSI_CSICR1_REDGE_SHIFT 1 |
| #define CSI_CSICR1_INV_PCLK_MASK 0x4u |
| #define CSI_CSICR1_INV_PCLK_SHIFT 2 |
| #define CSI_CSICR1_INV_DATA_MASK 0x8u |
| #define CSI_CSICR1_INV_DATA_SHIFT 3 |
| #define CSI_CSICR1_GCLK_MODE_MASK 0x10u |
| #define CSI_CSICR1_GCLK_MODE_SHIFT 4 |
| #define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u |
| #define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 |
| #define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u |
| #define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 |
| #define CSI_CSICR1_PACK_DIR_MASK 0x80u |
| #define CSI_CSICR1_PACK_DIR_SHIFT 7 |
| #define CSI_CSICR1_FCC_MASK 0x100u |
| #define CSI_CSICR1_FCC_SHIFT 8 |
| #define CSI_CSICR1_CCIR_EN_MASK 0x400u |
| #define CSI_CSICR1_CCIR_EN_SHIFT 10 |
| #define CSI_CSICR1_HSYNC_POL_MASK 0x800u |
| #define CSI_CSICR1_HSYNC_POL_SHIFT 11 |
| #define CSI_CSICR1_SOF_INTEN_MASK 0x10000u |
| #define CSI_CSICR1_SOF_INTEN_SHIFT 16 |
| #define CSI_CSICR1_SOF_POL_MASK 0x20000u |
| #define CSI_CSICR1_SOF_POL_SHIFT 17 |
| #define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u |
| #define CSI_CSICR1_RXFF_INTEN_SHIFT 18 |
| #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u |
| #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 |
| #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u |
| #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 |
| #define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u |
| #define CSI_CSICR1_STATFF_INTEN_SHIFT 21 |
| #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u |
| #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 |
| #define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u |
| #define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 |
| #define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u |
| #define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 |
| #define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u |
| #define CSI_CSICR1_COF_INT_EN_SHIFT 26 |
| #define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u |
| #define CSI_CSICR1_VIDEO_MODE_SHIFT 27 |
| #define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u |
| #define CSI_CSICR1_PrP_IF_EN_SHIFT 28 |
| #define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u |
| #define CSI_CSICR1_EOF_INT_EN_SHIFT 29 |
| #define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u |
| #define CSI_CSICR1_EXT_VSYNC_SHIFT 30 |
| #define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u |
| #define CSI_CSICR1_SWAP16_EN_SHIFT 31 |
| /* CSICR2 Bit Fields */ |
| #define CSI_CSICR2_HSC_MASK 0xFFu |
| #define CSI_CSICR2_HSC_SHIFT 0 |
| #define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_HSC_SHIFT))&CSI_CSICR2_HSC_MASK) |
| #define CSI_CSICR2_VSC_MASK 0xFF00u |
| #define CSI_CSICR2_VSC_SHIFT 8 |
| #define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_VSC_SHIFT))&CSI_CSICR2_VSC_MASK) |
| #define CSI_CSICR2_LVRM_MASK 0x70000u |
| #define CSI_CSICR2_LVRM_SHIFT 16 |
| #define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_LVRM_SHIFT))&CSI_CSICR2_LVRM_MASK) |
| #define CSI_CSICR2_BTS_MASK 0x180000u |
| #define CSI_CSICR2_BTS_SHIFT 19 |
| #define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_BTS_SHIFT))&CSI_CSICR2_BTS_MASK) |
| #define CSI_CSICR2_SCE_MASK 0x800000u |
| #define CSI_CSICR2_SCE_SHIFT 23 |
| #define CSI_CSICR2_AFS_MASK 0x3000000u |
| #define CSI_CSICR2_AFS_SHIFT 24 |
| #define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_AFS_SHIFT))&CSI_CSICR2_AFS_MASK) |
| #define CSI_CSICR2_DRM_MASK 0x4000000u |
| #define CSI_CSICR2_DRM_SHIFT 26 |
| #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK 0x30000000u |
| #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT 28 |
| #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) |
| #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK 0xC0000000u |
| #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT 30 |
| #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) |
| /* CSICR3 Bit Fields */ |
| #define CSI_CSICR3_ECC_AUTO_EN_MASK 0x1u |
| #define CSI_CSICR3_ECC_AUTO_EN_SHIFT 0 |
| #define CSI_CSICR3_ECC_INT_EN_MASK 0x2u |
| #define CSI_CSICR3_ECC_INT_EN_SHIFT 1 |
| #define CSI_CSICR3_ZERO_PACK_EN_MASK 0x4u |
| #define CSI_CSICR3_ZERO_PACK_EN_SHIFT 2 |
| #define CSI_CSICR3_TWO_8BIT_SENSOR_MASK 0x8u |
| #define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT 3 |
| #define CSI_CSICR3_RxFF_LEVEL_MASK 0x70u |
| #define CSI_CSICR3_RxFF_LEVEL_SHIFT 4 |
| #define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_RxFF_LEVEL_SHIFT))&CSI_CSICR3_RxFF_LEVEL_MASK) |
| #define CSI_CSICR3_HRESP_ERR_EN_MASK 0x80u |
| #define CSI_CSICR3_HRESP_ERR_EN_SHIFT 7 |
| #define CSI_CSICR3_STATFF_LEVEL_MASK 0x700u |
| #define CSI_CSICR3_STATFF_LEVEL_SHIFT 8 |
| #define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_STATFF_LEVEL_SHIFT))&CSI_CSICR3_STATFF_LEVEL_MASK) |
| #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK 0x800u |
| #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT 11 |
| #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK 0x1000u |
| #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT 12 |
| #define CSI_CSICR3_DMA_REFLASH_SFF_MASK 0x2000u |
| #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT 13 |
| #define CSI_CSICR3_DMA_REFLASH_RFF_MASK 0x4000u |
| #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT 14 |
| #define CSI_CSICR3_FRMCNT_RST_MASK 0x8000u |
| #define CSI_CSICR3_FRMCNT_RST_SHIFT 15 |
| #define CSI_CSICR3_FRMCNT_MASK 0xFFFF0000u |
| #define CSI_CSICR3_FRMCNT_SHIFT 16 |
| #define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_FRMCNT_SHIFT))&CSI_CSICR3_FRMCNT_MASK) |
| /* CSISTATFIFO Bit Fields */ |
| #define CSI_CSISTATFIFO_STAT_MASK 0xFFFFFFFFu |
| #define CSI_CSISTATFIFO_STAT_SHIFT 0 |
| #define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSISTATFIFO_STAT_SHIFT))&CSI_CSISTATFIFO_STAT_MASK) |
| /* CSIRFIFO Bit Fields */ |
| #define CSI_CSIRFIFO_IMAGE_MASK 0xFFFFFFFFu |
| #define CSI_CSIRFIFO_IMAGE_SHIFT 0 |
| #define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIRFIFO_IMAGE_SHIFT))&CSI_CSIRFIFO_IMAGE_MASK) |
| /* CSIRXCNT Bit Fields */ |
| #define CSI_CSIRXCNT_RXCNT_MASK 0x3FFFFFu |
| #define CSI_CSIRXCNT_RXCNT_SHIFT 0 |
| #define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIRXCNT_RXCNT_SHIFT))&CSI_CSIRXCNT_RXCNT_MASK) |
| /* CSISR Bit Fields */ |
| #define CSI_CSISR_DRDY_MASK 0x1u |
| #define CSI_CSISR_DRDY_SHIFT 0 |
| #define CSI_CSISR_ECC_INT_MASK 0x2u |
| #define CSI_CSISR_ECC_INT_SHIFT 1 |
| #define CSI_CSISR_HRESP_ERR_INT_MASK 0x80u |
| #define CSI_CSISR_HRESP_ERR_INT_SHIFT 7 |
| #define CSI_CSISR_COF_INT_MASK 0x2000u |
| #define CSI_CSISR_COF_INT_SHIFT 13 |
| #define CSI_CSISR_F1_INT_MASK 0x4000u |
| #define CSI_CSISR_F1_INT_SHIFT 14 |
| #define CSI_CSISR_F2_INT_MASK 0x8000u |
| #define CSI_CSISR_F2_INT_SHIFT 15 |
| #define CSI_CSISR_SOF_INT_MASK 0x10000u |
| #define CSI_CSISR_SOF_INT_SHIFT 16 |
| #define CSI_CSISR_EOF_INT_MASK 0x20000u |
| #define CSI_CSISR_EOF_INT_SHIFT 17 |
| #define CSI_CSISR_RxFF_INT_MASK 0x40000u |
| #define CSI_CSISR_RxFF_INT_SHIFT 18 |
| #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK 0x80000u |
| #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT 19 |
| #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK 0x100000u |
| #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT 20 |
| #define CSI_CSISR_STATFF_INT_MASK 0x200000u |
| #define CSI_CSISR_STATFF_INT_SHIFT 21 |
| #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK 0x400000u |
| #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT 22 |
| #define CSI_CSISR_RF_OR_INT_MASK 0x1000000u |
| #define CSI_CSISR_RF_OR_INT_SHIFT 24 |
| #define CSI_CSISR_SF_OR_INT_MASK 0x2000000u |
| #define CSI_CSISR_SF_OR_INT_SHIFT 25 |
| #define CSI_CSISR_DMA_FIELD1_DONE_MASK 0x4000000u |
| #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT 26 |
| #define CSI_CSISR_DMA_FIELD0_DONE_MASK 0x8000000u |
| #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT 27 |
| #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK 0x10000000u |
| #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT 28 |
| /* CSIDMASA_STATFIFO Bit Fields */ |
| #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK 0xFFFFFFFCu |
| #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT 2 |
| #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT))&CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) |
| /* CSIDMATS_STATFIFO Bit Fields */ |
| #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK 0xFFFFFFFFu |
| #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT 0 |
| #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT))&CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) |
| /* CSIDMASA_FB1 Bit Fields */ |
| #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK 0xFFFFFFFCu |
| #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT 2 |
| #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT))&CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) |
| /* CSIDMASA_FB2 Bit Fields */ |
| #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK 0xFFFFFFFCu |
| #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT 2 |
| #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT))&CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) |
| /* CSIFBUF_PARA Bit Fields */ |
| #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK 0xFFFFu |
| #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT 0 |
| #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) |
| /* CSIIMAG_PARA Bit Fields */ |
| #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK 0xFFFFu |
| #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT 0 |
| #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) |
| #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK 0xFFFF0000u |
| #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT 16 |
| #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) |
| /* CSICR18 Bit Fields */ |
| #define CSI_CSICR18_NTSC_EN_MASK 0x1u |
| #define CSI_CSICR18_NTSC_EN_SHIFT 0 |
| #define CSI_CSICR18_TVDECODER_IN_EN_MASK 0x2u |
| #define CSI_CSICR18_TVDECODER_IN_EN_SHIFT 1 |
| #define CSI_CSICR18_DEINTERLACE_EN_MASK 0x4u |
| #define CSI_CSICR18_DEINTERLACE_EN_SHIFT 2 |
| #define CSI_CSICR18_PARALLEL24_EN_MASK 0x8u |
| #define CSI_CSICR18_PARALLEL24_EN_SHIFT 3 |
| #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK 0x10u |
| #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT 4 |
| #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK 0x20u |
| #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT 5 |
| #define CSI_CSICR18_FIELD0_DONE_IE_MASK 0x40u |
| #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT 6 |
| #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK 0x80u |
| #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT 7 |
| #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK 0x100u |
| #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT 8 |
| #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK 0x200u |
| #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT 9 |
| #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK 0x400u |
| #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT 10 |
| #define CSI_CSICR18_AHB_HPROT_MASK 0xF000u |
| #define CSI_CSICR18_AHB_HPROT_SHIFT 12 |
| #define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_AHB_HPROT_SHIFT))&CSI_CSICR18_AHB_HPROT_MASK) |
| #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK 0x30000u |
| #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT 16 |
| #define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT))&CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) |
| #define CSI_CSICR18_MASK_OPTION_MASK 0xC0000u |
| #define CSI_CSICR18_MASK_OPTION_SHIFT 18 |
| #define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MASK_OPTION_SHIFT))&CSI_CSICR18_MASK_OPTION_MASK) |
| #define CSI_CSICR18_CSI_ENABLE_MASK 0x80000000u |
| #define CSI_CSICR18_CSI_ENABLE_SHIFT 31 |
| /* CSICR19 Bit Fields */ |
| #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK 0xFFu |
| #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT 0 |
| #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT))&CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group CSI_Register_Masks */ |
| |
| /* CSI - Peripheral instance base addresses */ |
| /** Peripheral CSI1 base address */ |
| #define CSI1_BASE (0x42214000u) |
| /** Peripheral CSI1 base pointer */ |
| #define CSI1 ((CSI_Type *)CSI1_BASE) |
| #define CSI1_BASE_PTR (CSI1) |
| /** Peripheral CSI2 base address */ |
| #define CSI2_BASE (0x4221C000u) |
| /** Peripheral CSI2 base pointer */ |
| #define CSI2 ((CSI_Type *)CSI2_BASE) |
| #define CSI2_BASE_PTR (CSI2) |
| /** Array initializer of CSI peripheral base addresses */ |
| #define CSI_BASE_ADDRS { CSI1_BASE, CSI2_BASE } |
| /** Array initializer of CSI peripheral base pointers */ |
| #define CSI_BASE_PTRS { CSI1, CSI2 } |
| /** Interrupt vectors for the CSI peripheral type */ |
| #define CSI_IRQS { CSI1_IRQn, CSI2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- CSI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros |
| * @{ |
| */ |
| |
| /* CSI - Register instance definitions */ |
| /* CSI1 */ |
| #define CSI1_CSICR1 CSI_CSICR1_REG(CSI1_BASE_PTR) |
| #define CSI1_CSICR2 CSI_CSICR2_REG(CSI1_BASE_PTR) |
| #define CSI1_CSICR3 CSI_CSICR3_REG(CSI1_BASE_PTR) |
| #define CSI1_CSISTATFIFO CSI_CSISTATFIFO_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIRFIFO CSI_CSIRFIFO_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIRXCNT CSI_CSIRXCNT_REG(CSI1_BASE_PTR) |
| #define CSI1_CSISR CSI_CSISR_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIDMASA_STATFIFO CSI_CSIDMASA_STATFIFO_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIDMATS_STATFIFO CSI_CSIDMATS_STATFIFO_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIDMASA_FB1 CSI_CSIDMASA_FB1_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIDMASA_FB2 CSI_CSIDMASA_FB2_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI1_BASE_PTR) |
| #define CSI1_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI1_BASE_PTR) |
| #define CSI1_CSICR18 CSI_CSICR18_REG(CSI1_BASE_PTR) |
| #define CSI1_CSICR19 CSI_CSICR19_REG(CSI1_BASE_PTR) |
| /* CSI2 */ |
| #define CSI2_CSICR1 CSI_CSICR1_REG(CSI2_BASE_PTR) |
| #define CSI2_CSICR2 CSI_CSICR2_REG(CSI2_BASE_PTR) |
| #define CSI2_CSICR3 CSI_CSICR3_REG(CSI2_BASE_PTR) |
| #define CSI2_CSISTATFIFO CSI_CSISTATFIFO_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIRFIFO CSI_CSIRFIFO_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIRXCNT CSI_CSIRXCNT_REG(CSI2_BASE_PTR) |
| #define CSI2_CSISR CSI_CSISR_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIDMASA_STATFIFO CSI_CSIDMASA_STATFIFO_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIDMATS_STATFIFO CSI_CSIDMATS_STATFIFO_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIDMASA_FB1 CSI_CSIDMASA_FB1_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIDMASA_FB2 CSI_CSIDMASA_FB2_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI2_BASE_PTR) |
| #define CSI2_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI2_BASE_PTR) |
| #define CSI2_CSICR18 CSI_CSICR18_REG(CSI2_BASE_PTR) |
| #define CSI2_CSICR19 CSI_CSICR19_REG(CSI2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group CSI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group CSI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- DCIC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DCIC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DCICC; /**< DCIC Control Register, offset: 0x0 */ |
| __IO uint32_t DCICIC; /**< DCIC Interrupt Control Register, offset: 0x4 */ |
| __IO uint32_t DCICS; /**< DCIC Status Register, offset: 0x8 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t DCICRC; /**< DCIC ROI Config Register m, offset: 0x10 */ |
| __IO uint32_t DCICRS; /**< DCIC ROI Size Register m, offset: 0x14 */ |
| __IO uint32_t DCICRRS; /**< DCIC ROI Reference Signature Register m, offset: 0x18 */ |
| __I uint32_t DCICRCS; /**< DCIC ROI Calculated Signature m, offset: 0x1C */ |
| } DCIC_Type, *DCIC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DCIC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DCIC_Register_Accessor_Macros DCIC - Register accessor macros |
| * @{ |
| */ |
| |
| /* DCIC - Register accessors */ |
| #define DCIC_DCICC_REG(base) ((base)->DCICC) |
| #define DCIC_DCICIC_REG(base) ((base)->DCICIC) |
| #define DCIC_DCICS_REG(base) ((base)->DCICS) |
| #define DCIC_DCICRC_REG(base) ((base)->DCICRC) |
| #define DCIC_DCICRS_REG(base) ((base)->DCICRS) |
| #define DCIC_DCICRRS_REG(base) ((base)->DCICRRS) |
| #define DCIC_DCICRCS_REG(base) ((base)->DCICRCS) |
| |
| /*! |
| * @} |
| */ /* end of group DCIC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- DCIC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DCIC_Register_Masks DCIC Register Masks |
| * @{ |
| */ |
| |
| /* DCICC Bit Fields */ |
| #define DCIC_DCICC_IC_EN_MASK 0x1u |
| #define DCIC_DCICC_IC_EN_SHIFT 0 |
| #define DCIC_DCICC_DE_POL_MASK 0x10u |
| #define DCIC_DCICC_DE_POL_SHIFT 4 |
| #define DCIC_DCICC_HSYNC_POL_MASK 0x20u |
| #define DCIC_DCICC_HSYNC_POL_SHIFT 5 |
| #define DCIC_DCICC_VSYNC_POL_MASK 0x40u |
| #define DCIC_DCICC_VSYNC_POL_SHIFT 6 |
| #define DCIC_DCICC_CLK_POL_MASK 0x80u |
| #define DCIC_DCICC_CLK_POL_SHIFT 7 |
| /* DCICIC Bit Fields */ |
| #define DCIC_DCICIC_EI_MASK_MASK 0x1u |
| #define DCIC_DCICIC_EI_MASK_SHIFT 0 |
| #define DCIC_DCICIC_FI_MASK_MASK 0x2u |
| #define DCIC_DCICIC_FI_MASK_SHIFT 1 |
| #define DCIC_DCICIC_FREEZE_MASK_MASK 0x8u |
| #define DCIC_DCICIC_FREEZE_MASK_SHIFT 3 |
| #define DCIC_DCICIC_EXT_SIG_EN_MASK 0x10000u |
| #define DCIC_DCICIC_EXT_SIG_EN_SHIFT 16 |
| /* DCICS Bit Fields */ |
| #define DCIC_DCICS_ROI_MATCH_STAT_MASK 0xFFFFu |
| #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT 0 |
| #define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICS_ROI_MATCH_STAT_SHIFT))&DCIC_DCICS_ROI_MATCH_STAT_MASK) |
| #define DCIC_DCICS_EI_STAT_MASK 0x10000u |
| #define DCIC_DCICS_EI_STAT_SHIFT 16 |
| #define DCIC_DCICS_FI_STAT_MASK 0x20000u |
| #define DCIC_DCICS_FI_STAT_SHIFT 17 |
| /* DCICRC Bit Fields */ |
| #define DCIC_DCICRC_START_OFFSET_X_MASK 0x1FFFu |
| #define DCIC_DCICRC_START_OFFSET_X_SHIFT 0 |
| #define DCIC_DCICRC_START_OFFSET_X(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRC_START_OFFSET_X_SHIFT))&DCIC_DCICRC_START_OFFSET_X_MASK) |
| #define DCIC_DCICRC_START_OFFSET_Y_MASK 0xFFF0000u |
| #define DCIC_DCICRC_START_OFFSET_Y_SHIFT 16 |
| #define DCIC_DCICRC_START_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRC_START_OFFSET_Y_SHIFT))&DCIC_DCICRC_START_OFFSET_Y_MASK) |
| #define DCIC_DCICRC_ROI_FREEZE_MASK 0x40000000u |
| #define DCIC_DCICRC_ROI_FREEZE_SHIFT 30 |
| #define DCIC_DCICRC_ROI_EN_MASK 0x80000000u |
| #define DCIC_DCICRC_ROI_EN_SHIFT 31 |
| /* DCICRS Bit Fields */ |
| #define DCIC_DCICRS_END_OFFSET_X_MASK 0x1FFFu |
| #define DCIC_DCICRS_END_OFFSET_X_SHIFT 0 |
| #define DCIC_DCICRS_END_OFFSET_X(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRS_END_OFFSET_X_SHIFT))&DCIC_DCICRS_END_OFFSET_X_MASK) |
| #define DCIC_DCICRS_END_OFFSET_Y_MASK 0xFFF0000u |
| #define DCIC_DCICRS_END_OFFSET_Y_SHIFT 16 |
| #define DCIC_DCICRS_END_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRS_END_OFFSET_Y_SHIFT))&DCIC_DCICRS_END_OFFSET_Y_MASK) |
| /* DCICRRS Bit Fields */ |
| #define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK 0xFFFFFFFFu |
| #define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT 0 |
| #define DCIC_DCICRRS_REFERENCE_SIGNATURE(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT))&DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK) |
| /* DCICRCS Bit Fields */ |
| #define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK 0xFFFFFFFFu |
| #define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT 0 |
| #define DCIC_DCICRCS_CALCULATED_SIGNATURE(x) (((uint32_t)(((uint32_t)(x))<<DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT))&DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group DCIC_Register_Masks */ |
| |
| /* DCIC - Peripheral instance base addresses */ |
| /** Peripheral DCIC1 base address */ |
| #define DCIC1_BASE (0x4220C000u) |
| /** Peripheral DCIC1 base pointer */ |
| #define DCIC1 ((DCIC_Type *)DCIC1_BASE) |
| #define DCIC1_BASE_PTR (DCIC1) |
| /** Peripheral DCIC2 base address */ |
| #define DCIC2_BASE (0x42210000u) |
| /** Peripheral DCIC2 base pointer */ |
| #define DCIC2 ((DCIC_Type *)DCIC2_BASE) |
| #define DCIC2_BASE_PTR (DCIC2) |
| /** Array initializer of DCIC peripheral base addresses */ |
| #define DCIC_BASE_ADDRS { DCIC1_BASE, DCIC2_BASE } |
| /** Array initializer of DCIC peripheral base pointers */ |
| #define DCIC_BASE_PTRS { DCIC1, DCIC2 } |
| /** Interrupt vectors for the DCIC peripheral type */ |
| #define DCIC_IRQS { DCIC1_IRQn, DCIC2_IRQn } |
| /* ---------------------------------------------------------------------------- |
| -- DCIC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DCIC_Register_Accessor_Macros DCIC - Register accessor macros |
| * @{ |
| */ |
| |
| /* DCIC - Register instance definitions */ |
| /* DCIC1 */ |
| #define DCIC1_DCICC DCIC_DCICC_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICIC DCIC_DCICIC_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICS DCIC_DCICS_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICRC DCIC_DCICRC_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICRS DCIC_DCICRS_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICRRS DCIC_DCICRRS_REG(DCIC1_BASE_PTR) |
| #define DCIC1_DCICRCS DCIC_DCICRCS_REG(DCIC1_BASE_PTR) |
| /* DCIC2 */ |
| #define DCIC2_DCICC DCIC_DCICC_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICIC DCIC_DCICIC_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICS DCIC_DCICS_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICRC DCIC_DCICRC_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICRS DCIC_DCICRS_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICRRS DCIC_DCICRRS_REG(DCIC2_BASE_PTR) |
| #define DCIC2_DCICRCS DCIC_DCICRCS_REG(DCIC2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group DCIC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group DCIC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- DVFSC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DVFSC_Peripheral_Access_Layer DVFSC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** DVFSC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t THRS; /**< DVFS Thresholds, offset: 0x0 */ |
| __IO uint32_t COUN; /**< DVFS Counters thresholds, offset: 0x4 */ |
| __IO uint32_t SIG1; /**< DVFS general purpose bits weight, offset: 0x8 */ |
| __IO uint32_t DVFSSIG0; /**< DVFS general purpose bits weight, offset: 0xC */ |
| __IO uint32_t DVFSGPC0; /**< DVFS general purpose bit 0 weight counter, offset: 0x10 */ |
| __IO uint32_t DVFSGPC1; /**< DVFS general purpose bit 1 weight counter, offset: 0x14 */ |
| __IO uint32_t DVFSGPBT; /**< DVFS general purpose bits enables, offset: 0x18 */ |
| __IO uint32_t DVFSEMAC; /**< DVFS EMAC settings, offset: 0x1C */ |
| __IO uint32_t CNTR; /**< DVFS Control, offset: 0x20 */ |
| __I uint32_t DVFSLTR0_0; /**< DVFS Load Tracking Register 0, portion 0, offset: 0x24 */ |
| __I uint32_t DVFSLTR0_1; /**< DVFS Load Tracking Register 0, portion 1, offset: 0x28 */ |
| __I uint32_t DVFSLTR1_0; /**< DVFS Load Tracking Register 1, portion 0, offset: 0x2C */ |
| __I uint32_t DVFSLTR1_1; /**< DVFS Load Tracking Register 3, portion 1, offset: 0x30 */ |
| __IO uint32_t DVFSPT0; /**< DVFS pattern 0 length, offset: 0x34 */ |
| __IO uint32_t DVFSPT1; /**< DVFS pattern 1 length, offset: 0x38 */ |
| __IO uint32_t DVFSPT2; /**< DVFS pattern 2 length, offset: 0x3C */ |
| __IO uint32_t DVFSPT3; /**< DVFS pattern 3 length, offset: 0x40 */ |
| } DVFSC_Type, *DVFSC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- DVFSC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DVFSC_Register_Accessor_Macros DVFSC - Register accessor macros |
| * @{ |
| */ |
| |
| /* DVFSC - Register accessors */ |
| #define DVFSC_THRS_REG(base) ((base)->THRS) |
| #define DVFSC_COUN_REG(base) ((base)->COUN) |
| #define DVFSC_SIG1_REG(base) ((base)->SIG1) |
| #define DVFSC_DVFSSIG0_REG(base) ((base)->DVFSSIG0) |
| #define DVFSC_DVFSGPC0_REG(base) ((base)->DVFSGPC0) |
| #define DVFSC_DVFSGPC1_REG(base) ((base)->DVFSGPC1) |
| #define DVFSC_DVFSGPBT_REG(base) ((base)->DVFSGPBT) |
| #define DVFSC_DVFSEMAC_REG(base) ((base)->DVFSEMAC) |
| #define DVFSC_CNTR_REG(base) ((base)->CNTR) |
| #define DVFSC_DVFSLTR0_0_REG(base) ((base)->DVFSLTR0_0) |
| #define DVFSC_DVFSLTR0_1_REG(base) ((base)->DVFSLTR0_1) |
| #define DVFSC_DVFSLTR1_0_REG(base) ((base)->DVFSLTR1_0) |
| #define DVFSC_DVFSLTR1_1_REG(base) ((base)->DVFSLTR1_1) |
| #define DVFSC_DVFSPT0_REG(base) ((base)->DVFSPT0) |
| #define DVFSC_DVFSPT1_REG(base) ((base)->DVFSPT1) |
| #define DVFSC_DVFSPT2_REG(base) ((base)->DVFSPT2) |
| #define DVFSC_DVFSPT3_REG(base) ((base)->DVFSPT3) |
| |
| /*! |
| * @} |
| */ /* end of group DVFSC_Register_Accessor_Macros */ |
| /* ---------------------------------------------------------------------------- |
| -- DVFSC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DVFSC_Register_Masks DVFSC Register Masks |
| * @{ |
| */ |
| |
| /* THRS Bit Fields */ |
| #define DVFSC_THRS_PNCTHR_MASK 0x3Fu |
| #define DVFSC_THRS_PNCTHR_SHIFT 0 |
| #define DVFSC_THRS_PNCTHR(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_PNCTHR_SHIFT))&DVFSC_THRS_PNCTHR_MASK) |
| #define DVFSC_THRS_DWTHR_MASK 0x3F0000u |
| #define DVFSC_THRS_DWTHR_SHIFT 16 |
| #define DVFSC_THRS_DWTHR(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_DWTHR_SHIFT))&DVFSC_THRS_DWTHR_MASK) |
| #define DVFSC_THRS_UPTHR_MASK 0xFC00000u |
| #define DVFSC_THRS_UPTHR_SHIFT 22 |
| #define DVFSC_THRS_UPTHR(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_THRS_UPTHR_SHIFT))&DVFSC_THRS_UPTHR_MASK) |
| /* COUN Bit Fields */ |
| #define DVFSC_COUN_UPCNT_MASK 0xFFu |
| #define DVFSC_COUN_UPCNT_SHIFT 0 |
| #define DVFSC_COUN_UPCNT(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_COUN_UPCNT_SHIFT))&DVFSC_COUN_UPCNT_MASK) |
| #define DVFSC_COUN_DN_CNT_MASK 0xFF0000u |
| #define DVFSC_COUN_DN_CNT_SHIFT 16 |
| #define DVFSC_COUN_DN_CNT(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_COUN_DN_CNT_SHIFT))&DVFSC_COUN_DN_CNT_MASK) |
| /* SIG1 Bit Fields */ |
| #define DVFSC_SIG1_WSW6_MASK 0x1Cu |
| #define DVFSC_SIG1_WSW6_SHIFT 2 |
| #define DVFSC_SIG1_WSW6(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW6_SHIFT))&DVFSC_SIG1_WSW6_MASK) |
| #define DVFSC_SIG1_WSW7_MASK 0xE0u |
| #define DVFSC_SIG1_WSW7_SHIFT 5 |
| #define DVFSC_SIG1_WSW7(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW7_SHIFT))&DVFSC_SIG1_WSW7_MASK) |
| #define DVFSC_SIG1_WSW8_MASK 0x700u |
| #define DVFSC_SIG1_WSW8_SHIFT 8 |
| #define DVFSC_SIG1_WSW8(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW8_SHIFT))&DVFSC_SIG1_WSW8_MASK) |
| #define DVFSC_SIG1_WSW9_MASK 0x3800u |
| #define DVFSC_SIG1_WSW9_SHIFT 11 |
| #define DVFSC_SIG1_WSW9(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW9_SHIFT))&DVFSC_SIG1_WSW9_MASK) |
| #define DVFSC_SIG1_WSW10_MASK 0x1C000u |
| #define DVFSC_SIG1_WSW10_SHIFT 14 |
| #define DVFSC_SIG1_WSW10(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW10_SHIFT))&DVFSC_SIG1_WSW10_MASK) |
| #define DVFSC_SIG1_WSW11_MASK 0xE0000u |
| #define DVFSC_SIG1_WSW11_SHIFT 17 |
| #define DVFSC_SIG1_WSW11(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW11_SHIFT))&DVFSC_SIG1_WSW11_MASK) |
| #define DVFSC_SIG1_WSW12_MASK 0x700000u |
| #define DVFSC_SIG1_WSW12_SHIFT 20 |
| #define DVFSC_SIG1_WSW12(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW12_SHIFT))&DVFSC_SIG1_WSW12_MASK) |
| #define DVFSC_SIG1_WSW13_MASK 0x3800000u |
| #define DVFSC_SIG1_WSW13_SHIFT 23 |
| #define DVFSC_SIG1_WSW13(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW13_SHIFT))&DVFSC_SIG1_WSW13_MASK) |
| #define DVFSC_SIG1_WSW14_MASK 0x1C000000u |
| #define DVFSC_SIG1_WSW14_SHIFT 26 |
| #define DVFSC_SIG1_WSW14(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW14_SHIFT))&DVFSC_SIG1_WSW14_MASK) |
| #define DVFSC_SIG1_WSW15_MASK 0xE0000000u |
| #define DVFSC_SIG1_WSW15_SHIFT 29 |
| #define DVFSC_SIG1_WSW15(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_SIG1_WSW15_SHIFT))&DVFSC_SIG1_WSW15_MASK) |
| /* DVFSSIG0 Bit Fields */ |
| #define DVFSC_DVFSSIG0_WSW0_MASK 0x3Fu |
| #define DVFSC_DVFSSIG0_WSW0_SHIFT 0 |
| #define DVFSC_DVFSSIG0_WSW0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW0_SHIFT))&DVFSC_DVFSSIG0_WSW0_MASK) |
| #define DVFSC_DVFSSIG0_WSW1_MASK 0xFC0u |
| #define DVFSC_DVFSSIG0_WSW1_SHIFT 6 |
| #define DVFSC_DVFSSIG0_WSW1(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW1_SHIFT))&DVFSC_DVFSSIG0_WSW1_MASK) |
| #define DVFSC_DVFSSIG0_WSW2_MASK 0x700000u |
| #define DVFSC_DVFSSIG0_WSW2_SHIFT 20 |
| #define DVFSC_DVFSSIG0_WSW2(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW2_SHIFT))&DVFSC_DVFSSIG0_WSW2_MASK) |
| #define DVFSC_DVFSSIG0_WSW3_MASK 0x3800000u |
| #define DVFSC_DVFSSIG0_WSW3_SHIFT 23 |
| #define DVFSC_DVFSSIG0_WSW3(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW3_SHIFT))&DVFSC_DVFSSIG0_WSW3_MASK) |
| #define DVFSC_DVFSSIG0_WSW4_MASK 0x1C000000u |
| #define DVFSC_DVFSSIG0_WSW4_SHIFT 26 |
| #define DVFSC_DVFSSIG0_WSW4(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW4_SHIFT))&DVFSC_DVFSSIG0_WSW4_MASK) |
| #define DVFSC_DVFSSIG0_WSW5_MASK 0xE0000000u |
| #define DVFSC_DVFSSIG0_WSW5_SHIFT 29 |
| #define DVFSC_DVFSSIG0_WSW5(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSSIG0_WSW5_SHIFT))&DVFSC_DVFSSIG0_WSW5_MASK) |
| /* DVFSGPC0 Bit Fields */ |
| #define DVFSC_DVFSGPC0_GPBC0_MASK 0x1FFFFu |
| #define DVFSC_DVFSGPC0_GPBC0_SHIFT 0 |
| #define DVFSC_DVFSGPC0_GPBC0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSGPC0_GPBC0_SHIFT))&DVFSC_DVFSGPC0_GPBC0_MASK) |
| #define DVFSC_DVFSGPC0_C0ACT_MASK 0x40000000u |
| #define DVFSC_DVFSGPC0_C0ACT_SHIFT 30 |
| #define DVFSC_DVFSGPC0_C0STRT_MASK 0x80000000u |
| #define DVFSC_DVFSGPC0_C0STRT_SHIFT 31 |
| /* DVFSGPC1 Bit Fields */ |
| #define DVFSC_DVFSGPC1_GPBC1_MASK 0x1FFFFu |
| #define DVFSC_DVFSGPC1_GPBC1_SHIFT 0 |
| #define DVFSC_DVFSGPC1_GPBC1(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSGPC1_GPBC1_SHIFT))&DVFSC_DVFSGPC1_GPBC1_MASK) |
| #define DVFSC_DVFSGPC1_C1ACT_MASK 0x40000000u |
| #define DVFSC_DVFSGPC1_C1ACT_SHIFT 30 |
| #define DVFSC_DVFSGPC1_C1STRT_MASK 0x80000000u |
| #define DVFSC_DVFSGPC1_C1STRT_SHIFT 31 |
| /* DVFSGPBT Bit Fields */ |
| #define DVFSC_DVFSGPBT_GPB0_MASK 0x1u |
| #define DVFSC_DVFSGPBT_GPB0_SHIFT 0 |
| #define DVFSC_DVFSGPBT_GPB1_MASK 0x2u |
| #define DVFSC_DVFSGPBT_GPB1_SHIFT 1 |
| #define DVFSC_DVFSGPBT_GPB2_MASK 0x4u |
| #define DVFSC_DVFSGPBT_GPB2_SHIFT 2 |
| #define DVFSC_DVFSGPBT_GPB3_MASK 0x8u |
| #define DVFSC_DVFSGPBT_GPB3_SHIFT 3 |
| #define DVFSC_DVFSGPBT_GPB4_MASK 0x10u |
| #define DVFSC_DVFSGPBT_GPB4_SHIFT 4 |
| #define DVFSC_DVFSGPBT_GPB5_MASK 0x20u |
| #define DVFSC_DVFSGPBT_GPB5_SHIFT 5 |
| #define DVFSC_DVFSGPBT_GPB6_MASK 0x40u |
| #define DVFSC_DVFSGPBT_GPB6_SHIFT 6 |
| #define DVFSC_DVFSGPBT_GPB7_MASK 0x80u |
| #define DVFSC_DVFSGPBT_GPB7_SHIFT 7 |
| #define DVFSC_DVFSGPBT_GPB8_MASK 0x100u |
| #define DVFSC_DVFSGPBT_GPB8_SHIFT 8 |
| #define DVFSC_DVFSGPBT_GPB9_MASK 0x200u |
| #define DVFSC_DVFSGPBT_GPB9_SHIFT 9 |
| #define DVFSC_DVFSGPBT_GPB10_MASK 0x400u |
| #define DVFSC_DVFSGPBT_GPB10_SHIFT 10 |
| #define DVFSC_DVFSGPBT_GPB11_MASK 0x800u |
| #define DVFSC_DVFSGPBT_GPB11_SHIFT 11 |
| #define DVFSC_DVFSGPBT_GPB12_MASK 0x1000u |
| #define DVFSC_DVFSGPBT_GPB12_SHIFT 12 |
| #define DVFSC_DVFSGPBT_GPB13_MASK 0x2000u |
| #define DVFSC_DVFSGPBT_GPB13_SHIFT 13 |
| #define DVFSC_DVFSGPBT_GPB14_MASK 0x4000u |
| #define DVFSC_DVFSGPBT_GPB14_SHIFT 14 |
| #define DVFSC_DVFSGPBT_GPB15_MASK 0x8000u |
| #define DVFSC_DVFSGPBT_GPB15_SHIFT 15 |
| /* DVFSEMAC Bit Fields */ |
| #define DVFSC_DVFSEMAC_EMAC_MASK 0x1FFu |
| #define DVFSC_DVFSEMAC_EMAC_SHIFT 0 |
| #define DVFSC_DVFSEMAC_EMAC(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSEMAC_EMAC_SHIFT))&DVFSC_DVFSEMAC_EMAC_MASK) |
| #define DVFSC_DVFSEMAC_DVFEN0_MASK 0x200u |
| #define DVFSC_DVFSEMAC_DVFEN0_SHIFT 9 |
| #define DVFSC_DVFSEMAC_FSVAI0_MASK 0x30000u |
| #define DVFSC_DVFSEMAC_FSVAI0_SHIFT 16 |
| #define DVFSC_DVFSEMAC_FSVAI0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSEMAC_FSVAI0_SHIFT))&DVFSC_DVFSEMAC_FSVAI0_MASK) |
| #define DVFSC_DVFSEMAC_WFIM0_MASK 0x1000000u |
| #define DVFSC_DVFSEMAC_WFIM0_SHIFT 24 |
| /* CNTR Bit Fields */ |
| #define DVFSC_CNTR_LTBRSR_MASK 0x18u |
| #define DVFSC_CNTR_LTBRSR_SHIFT 3 |
| #define DVFSC_CNTR_LTBRSR(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_LTBRSR_SHIFT))&DVFSC_CNTR_LTBRSR_MASK) |
| #define DVFSC_CNTR_LTBRSH_MASK 0x20u |
| #define DVFSC_CNTR_LTBRSH_SHIFT 5 |
| #define DVFSC_CNTR_PFUS_MASK 0x1C0u |
| #define DVFSC_CNTR_PFUS_SHIFT 6 |
| #define DVFSC_CNTR_PFUS(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_PFUS_SHIFT))&DVFSC_CNTR_PFUS_MASK) |
| #define DVFSC_CNTR_PFUE_MASK 0x200u |
| #define DVFSC_CNTR_PFUE_SHIFT 9 |
| #define DVFSC_CNTR_DIV_RATIO_MASK 0x1F800u |
| #define DVFSC_CNTR_DIV_RATIO_SHIFT 11 |
| #define DVFSC_CNTR_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_DIV_RATIO_SHIFT))&DVFSC_CNTR_DIV_RATIO_MASK) |
| #define DVFSC_CNTR_MINF_MASK 0x20000u |
| #define DVFSC_CNTR_MINF_SHIFT 17 |
| #define DVFSC_CNTR_MAXF_MASK 0x40000u |
| #define DVFSC_CNTR_MAXF_SHIFT 18 |
| #define DVFSC_CNTR_FSVAI_MASK 0x300000u |
| #define DVFSC_CNTR_FSVAI_SHIFT 20 |
| #define DVFSC_CNTR_FSVAI(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_FSVAI_SHIFT))&DVFSC_CNTR_FSVAI_MASK) |
| #define DVFSC_CNTR_FSVAIM_MASK 0x400000u |
| #define DVFSC_CNTR_FSVAIM_SHIFT 22 |
| #define DVFSC_CNTR_PIRQS_MASK 0x800000u |
| #define DVFSC_CNTR_PIRQS_SHIFT 23 |
| #define DVFSC_CNTR_DVFIS_MASK 0x1000000u |
| #define DVFSC_CNTR_DVFIS_SHIFT 24 |
| #define DVFSC_CNTR_LBFL0_MASK 0x2000000u |
| #define DVFSC_CNTR_LBFL0_SHIFT 25 |
| #define DVFSC_CNTR_LBFL1_MASK 0x4000000u |
| #define DVFSC_CNTR_LBFL1_SHIFT 26 |
| #define DVFSC_CNTR_LBMI_MASK 0x8000000u |
| #define DVFSC_CNTR_LBMI_SHIFT 27 |
| #define DVFSC_CNTR_DVFEV_MASK 0x10000000u |
| #define DVFSC_CNTR_DVFEV_SHIFT 28 |
| #define DVFSC_CNTR_DIV3CK_MASK 0xE0000000u |
| #define DVFSC_CNTR_DIV3CK_SHIFT 29 |
| #define DVFSC_CNTR_DIV3CK(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_CNTR_DIV3CK_SHIFT))&DVFSC_CNTR_DIV3CK_MASK) |
| /* DVFSLTR0_0 Bit Fields */ |
| #define DVFSC_DVFSLTR0_0_LTS0_0_MASK 0xFu |
| #define DVFSC_DVFSLTR0_0_LTS0_0_SHIFT 0 |
| #define DVFSC_DVFSLTR0_0_LTS0_0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_0_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_0_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_1_MASK 0xF0u |
| #define DVFSC_DVFSLTR0_0_LTS0_1_SHIFT 4 |
| #define DVFSC_DVFSLTR0_0_LTS0_1(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_1_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_1_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_2_MASK 0xF00u |
| #define DVFSC_DVFSLTR0_0_LTS0_2_SHIFT 8 |
| #define DVFSC_DVFSLTR0_0_LTS0_2(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_2_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_2_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_3_MASK 0xF000u |
| #define DVFSC_DVFSLTR0_0_LTS0_3_SHIFT 12 |
| #define DVFSC_DVFSLTR0_0_LTS0_3(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_3_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_3_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_4_MASK 0xF0000u |
| #define DVFSC_DVFSLTR0_0_LTS0_4_SHIFT 16 |
| #define DVFSC_DVFSLTR0_0_LTS0_4(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_4_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_4_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_5_MASK 0xF00000u |
| #define DVFSC_DVFSLTR0_0_LTS0_5_SHIFT 20 |
| #define DVFSC_DVFSLTR0_0_LTS0_5(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_5_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_5_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_6_MASK 0xF000000u |
| #define DVFSC_DVFSLTR0_0_LTS0_6_SHIFT 24 |
| #define DVFSC_DVFSLTR0_0_LTS0_6(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_6_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_6_MASK) |
| #define DVFSC_DVFSLTR0_0_LTS0_7_MASK 0xF0000000u |
| #define DVFSC_DVFSLTR0_0_LTS0_7_SHIFT 28 |
| #define DVFSC_DVFSLTR0_0_LTS0_7(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_0_LTS0_7_SHIFT))&DVFSC_DVFSLTR0_0_LTS0_7_MASK) |
| /* DVFSLTR0_1 Bit Fields */ |
| #define DVFSC_DVFSLTR0_1_LTS0_8_MASK 0xFu |
| #define DVFSC_DVFSLTR0_1_LTS0_8_SHIFT 0 |
| #define DVFSC_DVFSLTR0_1_LTS0_8(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_8_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_8_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_9_MASK 0xF0u |
| #define DVFSC_DVFSLTR0_1_LTS0_9_SHIFT 4 |
| #define DVFSC_DVFSLTR0_1_LTS0_9(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_9_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_9_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_10_MASK 0xF00u |
| #define DVFSC_DVFSLTR0_1_LTS0_10_SHIFT 8 |
| #define DVFSC_DVFSLTR0_1_LTS0_10(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_10_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_10_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_11_MASK 0xF000u |
| #define DVFSC_DVFSLTR0_1_LTS0_11_SHIFT 12 |
| #define DVFSC_DVFSLTR0_1_LTS0_11(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_11_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_11_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_12_MASK 0xF0000u |
| #define DVFSC_DVFSLTR0_1_LTS0_12_SHIFT 16 |
| #define DVFSC_DVFSLTR0_1_LTS0_12(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_12_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_12_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_13_MASK 0xF00000u |
| #define DVFSC_DVFSLTR0_1_LTS0_13_SHIFT 20 |
| #define DVFSC_DVFSLTR0_1_LTS0_13(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_13_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_13_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_14_MASK 0xF000000u |
| #define DVFSC_DVFSLTR0_1_LTS0_14_SHIFT 24 |
| #define DVFSC_DVFSLTR0_1_LTS0_14(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_14_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_14_MASK) |
| #define DVFSC_DVFSLTR0_1_LTS0_15_MASK 0xF0000000u |
| #define DVFSC_DVFSLTR0_1_LTS0_15_SHIFT 28 |
| #define DVFSC_DVFSLTR0_1_LTS0_15(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR0_1_LTS0_15_SHIFT))&DVFSC_DVFSLTR0_1_LTS0_15_MASK) |
| /* DVFSLTR1_0 Bit Fields */ |
| #define DVFSC_DVFSLTR1_0_LTS1_0_MASK 0xFu |
| #define DVFSC_DVFSLTR1_0_LTS1_0_SHIFT 0 |
| #define DVFSC_DVFSLTR1_0_LTS1_0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_0_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_0_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_1_MASK 0xF0u |
| #define DVFSC_DVFSLTR1_0_LTS1_1_SHIFT 4 |
| #define DVFSC_DVFSLTR1_0_LTS1_1(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_1_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_1_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_2_MASK 0xF00u |
| #define DVFSC_DVFSLTR1_0_LTS1_2_SHIFT 8 |
| #define DVFSC_DVFSLTR1_0_LTS1_2(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_2_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_2_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_3_MASK 0xF000u |
| #define DVFSC_DVFSLTR1_0_LTS1_3_SHIFT 12 |
| #define DVFSC_DVFSLTR1_0_LTS1_3(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_3_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_3_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_4_MASK 0xF0000u |
| #define DVFSC_DVFSLTR1_0_LTS1_4_SHIFT 16 |
| #define DVFSC_DVFSLTR1_0_LTS1_4(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_4_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_4_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_5_MASK 0xF00000u |
| #define DVFSC_DVFSLTR1_0_LTS1_5_SHIFT 20 |
| #define DVFSC_DVFSLTR1_0_LTS1_5(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_5_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_5_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_6_MASK 0xF000000u |
| #define DVFSC_DVFSLTR1_0_LTS1_6_SHIFT 24 |
| #define DVFSC_DVFSLTR1_0_LTS1_6(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_6_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_6_MASK) |
| #define DVFSC_DVFSLTR1_0_LTS1_7_MASK 0xF0000000u |
| #define DVFSC_DVFSLTR1_0_LTS1_7_SHIFT 28 |
| #define DVFSC_DVFSLTR1_0_LTS1_7(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_0_LTS1_7_SHIFT))&DVFSC_DVFSLTR1_0_LTS1_7_MASK) |
| /* DVFSLTR1_1 Bit Fields */ |
| #define DVFSC_DVFSLTR1_1_LTS1_8_MASK 0xFu |
| #define DVFSC_DVFSLTR1_1_LTS1_8_SHIFT 0 |
| #define DVFSC_DVFSLTR1_1_LTS1_8(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_8_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_8_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_9_MASK 0xF0u |
| #define DVFSC_DVFSLTR1_1_LTS1_9_SHIFT 4 |
| #define DVFSC_DVFSLTR1_1_LTS1_9(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_9_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_9_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_10_MASK 0xF00u |
| #define DVFSC_DVFSLTR1_1_LTS1_10_SHIFT 8 |
| #define DVFSC_DVFSLTR1_1_LTS1_10(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_10_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_10_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_11_MASK 0xF000u |
| #define DVFSC_DVFSLTR1_1_LTS1_11_SHIFT 12 |
| #define DVFSC_DVFSLTR1_1_LTS1_11(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_11_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_11_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_12_MASK 0xF0000u |
| #define DVFSC_DVFSLTR1_1_LTS1_12_SHIFT 16 |
| #define DVFSC_DVFSLTR1_1_LTS1_12(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_12_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_12_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_13_MASK 0xF00000u |
| #define DVFSC_DVFSLTR1_1_LTS1_13_SHIFT 20 |
| #define DVFSC_DVFSLTR1_1_LTS1_13(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_13_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_13_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_14_MASK 0xF000000u |
| #define DVFSC_DVFSLTR1_1_LTS1_14_SHIFT 24 |
| #define DVFSC_DVFSLTR1_1_LTS1_14(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_14_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_14_MASK) |
| #define DVFSC_DVFSLTR1_1_LTS1_15_MASK 0xF0000000u |
| #define DVFSC_DVFSLTR1_1_LTS1_15_SHIFT 28 |
| #define DVFSC_DVFSLTR1_1_LTS1_15(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSLTR1_1_LTS1_15_SHIFT))&DVFSC_DVFSLTR1_1_LTS1_15_MASK) |
| /* DVFSPT0 Bit Fields */ |
| #define DVFSC_DVFSPT0_FPTN0_MASK 0x1FFFFu |
| #define DVFSC_DVFSPT0_FPTN0_SHIFT 0 |
| #define DVFSC_DVFSPT0_FPTN0(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT0_FPTN0_SHIFT))&DVFSC_DVFSPT0_FPTN0_MASK) |
| #define DVFSC_DVFSPT0_PT0A_MASK 0x20000u |
| #define DVFSC_DVFSPT0_PT0A_SHIFT 17 |
| /* DVFSPT1 Bit Fields */ |
| #define DVFSC_DVFSPT1_FPTN1_MASK 0x1FFFFu |
| #define DVFSC_DVFSPT1_FPTN1_SHIFT 0 |
| #define DVFSC_DVFSPT1_FPTN1(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT1_FPTN1_SHIFT))&DVFSC_DVFSPT1_FPTN1_MASK) |
| #define DVFSC_DVFSPT1_PT1A_MASK 0x20000u |
| #define DVFSC_DVFSPT1_PT1A_SHIFT 17 |
| /* DVFSPT2 Bit Fields */ |
| #define DVFSC_DVFSPT2_FPTN2_MASK 0x1FFFFu |
| #define DVFSC_DVFSPT2_FPTN2_SHIFT 0 |
| #define DVFSC_DVFSPT2_FPTN2(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT2_FPTN2_SHIFT))&DVFSC_DVFSPT2_FPTN2_MASK) |
| #define DVFSC_DVFSPT2_PT2A_MASK 0x20000u |
| #define DVFSC_DVFSPT2_PT2A_SHIFT 17 |
| #define DVFSC_DVFSPT2_P2THR_MASK 0xFC000000u |
| #define DVFSC_DVFSPT2_P2THR_SHIFT 26 |
| #define DVFSC_DVFSPT2_P2THR(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT2_P2THR_SHIFT))&DVFSC_DVFSPT2_P2THR_MASK) |
| /* DVFSPT3 Bit Fields */ |
| #define DVFSC_DVFSPT3_FPTN3_MASK 0x1FFFFu |
| #define DVFSC_DVFSPT3_FPTN3_SHIFT 0 |
| #define DVFSC_DVFSPT3_FPTN3(x) (((uint32_t)(((uint32_t)(x))<<DVFSC_DVFSPT3_FPTN3_SHIFT))&DVFSC_DVFSPT3_FPTN3_MASK) |
| #define DVFSC_DVFSPT3_PT3A_MASK 0x20000u |
| #define DVFSC_DVFSPT3_PT3A_SHIFT 17 |
| |
| /*! |
| * @} |
| */ /* end of group DVFSC_Register_Masks */ |
| |
| /* DVFSC - Peripheral instance base addresses */ |
| /** Peripheral DVFSC base address */ |
| #define DVFSC_BASE (0x420DC180u) |
| /** Peripheral DVFSC base pointer */ |
| #define DVFSC ((DVFSC_Type *)DVFSC_BASE) |
| #define DVFSC_BASE_PTR (DVFSC) |
| /** Array initializer of DVFSC peripheral base addresses */ |
| #define DVFSC_BASE_ADDRS { DVFSC_BASE } |
| /** Array initializer of DVFSC peripheral base pointers */ |
| #define DVFSC_BASE_PTRS { DVFSC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- DVFSC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup DVFSC_Register_Accessor_Macros DVFSC - Register accessor macros |
| * @{ |
| */ |
| |
| /* DVFSC - Register instance definitions */ |
| /* DVFSC */ |
| #define DVFSC_THRS DVFSC_THRS_REG(DVFSC_BASE_PTR) |
| #define DVFSC_COUN DVFSC_COUN_REG(DVFSC_BASE_PTR) |
| #define DVFSC_SIG1 DVFSC_SIG1_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSSIG0 DVFSC_DVFSSIG0_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSGPC0 DVFSC_DVFSGPC0_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSGPC1 DVFSC_DVFSGPC1_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSGPBT DVFSC_DVFSGPBT_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSEMAC DVFSC_DVFSEMAC_REG(DVFSC_BASE_PTR) |
| #define DVFSC_CNTR DVFSC_CNTR_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSLTR0_0 DVFSC_DVFSLTR0_0_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSLTR0_1 DVFSC_DVFSLTR0_1_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSLTR1_0 DVFSC_DVFSLTR1_0_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSLTR1_1 DVFSC_DVFSLTR1_1_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSPT0 DVFSC_DVFSPT0_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSPT1 DVFSC_DVFSPT1_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSPT2 DVFSC_DVFSPT2_REG(DVFSC_BASE_PTR) |
| #define DVFSC_DVFSPT3 DVFSC_DVFSPT3_REG(DVFSC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group DVFSC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group DVFSC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ECSPI - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ |
| __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ |
| __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ |
| __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ |
| __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ |
| __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ |
| __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ |
| __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ |
| __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ |
| uint8_t RESERVED_0[28]; |
| __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ |
| } ECSPI_Type, *ECSPI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros |
| * @{ |
| */ |
| |
| /* ECSPI - Register accessors */ |
| #define ECSPI_RXDATA_REG(base) ((base)->RXDATA) |
| #define ECSPI_TXDATA_REG(base) ((base)->TXDATA) |
| #define ECSPI_CONREG_REG(base) ((base)->CONREG) |
| #define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) |
| #define ECSPI_INTREG_REG(base) ((base)->INTREG) |
| #define ECSPI_DMAREG_REG(base) ((base)->DMAREG) |
| #define ECSPI_STATREG_REG(base) ((base)->STATREG) |
| #define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) |
| #define ECSPI_TESTREG_REG(base) ((base)->TESTREG) |
| #define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Register_Masks ECSPI Register Masks |
| * @{ |
| */ |
| |
| /* RXDATA Bit Fields */ |
| #define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu |
| #define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 |
| #define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_RXDATA_ECSPI_RXDATA_SHIFT))&ECSPI_RXDATA_ECSPI_RXDATA_MASK) |
| /* TXDATA Bit Fields */ |
| #define ECSPI_TXDATA_ECSPI_TXDATA_MASK 0xFFFFFFFFu |
| #define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT 0 |
| #define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TXDATA_ECSPI_TXDATA_SHIFT))&ECSPI_TXDATA_ECSPI_TXDATA_MASK) |
| /* CONREG Bit Fields */ |
| #define ECSPI_CONREG_EN_MASK 0x1u |
| #define ECSPI_CONREG_EN_SHIFT 0 |
| #define ECSPI_CONREG_HT_MASK 0x2u |
| #define ECSPI_CONREG_HT_SHIFT 1 |
| #define ECSPI_CONREG_XCH_MASK 0x4u |
| #define ECSPI_CONREG_XCH_SHIFT 2 |
| #define ECSPI_CONREG_SMC_MASK 0x8u |
| #define ECSPI_CONREG_SMC_SHIFT 3 |
| #define ECSPI_CONREG_CHANNEL_MODE_MASK 0xF0u |
| #define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4 |
| #define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_MODE_SHIFT))&ECSPI_CONREG_CHANNEL_MODE_MASK) |
| #define ECSPI_CONREG_POST_DIVIDER_MASK 0xF00u |
| #define ECSPI_CONREG_POST_DIVIDER_SHIFT 8 |
| #define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_POST_DIVIDER_SHIFT))&ECSPI_CONREG_POST_DIVIDER_MASK) |
| #define ECSPI_CONREG_PRE_DIVIDER_MASK 0xF000u |
| #define ECSPI_CONREG_PRE_DIVIDER_SHIFT 12 |
| #define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_PRE_DIVIDER_SHIFT))&ECSPI_CONREG_PRE_DIVIDER_MASK) |
| #define ECSPI_CONREG_DRCTL_MASK 0x30000u |
| #define ECSPI_CONREG_DRCTL_SHIFT 16 |
| #define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_DRCTL_SHIFT))&ECSPI_CONREG_DRCTL_MASK) |
| #define ECSPI_CONREG_CHANNEL_SELECT_MASK 0xC0000u |
| #define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18 |
| #define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_SELECT_SHIFT))&ECSPI_CONREG_CHANNEL_SELECT_MASK) |
| #define ECSPI_CONREG_BURST_LENGTH_MASK 0xFFF00000u |
| #define ECSPI_CONREG_BURST_LENGTH_SHIFT 20 |
| #define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_BURST_LENGTH_SHIFT))&ECSPI_CONREG_BURST_LENGTH_MASK) |
| /* CONFIGREG Bit Fields */ |
| #define ECSPI_CONFIGREG_SCLK_PHA_MASK 0xFu |
| #define ECSPI_CONFIGREG_SCLK_PHA_SHIFT 0 |
| #define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_PHA_SHIFT))&ECSPI_CONFIGREG_SCLK_PHA_MASK) |
| #define ECSPI_CONFIGREG_SCLK_POL_MASK 0xF0u |
| #define ECSPI_CONFIGREG_SCLK_POL_SHIFT 4 |
| #define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_POL_SHIFT))&ECSPI_CONFIGREG_SCLK_POL_MASK) |
| #define ECSPI_CONFIGREG_SS_CTL_MASK 0xF00u |
| #define ECSPI_CONFIGREG_SS_CTL_SHIFT 8 |
| #define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_CTL_SHIFT))&ECSPI_CONFIGREG_SS_CTL_MASK) |
| #define ECSPI_CONFIGREG_SS_POL_MASK 0xF000u |
| #define ECSPI_CONFIGREG_SS_POL_SHIFT 12 |
| #define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_POL_SHIFT))&ECSPI_CONFIGREG_SS_POL_MASK) |
| #define ECSPI_CONFIGREG_DATA_CTL_MASK 0xF0000u |
| #define ECSPI_CONFIGREG_DATA_CTL_SHIFT 16 |
| #define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_DATA_CTL_SHIFT))&ECSPI_CONFIGREG_DATA_CTL_MASK) |
| #define ECSPI_CONFIGREG_SCLK_CTL_MASK 0xF00000u |
| #define ECSPI_CONFIGREG_SCLK_CTL_SHIFT 20 |
| #define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_CTL_SHIFT))&ECSPI_CONFIGREG_SCLK_CTL_MASK) |
| #define ECSPI_CONFIGREG_HT_LENGTH_MASK 0x1F000000u |
| #define ECSPI_CONFIGREG_HT_LENGTH_SHIFT 24 |
| #define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_HT_LENGTH_SHIFT))&ECSPI_CONFIGREG_HT_LENGTH_MASK) |
| /* INTREG Bit Fields */ |
| #define ECSPI_INTREG_TEEN_MASK 0x1u |
| #define ECSPI_INTREG_TEEN_SHIFT 0 |
| #define ECSPI_INTREG_TDREN_MASK 0x2u |
| #define ECSPI_INTREG_TDREN_SHIFT 1 |
| #define ECSPI_INTREG_TFEN_MASK 0x4u |
| #define ECSPI_INTREG_TFEN_SHIFT 2 |
| #define ECSPI_INTREG_RREN_MASK 0x8u |
| #define ECSPI_INTREG_RREN_SHIFT 3 |
| #define ECSPI_INTREG_RDREN_MASK 0x10u |
| #define ECSPI_INTREG_RDREN_SHIFT 4 |
| #define ECSPI_INTREG_RFEN_MASK 0x20u |
| #define ECSPI_INTREG_RFEN_SHIFT 5 |
| #define ECSPI_INTREG_ROEN_MASK 0x40u |
| #define ECSPI_INTREG_ROEN_SHIFT 6 |
| #define ECSPI_INTREG_TCEN_MASK 0x80u |
| #define ECSPI_INTREG_TCEN_SHIFT 7 |
| /* DMAREG Bit Fields */ |
| #define ECSPI_DMAREG_TX_THRESHOLD_MASK 0x3Fu |
| #define ECSPI_DMAREG_TX_THRESHOLD_SHIFT 0 |
| #define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_TX_THRESHOLD_SHIFT))&ECSPI_DMAREG_TX_THRESHOLD_MASK) |
| #define ECSPI_DMAREG_TEDEN_MASK 0x80u |
| #define ECSPI_DMAREG_TEDEN_SHIFT 7 |
| #define ECSPI_DMAREG_RX_THRESHOLD_MASK 0x3F0000u |
| #define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16 |
| #define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_THRESHOLD_SHIFT))&ECSPI_DMAREG_RX_THRESHOLD_MASK) |
| #define ECSPI_DMAREG_RXDEN_MASK 0x800000u |
| #define ECSPI_DMAREG_RXDEN_SHIFT 23 |
| #define ECSPI_DMAREG_RX_DMA_LENGTH_MASK 0x3F000000u |
| #define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT 24 |
| #define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT))&ECSPI_DMAREG_RX_DMA_LENGTH_MASK) |
| #define ECSPI_DMAREG_RXTDEN_MASK 0x80000000u |
| #define ECSPI_DMAREG_RXTDEN_SHIFT 31 |
| /* STATREG Bit Fields */ |
| #define ECSPI_STATREG_TE_MASK 0x1u |
| #define ECSPI_STATREG_TE_SHIFT 0 |
| #define ECSPI_STATREG_TDR_MASK 0x2u |
| #define ECSPI_STATREG_TDR_SHIFT 1 |
| #define ECSPI_STATREG_TF_MASK 0x4u |
| #define ECSPI_STATREG_TF_SHIFT 2 |
| #define ECSPI_STATREG_RR_MASK 0x8u |
| #define ECSPI_STATREG_RR_SHIFT 3 |
| #define ECSPI_STATREG_RDR_MASK 0x10u |
| #define ECSPI_STATREG_RDR_SHIFT 4 |
| #define ECSPI_STATREG_RF_MASK 0x20u |
| #define ECSPI_STATREG_RF_SHIFT 5 |
| #define ECSPI_STATREG_RO_MASK 0x40u |
| #define ECSPI_STATREG_RO_SHIFT 6 |
| #define ECSPI_STATREG_TC_MASK 0x80u |
| #define ECSPI_STATREG_TC_SHIFT 7 |
| /* PERIODREG Bit Fields */ |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK 0x7FFFu |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT 0 |
| #define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT))&ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) |
| #define ECSPI_PERIODREG_CSRC_MASK 0x8000u |
| #define ECSPI_PERIODREG_CSRC_SHIFT 15 |
| #define ECSPI_PERIODREG_CSD_CTL_MASK 0x3F0000u |
| #define ECSPI_PERIODREG_CSD_CTL_SHIFT 16 |
| #define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_CSD_CTL_SHIFT))&ECSPI_PERIODREG_CSD_CTL_MASK) |
| /* TESTREG Bit Fields */ |
| #define ECSPI_TESTREG_TXCNT_MASK 0x7Fu |
| #define ECSPI_TESTREG_TXCNT_SHIFT 0 |
| #define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_TXCNT_SHIFT))&ECSPI_TESTREG_TXCNT_MASK) |
| #define ECSPI_TESTREG_RXCNT_MASK 0x7F00u |
| #define ECSPI_TESTREG_RXCNT_SHIFT 8 |
| #define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_RXCNT_SHIFT))&ECSPI_TESTREG_RXCNT_MASK) |
| #define ECSPI_TESTREG_LBC_MASK 0x80000000u |
| #define ECSPI_TESTREG_LBC_SHIFT 31 |
| /* MSGDATA Bit Fields */ |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK 0xFFFFFFFFu |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT 0 |
| #define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT))&ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Register_Masks */ |
| |
| /* ECSPI - Peripheral instance base addresses */ |
| /** Peripheral ECSPI1 base address */ |
| #define ECSPI1_BASE (0x42008000u) |
| /** Peripheral ECSPI1 base pointer */ |
| #define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) |
| #define ECSPI1_BASE_PTR (ECSPI1) |
| /** Peripheral ECSPI2 base address */ |
| #define ECSPI2_BASE (0x4200C000u) |
| /** Peripheral ECSPI2 base pointer */ |
| #define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) |
| #define ECSPI2_BASE_PTR (ECSPI2) |
| /** Peripheral ECSPI3 base address */ |
| #define ECSPI3_BASE (0x42010000u) |
| /** Peripheral ECSPI3 base pointer */ |
| #define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) |
| #define ECSPI3_BASE_PTR (ECSPI3) |
| /** Peripheral ECSPI4 base address */ |
| #define ECSPI4_BASE (0x42014000u) |
| /** Peripheral ECSPI4 base pointer */ |
| #define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) |
| #define ECSPI4_BASE_PTR (ECSPI4) |
| /** Peripheral ECSPI5 base address */ |
| #define ECSPI5_BASE (0x4228C000u) |
| /** Peripheral ECSPI5 base pointer */ |
| #define ECSPI5 ((ECSPI_Type *)ECSPI5_BASE) |
| #define ECSPI5_BASE_PTR (ECSPI5) |
| /** Array initializer of ECSPI peripheral base addresses */ |
| #define ECSPI_BASE_ADDRS { ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE, ECSPI5_BASE } |
| /** Array initializer of ECSPI peripheral base pointers */ |
| #define ECSPI_BASE_PTRS { ECSPI1, ECSPI2, ECSPI3, ECSPI4, ECSPI5 } |
| /** Interrupt vectors for the ECSPI peripheral type */ |
| #define ECSPI_IRQS { eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn, eCSPI5_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ECSPI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros |
| * @{ |
| */ |
| |
| /* ECSPI - Register instance definitions */ |
| /* ECSPI1 */ |
| #define ECSPI1_RXDATA ECSPI_RXDATA_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_TXDATA ECSPI_TXDATA_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_CONREG ECSPI_CONREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_INTREG ECSPI_INTREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_DMAREG ECSPI_DMAREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_STATREG ECSPI_STATREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_PERIODREG ECSPI_PERIODREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_TESTREG ECSPI_TESTREG_REG(ECSPI1_BASE_PTR) |
| #define ECSPI1_MSGDATA ECSPI_MSGDATA_REG(ECSPI1_BASE_PTR) |
| /* ECSPI2 */ |
| #define ECSPI2_RXDATA ECSPI_RXDATA_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_TXDATA ECSPI_TXDATA_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_CONREG ECSPI_CONREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_INTREG ECSPI_INTREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_DMAREG ECSPI_DMAREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_STATREG ECSPI_STATREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_PERIODREG ECSPI_PERIODREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_TESTREG ECSPI_TESTREG_REG(ECSPI2_BASE_PTR) |
| #define ECSPI2_MSGDATA ECSPI_MSGDATA_REG(ECSPI2_BASE_PTR) |
| /* ECSPI3 */ |
| #define ECSPI3_RXDATA ECSPI_RXDATA_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_TXDATA ECSPI_TXDATA_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_CONREG ECSPI_CONREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_INTREG ECSPI_INTREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_DMAREG ECSPI_DMAREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_STATREG ECSPI_STATREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_PERIODREG ECSPI_PERIODREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_TESTREG ECSPI_TESTREG_REG(ECSPI3_BASE_PTR) |
| #define ECSPI3_MSGDATA ECSPI_MSGDATA_REG(ECSPI3_BASE_PTR) |
| /* ECSPI4 */ |
| #define ECSPI4_RXDATA ECSPI_RXDATA_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_TXDATA ECSPI_TXDATA_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_CONREG ECSPI_CONREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_INTREG ECSPI_INTREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_DMAREG ECSPI_DMAREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_STATREG ECSPI_STATREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_PERIODREG ECSPI_PERIODREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_TESTREG ECSPI_TESTREG_REG(ECSPI4_BASE_PTR) |
| #define ECSPI4_MSGDATA ECSPI_MSGDATA_REG(ECSPI4_BASE_PTR) |
| /* ECSPI5 */ |
| #define ECSPI5_RXDATA ECSPI_RXDATA_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_TXDATA ECSPI_TXDATA_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_CONREG ECSPI_CONREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_INTREG ECSPI_INTREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_DMAREG ECSPI_DMAREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_STATREG ECSPI_STATREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_PERIODREG ECSPI_PERIODREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_TESTREG ECSPI_TESTREG_REG(ECSPI5_BASE_PTR) |
| #define ECSPI5_MSGDATA ECSPI_MSGDATA_REG(ECSPI5_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ECSPI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- EIM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** EIM - Register Layout Typedef */ |
| typedef struct { |
| struct { /* offset: 0x0, array step: 0x18 */ |
| __IO uint32_t CSGCR1; /**< Chip Select n General Configuration Register 1, array offset: 0x0, array step: 0x18 */ |
| __IO uint32_t CSGCR2; /**< Chip Select n General Configuration Register 2, array offset: 0x4, array step: 0x18 */ |
| __IO uint32_t CSRCR1; /**< Chip Select n Read Configuration Register 1, array offset: 0x8, array step: 0x18 */ |
| __IO uint32_t CSRCR2; /**< Chip Select n Read Configuration Register 2, array offset: 0xC, array step: 0x18 */ |
| __IO uint32_t CSWCR1; /**< Chip Select n Write Configuration Register 1, array offset: 0x10, array step: 0x18 */ |
| __IO uint32_t CSWCR2; /**< Chip Select n Write Configuration Register 2, array offset: 0x14, array step: 0x18 */ |
| } CS[6]; |
| __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ |
| __IO uint32_t DCR; /**< DLL Control Register, offset: 0x94 */ |
| __I uint32_t DSR; /**< DLL Status Register, offset: 0x98 */ |
| __IO uint32_t WIAR; /**< EIM IP Access Register, offset: 0x9C */ |
| __IO uint32_t EAR; /**< Error Address Register, offset: 0xA0 */ |
| } EIM_Type, *EIM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- EIM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros |
| * @{ |
| */ |
| |
| /* EIM - Register accessors */ |
| #define EIM_CSGCR1_REG(base,index) ((base)->CS[index].CSGCR1) |
| #define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) |
| #define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) |
| #define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) |
| #define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) |
| #define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) |
| #define EIM_WCR_REG(base) ((base)->WCR) |
| #define EIM_DCR_REG(base) ((base)->DCR) |
| #define EIM_DSR_REG(base) ((base)->DSR) |
| #define EIM_WIAR_REG(base) ((base)->WIAR) |
| #define EIM_EAR_REG(base) ((base)->EAR) |
| |
| /*! |
| * @} |
| */ /* end of group EIM_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- EIM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EIM_Register_Masks EIM Register Masks |
| * @{ |
| */ |
| |
| /* CSGCR1 Bit Fields */ |
| #define EIM_CSGCR1_CSEN_MASK 0x1u |
| #define EIM_CSGCR1_CSEN_SHIFT 0 |
| #define EIM_CSGCR1_SWR_MASK 0x2u |
| #define EIM_CSGCR1_SWR_SHIFT 1 |
| #define EIM_CSGCR1_SRD_MASK 0x4u |
| #define EIM_CSGCR1_SRD_SHIFT 2 |
| #define EIM_CSGCR1_MUM_MASK 0x8u |
| #define EIM_CSGCR1_MUM_SHIFT 3 |
| #define EIM_CSGCR1_WFL_MASK 0x10u |
| #define EIM_CSGCR1_WFL_SHIFT 4 |
| #define EIM_CSGCR1_RFL_MASK 0x20u |
| #define EIM_CSGCR1_RFL_SHIFT 5 |
| #define EIM_CSGCR1_CRE_MASK 0x40u |
| #define EIM_CSGCR1_CRE_SHIFT 6 |
| #define EIM_CSGCR1_CREP_MASK 0x80u |
| #define EIM_CSGCR1_CREP_SHIFT 7 |
| #define EIM_CSGCR1_BL_MASK 0x700u |
| #define EIM_CSGCR1_BL_SHIFT 8 |
| #define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BL_SHIFT))&EIM_CSGCR1_BL_MASK) |
| #define EIM_CSGCR1_WC_MASK 0x800u |
| #define EIM_CSGCR1_WC_SHIFT 11 |
| #define EIM_CSGCR1_BCD_MASK 0x3000u |
| #define EIM_CSGCR1_BCD_SHIFT 12 |
| #define EIM_CSGCR1_BCD(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCD_SHIFT))&EIM_CSGCR1_BCD_MASK) |
| #define EIM_CSGCR1_BCS_MASK 0xC000u |
| #define EIM_CSGCR1_BCS_SHIFT 14 |
| #define EIM_CSGCR1_BCS(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCS_SHIFT))&EIM_CSGCR1_BCS_MASK) |
| #define EIM_CSGCR1_DSZ_MASK 0x70000u |
| #define EIM_CSGCR1_DSZ_SHIFT 16 |
| #define EIM_CSGCR1_DSZ(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_DSZ_SHIFT))&EIM_CSGCR1_DSZ_MASK) |
| #define EIM_CSGCR1_SP_MASK 0x80000u |
| #define EIM_CSGCR1_SP_SHIFT 19 |
| #define EIM_CSGCR1_CSREC_MASK 0x700000u |
| #define EIM_CSGCR1_CSREC_SHIFT 20 |
| #define EIM_CSGCR1_CSREC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_CSREC_SHIFT))&EIM_CSGCR1_CSREC_MASK) |
| #define EIM_CSGCR1_AUS_MASK 0x800000u |
| #define EIM_CSGCR1_AUS_SHIFT 23 |
| #define EIM_CSGCR1_GBC_MASK 0x7000000u |
| #define EIM_CSGCR1_GBC_SHIFT 24 |
| #define EIM_CSGCR1_GBC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_GBC_SHIFT))&EIM_CSGCR1_GBC_MASK) |
| #define EIM_CSGCR1_WP_MASK 0x8000000u |
| #define EIM_CSGCR1_WP_SHIFT 27 |
| #define EIM_CSGCR1_PSZ_MASK 0xF0000000u |
| #define EIM_CSGCR1_PSZ_SHIFT 28 |
| #define EIM_CSGCR1_PSZ(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_PSZ_SHIFT))&EIM_CSGCR1_PSZ_MASK) |
| /* CSGCR2 Bit Fields */ |
| #define EIM_CSGCR2_ADH_MASK 0x3u |
| #define EIM_CSGCR2_ADH_SHIFT 0 |
| #define EIM_CSGCR2_ADH(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_ADH_SHIFT))&EIM_CSGCR2_ADH_MASK) |
| #define EIM_CSGCR2_DAPS_MASK 0xF0u |
| #define EIM_CSGCR2_DAPS_SHIFT 4 |
| #define EIM_CSGCR2_DAPS(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_DAPS_SHIFT))&EIM_CSGCR2_DAPS_MASK) |
| #define EIM_CSGCR2_DAE_MASK 0x100u |
| #define EIM_CSGCR2_DAE_SHIFT 8 |
| #define EIM_CSGCR2_DAP_MASK 0x200u |
| #define EIM_CSGCR2_DAP_SHIFT 9 |
| #define EIM_CSGCR2_MUX16_BYP_GRANT_MASK 0x1000u |
| #define EIM_CSGCR2_MUX16_BYP_GRANT_SHIFT 12 |
| /* CSRCR1 Bit Fields */ |
| #define EIM_CSRCR1_RCSN_MASK 0x7u |
| #define EIM_CSRCR1_RCSN_SHIFT 0 |
| #define EIM_CSRCR1_RCSN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSN_SHIFT))&EIM_CSRCR1_RCSN_MASK) |
| #define EIM_CSRCR1_RCSA_MASK 0x70u |
| #define EIM_CSRCR1_RCSA_SHIFT 4 |
| #define EIM_CSRCR1_RCSA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSA_SHIFT))&EIM_CSRCR1_RCSA_MASK) |
| #define EIM_CSRCR1_OEN_MASK 0x700u |
| #define EIM_CSRCR1_OEN_SHIFT 8 |
| #define EIM_CSRCR1_OEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEN_SHIFT))&EIM_CSRCR1_OEN_MASK) |
| #define EIM_CSRCR1_OEA_MASK 0x7000u |
| #define EIM_CSRCR1_OEA_SHIFT 12 |
| #define EIM_CSRCR1_OEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEA_SHIFT))&EIM_CSRCR1_OEA_MASK) |
| #define EIM_CSRCR1_RADVN_MASK 0x70000u |
| #define EIM_CSRCR1_RADVN_SHIFT 16 |
| #define EIM_CSRCR1_RADVN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVN_SHIFT))&EIM_CSRCR1_RADVN_MASK) |
| #define EIM_CSRCR1_RAL_MASK 0x80000u |
| #define EIM_CSRCR1_RAL_SHIFT 19 |
| #define EIM_CSRCR1_RADVA_MASK 0x700000u |
| #define EIM_CSRCR1_RADVA_SHIFT 20 |
| #define EIM_CSRCR1_RADVA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVA_SHIFT))&EIM_CSRCR1_RADVA_MASK) |
| #define EIM_CSRCR1_RWSC_MASK 0x3F000000u |
| #define EIM_CSRCR1_RWSC_SHIFT 24 |
| #define EIM_CSRCR1_RWSC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RWSC_SHIFT))&EIM_CSRCR1_RWSC_MASK) |
| /* CSRCR2 Bit Fields */ |
| #define EIM_CSRCR2_RBEN_MASK 0x7u |
| #define EIM_CSRCR2_RBEN_SHIFT 0 |
| #define EIM_CSRCR2_RBEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEN_SHIFT))&EIM_CSRCR2_RBEN_MASK) |
| #define EIM_CSRCR2_RBE_MASK 0x8u |
| #define EIM_CSRCR2_RBE_SHIFT 3 |
| #define EIM_CSRCR2_RBEA_MASK 0x70u |
| #define EIM_CSRCR2_RBEA_SHIFT 4 |
| #define EIM_CSRCR2_RBEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEA_SHIFT))&EIM_CSRCR2_RBEA_MASK) |
| #define EIM_CSRCR2_RL_MASK 0x300u |
| #define EIM_CSRCR2_RL_SHIFT 8 |
| #define EIM_CSRCR2_RL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RL_SHIFT))&EIM_CSRCR2_RL_MASK) |
| #define EIM_CSRCR2_PAT_MASK 0x7000u |
| #define EIM_CSRCR2_PAT_SHIFT 12 |
| #define EIM_CSRCR2_PAT(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_PAT_SHIFT))&EIM_CSRCR2_PAT_MASK) |
| #define EIM_CSRCR2_APR_MASK 0x8000u |
| #define EIM_CSRCR2_APR_SHIFT 15 |
| /* CSWCR1 Bit Fields */ |
| #define EIM_CSWCR1_WCSN_MASK 0x7u |
| #define EIM_CSWCR1_WCSN_SHIFT 0 |
| #define EIM_CSWCR1_WCSN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSN_SHIFT))&EIM_CSWCR1_WCSN_MASK) |
| #define EIM_CSWCR1_WCSA_MASK 0x38u |
| #define EIM_CSWCR1_WCSA_SHIFT 3 |
| #define EIM_CSWCR1_WCSA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSA_SHIFT))&EIM_CSWCR1_WCSA_MASK) |
| #define EIM_CSWCR1_WEN_MASK 0x1C0u |
| #define EIM_CSWCR1_WEN_SHIFT 6 |
| #define EIM_CSWCR1_WEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEN_SHIFT))&EIM_CSWCR1_WEN_MASK) |
| #define EIM_CSWCR1_WEA_MASK 0xE00u |
| #define EIM_CSWCR1_WEA_SHIFT 9 |
| #define EIM_CSWCR1_WEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEA_SHIFT))&EIM_CSWCR1_WEA_MASK) |
| #define EIM_CSWCR1_WBEN_MASK 0x7000u |
| #define EIM_CSWCR1_WBEN_SHIFT 12 |
| #define EIM_CSWCR1_WBEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEN_SHIFT))&EIM_CSWCR1_WBEN_MASK) |
| #define EIM_CSWCR1_WBEA_MASK 0x38000u |
| #define EIM_CSWCR1_WBEA_SHIFT 15 |
| #define EIM_CSWCR1_WBEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEA_SHIFT))&EIM_CSWCR1_WBEA_MASK) |
| #define EIM_CSWCR1_WADVN_MASK 0x1C0000u |
| #define EIM_CSWCR1_WADVN_SHIFT 18 |
| #define EIM_CSWCR1_WADVN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVN_SHIFT))&EIM_CSWCR1_WADVN_MASK) |
| #define EIM_CSWCR1_WADVA_MASK 0xE00000u |
| #define EIM_CSWCR1_WADVA_SHIFT 21 |
| #define EIM_CSWCR1_WADVA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVA_SHIFT))&EIM_CSWCR1_WADVA_MASK) |
| #define EIM_CSWCR1_WWSC_MASK 0x3F000000u |
| #define EIM_CSWCR1_WWSC_SHIFT 24 |
| #define EIM_CSWCR1_WWSC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WWSC_SHIFT))&EIM_CSWCR1_WWSC_MASK) |
| #define EIM_CSWCR1_WBED_MASK 0x40000000u |
| #define EIM_CSWCR1_WBED_SHIFT 30 |
| #define EIM_CSWCR1_WAL_MASK 0x80000000u |
| #define EIM_CSWCR1_WAL_SHIFT 31 |
| /* CSWCR2 Bit Fields */ |
| #define EIM_CSWCR2_WBCDD_MASK 0x1u |
| #define EIM_CSWCR2_WBCDD_SHIFT 0 |
| /* WCR Bit Fields */ |
| #define EIM_WCR_BCM_MASK 0x1u |
| #define EIM_WCR_BCM_SHIFT 0 |
| #define EIM_WCR_GBCD_MASK 0x6u |
| #define EIM_WCR_GBCD_SHIFT 1 |
| #define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x))<<EIM_WCR_GBCD_SHIFT))&EIM_WCR_GBCD_MASK) |
| #define EIM_WCR_CONT_BCLK_SEL_MASK 0x8u |
| #define EIM_WCR_CONT_BCLK_SEL_SHIFT 3 |
| #define EIM_WCR_INTEN_MASK 0x10u |
| #define EIM_WCR_INTEN_SHIFT 4 |
| #define EIM_WCR_INTPOL_MASK 0x20u |
| #define EIM_WCR_INTPOL_SHIFT 5 |
| #define EIM_WCR_WDOG_EN_MASK 0x100u |
| #define EIM_WCR_WDOG_EN_SHIFT 8 |
| #define EIM_WCR_WDOG_LIMIT_MASK 0x600u |
| #define EIM_WCR_WDOG_LIMIT_SHIFT 9 |
| #define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x))<<EIM_WCR_WDOG_LIMIT_SHIFT))&EIM_WCR_WDOG_LIMIT_MASK) |
| #define EIM_WCR_FRUN_ACLK_EN_MASK 0x800u |
| #define EIM_WCR_FRUN_ACLK_EN_SHIFT 11 |
| /* DCR Bit Fields */ |
| #define EIM_DCR_DLL_CTRL_ENABLE_MASK 0x1u |
| #define EIM_DCR_DLL_CTRL_ENABLE_SHIFT 0 |
| #define EIM_DCR_DLL_CTRL_RESET_MASK 0x2u |
| #define EIM_DCR_DLL_CTRL_RESET_SHIFT 1 |
| #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u |
| #define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 |
| #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_MASK 0x8u |
| #define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_SHIFT 3 |
| #define EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK 0x70u |
| #define EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT 4 |
| #define EIM_DCR_DLL_CTRL_SLV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK) |
| #define EIM_DCR_DLL_CTRL_GATE_UPDATE_MASK 0x80u |
| #define EIM_DCR_DLL_CTRL_GATE_UPDATE_SHIFT 7 |
| #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u |
| #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_SHIFT 8 |
| #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u |
| #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9 |
| #define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK 0x7F0000u |
| #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT 16 |
| #define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT))&EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK) |
| #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xF800000u |
| #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 23 |
| #define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u |
| #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 |
| #define EIM_DCR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /* DSR Bit Fields */ |
| #define EIM_DSR_DLL_STS_SLV_LOCK_MASK 0x1u |
| #define EIM_DSR_DLL_STS_SLV_LOCK_SHIFT 0 |
| #define EIM_DSR_DLL_STS_REF_LOCK_MASK 0x2u |
| #define EIM_DSR_DLL_STS_REF_LOCK_SHIFT 1 |
| #define EIM_DSR_DLL_STS_SLV_SEL_MASK 0x1FCu |
| #define EIM_DSR_DLL_STS_SLV_SEL_SHIFT 2 |
| #define EIM_DSR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_SLV_SEL_SHIFT))&EIM_DSR_DLL_STS_SLV_SEL_MASK) |
| #define EIM_DSR_DLL_STS_REF_SEL_MASK 0xFE00u |
| #define EIM_DSR_DLL_STS_REF_SEL_SHIFT 9 |
| #define EIM_DSR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_REF_SEL_SHIFT))&EIM_DSR_DLL_STS_REF_SEL_MASK) |
| /* WIAR Bit Fields */ |
| #define EIM_WIAR_IPS_REQ_MASK 0x1u |
| #define EIM_WIAR_IPS_REQ_SHIFT 0 |
| #define EIM_WIAR_IPS_ACK_MASK 0x2u |
| #define EIM_WIAR_IPS_ACK_SHIFT 1 |
| #define EIM_WIAR_INT_MASK 0x4u |
| #define EIM_WIAR_INT_SHIFT 2 |
| #define EIM_WIAR_ERRST_MASK 0x8u |
| #define EIM_WIAR_ERRST_SHIFT 3 |
| #define EIM_WIAR_ACLK_EN_MASK 0x10u |
| #define EIM_WIAR_ACLK_EN_SHIFT 4 |
| /* EAR Bit Fields */ |
| #define EIM_EAR_Error_ADDR_MASK 0xFFFFFFFFu |
| #define EIM_EAR_Error_ADDR_SHIFT 0 |
| #define EIM_EAR_Error_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EIM_EAR_Error_ADDR_SHIFT))&EIM_EAR_Error_ADDR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group EIM_Register_Masks */ |
| |
| /* EIM - Peripheral instance base addresses */ |
| /** Peripheral EIM base address */ |
| #define EIM_BASE (0x421B8000u) |
| /** Peripheral EIM base pointer */ |
| #define EIM ((EIM_Type *)EIM_BASE) |
| #define EIM_BASE_PTR (EIM) |
| /** Array initializer of EIM peripheral base addresses */ |
| #define EIM_BASE_ADDRS { EIM_BASE } |
| /** Array initializer of EIM peripheral base pointers */ |
| #define EIM_BASE_PTRS { EIM } |
| /** Interrupt vectors for the EIM peripheral type */ |
| #define EIM_IRQS { EIM_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- EIM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros |
| * @{ |
| */ |
| |
| /* EIM - Register instance definitions */ |
| /* EIM */ |
| #define EIM_CS0GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,0) |
| #define EIM_CS0GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,0) |
| #define EIM_CS0RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,0) |
| #define EIM_CS0RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,0) |
| #define EIM_CS0WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,0) |
| #define EIM_CS0WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,0) |
| #define EIM_CS1GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,1) |
| #define EIM_CS1GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,1) |
| #define EIM_CS1RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,1) |
| #define EIM_CS1RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,1) |
| #define EIM_CS1WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,1) |
| #define EIM_CS1WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,1) |
| #define EIM_CS2GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,2) |
| #define EIM_CS2GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,2) |
| #define EIM_CS2RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,2) |
| #define EIM_CS2RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,2) |
| #define EIM_CS2WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,2) |
| #define EIM_CS2WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,2) |
| #define EIM_CS3GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,3) |
| #define EIM_CS3GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,3) |
| #define EIM_CS3RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,3) |
| #define EIM_CS3RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,3) |
| #define EIM_CS3WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,3) |
| #define EIM_CS3WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,3) |
| #define EIM_CS4GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,4) |
| #define EIM_CS4GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,4) |
| #define EIM_CS4RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,4) |
| #define EIM_CS4RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,4) |
| #define EIM_CS4WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,4) |
| #define EIM_CS4WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,4) |
| #define EIM_CS5GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,5) |
| #define EIM_CS5GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,5) |
| #define EIM_CS5RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,5) |
| #define EIM_CS5RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,5) |
| #define EIM_CS5WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,5) |
| #define EIM_CS5WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,5) |
| #define EIM_WCR EIM_WCR_REG(EIM_BASE_PTR) |
| #define EIM_DCR EIM_DCR_REG(EIM_BASE_PTR) |
| #define EIM_DSR EIM_DSR_REG(EIM_BASE_PTR) |
| #define EIM_WIAR EIM_WIAR_REG(EIM_BASE_PTR) |
| #define EIM_EAR EIM_EAR_REG(EIM_BASE_PTR) |
| /* EIM - Register array accessors */ |
| #define EIM_CSGCR1(index) EIM_CSGCR1_REG(EIM_BASE_PTR,index) |
| #define EIM_CSGCR2(index) EIM_CSGCR2_REG(EIM_BASE_PTR,index) |
| #define EIM_CSRCR1(index) EIM_CSRCR1_REG(EIM_BASE_PTR,index) |
| #define EIM_CSRCR2(index) EIM_CSRCR2_REG(EIM_BASE_PTR,index) |
| #define EIM_CSWCR1(index) EIM_CSWCR1_REG(EIM_BASE_PTR,index) |
| #define EIM_CSWCR2(index) EIM_CSWCR2_REG(EIM_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group EIM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group EIM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ENET - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ |
| __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ |
| __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ |
| uint8_t RESERVED_3[24]; |
| __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ |
| __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ |
| uint8_t RESERVED_4[28]; |
| __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ |
| uint8_t RESERVED_5[28]; |
| __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ |
| uint8_t RESERVED_6[60]; |
| __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ |
| uint8_t RESERVED_7[28]; |
| __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ |
| __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ |
| __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ |
| __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ |
| uint8_t RESERVED_8[4]; |
| __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ |
| __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ |
| __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ |
| __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ |
| uint8_t RESERVED_10[28]; |
| __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ |
| uint8_t RESERVED_11[24]; |
| __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ |
| __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ |
| __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ |
| __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ |
| __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ |
| __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ |
| uint8_t RESERVED_12[8]; |
| __IO uint32_t RDSR; /**< Receive Descriptor Ring , offset: 0x180 */ |
| __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring , offset: 0x184 */ |
| __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ |
| uint8_t RESERVED_13[4]; |
| __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ |
| __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ |
| __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ |
| __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ |
| __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ |
| __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ |
| __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ |
| __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ |
| __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ |
| __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ |
| __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ |
| uint8_t RESERVED_15[8]; |
| __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ |
| __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ |
| __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ |
| __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ |
| __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ |
| __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ |
| uint8_t RESERVED_16[12]; |
| __I uint32_t RMON_T_DROP; /**< Incorrectly Counted Frames Statistic Register, offset: 0x200 */ |
| __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ |
| __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ |
| __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ |
| __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ |
| __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ |
| __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ |
| __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ |
| __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ |
| __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ |
| __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ |
| __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ |
| __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ |
| __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ |
| __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ |
| __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ |
| __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ |
| __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ |
| __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Statistic Register, offset: 0x248 */ |
| __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ |
| __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ |
| __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ |
| __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ |
| __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ |
| __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ |
| __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ |
| __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ |
| __I uint32_t IEEE_T_SQE; /**< , offset: 0x26C */ |
| __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ |
| __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ |
| uint8_t RESERVED_17[12]; |
| __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ |
| __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ |
| __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ |
| __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ |
| __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ |
| __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ |
| __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ |
| __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ |
| __I uint32_t RMON_R_RESVD_0; /**< RMON Reserved Register, offset: 0x2A4 */ |
| __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ |
| __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ |
| __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ |
| __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ |
| __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ |
| __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ |
| __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ |
| __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ |
| __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ |
| __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ |
| __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ |
| __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ |
| __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ |
| __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ |
| __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ |
| uint8_t RESERVED_18[284]; |
| __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ |
| __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ |
| __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ |
| __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ |
| __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ |
| __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ |
| __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ |
| uint8_t RESERVED_19[488]; |
| __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ |
| struct { /* offset: 0x608, array step: 0x8 */ |
| __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ |
| __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ |
| } TC[4]; |
| } ENET_Type, *ENET_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros |
| * @{ |
| */ |
| |
| /* ENET - Register accessors */ |
| #define ENET_EIR_REG(base) ((base)->EIR) |
| #define ENET_EIMR_REG(base) ((base)->EIMR) |
| #define ENET_RDAR_REG(base) ((base)->RDAR) |
| #define ENET_TDAR_REG(base) ((base)->TDAR) |
| #define ENET_ECR_REG(base) ((base)->ECR) |
| #define ENET_MMFR_REG(base) ((base)->MMFR) |
| #define ENET_MSCR_REG(base) ((base)->MSCR) |
| #define ENET_MIBC_REG(base) ((base)->MIBC) |
| #define ENET_RCR_REG(base) ((base)->RCR) |
| #define ENET_TCR_REG(base) ((base)->TCR) |
| #define ENET_PALR_REG(base) ((base)->PALR) |
| #define ENET_PAUR_REG(base) ((base)->PAUR) |
| #define ENET_OPD_REG(base) ((base)->OPD) |
| #define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) |
| #define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) |
| #define ENET_IAUR_REG(base) ((base)->IAUR) |
| #define ENET_IALR_REG(base) ((base)->IALR) |
| #define ENET_GAUR_REG(base) ((base)->GAUR) |
| #define ENET_GALR_REG(base) ((base)->GALR) |
| #define ENET_TFWR_REG(base) ((base)->TFWR) |
| #define ENET_RDSR1_REG(base) ((base)->RDSR1) |
| #define ENET_TDSR1_REG(base) ((base)->TDSR1) |
| #define ENET_MRBR1_REG(base) ((base)->MRBR1) |
| #define ENET_RDSR2_REG(base) ((base)->RDSR2) |
| #define ENET_TDSR2_REG(base) ((base)->TDSR2) |
| #define ENET_MRBR2_REG(base) ((base)->MRBR2) |
| #define ENET_RDSR_REG(base) ((base)->RDSR) |
| #define ENET_TDSR_REG(base) ((base)->TDSR) |
| #define ENET_MRBR_REG(base) ((base)->MRBR) |
| #define ENET_RSFL_REG(base) ((base)->RSFL) |
| #define ENET_RSEM_REG(base) ((base)->RSEM) |
| #define ENET_RAEM_REG(base) ((base)->RAEM) |
| #define ENET_RAFL_REG(base) ((base)->RAFL) |
| #define ENET_TSEM_REG(base) ((base)->TSEM) |
| #define ENET_TAEM_REG(base) ((base)->TAEM) |
| #define ENET_TAFL_REG(base) ((base)->TAFL) |
| #define ENET_TIPG_REG(base) ((base)->TIPG) |
| #define ENET_FTRL_REG(base) ((base)->FTRL) |
| #define ENET_TACC_REG(base) ((base)->TACC) |
| #define ENET_RACC_REG(base) ((base)->RACC) |
| #define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) |
| #define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) |
| #define ENET_RDAR1_REG(base) ((base)->RDAR1) |
| #define ENET_TDAR1_REG(base) ((base)->TDAR1) |
| #define ENET_RDAR2_REG(base) ((base)->RDAR2) |
| #define ENET_TDAR2_REG(base) ((base)->TDAR2) |
| #define ENET_QOS_REG(base) ((base)->QOS) |
| #define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) |
| #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) |
| #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) |
| #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) |
| #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) |
| #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) |
| #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) |
| #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) |
| #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) |
| #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) |
| #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) |
| #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) |
| #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) |
| #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) |
| #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) |
| #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) |
| #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) |
| #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) |
| #define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) |
| #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) |
| #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) |
| #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) |
| #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) |
| #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) |
| #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) |
| #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) |
| #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) |
| #define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) |
| #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) |
| #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) |
| #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) |
| #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) |
| #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) |
| #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) |
| #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) |
| #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) |
| #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) |
| #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) |
| #define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) |
| #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) |
| #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) |
| #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) |
| #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) |
| #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) |
| #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) |
| #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) |
| #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) |
| #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) |
| #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) |
| #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) |
| #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) |
| #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) |
| #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) |
| #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) |
| #define ENET_ATCR_REG(base) ((base)->ATCR) |
| #define ENET_ATVR_REG(base) ((base)->ATVR) |
| #define ENET_ATOFF_REG(base) ((base)->ATOFF) |
| #define ENET_ATPER_REG(base) ((base)->ATPER) |
| #define ENET_ATCOR_REG(base) ((base)->ATCOR) |
| #define ENET_ATINC_REG(base) ((base)->ATINC) |
| #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) |
| #define ENET_TGSR_REG(base) ((base)->TGSR) |
| #define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) |
| #define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Register_Masks ENET Register Masks |
| * @{ |
| */ |
| |
| /* EIR Bit Fields */ |
| #define ENET_EIR_RXB1_MASK 0x1u |
| #define ENET_EIR_RXB1_SHIFT 0 |
| #define ENET_EIR_RXF1_MASK 0x2u |
| #define ENET_EIR_RXF1_SHIFT 1 |
| #define ENET_EIR_TXB1_MASK 0x4u |
| #define ENET_EIR_TXB1_SHIFT 2 |
| #define ENET_EIR_TXF1_MASK 0x8u |
| #define ENET_EIR_TXF1_SHIFT 3 |
| #define ENET_EIR_RXB2_MASK 0x10u |
| #define ENET_EIR_RXB2_SHIFT 4 |
| #define ENET_EIR_RXF2_MASK 0x20u |
| #define ENET_EIR_RXF2_SHIFT 5 |
| #define ENET_EIR_TXB2_MASK 0x40u |
| #define ENET_EIR_TXB2_SHIFT 6 |
| #define ENET_EIR_TXF2_MASK 0x80u |
| #define ENET_EIR_TXF2_SHIFT 7 |
| #define ENET_EIR_RXFLUSH_0_MASK 0x1000u |
| #define ENET_EIR_RXFLUSH_0_SHIFT 12 |
| #define ENET_EIR_RXFLUSH_1_MASK 0x2000u |
| #define ENET_EIR_RXFLUSH_1_SHIFT 13 |
| #define ENET_EIR_RXFLUSH_2_MASK 0x4000u |
| #define ENET_EIR_RXFLUSH_2_SHIFT 14 |
| #define ENET_EIR_TS_TIMER_MASK 0x8000u |
| #define ENET_EIR_TS_TIMER_SHIFT 15 |
| #define ENET_EIR_TS_AVAIL_MASK 0x10000u |
| #define ENET_EIR_TS_AVAIL_SHIFT 16 |
| #define ENET_EIR_WAKEUP_MASK 0x20000u |
| #define ENET_EIR_WAKEUP_SHIFT 17 |
| #define ENET_EIR_PLR_MASK 0x40000u |
| #define ENET_EIR_PLR_SHIFT 18 |
| #define ENET_EIR_UN_MASK 0x80000u |
| #define ENET_EIR_UN_SHIFT 19 |
| #define ENET_EIR_RL_MASK 0x100000u |
| #define ENET_EIR_RL_SHIFT 20 |
| #define ENET_EIR_LC_MASK 0x200000u |
| #define ENET_EIR_LC_SHIFT 21 |
| #define ENET_EIR_EBERR_MASK 0x400000u |
| #define ENET_EIR_EBERR_SHIFT 22 |
| #define ENET_EIR_MII_MASK 0x800000u |
| #define ENET_EIR_MII_SHIFT 23 |
| #define ENET_EIR_RXB_MASK 0x1000000u |
| #define ENET_EIR_RXB_SHIFT 24 |
| #define ENET_EIR_RXF_MASK 0x2000000u |
| #define ENET_EIR_RXF_SHIFT 25 |
| #define ENET_EIR_TXB_MASK 0x4000000u |
| #define ENET_EIR_TXB_SHIFT 26 |
| #define ENET_EIR_TXF_MASK 0x8000000u |
| #define ENET_EIR_TXF_SHIFT 27 |
| #define ENET_EIR_GRA_MASK 0x10000000u |
| #define ENET_EIR_GRA_SHIFT 28 |
| #define ENET_EIR_BABT_MASK 0x20000000u |
| #define ENET_EIR_BABT_SHIFT 29 |
| #define ENET_EIR_BABR_MASK 0x40000000u |
| #define ENET_EIR_BABR_SHIFT 30 |
| /* EIMR Bit Fields */ |
| #define ENET_EIMR_RXB1_MASK 0x1u |
| #define ENET_EIMR_RXB1_SHIFT 0 |
| #define ENET_EIMR_RXF1_MASK 0x2u |
| #define ENET_EIMR_RXF1_SHIFT 1 |
| #define ENET_EIMR_TXB1_MASK 0x4u |
| #define ENET_EIMR_TXB1_SHIFT 2 |
| #define ENET_EIMR_TXF1_MASK 0x8u |
| #define ENET_EIMR_TXF1_SHIFT 3 |
| #define ENET_EIMR_RXB2_MASK 0x10u |
| #define ENET_EIMR_RXB2_SHIFT 4 |
| #define ENET_EIMR_RXF2_MASK 0x20u |
| #define ENET_EIMR_RXF2_SHIFT 5 |
| #define ENET_EIMR_TXB2_MASK 0x40u |
| #define ENET_EIMR_TXB2_SHIFT 6 |
| #define ENET_EIMR_TXF2_MASK 0x80u |
| #define ENET_EIMR_TXF2_SHIFT 7 |
| #define ENET_EIMR_RXFLUSH_0_MASK 0x1000u |
| #define ENET_EIMR_RXFLUSH_0_SHIFT 12 |
| #define ENET_EIMR_RXFLUSH_1_MASK 0x2000u |
| #define ENET_EIMR_RXFLUSH_1_SHIFT 13 |
| #define ENET_EIMR_RXFLUSH_2_MASK 0x4000u |
| #define ENET_EIMR_RXFLUSH_2_SHIFT 14 |
| #define ENET_EIMR_TS_TIMER_MASK 0x8000u |
| #define ENET_EIMR_TS_TIMER_SHIFT 15 |
| #define ENET_EIMR_TS_AVAIL_MASK 0x10000u |
| #define ENET_EIMR_TS_AVAIL_SHIFT 16 |
| #define ENET_EIMR_WAKEUP_MASK 0x20000u |
| #define ENET_EIMR_WAKEUP_SHIFT 17 |
| #define ENET_EIMR_PLR_MASK 0x40000u |
| #define ENET_EIMR_PLR_SHIFT 18 |
| #define ENET_EIMR_UN_MASK 0x80000u |
| #define ENET_EIMR_UN_SHIFT 19 |
| #define ENET_EIMR_RL_MASK 0x100000u |
| #define ENET_EIMR_RL_SHIFT 20 |
| #define ENET_EIMR_LC_MASK 0x200000u |
| #define ENET_EIMR_LC_SHIFT 21 |
| #define ENET_EIMR_EBERR_MASK 0x400000u |
| #define ENET_EIMR_EBERR_SHIFT 22 |
| #define ENET_EIMR_MII_MASK 0x800000u |
| #define ENET_EIMR_MII_SHIFT 23 |
| #define ENET_EIMR_RXB_MASK 0x1000000u |
| #define ENET_EIMR_RXB_SHIFT 24 |
| #define ENET_EIMR_RXF_MASK 0x2000000u |
| #define ENET_EIMR_RXF_SHIFT 25 |
| #define ENET_EIMR_TXB_MASK 0x4000000u |
| #define ENET_EIMR_TXB_SHIFT 26 |
| #define ENET_EIMR_TXF_MASK 0x8000000u |
| #define ENET_EIMR_TXF_SHIFT 27 |
| #define ENET_EIMR_GRA_MASK 0x10000000u |
| #define ENET_EIMR_GRA_SHIFT 28 |
| #define ENET_EIMR_BABT_MASK 0x20000000u |
| #define ENET_EIMR_BABT_SHIFT 29 |
| #define ENET_EIMR_BABR_MASK 0x40000000u |
| #define ENET_EIMR_BABR_SHIFT 30 |
| /* RDAR Bit Fields */ |
| #define ENET_RDAR_RDAR_MASK 0x1000000u |
| #define ENET_RDAR_RDAR_SHIFT 24 |
| /* TDAR Bit Fields */ |
| #define ENET_TDAR_TDAR_MASK 0x1000000u |
| #define ENET_TDAR_TDAR_SHIFT 24 |
| /* ECR Bit Fields */ |
| #define ENET_ECR_RESET_MASK 0x1u |
| #define ENET_ECR_RESET_SHIFT 0 |
| #define ENET_ECR_ETHEREN_MASK 0x2u |
| #define ENET_ECR_ETHEREN_SHIFT 1 |
| #define ENET_ECR_MAGICEN_MASK 0x4u |
| #define ENET_ECR_MAGICEN_SHIFT 2 |
| #define ENET_ECR_SLEEP_MASK 0x8u |
| #define ENET_ECR_SLEEP_SHIFT 3 |
| #define ENET_ECR_EN1588_MASK 0x10u |
| #define ENET_ECR_EN1588_SHIFT 4 |
| #define ENET_ECR_SPEED_MASK 0x20u |
| #define ENET_ECR_SPEED_SHIFT 5 |
| #define ENET_ECR_DBGEN_MASK 0x40u |
| #define ENET_ECR_DBGEN_SHIFT 6 |
| #define ENET_ECR_DBSWP_MASK 0x100u |
| #define ENET_ECR_DBSWP_SHIFT 8 |
| #define ENET_ECR_SVLANEN_MASK 0x200u |
| #define ENET_ECR_SVLANEN_SHIFT 9 |
| #define ENET_ECR_VLANUSE2ND_MASK 0x400u |
| #define ENET_ECR_VLANUSE2ND_SHIFT 10 |
| #define ENET_ECR_SVLANDBL_MASK 0x800u |
| #define ENET_ECR_SVLANDBL_SHIFT 11 |
| /* MMFR Bit Fields */ |
| #define ENET_MMFR_DATA_MASK 0xFFFFu |
| #define ENET_MMFR_DATA_SHIFT 0 |
| #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK) |
| #define ENET_MMFR_TA_MASK 0x30000u |
| #define ENET_MMFR_TA_SHIFT 16 |
| #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK) |
| #define ENET_MMFR_RA_MASK 0x7C0000u |
| #define ENET_MMFR_RA_SHIFT 18 |
| #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK) |
| #define ENET_MMFR_PA_MASK 0xF800000u |
| #define ENET_MMFR_PA_SHIFT 23 |
| #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK) |
| #define ENET_MMFR_OP_MASK 0x30000000u |
| #define ENET_MMFR_OP_SHIFT 28 |
| #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK) |
| #define ENET_MMFR_ST_MASK 0xC0000000u |
| #define ENET_MMFR_ST_SHIFT 30 |
| #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK) |
| /* MSCR Bit Fields */ |
| #define ENET_MSCR_MII_SPEED_MASK 0x7Eu |
| #define ENET_MSCR_MII_SPEED_SHIFT 1 |
| #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK) |
| #define ENET_MSCR_DIS_PRE_MASK 0x80u |
| #define ENET_MSCR_DIS_PRE_SHIFT 7 |
| #define ENET_MSCR_HOLDTIME_MASK 0x700u |
| #define ENET_MSCR_HOLDTIME_SHIFT 8 |
| #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK) |
| /* MIBC Bit Fields */ |
| #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u |
| #define ENET_MIBC_MIB_CLEAR_SHIFT 29 |
| #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u |
| #define ENET_MIBC_MIB_IDLE_SHIFT 30 |
| #define ENET_MIBC_MIB_DIS_MASK 0x80000000u |
| #define ENET_MIBC_MIB_DIS_SHIFT 31 |
| /* RCR Bit Fields */ |
| #define ENET_RCR_LOOP_MASK 0x1u |
| #define ENET_RCR_LOOP_SHIFT 0 |
| #define ENET_RCR_DRT_MASK 0x2u |
| #define ENET_RCR_DRT_SHIFT 1 |
| #define ENET_RCR_MII_MODE_MASK 0x4u |
| #define ENET_RCR_MII_MODE_SHIFT 2 |
| #define ENET_RCR_PROM_MASK 0x8u |
| #define ENET_RCR_PROM_SHIFT 3 |
| #define ENET_RCR_BC_REJ_MASK 0x10u |
| #define ENET_RCR_BC_REJ_SHIFT 4 |
| #define ENET_RCR_FCE_MASK 0x20u |
| #define ENET_RCR_FCE_SHIFT 5 |
| #define ENET_RCR_RGMII_EN_MASK 0x40u |
| #define ENET_RCR_RGMII_EN_SHIFT 6 |
| #define ENET_RCR_RMII_MODE_MASK 0x100u |
| #define ENET_RCR_RMII_MODE_SHIFT 8 |
| #define ENET_RCR_RMII_10T_MASK 0x200u |
| #define ENET_RCR_RMII_10T_SHIFT 9 |
| #define ENET_RCR_PADEN_MASK 0x1000u |
| #define ENET_RCR_PADEN_SHIFT 12 |
| #define ENET_RCR_PAUFWD_MASK 0x2000u |
| #define ENET_RCR_PAUFWD_SHIFT 13 |
| #define ENET_RCR_CRCFWD_MASK 0x4000u |
| #define ENET_RCR_CRCFWD_SHIFT 14 |
| #define ENET_RCR_CFEN_MASK 0x8000u |
| #define ENET_RCR_CFEN_SHIFT 15 |
| #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u |
| #define ENET_RCR_MAX_FL_SHIFT 16 |
| #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK) |
| #define ENET_RCR_NLC_MASK 0x40000000u |
| #define ENET_RCR_NLC_SHIFT 30 |
| #define ENET_RCR_GRS_MASK 0x80000000u |
| #define ENET_RCR_GRS_SHIFT 31 |
| /* TCR Bit Fields */ |
| #define ENET_TCR_GTS_MASK 0x1u |
| #define ENET_TCR_GTS_SHIFT 0 |
| #define ENET_TCR_FDEN_MASK 0x4u |
| #define ENET_TCR_FDEN_SHIFT 2 |
| #define ENET_TCR_TFC_PAUSE_MASK 0x8u |
| #define ENET_TCR_TFC_PAUSE_SHIFT 3 |
| #define ENET_TCR_RFC_PAUSE_MASK 0x10u |
| #define ENET_TCR_RFC_PAUSE_SHIFT 4 |
| #define ENET_TCR_ADDSEL_MASK 0xE0u |
| #define ENET_TCR_ADDSEL_SHIFT 5 |
| #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK) |
| #define ENET_TCR_ADDINS_MASK 0x100u |
| #define ENET_TCR_ADDINS_SHIFT 8 |
| #define ENET_TCR_CRCFWD_MASK 0x200u |
| #define ENET_TCR_CRCFWD_SHIFT 9 |
| /* PALR Bit Fields */ |
| #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu |
| #define ENET_PALR_PADDR1_SHIFT 0 |
| #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK) |
| /* PAUR Bit Fields */ |
| #define ENET_PAUR_TYPE_MASK 0xFFFFu |
| #define ENET_PAUR_TYPE_SHIFT 0 |
| #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK) |
| #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u |
| #define ENET_PAUR_PADDR2_SHIFT 16 |
| #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK) |
| /* OPD Bit Fields */ |
| #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu |
| #define ENET_OPD_PAUSE_DUR_SHIFT 0 |
| #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK) |
| #define ENET_OPD_OPCODE_MASK 0xFFFF0000u |
| #define ENET_OPD_OPCODE_SHIFT 16 |
| #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK) |
| /* TXIC Bit Fields */ |
| #define ENET_TXIC_ICTT_MASK 0xFFFFu |
| #define ENET_TXIC_ICTT_SHIFT 0 |
| #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICTT_SHIFT))&ENET_TXIC_ICTT_MASK) |
| #define ENET_TXIC_ICFT_MASK 0xFF00000u |
| #define ENET_TXIC_ICFT_SHIFT 20 |
| #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICFT_SHIFT))&ENET_TXIC_ICFT_MASK) |
| #define ENET_TXIC_ICCS_MASK 0x40000000u |
| #define ENET_TXIC_ICCS_SHIFT 30 |
| #define ENET_TXIC_ICEN_MASK 0x80000000u |
| #define ENET_TXIC_ICEN_SHIFT 31 |
| /* RXIC Bit Fields */ |
| #define ENET_RXIC_ICTT_MASK 0xFFFFu |
| #define ENET_RXIC_ICTT_SHIFT 0 |
| #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICTT_SHIFT))&ENET_RXIC_ICTT_MASK) |
| #define ENET_RXIC_ICFT_MASK 0xFF00000u |
| #define ENET_RXIC_ICFT_SHIFT 20 |
| #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICFT_SHIFT))&ENET_RXIC_ICFT_MASK) |
| #define ENET_RXIC_ICCS_MASK 0x40000000u |
| #define ENET_RXIC_ICCS_SHIFT 30 |
| #define ENET_RXIC_ICEN_MASK 0x80000000u |
| #define ENET_RXIC_ICEN_SHIFT 31 |
| /* IAUR Bit Fields */ |
| #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu |
| #define ENET_IAUR_IADDR1_SHIFT 0 |
| #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK) |
| /* IALR Bit Fields */ |
| #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu |
| #define ENET_IALR_IADDR2_SHIFT 0 |
| #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK) |
| /* GAUR Bit Fields */ |
| #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu |
| #define ENET_GAUR_GADDR1_SHIFT 0 |
| #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK) |
| /* GALR Bit Fields */ |
| #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu |
| #define ENET_GALR_GADDR2_SHIFT 0 |
| #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK) |
| /* TFWR Bit Fields */ |
| #define ENET_TFWR_TFWR_MASK 0x3Fu |
| #define ENET_TFWR_TFWR_SHIFT 0 |
| #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK) |
| #define ENET_TFWR_STRFWD_MASK 0x100u |
| #define ENET_TFWR_STRFWD_SHIFT 8 |
| /* RDSR1 Bit Fields */ |
| #define ENET_RDSR1_R_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_RDSR1_R_DES_START_SHIFT 3 |
| #define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR1_R_DES_START_SHIFT))&ENET_RDSR1_R_DES_START_MASK) |
| /* TDSR1 Bit Fields */ |
| #define ENET_TDSR1_X_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_TDSR1_X_DES_START_SHIFT 3 |
| #define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK) |
| /* MRBR1 Bit Fields */ |
| #define ENET_MRBR1_R_BUF_SIZE_MASK 0x7F0u |
| #define ENET_MRBR1_R_BUF_SIZE_SHIFT 4 |
| #define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK) |
| /* RDSR2 Bit Fields */ |
| #define ENET_RDSR2_R_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_RDSR2_R_DES_START_SHIFT 3 |
| #define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR2_R_DES_START_SHIFT))&ENET_RDSR2_R_DES_START_MASK) |
| /* TDSR2 Bit Fields */ |
| #define ENET_TDSR2_X_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_TDSR2_X_DES_START_SHIFT 3 |
| #define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK) |
| /* MRBR2 Bit Fields */ |
| #define ENET_MRBR2_R_BUF_SIZE_MASK 0x7F0u |
| #define ENET_MRBR2_R_BUF_SIZE_SHIFT 4 |
| #define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK) |
| /* RDSR Bit Fields */ |
| #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_RDSR_R_DES_START_SHIFT 3 |
| #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK) |
| /* TDSR Bit Fields */ |
| #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u |
| #define ENET_TDSR_X_DES_START_SHIFT 3 |
| #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK) |
| /* MRBR Bit Fields */ |
| #define ENET_MRBR_R_BUF_SIZE_MASK 0x7F0u |
| #define ENET_MRBR_R_BUF_SIZE_SHIFT 4 |
| #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK) |
| /* RSFL Bit Fields */ |
| #define ENET_RSFL_RX_SECTION_FULL_MASK 0x3FFu |
| #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0 |
| #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK) |
| /* RSEM Bit Fields */ |
| #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0x3FFu |
| #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0 |
| #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK) |
| #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u |
| #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16 |
| #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK) |
| /* RAEM Bit Fields */ |
| #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0x3FFu |
| #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0 |
| #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK) |
| /* RAFL Bit Fields */ |
| #define ENET_RAFL_RX_ALMOST_FULL_MASK 0x3FFu |
| #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0 |
| #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK) |
| /* TSEM Bit Fields */ |
| #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0x3FFu |
| #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0 |
| #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK) |
| /* TAEM Bit Fields */ |
| #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0x3FFu |
| #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0 |
| #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK) |
| /* TAFL Bit Fields */ |
| #define ENET_TAFL_TX_ALMOST_FULL_MASK 0x3FFu |
| #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0 |
| #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK) |
| /* TIPG Bit Fields */ |
| #define ENET_TIPG_IPG_MASK 0x1Fu |
| #define ENET_TIPG_IPG_SHIFT 0 |
| #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK) |
| /* FTRL Bit Fields */ |
| #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu |
| #define ENET_FTRL_TRUNC_FL_SHIFT 0 |
| #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK) |
| /* TACC Bit Fields */ |
| #define ENET_TACC_SHIFT16_MASK 0x1u |
| #define ENET_TACC_SHIFT16_SHIFT 0 |
| #define ENET_TACC_IPCHK_MASK 0x8u |
| #define ENET_TACC_IPCHK_SHIFT 3 |
| #define ENET_TACC_PROCHK_MASK 0x10u |
| #define ENET_TACC_PROCHK_SHIFT 4 |
| /* RACC Bit Fields */ |
| #define ENET_RACC_PADREM_MASK 0x1u |
| #define ENET_RACC_PADREM_SHIFT 0 |
| #define ENET_RACC_IPDIS_MASK 0x2u |
| #define ENET_RACC_IPDIS_SHIFT 1 |
| #define ENET_RACC_PRODIS_MASK 0x4u |
| #define ENET_RACC_PRODIS_SHIFT 2 |
| #define ENET_RACC_LINEDIS_MASK 0x40u |
| #define ENET_RACC_LINEDIS_SHIFT 6 |
| #define ENET_RACC_SHIFT16_MASK 0x80u |
| #define ENET_RACC_SHIFT16_SHIFT 7 |
| /* RCMR Bit Fields */ |
| #define ENET_RCMR_CMP0_MASK 0x7u |
| #define ENET_RCMR_CMP0_SHIFT 0 |
| #define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP0_SHIFT))&ENET_RCMR_CMP0_MASK) |
| #define ENET_RCMR_CMP1_MASK 0x70u |
| #define ENET_RCMR_CMP1_SHIFT 4 |
| #define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP1_SHIFT))&ENET_RCMR_CMP1_MASK) |
| #define ENET_RCMR_CMP2_MASK 0x700u |
| #define ENET_RCMR_CMP2_SHIFT 8 |
| #define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP2_SHIFT))&ENET_RCMR_CMP2_MASK) |
| #define ENET_RCMR_CMP3_MASK 0x7000u |
| #define ENET_RCMR_CMP3_SHIFT 12 |
| #define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP3_SHIFT))&ENET_RCMR_CMP3_MASK) |
| #define ENET_RCMR_MATCHEN_MASK 0x10000u |
| #define ENET_RCMR_MATCHEN_SHIFT 16 |
| /* DMACFG Bit Fields */ |
| #define ENET_DMACFG_IDLE_SLOPE_MASK 0xFFFFu |
| #define ENET_DMACFG_IDLE_SLOPE_SHIFT 0 |
| #define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_DMACFG_IDLE_SLOPE_SHIFT))&ENET_DMACFG_IDLE_SLOPE_MASK) |
| #define ENET_DMACFG_DMA_CLASS_EN_MASK 0x10000u |
| #define ENET_DMACFG_DMA_CLASS_EN_SHIFT 16 |
| #define ENET_DMACFG_CALC_NOIPG_MASK 0x20000u |
| #define ENET_DMACFG_CALC_NOIPG_SHIFT 17 |
| /* RDAR1 Bit Fields */ |
| #define ENET_RDAR1_RDAR_MASK 0x1000000u |
| #define ENET_RDAR1_RDAR_SHIFT 24 |
| /* TDAR1 Bit Fields */ |
| #define ENET_TDAR1_TDAR_MASK 0x1000000u |
| #define ENET_TDAR1_TDAR_SHIFT 24 |
| /* RDAR2 Bit Fields */ |
| #define ENET_RDAR2_RDAR_MASK 0x1000000u |
| #define ENET_RDAR2_RDAR_SHIFT 24 |
| /* TDAR2 Bit Fields */ |
| #define ENET_TDAR2_TDAR_MASK 0x1000000u |
| #define ENET_TDAR2_TDAR_SHIFT 24 |
| /* QOS Bit Fields */ |
| #define ENET_QOS_TX_SCHEME_MASK 0x7u |
| #define ENET_QOS_TX_SCHEME_SHIFT 0 |
| #define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x))<<ENET_QOS_TX_SCHEME_SHIFT))&ENET_QOS_TX_SCHEME_MASK) |
| #define ENET_QOS_RX_FLUSH0_MASK 0x8u |
| #define ENET_QOS_RX_FLUSH0_SHIFT 3 |
| #define ENET_QOS_RX_FLUSH1_MASK 0x10u |
| #define ENET_QOS_RX_FLUSH1_SHIFT 4 |
| #define ENET_QOS_RX_FLUSH2_MASK 0x20u |
| #define ENET_QOS_RX_FLUSH2_SHIFT 5 |
| /* RMON_T_DROP Bit Fields */ |
| #define ENET_RMON_T_DROP_INCCNTF_MASK 0xFFFFu |
| #define ENET_RMON_T_DROP_INCCNTF_SHIFT 0 |
| #define ENET_RMON_T_DROP_INCCNTF(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_DROP_INCCNTF_SHIFT))&ENET_RMON_T_DROP_INCCNTF_MASK) |
| /* RMON_T_PACKETS Bit Fields */ |
| #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK) |
| /* RMON_T_BC_PKT Bit Fields */ |
| #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK) |
| /* RMON_T_MC_PKT Bit Fields */ |
| #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK) |
| /* RMON_T_CRC_ALIGN Bit Fields */ |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) |
| /* RMON_T_UNDERSIZE Bit Fields */ |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) |
| /* RMON_T_OVERSIZE Bit Fields */ |
| #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK) |
| /* RMON_T_FRAG Bit Fields */ |
| #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK) |
| /* RMON_T_JAB Bit Fields */ |
| #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK) |
| /* RMON_T_COL Bit Fields */ |
| #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_COL_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK) |
| /* RMON_T_P64 Bit Fields */ |
| #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P64_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK) |
| /* RMON_T_P65TO127 Bit Fields */ |
| #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK) |
| /* RMON_T_P128TO255 Bit Fields */ |
| #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK) |
| /* RMON_T_P256TO511 Bit Fields */ |
| #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK) |
| /* RMON_T_P512TO1023 Bit Fields */ |
| #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK) |
| /* RMON_T_P1024TO2047 Bit Fields */ |
| #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK) |
| /* RMON_T_P_GTE2048 Bit Fields */ |
| #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu |
| #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0 |
| #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK) |
| /* RMON_T_OCTETS Bit Fields */ |
| #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu |
| #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0 |
| #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK) |
| /* IEEE_T_DROP Bit Fields */ |
| #define ENET_IEEE_T_DROP_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_DROP_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DROP_COUNT_SHIFT))&ENET_IEEE_T_DROP_COUNT_MASK) |
| /* IEEE_T_FRAME_OK Bit Fields */ |
| #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK) |
| /* IEEE_T_1COL Bit Fields */ |
| #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_1COL_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK) |
| /* IEEE_T_MCOL Bit Fields */ |
| #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK) |
| /* IEEE_T_DEF Bit Fields */ |
| #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_DEF_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK) |
| /* IEEE_T_LCOL Bit Fields */ |
| #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK) |
| /* IEEE_T_EXCOL Bit Fields */ |
| #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK) |
| /* IEEE_T_MACERR Bit Fields */ |
| #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK) |
| /* IEEE_T_CSERR Bit Fields */ |
| #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK) |
| /* IEEE_T_SQE Bit Fields */ |
| #define ENET_IEEE_T_SQE_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_SQE_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK) |
| /* IEEE_T_FDXFC Bit Fields */ |
| #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK) |
| /* IEEE_T_OCTETS_OK Bit Fields */ |
| #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu |
| #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0 |
| #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK) |
| /* RMON_R_PACKETS Bit Fields */ |
| #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0 |
| #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK) |
| /* RMON_R_BC_PKT Bit Fields */ |
| #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0 |
| #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK) |
| /* RMON_R_MC_PKT Bit Fields */ |
| #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0 |
| #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK) |
| /* RMON_R_CRC_ALIGN Bit Fields */ |
| #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0 |
| #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK) |
| /* RMON_R_UNDERSIZE Bit Fields */ |
| #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0 |
| #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK) |
| /* RMON_R_OVERSIZE Bit Fields */ |
| #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0 |
| #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK) |
| /* RMON_R_FRAG Bit Fields */ |
| #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_FRAG_COUNT_SHIFT 0 |
| #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK) |
| /* RMON_R_JAB Bit Fields */ |
| #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_JAB_COUNT_SHIFT 0 |
| #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK) |
| /* RMON_R_RESVD_0 Bit Fields */ |
| /* RMON_R_P64 Bit Fields */ |
| #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P64_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK) |
| /* RMON_R_P65TO127 Bit Fields */ |
| #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK) |
| /* RMON_R_P128TO255 Bit Fields */ |
| #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK) |
| /* RMON_R_P256TO511 Bit Fields */ |
| #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK) |
| /* RMON_R_P512TO1023 Bit Fields */ |
| #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK) |
| /* RMON_R_P1024TO2047 Bit Fields */ |
| #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK) |
| /* RMON_R_P_GTE2048 Bit Fields */ |
| #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu |
| #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0 |
| #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK) |
| /* RMON_R_OCTETS Bit Fields */ |
| #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu |
| #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0 |
| #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK) |
| /* IEEE_R_DROP Bit Fields */ |
| #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_DROP_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK) |
| /* IEEE_R_FRAME_OK Bit Fields */ |
| #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK) |
| /* IEEE_R_CRC Bit Fields */ |
| #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_CRC_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK) |
| /* IEEE_R_ALIGN Bit Fields */ |
| #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK) |
| /* IEEE_R_MACERR Bit Fields */ |
| #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK) |
| /* IEEE_R_FDXFC Bit Fields */ |
| #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu |
| #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK) |
| /* IEEE_R_OCTETS_OK Bit Fields */ |
| #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu |
| #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0 |
| #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK) |
| /* ATCR Bit Fields */ |
| #define ENET_ATCR_EN_MASK 0x1u |
| #define ENET_ATCR_EN_SHIFT 0 |
| #define ENET_ATCR_OFFEN_MASK 0x4u |
| #define ENET_ATCR_OFFEN_SHIFT 2 |
| #define ENET_ATCR_OFFRST_MASK 0x8u |
| #define ENET_ATCR_OFFRST_SHIFT 3 |
| #define ENET_ATCR_PEREN_MASK 0x10u |
| #define ENET_ATCR_PEREN_SHIFT 4 |
| #define ENET_ATCR_PINPER_MASK 0x80u |
| #define ENET_ATCR_PINPER_SHIFT 7 |
| #define ENET_ATCR_RESTART_MASK 0x200u |
| #define ENET_ATCR_RESTART_SHIFT 9 |
| #define ENET_ATCR_CAPTURE_MASK 0x800u |
| #define ENET_ATCR_CAPTURE_SHIFT 11 |
| #define ENET_ATCR_SLAVE_MASK 0x2000u |
| #define ENET_ATCR_SLAVE_SHIFT 13 |
| /* ATVR Bit Fields */ |
| #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu |
| #define ENET_ATVR_ATIME_SHIFT 0 |
| #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK) |
| /* ATOFF Bit Fields */ |
| #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu |
| #define ENET_ATOFF_OFFSET_SHIFT 0 |
| #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK) |
| /* ATPER Bit Fields */ |
| #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu |
| #define ENET_ATPER_PERIOD_SHIFT 0 |
| #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK) |
| /* ATCOR Bit Fields */ |
| #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu |
| #define ENET_ATCOR_COR_SHIFT 0 |
| #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK) |
| /* ATINC Bit Fields */ |
| #define ENET_ATINC_INC_MASK 0x7Fu |
| #define ENET_ATINC_INC_SHIFT 0 |
| #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK) |
| #define ENET_ATINC_INC_CORR_MASK 0x7F00u |
| #define ENET_ATINC_INC_CORR_SHIFT 8 |
| #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK) |
| /* ATSTMP Bit Fields */ |
| #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu |
| #define ENET_ATSTMP_TIMESTAMP_SHIFT 0 |
| #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK) |
| /* TGSR Bit Fields */ |
| #define ENET_TGSR_TF0_MASK 0x1u |
| #define ENET_TGSR_TF0_SHIFT 0 |
| #define ENET_TGSR_TF1_MASK 0x2u |
| #define ENET_TGSR_TF1_SHIFT 1 |
| #define ENET_TGSR_TF2_MASK 0x4u |
| #define ENET_TGSR_TF2_SHIFT 2 |
| #define ENET_TGSR_TF3_MASK 0x8u |
| #define ENET_TGSR_TF3_SHIFT 3 |
| /* TCSR Bit Fields */ |
| #define ENET_TCSR_TDRE_MASK 0x1u |
| #define ENET_TCSR_TDRE_SHIFT 0 |
| #define ENET_TCSR_TMODE_MASK 0x3Cu |
| #define ENET_TCSR_TMODE_SHIFT 2 |
| #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK) |
| #define ENET_TCSR_TIE_MASK 0x40u |
| #define ENET_TCSR_TIE_SHIFT 6 |
| #define ENET_TCSR_TF_MASK 0x80u |
| #define ENET_TCSR_TF_SHIFT 7 |
| /* TCCR Bit Fields */ |
| #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu |
| #define ENET_TCCR_TCC_SHIFT 0 |
| #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Register_Masks */ |
| |
| /* ENET - Peripheral instance base addresses */ |
| /** Peripheral ENET1 base address */ |
| #define ENET1_BASE (0x42188000u) |
| /** Peripheral ENET1 base pointer */ |
| #define ENET1 ((ENET_Type *)ENET1_BASE) |
| #define ENET1_BASE_PTR (ENET1) |
| /** Peripheral ENET2 base address */ |
| #define ENET2_BASE (0x421B4000u) |
| /** Peripheral ENET2 base pointer */ |
| #define ENET2 ((ENET_Type *)ENET2_BASE) |
| #define ENET2_BASE_PTR (ENET2) |
| /** Array initializer of ENET peripheral base addresses */ |
| #define ENET_BASE_ADDRS { ENET1_BASE, ENET2_BASE } |
| /** Array initializer of ENET peripheral base pointers */ |
| #define ENET_BASE_PTRS { ENET1, ENET2 } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ENET - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros |
| * @{ |
| */ |
| |
| |
| /* ENET - Register instance definitions */ |
| /* ENET1 */ |
| #define ENET1_EIR ENET_EIR_REG(ENET1_BASE_PTR) |
| #define ENET1_EIMR ENET_EIMR_REG(ENET1_BASE_PTR) |
| #define ENET1_RDAR ENET_RDAR_REG(ENET1_BASE_PTR) |
| #define ENET1_TDAR ENET_TDAR_REG(ENET1_BASE_PTR) |
| #define ENET1_ECR ENET_ECR_REG(ENET1_BASE_PTR) |
| #define ENET1_MMFR ENET_MMFR_REG(ENET1_BASE_PTR) |
| #define ENET1_MSCR ENET_MSCR_REG(ENET1_BASE_PTR) |
| #define ENET1_MIBC ENET_MIBC_REG(ENET1_BASE_PTR) |
| #define ENET1_RCR ENET_RCR_REG(ENET1_BASE_PTR) |
| #define ENET1_TCR ENET_TCR_REG(ENET1_BASE_PTR) |
| #define ENET1_PALR ENET_PALR_REG(ENET1_BASE_PTR) |
| #define ENET1_PAUR ENET_PAUR_REG(ENET1_BASE_PTR) |
| #define ENET1_OPD ENET_OPD_REG(ENET1_BASE_PTR) |
| #define ENET1_TXIC0 ENET_TXIC_REG(ENET1_BASE_PTR,0) |
| #define ENET1_TXIC1 ENET_TXIC_REG(ENET1_BASE_PTR,1) |
| #define ENET1_TXIC2 ENET_TXIC_REG(ENET1_BASE_PTR,2) |
| #define ENET1_RXIC0 ENET_RXIC_REG(ENET1_BASE_PTR,0) |
| #define ENET1_RXIC1 ENET_RXIC_REG(ENET1_BASE_PTR,1) |
| #define ENET1_RXIC2 ENET_RXIC_REG(ENET1_BASE_PTR,2) |
| #define ENET1_IAUR ENET_IAUR_REG(ENET1_BASE_PTR) |
| #define ENET1_IALR ENET_IALR_REG(ENET1_BASE_PTR) |
| #define ENET1_GAUR ENET_GAUR_REG(ENET1_BASE_PTR) |
| #define ENET1_GALR ENET_GALR_REG(ENET1_BASE_PTR) |
| #define ENET1_TFWR ENET_TFWR_REG(ENET1_BASE_PTR) |
| #define ENET1_RDSR1 ENET_RDSR1_REG(ENET1_BASE_PTR) |
| #define ENET1_TDSR1 ENET_TDSR1_REG(ENET1_BASE_PTR) |
| #define ENET1_MRBR1 ENET_MRBR1_REG(ENET1_BASE_PTR) |
| #define ENET1_RDSR2 ENET_RDSR2_REG(ENET1_BASE_PTR) |
| #define ENET1_TDSR2 ENET_TDSR2_REG(ENET1_BASE_PTR) |
| #define ENET1_MRBR2 ENET_MRBR2_REG(ENET1_BASE_PTR) |
| #define ENET1_RDSR ENET_RDSR_REG(ENET1_BASE_PTR) |
| #define ENET1_TDSR ENET_TDSR_REG(ENET1_BASE_PTR) |
| #define ENET1_MRBR ENET_MRBR_REG(ENET1_BASE_PTR) |
| #define ENET1_RSFL ENET_RSFL_REG(ENET1_BASE_PTR) |
| #define ENET1_RSEM ENET_RSEM_REG(ENET1_BASE_PTR) |
| #define ENET1_RAEM ENET_RAEM_REG(ENET1_BASE_PTR) |
| #define ENET1_RAFL ENET_RAFL_REG(ENET1_BASE_PTR) |
| #define ENET1_TSEM ENET_TSEM_REG(ENET1_BASE_PTR) |
| #define ENET1_TAEM ENET_TAEM_REG(ENET1_BASE_PTR) |
| #define ENET1_TAFL ENET_TAFL_REG(ENET1_BASE_PTR) |
| #define ENET1_TIPG ENET_TIPG_REG(ENET1_BASE_PTR) |
| #define ENET1_FTRL ENET_FTRL_REG(ENET1_BASE_PTR) |
| #define ENET1_TACC ENET_TACC_REG(ENET1_BASE_PTR) |
| #define ENET1_RACC ENET_RACC_REG(ENET1_BASE_PTR) |
| #define ENET1_RCMR1 ENET_RCMR_REG(ENET1_BASE_PTR,0) |
| #define ENET1_RCMR2 ENET_RCMR_REG(ENET1_BASE_PTR,1) |
| #define ENET1_DMA1CFG ENET_DMACFG_REG(ENET1_BASE_PTR,0) |
| #define ENET1_DMA2CFG ENET_DMACFG_REG(ENET1_BASE_PTR,1) |
| #define ENET1_RDAR1 ENET_RDAR1_REG(ENET1_BASE_PTR) |
| #define ENET1_TDAR1 ENET_TDAR1_REG(ENET1_BASE_PTR) |
| #define ENET1_RDAR2 ENET_RDAR2_REG(ENET1_BASE_PTR) |
| #define ENET1_TDAR2 ENET_TDAR2_REG(ENET1_BASE_PTR) |
| #define ENET1_QOS ENET_QOS_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_COL ENET_RMON_T_COL_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P64 ENET_RMON_T_P64_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P64 ENET_RMON_R_P64_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET1_BASE_PTR) |
| #define ENET1_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET1_BASE_PTR) |
| #define ENET1_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET1_BASE_PTR) |
| #define ENET1_ATCR ENET_ATCR_REG(ENET1_BASE_PTR) |
| #define ENET1_ATVR ENET_ATVR_REG(ENET1_BASE_PTR) |
| #define ENET1_ATOFF ENET_ATOFF_REG(ENET1_BASE_PTR) |
| #define ENET1_ATPER ENET_ATPER_REG(ENET1_BASE_PTR) |
| #define ENET1_ATCOR ENET_ATCOR_REG(ENET1_BASE_PTR) |
| #define ENET1_ATINC ENET_ATINC_REG(ENET1_BASE_PTR) |
| #define ENET1_ATSTMP ENET_ATSTMP_REG(ENET1_BASE_PTR) |
| #define ENET1_TGSR ENET_TGSR_REG(ENET1_BASE_PTR) |
| #define ENET1_TCSR0 ENET_TCSR_REG(ENET1_BASE_PTR,0) |
| #define ENET1_TCCR0 ENET_TCCR_REG(ENET1_BASE_PTR,0) |
| #define ENET1_TCSR1 ENET_TCSR_REG(ENET1_BASE_PTR,1) |
| #define ENET1_TCCR1 ENET_TCCR_REG(ENET1_BASE_PTR,1) |
| #define ENET1_TCSR2 ENET_TCSR_REG(ENET1_BASE_PTR,2) |
| #define ENET1_TCCR2 ENET_TCCR_REG(ENET1_BASE_PTR,2) |
| #define ENET1_TCSR3 ENET_TCSR_REG(ENET1_BASE_PTR,3) |
| #define ENET1_TCCR3 ENET_TCCR_REG(ENET1_BASE_PTR,3) |
| /* ENET2 */ |
| #define ENET2_EIR ENET_EIR_REG(ENET2_BASE_PTR) |
| #define ENET2_EIMR ENET_EIMR_REG(ENET2_BASE_PTR) |
| #define ENET2_RDAR ENET_RDAR_REG(ENET2_BASE_PTR) |
| #define ENET2_TDAR ENET_TDAR_REG(ENET2_BASE_PTR) |
| #define ENET2_ECR ENET_ECR_REG(ENET2_BASE_PTR) |
| #define ENET2_MMFR ENET_MMFR_REG(ENET2_BASE_PTR) |
| #define ENET2_MSCR ENET_MSCR_REG(ENET2_BASE_PTR) |
| #define ENET2_MIBC ENET_MIBC_REG(ENET2_BASE_PTR) |
| #define ENET2_RCR ENET_RCR_REG(ENET2_BASE_PTR) |
| #define ENET2_TCR ENET_TCR_REG(ENET2_BASE_PTR) |
| #define ENET2_PALR ENET_PALR_REG(ENET2_BASE_PTR) |
| #define ENET2_PAUR ENET_PAUR_REG(ENET2_BASE_PTR) |
| #define ENET2_OPD ENET_OPD_REG(ENET2_BASE_PTR) |
| #define ENET2_TXIC0 ENET_TXIC_REG(ENET2_BASE_PTR,0) |
| #define ENET2_TXIC1 ENET_TXIC_REG(ENET2_BASE_PTR,1) |
| #define ENET2_TXIC2 ENET_TXIC_REG(ENET2_BASE_PTR,2) |
| #define ENET2_RXIC0 ENET_RXIC_REG(ENET2_BASE_PTR,0) |
| #define ENET2_RXIC1 ENET_RXIC_REG(ENET2_BASE_PTR,1) |
| #define ENET2_RXIC2 ENET_RXIC_REG(ENET2_BASE_PTR,2) |
| #define ENET2_IAUR ENET_IAUR_REG(ENET2_BASE_PTR) |
| #define ENET2_IALR ENET_IALR_REG(ENET2_BASE_PTR) |
| #define ENET2_GAUR ENET_GAUR_REG(ENET2_BASE_PTR) |
| #define ENET2_GALR ENET_GALR_REG(ENET2_BASE_PTR) |
| #define ENET2_TFWR ENET_TFWR_REG(ENET2_BASE_PTR) |
| #define ENET2_RDSR1 ENET_RDSR1_REG(ENET2_BASE_PTR) |
| #define ENET2_TDSR1 ENET_TDSR1_REG(ENET2_BASE_PTR) |
| #define ENET2_MRBR1 ENET_MRBR1_REG(ENET2_BASE_PTR) |
| #define ENET2_RDSR2 ENET_RDSR2_REG(ENET2_BASE_PTR) |
| #define ENET2_TDSR2 ENET_TDSR2_REG(ENET2_BASE_PTR) |
| #define ENET2_MRBR2 ENET_MRBR2_REG(ENET2_BASE_PTR) |
| #define ENET2_RDSR ENET_RDSR_REG(ENET2_BASE_PTR) |
| #define ENET2_TDSR ENET_TDSR_REG(ENET2_BASE_PTR) |
| #define ENET2_MRBR ENET_MRBR_REG(ENET2_BASE_PTR) |
| #define ENET2_RSFL ENET_RSFL_REG(ENET2_BASE_PTR) |
| #define ENET2_RSEM ENET_RSEM_REG(ENET2_BASE_PTR) |
| #define ENET2_RAEM ENET_RAEM_REG(ENET2_BASE_PTR) |
| #define ENET2_RAFL ENET_RAFL_REG(ENET2_BASE_PTR) |
| #define ENET2_TSEM ENET_TSEM_REG(ENET2_BASE_PTR) |
| #define ENET2_TAEM ENET_TAEM_REG(ENET2_BASE_PTR) |
| #define ENET2_TAFL ENET_TAFL_REG(ENET2_BASE_PTR) |
| #define ENET2_TIPG ENET_TIPG_REG(ENET2_BASE_PTR) |
| #define ENET2_FTRL ENET_FTRL_REG(ENET2_BASE_PTR) |
| #define ENET2_TACC ENET_TACC_REG(ENET2_BASE_PTR) |
| #define ENET2_RACC ENET_RACC_REG(ENET2_BASE_PTR) |
| #define ENET2_RCMR1 ENET_RCMR_REG(ENET2_BASE_PTR,0) |
| #define ENET2_RCMR2 ENET_RCMR_REG(ENET2_BASE_PTR,1) |
| #define ENET2_DMA1CFG ENET_DMACFG_REG(ENET2_BASE_PTR,0) |
| #define ENET2_DMA2CFG ENET_DMACFG_REG(ENET2_BASE_PTR,1) |
| #define ENET2_RDAR1 ENET_RDAR1_REG(ENET2_BASE_PTR) |
| #define ENET2_TDAR1 ENET_TDAR1_REG(ENET2_BASE_PTR) |
| #define ENET2_RDAR2 ENET_RDAR2_REG(ENET2_BASE_PTR) |
| #define ENET2_TDAR2 ENET_TDAR2_REG(ENET2_BASE_PTR) |
| #define ENET2_QOS ENET_QOS_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_COL ENET_RMON_T_COL_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P64 ENET_RMON_T_P64_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P64 ENET_RMON_R_P64_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET2_BASE_PTR) |
| #define ENET2_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET2_BASE_PTR) |
| #define ENET2_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET2_BASE_PTR) |
| #define ENET2_ATCR ENET_ATCR_REG(ENET2_BASE_PTR) |
| #define ENET2_ATVR ENET_ATVR_REG(ENET2_BASE_PTR) |
| #define ENET2_ATOFF ENET_ATOFF_REG(ENET2_BASE_PTR) |
| #define ENET2_ATPER ENET_ATPER_REG(ENET2_BASE_PTR) |
| #define ENET2_ATCOR ENET_ATCOR_REG(ENET2_BASE_PTR) |
| #define ENET2_ATINC ENET_ATINC_REG(ENET2_BASE_PTR) |
| #define ENET2_ATSTMP ENET_ATSTMP_REG(ENET2_BASE_PTR) |
| #define ENET2_TGSR ENET_TGSR_REG(ENET2_BASE_PTR) |
| #define ENET2_TCSR0 ENET_TCSR_REG(ENET2_BASE_PTR,0) |
| #define ENET2_TCCR0 ENET_TCCR_REG(ENET2_BASE_PTR,0) |
| #define ENET2_TCSR1 ENET_TCSR_REG(ENET2_BASE_PTR,1) |
| #define ENET2_TCCR1 ENET_TCCR_REG(ENET2_BASE_PTR,1) |
| #define ENET2_TCSR2 ENET_TCSR_REG(ENET2_BASE_PTR,2) |
| #define ENET2_TCCR2 ENET_TCCR_REG(ENET2_BASE_PTR,2) |
| #define ENET2_TCSR3 ENET_TCSR_REG(ENET2_BASE_PTR,3) |
| #define ENET2_TCCR3 ENET_TCCR_REG(ENET2_BASE_PTR,3) |
| /* ENET - Register array accessors */ |
| #define ENET1_TXIC(index) ENET_TXIC_REG(ENET1_BASE_PTR,index) |
| #define ENET2_TXIC(index) ENET_TXIC_REG(ENET2_BASE_PTR,index) |
| #define ENET1_RXIC(index) ENET_RXIC_REG(ENET1_BASE_PTR,index) |
| #define ENET2_RXIC(index) ENET_RXIC_REG(ENET2_BASE_PTR,index) |
| #define ENET1_RCMR(index) ENET_RCMR_REG(ENET1_BASE_PTR,index) |
| #define ENET2_RCMR(index) ENET_RCMR_REG(ENET2_BASE_PTR,index) |
| #define ENET1_DMACFG(index) ENET_DMACFG_REG(ENET1_BASE_PTR,index) |
| #define ENET2_DMACFG(index) ENET_DMACFG_REG(ENET2_BASE_PTR,index) |
| #define ENET1_TCSR(index) ENET_TCSR_REG(ENET1_BASE_PTR,index) |
| #define ENET2_TCSR(index) ENET_TCSR_REG(ENET2_BASE_PTR,index) |
| #define ENET1_TCCR(index) ENET_TCCR_REG(ENET1_BASE_PTR,index) |
| #define ENET2_TCCR(index) ENET_TCCR_REG(ENET2_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ENET_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- EPIT Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** EPIT - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CR; /**< Control register, offset: 0x0 */ |
| __IO uint32_t SR; /**< Status register, offset: 0x4 */ |
| __IO uint32_t LR; /**< Load register, offset: 0x8 */ |
| __IO uint32_t CMPR; /**< Compare register, offset: 0xC */ |
| __I uint32_t CNR; /**< Counter register, offset: 0x10 */ |
| } EPIT_Type, *EPIT_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- EPIT - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EPIT_Register_Accessor_Macros EPIT - Register accessor macros |
| * @{ |
| */ |
| |
| /* EPIT - Register accessors */ |
| #define EPIT_CR_REG(base) ((base)->CR) |
| #define EPIT_SR_REG(base) ((base)->SR) |
| #define EPIT_LR_REG(base) ((base)->LR) |
| #define EPIT_CMPR_REG(base) ((base)->CMPR) |
| #define EPIT_CNR_REG(base) ((base)->CNR) |
| |
| /*! |
| * @} |
| */ /* end of group EPIT_Register_Accessor_Macros */ |
| /* ---------------------------------------------------------------------------- |
| -- EPIT Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EPIT_Register_Masks EPIT Register Masks |
| * @{ |
| */ |
| |
| /* CR Bit Fields */ |
| #define EPIT_CR_EN_MASK 0x1u |
| #define EPIT_CR_EN_SHIFT 0 |
| #define EPIT_CR_ENMOD_MASK 0x2u |
| #define EPIT_CR_ENMOD_SHIFT 1 |
| #define EPIT_CR_OCIEN_MASK 0x4u |
| #define EPIT_CR_OCIEN_SHIFT 2 |
| #define EPIT_CR_RLD_MASK 0x8u |
| #define EPIT_CR_RLD_SHIFT 3 |
| #define EPIT_CR_PRESCALAR_MASK 0xFFF0u |
| #define EPIT_CR_PRESCALAR_SHIFT 4 |
| #define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x))<<EPIT_CR_PRESCALAR_SHIFT))&EPIT_CR_PRESCALAR_MASK) |
| #define EPIT_CR_SWR_MASK 0x10000u |
| #define EPIT_CR_SWR_SHIFT 16 |
| #define EPIT_CR_IOVW_MASK 0x20000u |
| #define EPIT_CR_IOVW_SHIFT 17 |
| #define EPIT_CR_DBGEN_MASK 0x40000u |
| #define EPIT_CR_DBGEN_SHIFT 18 |
| #define EPIT_CR_WAITEN_MASK 0x80000u |
| #define EPIT_CR_WAITEN_SHIFT 19 |
| #define EPIT_CR_STOPEN_MASK 0x200000u |
| #define EPIT_CR_STOPEN_SHIFT 21 |
| #define EPIT_CR_OM_MASK 0xC00000u |
| #define EPIT_CR_OM_SHIFT 22 |
| #define EPIT_CR_OM(x) (((uint32_t)(((uint32_t)(x))<<EPIT_CR_OM_SHIFT))&EPIT_CR_OM_MASK) |
| #define EPIT_CR_CLKSRC_MASK 0x3000000u |
| #define EPIT_CR_CLKSRC_SHIFT 24 |
| #define EPIT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<EPIT_CR_CLKSRC_SHIFT))&EPIT_CR_CLKSRC_MASK) |
| /* SR Bit Fields */ |
| #define EPIT_SR_OCIF_MASK 0x1u |
| #define EPIT_SR_OCIF_SHIFT 0 |
| /* LR Bit Fields */ |
| #define EPIT_LR_LOAD_MASK 0xFFFFFFFFu |
| #define EPIT_LR_LOAD_SHIFT 0 |
| #define EPIT_LR_LOAD(x) (((uint32_t)(((uint32_t)(x))<<EPIT_LR_LOAD_SHIFT))&EPIT_LR_LOAD_MASK) |
| /* CMPR Bit Fields */ |
| #define EPIT_CMPR_COMPARE_MASK 0xFFFFFFFFu |
| #define EPIT_CMPR_COMPARE_SHIFT 0 |
| #define EPIT_CMPR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<EPIT_CMPR_COMPARE_SHIFT))&EPIT_CMPR_COMPARE_MASK) |
| /* CNR Bit Fields */ |
| #define EPIT_CNR_COUNT_MASK 0xFFFFFFFFu |
| #define EPIT_CNR_COUNT_SHIFT 0 |
| #define EPIT_CNR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<EPIT_CNR_COUNT_SHIFT))&EPIT_CNR_COUNT_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group EPIT_Register_Masks */ |
| |
| /* EPIT - Peripheral instance base addresses */ |
| /** Peripheral EPIT1 base address */ |
| #define EPIT1_BASE (0x420D0000u) |
| /** Peripheral EPIT1 base pointer */ |
| #define EPIT1 ((EPIT_Type *)EPIT1_BASE) |
| #define EPIT1_BASE_PTR (EPIT1) |
| /** Peripheral EPIT2 base address */ |
| #define EPIT2_BASE (0x420D4000u) |
| /** Peripheral EPIT2 base pointer */ |
| #define EPIT2 ((EPIT_Type *)EPIT2_BASE) |
| #define EPIT2_BASE_PTR (EPIT2) |
| /** Array initializer of EPIT peripheral base addresses */ |
| #define EPIT_BASE_ADDRS { EPIT1_BASE, EPIT2_BASE } |
| /** Array initializer of EPIT peripheral base pointers */ |
| #define EPIT_BASE_PTRS { EPIT1, EPIT2 } |
| /** Interrupt vectors for the EPIT peripheral type */ |
| #define EPIT_IRQS { EPIT1_IRQn, EPIT2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- EPIT - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup EPIT_Register_Accessor_Macros EPIT - Register accessor macros |
| * @{ |
| */ |
| |
| /* EPIT - Register instance definitions */ |
| /* EPIT1 */ |
| #define EPIT1_CR EPIT_CR_REG(EPIT1_BASE_PTR) |
| #define EPIT1_SR EPIT_SR_REG(EPIT1_BASE_PTR) |
| #define EPIT1_LR EPIT_LR_REG(EPIT1_BASE_PTR) |
| #define EPIT1_CMPR EPIT_CMPR_REG(EPIT1_BASE_PTR) |
| #define EPIT1_CNR EPIT_CNR_REG(EPIT1_BASE_PTR) |
| /* EPIT2 */ |
| #define EPIT2_CR EPIT_CR_REG(EPIT2_BASE_PTR) |
| #define EPIT2_SR EPIT_SR_REG(EPIT2_BASE_PTR) |
| #define EPIT2_LR EPIT_LR_REG(EPIT2_BASE_PTR) |
| #define EPIT2_CMPR EPIT_CMPR_REG(EPIT2_BASE_PTR) |
| #define EPIT2_CNR EPIT_CNR_REG(EPIT2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group EPIT_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group EPIT_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ESAI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ESAI - Register Layout Typedef */ |
| typedef struct { |
| __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ |
| __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ |
| __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ |
| __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ |
| __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ |
| __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ |
| __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ |
| __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ |
| uint8_t RESERVED_0[96]; |
| __O uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ |
| __O uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ |
| uint8_t RESERVED_1[4]; |
| __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ |
| uint8_t RESERVED_2[28]; |
| __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ |
| __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ |
| __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ |
| __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ |
| __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ |
| __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ |
| __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ |
| __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ |
| __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ |
| __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ |
| __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ |
| } ESAI_Type, *ESAI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ESAI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ESAI_Register_Accessor_Macros ESAI - Register accessor macros |
| * @{ |
| */ |
| |
| /* ESAI - Register accessors */ |
| #define ESAI_ETDR_REG(base) ((base)->ETDR) |
| #define ESAI_ERDR_REG(base) ((base)->ERDR) |
| #define ESAI_ECR_REG(base) ((base)->ECR) |
| #define ESAI_ESR_REG(base) ((base)->ESR) |
| #define ESAI_TFCR_REG(base) ((base)->TFCR) |
| #define ESAI_TFSR_REG(base) ((base)->TFSR) |
| #define ESAI_RFCR_REG(base) ((base)->RFCR) |
| #define ESAI_RFSR_REG(base) ((base)->RFSR) |
| #define ESAI_TX_REG(base,index) ((base)->TX[index]) |
| #define ESAI_TSR_REG(base) ((base)->TSR) |
| #define ESAI_RX_REG(base,index) ((base)->RX[index]) |
| #define ESAI_SAISR_REG(base) ((base)->SAISR) |
| #define ESAI_SAICR_REG(base) ((base)->SAICR) |
| #define ESAI_TCR_REG(base) ((base)->TCR) |
| #define ESAI_TCCR_REG(base) ((base)->TCCR) |
| #define ESAI_RCR_REG(base) ((base)->RCR) |
| #define ESAI_RCCR_REG(base) ((base)->RCCR) |
| #define ESAI_TSMA_REG(base) ((base)->TSMA) |
| #define ESAI_TSMB_REG(base) ((base)->TSMB) |
| #define ESAI_RSMA_REG(base) ((base)->RSMA) |
| #define ESAI_RSMB_REG(base) ((base)->RSMB) |
| #define ESAI_PRRC_REG(base) ((base)->PRRC) |
| #define ESAI_PCRC_REG(base) ((base)->PCRC) |
| |
| /*! |
| * @} |
| */ /* end of group ESAI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ESAI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ESAI_Register_Masks ESAI Register Masks |
| * @{ |
| */ |
| |
| /* ETDR Bit Fields */ |
| #define ESAI_ETDR_ETDR_MASK 0xFFFFFFFFu |
| #define ESAI_ETDR_ETDR_SHIFT 0 |
| #define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x))<<ESAI_ETDR_ETDR_SHIFT))&ESAI_ETDR_ETDR_MASK) |
| /* ERDR Bit Fields */ |
| #define ESAI_ERDR_ERDR_MASK 0xFFFFFFFFu |
| #define ESAI_ERDR_ERDR_SHIFT 0 |
| #define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x))<<ESAI_ERDR_ERDR_SHIFT))&ESAI_ERDR_ERDR_MASK) |
| /* ECR Bit Fields */ |
| #define ESAI_ECR_ESAIEN_MASK 0x1u |
| #define ESAI_ECR_ESAIEN_SHIFT 0 |
| #define ESAI_ECR_ERST_MASK 0x2u |
| #define ESAI_ECR_ERST_SHIFT 1 |
| #define ESAI_ECR_ERO_MASK 0x10000u |
| #define ESAI_ECR_ERO_SHIFT 16 |
| #define ESAI_ECR_ERI_MASK 0x20000u |
| #define ESAI_ECR_ERI_SHIFT 17 |
| #define ESAI_ECR_ETO_MASK 0x40000u |
| #define ESAI_ECR_ETO_SHIFT 18 |
| #define ESAI_ECR_ETI_MASK 0x80000u |
| #define ESAI_ECR_ETI_SHIFT 19 |
| /* ESR Bit Fields */ |
| #define ESAI_ESR_RD_MASK 0x1u |
| #define ESAI_ESR_RD_SHIFT 0 |
| #define ESAI_ESR_RED_MASK 0x2u |
| #define ESAI_ESR_RED_SHIFT 1 |
| #define ESAI_ESR_RDE_MASK 0x4u |
| #define ESAI_ESR_RDE_SHIFT 2 |
| #define ESAI_ESR_RLS_MASK 0x8u |
| #define ESAI_ESR_RLS_SHIFT 3 |
| #define ESAI_ESR_TD_MASK 0x10u |
| #define ESAI_ESR_TD_SHIFT 4 |
| #define ESAI_ESR_TED_MASK 0x20u |
| #define ESAI_ESR_TED_SHIFT 5 |
| #define ESAI_ESR_TDE_MASK 0x40u |
| #define ESAI_ESR_TDE_SHIFT 6 |
| #define ESAI_ESR_TLS_MASK 0x80u |
| #define ESAI_ESR_TLS_SHIFT 7 |
| #define ESAI_ESR_TFE_MASK 0x100u |
| #define ESAI_ESR_TFE_SHIFT 8 |
| #define ESAI_ESR_RFF_MASK 0x200u |
| #define ESAI_ESR_RFF_SHIFT 9 |
| #define ESAI_ESR_TINIT_MASK 0x400u |
| #define ESAI_ESR_TINIT_SHIFT 10 |
| /* TFCR Bit Fields */ |
| #define ESAI_TFCR_TFE_MASK 0x1u |
| #define ESAI_TFCR_TFE_SHIFT 0 |
| #define ESAI_TFCR_TFR_MASK 0x2u |
| #define ESAI_TFCR_TFR_SHIFT 1 |
| #define ESAI_TFCR_TE0_MASK 0x4u |
| #define ESAI_TFCR_TE0_SHIFT 2 |
| #define ESAI_TFCR_TE1_MASK 0x8u |
| #define ESAI_TFCR_TE1_SHIFT 3 |
| #define ESAI_TFCR_TE2_MASK 0x10u |
| #define ESAI_TFCR_TE2_SHIFT 4 |
| #define ESAI_TFCR_TE3_MASK 0x20u |
| #define ESAI_TFCR_TE3_SHIFT 5 |
| #define ESAI_TFCR_TE4_MASK 0x40u |
| #define ESAI_TFCR_TE4_SHIFT 6 |
| #define ESAI_TFCR_TE5_MASK 0x80u |
| #define ESAI_TFCR_TE5_SHIFT 7 |
| #define ESAI_TFCR_TFWM_MASK 0xFF00u |
| #define ESAI_TFCR_TFWM_SHIFT 8 |
| #define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TFWM_SHIFT))&ESAI_TFCR_TFWM_MASK) |
| #define ESAI_TFCR_TWA_MASK 0x70000u |
| #define ESAI_TFCR_TWA_SHIFT 16 |
| #define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TFCR_TWA_SHIFT))&ESAI_TFCR_TWA_MASK) |
| #define ESAI_TFCR_TIEN_MASK 0x80000u |
| #define ESAI_TFCR_TIEN_SHIFT 19 |
| /* TFSR Bit Fields */ |
| #define ESAI_TFSR_TFCNT_MASK 0xFFu |
| #define ESAI_TFSR_TFCNT_SHIFT 0 |
| #define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_TFCNT_SHIFT))&ESAI_TFSR_TFCNT_MASK) |
| #define ESAI_TFSR_NTFI_MASK 0x700u |
| #define ESAI_TFSR_NTFI_SHIFT 8 |
| #define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFI_SHIFT))&ESAI_TFSR_NTFI_MASK) |
| #define ESAI_TFSR_NTFO_MASK 0x7000u |
| #define ESAI_TFSR_NTFO_SHIFT 12 |
| #define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TFSR_NTFO_SHIFT))&ESAI_TFSR_NTFO_MASK) |
| /* RFCR Bit Fields */ |
| #define ESAI_RFCR_RFE_MASK 0x1u |
| #define ESAI_RFCR_RFE_SHIFT 0 |
| #define ESAI_RFCR_RFR_MASK 0x2u |
| #define ESAI_RFCR_RFR_SHIFT 1 |
| #define ESAI_RFCR_RE0_MASK 0x4u |
| #define ESAI_RFCR_RE0_SHIFT 2 |
| #define ESAI_RFCR_RE1_MASK 0x8u |
| #define ESAI_RFCR_RE1_SHIFT 3 |
| #define ESAI_RFCR_RE2_MASK 0x10u |
| #define ESAI_RFCR_RE2_SHIFT 4 |
| #define ESAI_RFCR_RE3_MASK 0x20u |
| #define ESAI_RFCR_RE3_SHIFT 5 |
| #define ESAI_RFCR_RFWM_MASK 0xFF00u |
| #define ESAI_RFCR_RFWM_SHIFT 8 |
| #define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RFWM_SHIFT))&ESAI_RFCR_RFWM_MASK) |
| #define ESAI_RFCR_RWA_MASK 0x70000u |
| #define ESAI_RFCR_RWA_SHIFT 16 |
| #define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RFCR_RWA_SHIFT))&ESAI_RFCR_RWA_MASK) |
| #define ESAI_RFCR_REXT_MASK 0x80000u |
| #define ESAI_RFCR_REXT_SHIFT 19 |
| /* RFSR Bit Fields */ |
| #define ESAI_RFSR_RFCNT_MASK 0xFFu |
| #define ESAI_RFSR_RFCNT_SHIFT 0 |
| #define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_RFCNT_SHIFT))&ESAI_RFSR_RFCNT_MASK) |
| #define ESAI_RFSR_NRFO_MASK 0x300u |
| #define ESAI_RFSR_NRFO_SHIFT 8 |
| #define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFO_SHIFT))&ESAI_RFSR_NRFO_MASK) |
| #define ESAI_RFSR_NRFI_MASK 0x3000u |
| #define ESAI_RFSR_NRFI_SHIFT 12 |
| #define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RFSR_NRFI_SHIFT))&ESAI_RFSR_NRFI_MASK) |
| /* TX Bit Fields */ |
| #define ESAI_TX_TXn_MASK 0xFFFFFFu |
| #define ESAI_TX_TXn_SHIFT 0 |
| #define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TX_TXn_SHIFT))&ESAI_TX_TXn_MASK) |
| /* TSR Bit Fields */ |
| #define ESAI_TSR_TSR_MASK 0xFFFFFFu |
| #define ESAI_TSR_TSR_SHIFT 0 |
| #define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TSR_TSR_SHIFT))&ESAI_TSR_TSR_MASK) |
| /* RX Bit Fields */ |
| #define ESAI_RX_RXn_MASK 0xFFFFFFu |
| #define ESAI_RX_RXn_SHIFT 0 |
| #define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RX_RXn_SHIFT))&ESAI_RX_RXn_MASK) |
| /* SAISR Bit Fields */ |
| #define ESAI_SAISR_IF0_MASK 0x1u |
| #define ESAI_SAISR_IF0_SHIFT 0 |
| #define ESAI_SAISR_IF1_MASK 0x2u |
| #define ESAI_SAISR_IF1_SHIFT 1 |
| #define ESAI_SAISR_IF2_MASK 0x4u |
| #define ESAI_SAISR_IF2_SHIFT 2 |
| #define ESAI_SAISR_RFS_MASK 0x40u |
| #define ESAI_SAISR_RFS_SHIFT 6 |
| #define ESAI_SAISR_ROE_MASK 0x80u |
| #define ESAI_SAISR_ROE_SHIFT 7 |
| #define ESAI_SAISR_RDF_MASK 0x100u |
| #define ESAI_SAISR_RDF_SHIFT 8 |
| #define ESAI_SAISR_REDF_MASK 0x200u |
| #define ESAI_SAISR_REDF_SHIFT 9 |
| #define ESAI_SAISR_RODF_MASK 0x400u |
| #define ESAI_SAISR_RODF_SHIFT 10 |
| #define ESAI_SAISR_TFS_MASK 0x2000u |
| #define ESAI_SAISR_TFS_SHIFT 13 |
| #define ESAI_SAISR_TUE_MASK 0x4000u |
| #define ESAI_SAISR_TUE_SHIFT 14 |
| #define ESAI_SAISR_TDE_MASK 0x8000u |
| #define ESAI_SAISR_TDE_SHIFT 15 |
| #define ESAI_SAISR_TEDE_MASK 0x10000u |
| #define ESAI_SAISR_TEDE_SHIFT 16 |
| #define ESAI_SAISR_TODFE_MASK 0x20000u |
| #define ESAI_SAISR_TODFE_SHIFT 17 |
| /* SAICR Bit Fields */ |
| #define ESAI_SAICR_OF0_MASK 0x1u |
| #define ESAI_SAICR_OF0_SHIFT 0 |
| #define ESAI_SAICR_OF1_MASK 0x2u |
| #define ESAI_SAICR_OF1_SHIFT 1 |
| #define ESAI_SAICR_OF2_MASK 0x4u |
| #define ESAI_SAICR_OF2_SHIFT 2 |
| #define ESAI_SAICR_SYN_MASK 0x40u |
| #define ESAI_SAICR_SYN_SHIFT 6 |
| #define ESAI_SAICR_TEBE_MASK 0x80u |
| #define ESAI_SAICR_TEBE_SHIFT 7 |
| #define ESAI_SAICR_ALC_MASK 0x100u |
| #define ESAI_SAICR_ALC_SHIFT 8 |
| /* TCR Bit Fields */ |
| #define ESAI_TCR_TE0_MASK 0x1u |
| #define ESAI_TCR_TE0_SHIFT 0 |
| #define ESAI_TCR_TE1_MASK 0x2u |
| #define ESAI_TCR_TE1_SHIFT 1 |
| #define ESAI_TCR_TE2_MASK 0x4u |
| #define ESAI_TCR_TE2_SHIFT 2 |
| #define ESAI_TCR_TE3_MASK 0x8u |
| #define ESAI_TCR_TE3_SHIFT 3 |
| #define ESAI_TCR_TE4_MASK 0x10u |
| #define ESAI_TCR_TE4_SHIFT 4 |
| #define ESAI_TCR_TE5_MASK 0x20u |
| #define ESAI_TCR_TE5_SHIFT 5 |
| #define ESAI_TCR_TSHFD_MASK 0x40u |
| #define ESAI_TCR_TSHFD_SHIFT 6 |
| #define ESAI_TCR_TWA_MASK 0x80u |
| #define ESAI_TCR_TWA_SHIFT 7 |
| #define ESAI_TCR_TMOD_MASK 0x300u |
| #define ESAI_TCR_TMOD_SHIFT 8 |
| #define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TMOD_SHIFT))&ESAI_TCR_TMOD_MASK) |
| #define ESAI_TCR_TSWS_MASK 0x7C00u |
| #define ESAI_TCR_TSWS_SHIFT 10 |
| #define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TCR_TSWS_SHIFT))&ESAI_TCR_TSWS_MASK) |
| #define ESAI_TCR_TFSL_MASK 0x8000u |
| #define ESAI_TCR_TFSL_SHIFT 15 |
| #define ESAI_TCR_TFSR_MASK 0x10000u |
| #define ESAI_TCR_TFSR_SHIFT 16 |
| #define ESAI_TCR_PADC_MASK 0x20000u |
| #define ESAI_TCR_PADC_SHIFT 17 |
| #define ESAI_TCR_TPR_MASK 0x80000u |
| #define ESAI_TCR_TPR_SHIFT 19 |
| #define ESAI_TCR_TEIE_MASK 0x100000u |
| #define ESAI_TCR_TEIE_SHIFT 20 |
| #define ESAI_TCR_TEDIE_MASK 0x200000u |
| #define ESAI_TCR_TEDIE_SHIFT 21 |
| #define ESAI_TCR_TIE_MASK 0x400000u |
| #define ESAI_TCR_TIE_SHIFT 22 |
| #define ESAI_TCR_TLIE_MASK 0x800000u |
| #define ESAI_TCR_TLIE_SHIFT 23 |
| /* TCCR Bit Fields */ |
| #define ESAI_TCCR_TPM_MASK 0xFFu |
| #define ESAI_TCCR_TPM_SHIFT 0 |
| #define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TPM_SHIFT))&ESAI_TCCR_TPM_MASK) |
| #define ESAI_TCCR_TPSR_MASK 0x100u |
| #define ESAI_TCCR_TPSR_SHIFT 8 |
| #define ESAI_TCCR_TDC_MASK 0x3E00u |
| #define ESAI_TCCR_TDC_SHIFT 9 |
| #define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TDC_SHIFT))&ESAI_TCCR_TDC_MASK) |
| #define ESAI_TCCR_TFP_MASK 0x3C000u |
| #define ESAI_TCCR_TFP_SHIFT 14 |
| #define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TCCR_TFP_SHIFT))&ESAI_TCCR_TFP_MASK) |
| #define ESAI_TCCR_TCKP_MASK 0x40000u |
| #define ESAI_TCCR_TCKP_SHIFT 18 |
| #define ESAI_TCCR_TFSP_MASK 0x80000u |
| #define ESAI_TCCR_TFSP_SHIFT 19 |
| #define ESAI_TCCR_THCKP_MASK 0x100000u |
| #define ESAI_TCCR_THCKP_SHIFT 20 |
| #define ESAI_TCCR_TCKD_MASK 0x200000u |
| #define ESAI_TCCR_TCKD_SHIFT 21 |
| #define ESAI_TCCR_TFSD_MASK 0x400000u |
| #define ESAI_TCCR_TFSD_SHIFT 22 |
| #define ESAI_TCCR_THCKD_MASK 0x800000u |
| #define ESAI_TCCR_THCKD_SHIFT 23 |
| /* RCR Bit Fields */ |
| #define ESAI_RCR_RE0_MASK 0x1u |
| #define ESAI_RCR_RE0_SHIFT 0 |
| #define ESAI_RCR_RE1_MASK 0x2u |
| #define ESAI_RCR_RE1_SHIFT 1 |
| #define ESAI_RCR_RE2_MASK 0x4u |
| #define ESAI_RCR_RE2_SHIFT 2 |
| #define ESAI_RCR_RE3_MASK 0x8u |
| #define ESAI_RCR_RE3_SHIFT 3 |
| #define ESAI_RCR_RSHFD_MASK 0x40u |
| #define ESAI_RCR_RSHFD_SHIFT 6 |
| #define ESAI_RCR_RWA_MASK 0x80u |
| #define ESAI_RCR_RWA_SHIFT 7 |
| #define ESAI_RCR_RMOD_MASK 0x300u |
| #define ESAI_RCR_RMOD_SHIFT 8 |
| #define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RMOD_SHIFT))&ESAI_RCR_RMOD_MASK) |
| #define ESAI_RCR_RSWS_MASK 0x7C00u |
| #define ESAI_RCR_RSWS_SHIFT 10 |
| #define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RCR_RSWS_SHIFT))&ESAI_RCR_RSWS_MASK) |
| #define ESAI_RCR_RFSL_MASK 0x8000u |
| #define ESAI_RCR_RFSL_SHIFT 15 |
| #define ESAI_RCR_RFSR_MASK 0x10000u |
| #define ESAI_RCR_RFSR_SHIFT 16 |
| #define ESAI_RCR_RPR_MASK 0x80000u |
| #define ESAI_RCR_RPR_SHIFT 19 |
| #define ESAI_RCR_REIE_MASK 0x100000u |
| #define ESAI_RCR_REIE_SHIFT 20 |
| #define ESAI_RCR_REDIE_MASK 0x200000u |
| #define ESAI_RCR_REDIE_SHIFT 21 |
| #define ESAI_RCR_RIE_MASK 0x400000u |
| #define ESAI_RCR_RIE_SHIFT 22 |
| #define ESAI_RCR_RLIE_MASK 0x800000u |
| #define ESAI_RCR_RLIE_SHIFT 23 |
| /* RCCR Bit Fields */ |
| #define ESAI_RCCR_RPM_MASK 0xFFu |
| #define ESAI_RCCR_RPM_SHIFT 0 |
| #define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RPM_SHIFT))&ESAI_RCCR_RPM_MASK) |
| #define ESAI_RCCR_RPSR_MASK 0x100u |
| #define ESAI_RCCR_RPSR_SHIFT 8 |
| #define ESAI_RCCR_RDC_MASK 0x3E00u |
| #define ESAI_RCCR_RDC_SHIFT 9 |
| #define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RDC_SHIFT))&ESAI_RCCR_RDC_MASK) |
| #define ESAI_RCCR_RFP_MASK 0x3C000u |
| #define ESAI_RCCR_RFP_SHIFT 14 |
| #define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RCCR_RFP_SHIFT))&ESAI_RCCR_RFP_MASK) |
| #define ESAI_RCCR_RCKP_MASK 0x40000u |
| #define ESAI_RCCR_RCKP_SHIFT 18 |
| #define ESAI_RCCR_RFSP_MASK 0x80000u |
| #define ESAI_RCCR_RFSP_SHIFT 19 |
| #define ESAI_RCCR_RHCKP_MASK 0x100000u |
| #define ESAI_RCCR_RHCKP_SHIFT 20 |
| #define ESAI_RCCR_RCKD_MASK 0x200000u |
| #define ESAI_RCCR_RCKD_SHIFT 21 |
| #define ESAI_RCCR_RFSD_MASK 0x400000u |
| #define ESAI_RCCR_RFSD_SHIFT 22 |
| #define ESAI_RCCR_RHCKD_MASK 0x800000u |
| #define ESAI_RCCR_RHCKD_SHIFT 23 |
| /* TSMA Bit Fields */ |
| #define ESAI_TSMA_TS_MASK 0xFFFFu |
| #define ESAI_TSMA_TS_SHIFT 0 |
| #define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TSMA_TS_SHIFT))&ESAI_TSMA_TS_MASK) |
| /* TSMB Bit Fields */ |
| #define ESAI_TSMB_TS_MASK 0xFFFFu |
| #define ESAI_TSMB_TS_SHIFT 0 |
| #define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_TSMB_TS_SHIFT))&ESAI_TSMB_TS_MASK) |
| /* RSMA Bit Fields */ |
| #define ESAI_RSMA_RS_MASK 0xFFFFu |
| #define ESAI_RSMA_RS_SHIFT 0 |
| #define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RSMA_RS_SHIFT))&ESAI_RSMA_RS_MASK) |
| /* RSMB Bit Fields */ |
| #define ESAI_RSMB_RS_MASK 0xFFFFu |
| #define ESAI_RSMB_RS_SHIFT 0 |
| #define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x))<<ESAI_RSMB_RS_SHIFT))&ESAI_RSMB_RS_MASK) |
| /* PRRC Bit Fields */ |
| #define ESAI_PRRC_PDC_MASK 0xFFFu |
| #define ESAI_PRRC_PDC_SHIFT 0 |
| #define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x))<<ESAI_PRRC_PDC_SHIFT))&ESAI_PRRC_PDC_MASK) |
| /* PCRC Bit Fields */ |
| #define ESAI_PCRC_PC_MASK 0xFFFu |
| #define ESAI_PCRC_PC_SHIFT 0 |
| #define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x))<<ESAI_PCRC_PC_SHIFT))&ESAI_PCRC_PC_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group ESAI_Register_Masks */ |
| |
| /* ESAI - Peripheral instance base addresses */ |
| /** Peripheral ESAI base address */ |
| #define ESAI_BASE (0x42024000u) |
| /** Peripheral ESAI base pointer */ |
| #define ESAI ((ESAI_Type *)ESAI_BASE) |
| #define ESAI_BASE_PTR (ESAI) |
| /** Array initializer of ESAI peripheral base addresses */ |
| #define ESAI_BASE_ADDRS { ESAI_BASE } |
| /** Array initializer of ESAI peripheral base pointers */ |
| #define ESAI_BASE_PTRS { ESAI } |
| /** Interrupt vectors for the ESAI peripheral type */ |
| #define ESAI_IRQS { ESAI_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ESAI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ESAI_Register_Accessor_Macros ESAI - Register accessor macros |
| * @{ |
| */ |
| |
| /* ESAI - Register instance definitions */ |
| /* ESAI */ |
| #define ESAI_ETDR ESAI_ETDR_REG(ESAI_BASE_PTR) |
| #define ESAI_ERDR ESAI_ERDR_REG(ESAI_BASE_PTR) |
| #define ESAI_ECR ESAI_ECR_REG(ESAI_BASE_PTR) |
| #define ESAI_ESR ESAI_ESR_REG(ESAI_BASE_PTR) |
| #define ESAI_TFCR ESAI_TFCR_REG(ESAI_BASE_PTR) |
| #define ESAI_TFSR ESAI_TFSR_REG(ESAI_BASE_PTR) |
| #define ESAI_RFCR ESAI_RFCR_REG(ESAI_BASE_PTR) |
| #define ESAI_RFSR ESAI_RFSR_REG(ESAI_BASE_PTR) |
| #define ESAI_TX0 ESAI_TX_REG(ESAI_BASE_PTR,0) |
| #define ESAI_TX1 ESAI_TX_REG(ESAI_BASE_PTR,1) |
| #define ESAI_TX2 ESAI_TX_REG(ESAI_BASE_PTR,2) |
| #define ESAI_TX3 ESAI_TX_REG(ESAI_BASE_PTR,3) |
| #define ESAI_TX4 ESAI_TX_REG(ESAI_BASE_PTR,4) |
| #define ESAI_TX5 ESAI_TX_REG(ESAI_BASE_PTR,5) |
| #define ESAI_TSR ESAI_TSR_REG(ESAI_BASE_PTR) |
| #define ESAI_RX0 ESAI_RX_REG(ESAI_BASE_PTR,0) |
| #define ESAI_RX1 ESAI_RX_REG(ESAI_BASE_PTR,1) |
| #define ESAI_RX2 ESAI_RX_REG(ESAI_BASE_PTR,2) |
| #define ESAI_RX3 ESAI_RX_REG(ESAI_BASE_PTR,3) |
| #define ESAI_SAISR ESAI_SAISR_REG(ESAI_BASE_PTR) |
| #define ESAI_SAICR ESAI_SAICR_REG(ESAI_BASE_PTR) |
| #define ESAI_TCR ESAI_TCR_REG(ESAI_BASE_PTR) |
| #define ESAI_TCCR ESAI_TCCR_REG(ESAI_BASE_PTR) |
| #define ESAI_RCR ESAI_RCR_REG(ESAI_BASE_PTR) |
| #define ESAI_RCCR ESAI_RCCR_REG(ESAI_BASE_PTR) |
| #define ESAI_TSMA ESAI_TSMA_REG(ESAI_BASE_PTR) |
| #define ESAI_TSMB ESAI_TSMB_REG(ESAI_BASE_PTR) |
| #define ESAI_RSMA ESAI_RSMA_REG(ESAI_BASE_PTR) |
| #define ESAI_RSMB ESAI_RSMB_REG(ESAI_BASE_PTR) |
| #define ESAI_PRRC ESAI_PRRC_REG(ESAI_BASE_PTR) |
| #define ESAI_PCRC ESAI_PCRC_REG(ESAI_BASE_PTR) |
| /* ESAI - Register array accessors */ |
| #define ESAI_TX(index) ESAI_TX_REG(ESAI_BASE_PTR,index) |
| #define ESAI_RX(index) ESAI_RX_REG(ESAI_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group ESAI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ESAI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GIS Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GIS_Peripheral_Access_Layer GIS Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GIS - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< GIS Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< GIS Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< GIS Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< GIS Control Register, offset: 0xC */ |
| __IO uint32_t CONFIG0; /**< GIS Configuration 0 Register, offset: 0x10 */ |
| __IO uint32_t CONFIG0_SET; /**< GIS Configuration 0 Register, offset: 0x14 */ |
| __IO uint32_t CONFIG0_CLR; /**< GIS Configuration 0 Register, offset: 0x18 */ |
| __IO uint32_t CONFIG0_TOG; /**< GIS Configuration 0 Register, offset: 0x1C */ |
| __IO uint32_t CONFIG1; /**< GIS Configuration 1 Register, offset: 0x20 */ |
| __IO uint32_t CONFIG1_SET; /**< GIS Configuration 1 Register, offset: 0x24 */ |
| __IO uint32_t CONFIG1_CLR; /**< GIS Configuration 1 Register, offset: 0x28 */ |
| __IO uint32_t CONFIG1_TOG; /**< GIS Configuration 1 Register, offset: 0x2C */ |
| __IO uint32_t FB0; /**< Camera Frame Buffer Address 0 Register, offset: 0x30 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t FB1; /**< Camera Frame Buffer Address 1 Register, offset: 0x40 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t PXP_FB0; /**< PXP Frame Buffer Address 0 Register., offset: 0x50 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t PXP_FB1; /**< PXP Frame Buffer Address 1 Register, offset: 0x60 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t CH0_CTRL; /**< Control Command Channel 0 Register, offset: 0x70 */ |
| __IO uint32_t CH0_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x74 */ |
| __IO uint32_t CH0_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x78 */ |
| __IO uint32_t CH0_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x7C */ |
| __IO uint32_t CH0_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x80 */ |
| __IO uint32_t CH0_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x84 */ |
| __IO uint32_t CH0_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x88 */ |
| __IO uint32_t CH0_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x8C */ |
| __IO uint32_t CH0_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x90 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t CH0_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0xA0 */ |
| __IO uint32_t CH0_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0xA4 */ |
| __IO uint32_t CH0_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0xA8 */ |
| __IO uint32_t CH0_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0xAC */ |
| __IO uint32_t CH0_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0xB0 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t CH0_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0xC0 */ |
| __IO uint32_t CH0_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0xC4 */ |
| __IO uint32_t CH0_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0xC8 */ |
| __IO uint32_t CH0_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0xCC */ |
| __IO uint32_t CH0_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0xD0 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t CH0_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0xE0 */ |
| __IO uint32_t CH0_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0xE4 */ |
| __IO uint32_t CH0_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0xE8 */ |
| __IO uint32_t CH0_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0xEC */ |
| __IO uint32_t CH0_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0xF0 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t CH1_CTRL; /**< Control Command Channel 0 Register, offset: 0x100 */ |
| __IO uint32_t CH1_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x104 */ |
| __IO uint32_t CH1_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x108 */ |
| __IO uint32_t CH1_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x10C */ |
| __IO uint32_t CH1_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x110 */ |
| __IO uint32_t CH1_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x114 */ |
| __IO uint32_t CH1_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x118 */ |
| __IO uint32_t CH1_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x11C */ |
| __IO uint32_t CH1_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x120 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t CH1_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0x130 */ |
| __IO uint32_t CH1_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0x134 */ |
| __IO uint32_t CH1_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0x138 */ |
| __IO uint32_t CH1_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0x13C */ |
| __IO uint32_t CH1_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0x140 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t CH1_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0x150 */ |
| __IO uint32_t CH1_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0x154 */ |
| __IO uint32_t CH1_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0x158 */ |
| __IO uint32_t CH1_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0x15C */ |
| __IO uint32_t CH1_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0x160 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t CH1_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0x170 */ |
| __IO uint32_t CH1_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0x174 */ |
| __IO uint32_t CH1_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0x178 */ |
| __IO uint32_t CH1_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0x17C */ |
| __IO uint32_t CH1_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0x180 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t CH2_CTRL; /**< Control Command Channel 0 Register, offset: 0x190 */ |
| __IO uint32_t CH2_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x194 */ |
| __IO uint32_t CH2_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x198 */ |
| __IO uint32_t CH2_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x19C */ |
| __IO uint32_t CH2_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x1A0 */ |
| __IO uint32_t CH2_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x1A4 */ |
| __IO uint32_t CH2_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x1A8 */ |
| __IO uint32_t CH2_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x1AC */ |
| __IO uint32_t CH2_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x1B0 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t CH2_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0x1C0 */ |
| __IO uint32_t CH2_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0x1C4 */ |
| __IO uint32_t CH2_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0x1C8 */ |
| __IO uint32_t CH2_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0x1CC */ |
| __IO uint32_t CH2_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0x1D0 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t CH2_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0x1E0 */ |
| __IO uint32_t CH2_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0x1E4 */ |
| __IO uint32_t CH2_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0x1E8 */ |
| __IO uint32_t CH2_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0x1EC */ |
| __IO uint32_t CH2_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0x1F0 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t CH2_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0x200 */ |
| __IO uint32_t CH2_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0x204 */ |
| __IO uint32_t CH2_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0x208 */ |
| __IO uint32_t CH2_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0x20C */ |
| __IO uint32_t CH2_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0x210 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t CH3_CTRL; /**< Control Command Channel 0 Register, offset: 0x220 */ |
| __IO uint32_t CH3_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x224 */ |
| __IO uint32_t CH3_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x228 */ |
| __IO uint32_t CH3_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x22C */ |
| __IO uint32_t CH3_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x230 */ |
| __IO uint32_t CH3_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x234 */ |
| __IO uint32_t CH3_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x238 */ |
| __IO uint32_t CH3_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x23C */ |
| __IO uint32_t CH3_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x240 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t CH3_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0x250 */ |
| __IO uint32_t CH3_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0x254 */ |
| __IO uint32_t CH3_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0x258 */ |
| __IO uint32_t CH3_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0x25C */ |
| __IO uint32_t CH3_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0x260 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t CH3_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0x270 */ |
| __IO uint32_t CH3_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0x274 */ |
| __IO uint32_t CH3_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0x278 */ |
| __IO uint32_t CH3_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0x27C */ |
| __IO uint32_t CH3_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0x280 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t CH3_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0x290 */ |
| __IO uint32_t CH3_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0x294 */ |
| __IO uint32_t CH3_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0x298 */ |
| __IO uint32_t CH3_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0x29C */ |
| __IO uint32_t CH3_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0x2A0 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t CH4_CTRL; /**< Control Command Channel 0 Register, offset: 0x2B0 */ |
| __IO uint32_t CH4_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x2B4 */ |
| __IO uint32_t CH4_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x2B8 */ |
| __IO uint32_t CH4_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x2BC */ |
| __IO uint32_t CH4_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x2C0 */ |
| __IO uint32_t CH4_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x2C4 */ |
| __IO uint32_t CH4_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x2C8 */ |
| __IO uint32_t CH4_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x2CC */ |
| __IO uint32_t CH4_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x2D0 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t CH4_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0x2E0 */ |
| __IO uint32_t CH4_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0x2E4 */ |
| __IO uint32_t CH4_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0x2E8 */ |
| __IO uint32_t CH4_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0x2EC */ |
| __IO uint32_t CH4_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0x2F0 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t CH4_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0x300 */ |
| __IO uint32_t CH4_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0x304 */ |
| __IO uint32_t CH4_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0x308 */ |
| __IO uint32_t CH4_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0x30C */ |
| __IO uint32_t CH4_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0x310 */ |
| uint8_t RESERVED_22[12]; |
| __IO uint32_t CH4_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0x320 */ |
| __IO uint32_t CH4_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0x324 */ |
| __IO uint32_t CH4_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0x328 */ |
| __IO uint32_t CH4_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0x32C */ |
| __IO uint32_t CH4_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0x330 */ |
| uint8_t RESERVED_23[12]; |
| __IO uint32_t CH5_CTRL; /**< Control Command Channel 0 Register, offset: 0x340 */ |
| __IO uint32_t CH5_CTRL_SET; /**< Control Command Channel 0 Register, offset: 0x344 */ |
| __IO uint32_t CH5_CTRL_CLR; /**< Control Command Channel 0 Register, offset: 0x348 */ |
| __IO uint32_t CH5_CTRL_TOG; /**< Control Command Channel 0 Register, offset: 0x34C */ |
| __IO uint32_t CH5_ADDR0; /**< Channel 0 Command 0 Address Register., offset: 0x350 */ |
| __IO uint32_t CH5_ADDR0_SET; /**< Channel 0 Command 0 Address Register., offset: 0x354 */ |
| __IO uint32_t CH5_ADDR0_CLR; /**< Channel 0 Command 0 Address Register., offset: 0x358 */ |
| __IO uint32_t CH5_ADDR0_TOG; /**< Channel 0 Command 0 Address Register., offset: 0x35C */ |
| __IO uint32_t CH5_DATA0; /**< Channel 0 Command 0 Data Register, offset: 0x360 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t CH5_ADDR1; /**< Channel 0 Command 1 Address Register., offset: 0x370 */ |
| __IO uint32_t CH5_ADDR1_SET; /**< Channel 0 Command 1 Address Register., offset: 0x374 */ |
| __IO uint32_t CH5_ADDR1_CLR; /**< Channel 0 Command 1 Address Register., offset: 0x378 */ |
| __IO uint32_t CH5_ADDR1_TOG; /**< Channel 0 Command 1 Address Register., offset: 0x37C */ |
| __IO uint32_t CH5_DATA1; /**< Channel 0 Command 1 Data Register, offset: 0x380 */ |
| uint8_t RESERVED_25[12]; |
| __IO uint32_t CH5_ADDR2; /**< Channel 0 Command 2 Address Register., offset: 0x390 */ |
| __IO uint32_t CH5_ADDR2_SET; /**< Channel 0 Command 2 Address Register., offset: 0x394 */ |
| __IO uint32_t CH5_ADDR2_CLR; /**< Channel 0 Command 2 Address Register., offset: 0x398 */ |
| __IO uint32_t CH5_ADDR2_TOG; /**< Channel 0 Command 2 Address Register., offset: 0x39C */ |
| __IO uint32_t CH5_DATA2; /**< Channel 0 Command 2 Data Register, offset: 0x3A0 */ |
| uint8_t RESERVED_26[12]; |
| __IO uint32_t CH5_ADDR3; /**< Channel 0 Command 3 Address Register., offset: 0x3B0 */ |
| __IO uint32_t CH5_ADDR3_SET; /**< Channel 0 Command 3 Address Register., offset: 0x3B4 */ |
| __IO uint32_t CH5_ADDR3_CLR; /**< Channel 0 Command 3 Address Register., offset: 0x3B8 */ |
| __IO uint32_t CH5_ADDR3_TOG; /**< Channel 0 Command 3 Address Register., offset: 0x3BC */ |
| __IO uint32_t CH5_DATA3; /**< Channel 0 Command 3 Data Register, offset: 0x3C0 */ |
| uint8_t RESERVED_27[12]; |
| __I uint32_t DEBUG0; /**< Debug 0 Register, offset: 0x3D0 */ |
| uint8_t RESERVED_28[12]; |
| __I uint32_t DEBUG1; /**< Debug 1 Register, offset: 0x3E0 */ |
| uint8_t RESERVED_29[12]; |
| __I uint32_t VERSION; /**< Version Register, offset: 0x3F0 */ |
| } GIS_Type, *GIS_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GIS - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GIS_Register_Accessor_Macros GIS - Register accessor macros |
| * @{ |
| */ |
| |
| /* GIS - Register accessors */ |
| #define GIS_CTRL_REG(base) ((base)->CTRL) |
| #define GIS_CTRL_SET_REG(base) ((base)->CTRL_SET) |
| #define GIS_CTRL_CLR_REG(base) ((base)->CTRL_CLR) |
| #define GIS_CTRL_TOG_REG(base) ((base)->CTRL_TOG) |
| #define GIS_CONFIG0_REG(base) ((base)->CONFIG0) |
| #define GIS_CONFIG0_SET_REG(base) ((base)->CONFIG0_SET) |
| #define GIS_CONFIG0_CLR_REG(base) ((base)->CONFIG0_CLR) |
| #define GIS_CONFIG0_TOG_REG(base) ((base)->CONFIG0_TOG) |
| #define GIS_CONFIG1_REG(base) ((base)->CONFIG1) |
| #define GIS_CONFIG1_SET_REG(base) ((base)->CONFIG1_SET) |
| #define GIS_CONFIG1_CLR_REG(base) ((base)->CONFIG1_CLR) |
| #define GIS_CONFIG1_TOG_REG(base) ((base)->CONFIG1_TOG) |
| #define GIS_FB0_REG(base) ((base)->FB0) |
| #define GIS_FB1_REG(base) ((base)->FB1) |
| #define GIS_PXP_FB0_REG(base) ((base)->PXP_FB0) |
| #define GIS_PXP_FB1_REG(base) ((base)->PXP_FB1) |
| #define GIS_CH0_CTRL_REG(base) ((base)->CH0_CTRL) |
| #define GIS_CH0_CTRL_SET_REG(base) ((base)->CH0_CTRL_SET) |
| #define GIS_CH0_CTRL_CLR_REG(base) ((base)->CH0_CTRL_CLR) |
| #define GIS_CH0_CTRL_TOG_REG(base) ((base)->CH0_CTRL_TOG) |
| #define GIS_CH0_ADDR0_REG(base) ((base)->CH0_ADDR0) |
| #define GIS_CH0_ADDR0_SET_REG(base) ((base)->CH0_ADDR0_SET) |
| #define GIS_CH0_ADDR0_CLR_REG(base) ((base)->CH0_ADDR0_CLR) |
| #define GIS_CH0_ADDR0_TOG_REG(base) ((base)->CH0_ADDR0_TOG) |
| #define GIS_CH0_DATA0_REG(base) ((base)->CH0_DATA0) |
| #define GIS_CH0_ADDR1_REG(base) ((base)->CH0_ADDR1) |
| #define GIS_CH0_ADDR1_SET_REG(base) ((base)->CH0_ADDR1_SET) |
| #define GIS_CH0_ADDR1_CLR_REG(base) ((base)->CH0_ADDR1_CLR) |
| #define GIS_CH0_ADDR1_TOG_REG(base) ((base)->CH0_ADDR1_TOG) |
| #define GIS_CH0_DATA1_REG(base) ((base)->CH0_DATA1) |
| #define GIS_CH0_ADDR2_REG(base) ((base)->CH0_ADDR2) |
| #define GIS_CH0_ADDR2_SET_REG(base) ((base)->CH0_ADDR2_SET) |
| #define GIS_CH0_ADDR2_CLR_REG(base) ((base)->CH0_ADDR2_CLR) |
| #define GIS_CH0_ADDR2_TOG_REG(base) ((base)->CH0_ADDR2_TOG) |
| #define GIS_CH0_DATA2_REG(base) ((base)->CH0_DATA2) |
| #define GIS_CH0_ADDR3_REG(base) ((base)->CH0_ADDR3) |
| #define GIS_CH0_ADDR3_SET_REG(base) ((base)->CH0_ADDR3_SET) |
| #define GIS_CH0_ADDR3_CLR_REG(base) ((base)->CH0_ADDR3_CLR) |
| #define GIS_CH0_ADDR3_TOG_REG(base) ((base)->CH0_ADDR3_TOG) |
| #define GIS_CH0_DATA3_REG(base) ((base)->CH0_DATA3) |
| #define GIS_CH1_CTRL_REG(base) ((base)->CH1_CTRL) |
| #define GIS_CH1_CTRL_SET_REG(base) ((base)->CH1_CTRL_SET) |
| #define GIS_CH1_CTRL_CLR_REG(base) ((base)->CH1_CTRL_CLR) |
| #define GIS_CH1_CTRL_TOG_REG(base) ((base)->CH1_CTRL_TOG) |
| #define GIS_CH1_ADDR0_REG(base) ((base)->CH1_ADDR0) |
| #define GIS_CH1_ADDR0_SET_REG(base) ((base)->CH1_ADDR0_SET) |
| #define GIS_CH1_ADDR0_CLR_REG(base) ((base)->CH1_ADDR0_CLR) |
| #define GIS_CH1_ADDR0_TOG_REG(base) ((base)->CH1_ADDR0_TOG) |
| #define GIS_CH1_DATA0_REG(base) ((base)->CH1_DATA0) |
| #define GIS_CH1_ADDR1_REG(base) ((base)->CH1_ADDR1) |
| #define GIS_CH1_ADDR1_SET_REG(base) ((base)->CH1_ADDR1_SET) |
| #define GIS_CH1_ADDR1_CLR_REG(base) ((base)->CH1_ADDR1_CLR) |
| #define GIS_CH1_ADDR1_TOG_REG(base) ((base)->CH1_ADDR1_TOG) |
| #define GIS_CH1_DATA1_REG(base) ((base)->CH1_DATA1) |
| #define GIS_CH1_ADDR2_REG(base) ((base)->CH1_ADDR2) |
| #define GIS_CH1_ADDR2_SET_REG(base) ((base)->CH1_ADDR2_SET) |
| #define GIS_CH1_ADDR2_CLR_REG(base) ((base)->CH1_ADDR2_CLR) |
| #define GIS_CH1_ADDR2_TOG_REG(base) ((base)->CH1_ADDR2_TOG) |
| #define GIS_CH1_DATA2_REG(base) ((base)->CH1_DATA2) |
| #define GIS_CH1_ADDR3_REG(base) ((base)->CH1_ADDR3) |
| #define GIS_CH1_ADDR3_SET_REG(base) ((base)->CH1_ADDR3_SET) |
| #define GIS_CH1_ADDR3_CLR_REG(base) ((base)->CH1_ADDR3_CLR) |
| #define GIS_CH1_ADDR3_TOG_REG(base) ((base)->CH1_ADDR3_TOG) |
| #define GIS_CH1_DATA3_REG(base) ((base)->CH1_DATA3) |
| #define GIS_CH2_CTRL_REG(base) ((base)->CH2_CTRL) |
| #define GIS_CH2_CTRL_SET_REG(base) ((base)->CH2_CTRL_SET) |
| #define GIS_CH2_CTRL_CLR_REG(base) ((base)->CH2_CTRL_CLR) |
| #define GIS_CH2_CTRL_TOG_REG(base) ((base)->CH2_CTRL_TOG) |
| #define GIS_CH2_ADDR0_REG(base) ((base)->CH2_ADDR0) |
| #define GIS_CH2_ADDR0_SET_REG(base) ((base)->CH2_ADDR0_SET) |
| #define GIS_CH2_ADDR0_CLR_REG(base) ((base)->CH2_ADDR0_CLR) |
| #define GIS_CH2_ADDR0_TOG_REG(base) ((base)->CH2_ADDR0_TOG) |
| #define GIS_CH2_DATA0_REG(base) ((base)->CH2_DATA0) |
| #define GIS_CH2_ADDR1_REG(base) ((base)->CH2_ADDR1) |
| #define GIS_CH2_ADDR1_SET_REG(base) ((base)->CH2_ADDR1_SET) |
| #define GIS_CH2_ADDR1_CLR_REG(base) ((base)->CH2_ADDR1_CLR) |
| #define GIS_CH2_ADDR1_TOG_REG(base) ((base)->CH2_ADDR1_TOG) |
| #define GIS_CH2_DATA1_REG(base) ((base)->CH2_DATA1) |
| #define GIS_CH2_ADDR2_REG(base) ((base)->CH2_ADDR2) |
| #define GIS_CH2_ADDR2_SET_REG(base) ((base)->CH2_ADDR2_SET) |
| #define GIS_CH2_ADDR2_CLR_REG(base) ((base)->CH2_ADDR2_CLR) |
| #define GIS_CH2_ADDR2_TOG_REG(base) ((base)->CH2_ADDR2_TOG) |
| #define GIS_CH2_DATA2_REG(base) ((base)->CH2_DATA2) |
| #define GIS_CH2_ADDR3_REG(base) ((base)->CH2_ADDR3) |
| #define GIS_CH2_ADDR3_SET_REG(base) ((base)->CH2_ADDR3_SET) |
| #define GIS_CH2_ADDR3_CLR_REG(base) ((base)->CH2_ADDR3_CLR) |
| #define GIS_CH2_ADDR3_TOG_REG(base) ((base)->CH2_ADDR3_TOG) |
| #define GIS_CH2_DATA3_REG(base) ((base)->CH2_DATA3) |
| #define GIS_CH3_CTRL_REG(base) ((base)->CH3_CTRL) |
| #define GIS_CH3_CTRL_SET_REG(base) ((base)->CH3_CTRL_SET) |
| #define GIS_CH3_CTRL_CLR_REG(base) ((base)->CH3_CTRL_CLR) |
| #define GIS_CH3_CTRL_TOG_REG(base) ((base)->CH3_CTRL_TOG) |
| #define GIS_CH3_ADDR0_REG(base) ((base)->CH3_ADDR0) |
| #define GIS_CH3_ADDR0_SET_REG(base) ((base)->CH3_ADDR0_SET) |
| #define GIS_CH3_ADDR0_CLR_REG(base) ((base)->CH3_ADDR0_CLR) |
| #define GIS_CH3_ADDR0_TOG_REG(base) ((base)->CH3_ADDR0_TOG) |
| #define GIS_CH3_DATA0_REG(base) ((base)->CH3_DATA0) |
| #define GIS_CH3_ADDR1_REG(base) ((base)->CH3_ADDR1) |
| #define GIS_CH3_ADDR1_SET_REG(base) ((base)->CH3_ADDR1_SET) |
| #define GIS_CH3_ADDR1_CLR_REG(base) ((base)->CH3_ADDR1_CLR) |
| #define GIS_CH3_ADDR1_TOG_REG(base) ((base)->CH3_ADDR1_TOG) |
| #define GIS_CH3_DATA1_REG(base) ((base)->CH3_DATA1) |
| #define GIS_CH3_ADDR2_REG(base) ((base)->CH3_ADDR2) |
| #define GIS_CH3_ADDR2_SET_REG(base) ((base)->CH3_ADDR2_SET) |
| #define GIS_CH3_ADDR2_CLR_REG(base) ((base)->CH3_ADDR2_CLR) |
| #define GIS_CH3_ADDR2_TOG_REG(base) ((base)->CH3_ADDR2_TOG) |
| #define GIS_CH3_DATA2_REG(base) ((base)->CH3_DATA2) |
| #define GIS_CH3_ADDR3_REG(base) ((base)->CH3_ADDR3) |
| #define GIS_CH3_ADDR3_SET_REG(base) ((base)->CH3_ADDR3_SET) |
| #define GIS_CH3_ADDR3_CLR_REG(base) ((base)->CH3_ADDR3_CLR) |
| #define GIS_CH3_ADDR3_TOG_REG(base) ((base)->CH3_ADDR3_TOG) |
| #define GIS_CH3_DATA3_REG(base) ((base)->CH3_DATA3) |
| #define GIS_CH4_CTRL_REG(base) ((base)->CH4_CTRL) |
| #define GIS_CH4_CTRL_SET_REG(base) ((base)->CH4_CTRL_SET) |
| #define GIS_CH4_CTRL_CLR_REG(base) ((base)->CH4_CTRL_CLR) |
| #define GIS_CH4_CTRL_TOG_REG(base) ((base)->CH4_CTRL_TOG) |
| #define GIS_CH4_ADDR0_REG(base) ((base)->CH4_ADDR0) |
| #define GIS_CH4_ADDR0_SET_REG(base) ((base)->CH4_ADDR0_SET) |
| #define GIS_CH4_ADDR0_CLR_REG(base) ((base)->CH4_ADDR0_CLR) |
| #define GIS_CH4_ADDR0_TOG_REG(base) ((base)->CH4_ADDR0_TOG) |
| #define GIS_CH4_DATA0_REG(base) ((base)->CH4_DATA0) |
| #define GIS_CH4_ADDR1_REG(base) ((base)->CH4_ADDR1) |
| #define GIS_CH4_ADDR1_SET_REG(base) ((base)->CH4_ADDR1_SET) |
| #define GIS_CH4_ADDR1_CLR_REG(base) ((base)->CH4_ADDR1_CLR) |
| #define GIS_CH4_ADDR1_TOG_REG(base) ((base)->CH4_ADDR1_TOG) |
| #define GIS_CH4_DATA1_REG(base) ((base)->CH4_DATA1) |
| #define GIS_CH4_ADDR2_REG(base) ((base)->CH4_ADDR2) |
| #define GIS_CH4_ADDR2_SET_REG(base) ((base)->CH4_ADDR2_SET) |
| #define GIS_CH4_ADDR2_CLR_REG(base) ((base)->CH4_ADDR2_CLR) |
| #define GIS_CH4_ADDR2_TOG_REG(base) ((base)->CH4_ADDR2_TOG) |
| #define GIS_CH4_DATA2_REG(base) ((base)->CH4_DATA2) |
| #define GIS_CH4_ADDR3_REG(base) ((base)->CH4_ADDR3) |
| #define GIS_CH4_ADDR3_SET_REG(base) ((base)->CH4_ADDR3_SET) |
| #define GIS_CH4_ADDR3_CLR_REG(base) ((base)->CH4_ADDR3_CLR) |
| #define GIS_CH4_ADDR3_TOG_REG(base) ((base)->CH4_ADDR3_TOG) |
| #define GIS_CH4_DATA3_REG(base) ((base)->CH4_DATA3) |
| #define GIS_CH5_CTRL_REG(base) ((base)->CH5_CTRL) |
| #define GIS_CH5_CTRL_SET_REG(base) ((base)->CH5_CTRL_SET) |
| #define GIS_CH5_CTRL_CLR_REG(base) ((base)->CH5_CTRL_CLR) |
| #define GIS_CH5_CTRL_TOG_REG(base) ((base)->CH5_CTRL_TOG) |
| #define GIS_CH5_ADDR0_REG(base) ((base)->CH5_ADDR0) |
| #define GIS_CH5_ADDR0_SET_REG(base) ((base)->CH5_ADDR0_SET) |
| #define GIS_CH5_ADDR0_CLR_REG(base) ((base)->CH5_ADDR0_CLR) |
| #define GIS_CH5_ADDR0_TOG_REG(base) ((base)->CH5_ADDR0_TOG) |
| #define GIS_CH5_DATA0_REG(base) ((base)->CH5_DATA0) |
| #define GIS_CH5_ADDR1_REG(base) ((base)->CH5_ADDR1) |
| #define GIS_CH5_ADDR1_SET_REG(base) ((base)->CH5_ADDR1_SET) |
| #define GIS_CH5_ADDR1_CLR_REG(base) ((base)->CH5_ADDR1_CLR) |
| #define GIS_CH5_ADDR1_TOG_REG(base) ((base)->CH5_ADDR1_TOG) |
| #define GIS_CH5_DATA1_REG(base) ((base)->CH5_DATA1) |
| #define GIS_CH5_ADDR2_REG(base) ((base)->CH5_ADDR2) |
| #define GIS_CH5_ADDR2_SET_REG(base) ((base)->CH5_ADDR2_SET) |
| #define GIS_CH5_ADDR2_CLR_REG(base) ((base)->CH5_ADDR2_CLR) |
| #define GIS_CH5_ADDR2_TOG_REG(base) ((base)->CH5_ADDR2_TOG) |
| #define GIS_CH5_DATA2_REG(base) ((base)->CH5_DATA2) |
| #define GIS_CH5_ADDR3_REG(base) ((base)->CH5_ADDR3) |
| #define GIS_CH5_ADDR3_SET_REG(base) ((base)->CH5_ADDR3_SET) |
| #define GIS_CH5_ADDR3_CLR_REG(base) ((base)->CH5_ADDR3_CLR) |
| #define GIS_CH5_ADDR3_TOG_REG(base) ((base)->CH5_ADDR3_TOG) |
| #define GIS_CH5_DATA3_REG(base) ((base)->CH5_DATA3) |
| #define GIS_DEBUG0_REG(base) ((base)->DEBUG0) |
| #define GIS_DEBUG1_REG(base) ((base)->DEBUG1) |
| #define GIS_VERSION_REG(base) ((base)->VERSION) |
| |
| /*! |
| * @} |
| */ /* end of group GIS_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GIS Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GIS_Register_Masks GIS Register Masks |
| * @{ |
| */ |
| |
| /* CTRL Bit Fields */ |
| #define GIS_CTRL_ENABLE_MASK 0x1u |
| #define GIS_CTRL_ENABLE_SHIFT 0 |
| #define GIS_CTRL_FB_START_MASK 0x2u |
| #define GIS_CTRL_FB_START_SHIFT 1 |
| #define GIS_CTRL_LCDIF_SEL_MASK 0x4u |
| #define GIS_CTRL_LCDIF_SEL_SHIFT 2 |
| #define GIS_CTRL_CSI_SEL_MASK 0x8u |
| #define GIS_CTRL_CSI_SEL_SHIFT 3 |
| #define GIS_CTRL_CSI0_IRQ_POLARITY_MASK 0x10u |
| #define GIS_CTRL_CSI0_IRQ_POLARITY_SHIFT 4 |
| #define GIS_CTRL_CSI1_IRQ_POLARITY_MASK 0x20u |
| #define GIS_CTRL_CSI1_IRQ_POLARITY_SHIFT 5 |
| #define GIS_CTRL_PXP_IRQ_POLARITY_MASK 0x40u |
| #define GIS_CTRL_PXP_IRQ_POLARITY_SHIFT 6 |
| #define GIS_CTRL_LCDIF0_IRQ_POLARITY_MASK 0x80u |
| #define GIS_CTRL_LCDIF0_IRQ_POLARITY_SHIFT 7 |
| #define GIS_CTRL_LCDIF1_IRQ_POLARITY_MASK 0x100u |
| #define GIS_CTRL_LCDIF1_IRQ_POLARITY_SHIFT 8 |
| #define GIS_CTRL_CLKGATE_MASK 0x40000000u |
| #define GIS_CTRL_CLKGATE_SHIFT 30 |
| #define GIS_CTRL_SFTRST_MASK 0x80000000u |
| #define GIS_CTRL_SFTRST_SHIFT 31 |
| /* CTRL_SET Bit Fields */ |
| #define GIS_CTRL_SET_ENABLE_MASK 0x1u |
| #define GIS_CTRL_SET_ENABLE_SHIFT 0 |
| #define GIS_CTRL_SET_FB_START_MASK 0x2u |
| #define GIS_CTRL_SET_FB_START_SHIFT 1 |
| #define GIS_CTRL_SET_LCDIF_SEL_MASK 0x4u |
| #define GIS_CTRL_SET_LCDIF_SEL_SHIFT 2 |
| #define GIS_CTRL_SET_CSI_SEL_MASK 0x8u |
| #define GIS_CTRL_SET_CSI_SEL_SHIFT 3 |
| #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_MASK 0x10u |
| #define GIS_CTRL_SET_CSI0_IRQ_POLARITY_SHIFT 4 |
| #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_MASK 0x20u |
| #define GIS_CTRL_SET_CSI1_IRQ_POLARITY_SHIFT 5 |
| #define GIS_CTRL_SET_PXP_IRQ_POLARITY_MASK 0x40u |
| #define GIS_CTRL_SET_PXP_IRQ_POLARITY_SHIFT 6 |
| #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_MASK 0x80u |
| #define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_SHIFT 7 |
| #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_MASK 0x100u |
| #define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_SHIFT 8 |
| #define GIS_CTRL_SET_CLKGATE_MASK 0x40000000u |
| #define GIS_CTRL_SET_CLKGATE_SHIFT 30 |
| #define GIS_CTRL_SET_SFTRST_MASK 0x80000000u |
| #define GIS_CTRL_SET_SFTRST_SHIFT 31 |
| /* CTRL_CLR Bit Fields */ |
| #define GIS_CTRL_CLR_ENABLE_MASK 0x1u |
| #define GIS_CTRL_CLR_ENABLE_SHIFT 0 |
| #define GIS_CTRL_CLR_FB_START_MASK 0x2u |
| #define GIS_CTRL_CLR_FB_START_SHIFT 1 |
| #define GIS_CTRL_CLR_LCDIF_SEL_MASK 0x4u |
| #define GIS_CTRL_CLR_LCDIF_SEL_SHIFT 2 |
| #define GIS_CTRL_CLR_CSI_SEL_MASK 0x8u |
| #define GIS_CTRL_CLR_CSI_SEL_SHIFT 3 |
| #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_MASK 0x10u |
| #define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_SHIFT 4 |
| #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_MASK 0x20u |
| #define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_SHIFT 5 |
| #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_MASK 0x40u |
| #define GIS_CTRL_CLR_PXP_IRQ_POLARITY_SHIFT 6 |
| #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_MASK 0x80u |
| #define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_SHIFT 7 |
| #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_MASK 0x100u |
| #define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_SHIFT 8 |
| #define GIS_CTRL_CLR_CLKGATE_MASK 0x40000000u |
| #define GIS_CTRL_CLR_CLKGATE_SHIFT 30 |
| #define GIS_CTRL_CLR_SFTRST_MASK 0x80000000u |
| #define GIS_CTRL_CLR_SFTRST_SHIFT 31 |
| /* CTRL_TOG Bit Fields */ |
| #define GIS_CTRL_TOG_ENABLE_MASK 0x1u |
| #define GIS_CTRL_TOG_ENABLE_SHIFT 0 |
| #define GIS_CTRL_TOG_FB_START_MASK 0x2u |
| #define GIS_CTRL_TOG_FB_START_SHIFT 1 |
| #define GIS_CTRL_TOG_LCDIF_SEL_MASK 0x4u |
| #define GIS_CTRL_TOG_LCDIF_SEL_SHIFT 2 |
| #define GIS_CTRL_TOG_CSI_SEL_MASK 0x8u |
| #define GIS_CTRL_TOG_CSI_SEL_SHIFT 3 |
| #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_MASK 0x10u |
| #define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_SHIFT 4 |
| #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_MASK 0x20u |
| #define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_SHIFT 5 |
| #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_MASK 0x40u |
| #define GIS_CTRL_TOG_PXP_IRQ_POLARITY_SHIFT 6 |
| #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_MASK 0x80u |
| #define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_SHIFT 7 |
| #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_MASK 0x100u |
| #define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_SHIFT 8 |
| #define GIS_CTRL_TOG_CLKGATE_MASK 0x40000000u |
| #define GIS_CTRL_TOG_CLKGATE_SHIFT 30 |
| #define GIS_CTRL_TOG_SFTRST_MASK 0x80000000u |
| #define GIS_CTRL_TOG_SFTRST_SHIFT 31 |
| /* CONFIG0 Bit Fields */ |
| #define GIS_CONFIG0_CH0_MAPPING_MASK 0x7u |
| #define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 |
| #define GIS_CONFIG0_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH0_MAPPING_SHIFT))&GIS_CONFIG0_CH0_MAPPING_MASK) |
| #define GIS_CONFIG0_CH0_NUM_MASK 0x38u |
| #define GIS_CONFIG0_CH0_NUM_SHIFT 3 |
| #define GIS_CONFIG0_CH0_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH0_NUM_SHIFT))&GIS_CONFIG0_CH0_NUM_MASK) |
| #define GIS_CONFIG0_CH1_MAPPING_MASK 0x700u |
| #define GIS_CONFIG0_CH1_MAPPING_SHIFT 8 |
| #define GIS_CONFIG0_CH1_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH1_MAPPING_SHIFT))&GIS_CONFIG0_CH1_MAPPING_MASK) |
| #define GIS_CONFIG0_CH1_NUM_MASK 0x3800u |
| #define GIS_CONFIG0_CH1_NUM_SHIFT 11 |
| #define GIS_CONFIG0_CH1_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH1_NUM_SHIFT))&GIS_CONFIG0_CH1_NUM_MASK) |
| #define GIS_CONFIG0_CH2_MAPPING_MASK 0x70000u |
| #define GIS_CONFIG0_CH2_MAPPING_SHIFT 16 |
| #define GIS_CONFIG0_CH2_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH2_MAPPING_SHIFT))&GIS_CONFIG0_CH2_MAPPING_MASK) |
| #define GIS_CONFIG0_CH2_NUM_MASK 0x380000u |
| #define GIS_CONFIG0_CH2_NUM_SHIFT 19 |
| #define GIS_CONFIG0_CH2_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH2_NUM_SHIFT))&GIS_CONFIG0_CH2_NUM_MASK) |
| #define GIS_CONFIG0_CH3_MAPPING_MASK 0x7000000u |
| #define GIS_CONFIG0_CH3_MAPPING_SHIFT 24 |
| #define GIS_CONFIG0_CH3_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH3_MAPPING_SHIFT))&GIS_CONFIG0_CH3_MAPPING_MASK) |
| #define GIS_CONFIG0_CH3_NUM_MASK 0x38000000u |
| #define GIS_CONFIG0_CH3_NUM_SHIFT 27 |
| #define GIS_CONFIG0_CH3_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CH3_NUM_SHIFT))&GIS_CONFIG0_CH3_NUM_MASK) |
| /* CONFIG0_SET Bit Fields */ |
| #define GIS_CONFIG0_SET_CH0_MAPPING_MASK 0x7u |
| #define GIS_CONFIG0_SET_CH0_MAPPING_SHIFT 0 |
| #define GIS_CONFIG0_SET_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH0_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH0_MAPPING_MASK) |
| #define GIS_CONFIG0_SET_CH0_NUM_MASK 0x38u |
| #define GIS_CONFIG0_SET_CH0_NUM_SHIFT 3 |
| #define GIS_CONFIG0_SET_CH0_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH0_NUM_SHIFT))&GIS_CONFIG0_SET_CH0_NUM_MASK) |
| #define GIS_CONFIG0_SET_CH1_MAPPING_MASK 0x700u |
| #define GIS_CONFIG0_SET_CH1_MAPPING_SHIFT 8 |
| #define GIS_CONFIG0_SET_CH1_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH1_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH1_MAPPING_MASK) |
| #define GIS_CONFIG0_SET_CH1_NUM_MASK 0x3800u |
| #define GIS_CONFIG0_SET_CH1_NUM_SHIFT 11 |
| #define GIS_CONFIG0_SET_CH1_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH1_NUM_SHIFT))&GIS_CONFIG0_SET_CH1_NUM_MASK) |
| #define GIS_CONFIG0_SET_CH2_MAPPING_MASK 0x70000u |
| #define GIS_CONFIG0_SET_CH2_MAPPING_SHIFT 16 |
| #define GIS_CONFIG0_SET_CH2_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH2_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH2_MAPPING_MASK) |
| #define GIS_CONFIG0_SET_CH2_NUM_MASK 0x380000u |
| #define GIS_CONFIG0_SET_CH2_NUM_SHIFT 19 |
| #define GIS_CONFIG0_SET_CH2_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH2_NUM_SHIFT))&GIS_CONFIG0_SET_CH2_NUM_MASK) |
| #define GIS_CONFIG0_SET_CH3_MAPPING_MASK 0x7000000u |
| #define GIS_CONFIG0_SET_CH3_MAPPING_SHIFT 24 |
| #define GIS_CONFIG0_SET_CH3_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH3_MAPPING_SHIFT))&GIS_CONFIG0_SET_CH3_MAPPING_MASK) |
| #define GIS_CONFIG0_SET_CH3_NUM_MASK 0x38000000u |
| #define GIS_CONFIG0_SET_CH3_NUM_SHIFT 27 |
| #define GIS_CONFIG0_SET_CH3_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_SET_CH3_NUM_SHIFT))&GIS_CONFIG0_SET_CH3_NUM_MASK) |
| /* CONFIG0_CLR Bit Fields */ |
| #define GIS_CONFIG0_CLR_CH0_MAPPING_MASK 0x7u |
| #define GIS_CONFIG0_CLR_CH0_MAPPING_SHIFT 0 |
| #define GIS_CONFIG0_CLR_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH0_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH0_MAPPING_MASK) |
| #define GIS_CONFIG0_CLR_CH0_NUM_MASK 0x38u |
| #define GIS_CONFIG0_CLR_CH0_NUM_SHIFT 3 |
| #define GIS_CONFIG0_CLR_CH0_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH0_NUM_SHIFT))&GIS_CONFIG0_CLR_CH0_NUM_MASK) |
| #define GIS_CONFIG0_CLR_CH1_MAPPING_MASK 0x700u |
| #define GIS_CONFIG0_CLR_CH1_MAPPING_SHIFT 8 |
| #define GIS_CONFIG0_CLR_CH1_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH1_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH1_MAPPING_MASK) |
| #define GIS_CONFIG0_CLR_CH1_NUM_MASK 0x3800u |
| #define GIS_CONFIG0_CLR_CH1_NUM_SHIFT 11 |
| #define GIS_CONFIG0_CLR_CH1_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH1_NUM_SHIFT))&GIS_CONFIG0_CLR_CH1_NUM_MASK) |
| #define GIS_CONFIG0_CLR_CH2_MAPPING_MASK 0x70000u |
| #define GIS_CONFIG0_CLR_CH2_MAPPING_SHIFT 16 |
| #define GIS_CONFIG0_CLR_CH2_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH2_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH2_MAPPING_MASK) |
| #define GIS_CONFIG0_CLR_CH2_NUM_MASK 0x380000u |
| #define GIS_CONFIG0_CLR_CH2_NUM_SHIFT 19 |
| #define GIS_CONFIG0_CLR_CH2_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH2_NUM_SHIFT))&GIS_CONFIG0_CLR_CH2_NUM_MASK) |
| #define GIS_CONFIG0_CLR_CH3_MAPPING_MASK 0x7000000u |
| #define GIS_CONFIG0_CLR_CH3_MAPPING_SHIFT 24 |
| #define GIS_CONFIG0_CLR_CH3_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH3_MAPPING_SHIFT))&GIS_CONFIG0_CLR_CH3_MAPPING_MASK) |
| #define GIS_CONFIG0_CLR_CH3_NUM_MASK 0x38000000u |
| #define GIS_CONFIG0_CLR_CH3_NUM_SHIFT 27 |
| #define GIS_CONFIG0_CLR_CH3_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_CLR_CH3_NUM_SHIFT))&GIS_CONFIG0_CLR_CH3_NUM_MASK) |
| /* CONFIG0_TOG Bit Fields */ |
| #define GIS_CONFIG0_TOG_CH0_MAPPING_MASK 0x7u |
| #define GIS_CONFIG0_TOG_CH0_MAPPING_SHIFT 0 |
| #define GIS_CONFIG0_TOG_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH0_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH0_MAPPING_MASK) |
| #define GIS_CONFIG0_TOG_CH0_NUM_MASK 0x38u |
| #define GIS_CONFIG0_TOG_CH0_NUM_SHIFT 3 |
| #define GIS_CONFIG0_TOG_CH0_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH0_NUM_SHIFT))&GIS_CONFIG0_TOG_CH0_NUM_MASK) |
| #define GIS_CONFIG0_TOG_CH1_MAPPING_MASK 0x700u |
| #define GIS_CONFIG0_TOG_CH1_MAPPING_SHIFT 8 |
| #define GIS_CONFIG0_TOG_CH1_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH1_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH1_MAPPING_MASK) |
| #define GIS_CONFIG0_TOG_CH1_NUM_MASK 0x3800u |
| #define GIS_CONFIG0_TOG_CH1_NUM_SHIFT 11 |
| #define GIS_CONFIG0_TOG_CH1_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH1_NUM_SHIFT))&GIS_CONFIG0_TOG_CH1_NUM_MASK) |
| #define GIS_CONFIG0_TOG_CH2_MAPPING_MASK 0x70000u |
| #define GIS_CONFIG0_TOG_CH2_MAPPING_SHIFT 16 |
| #define GIS_CONFIG0_TOG_CH2_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH2_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH2_MAPPING_MASK) |
| #define GIS_CONFIG0_TOG_CH2_NUM_MASK 0x380000u |
| #define GIS_CONFIG0_TOG_CH2_NUM_SHIFT 19 |
| #define GIS_CONFIG0_TOG_CH2_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH2_NUM_SHIFT))&GIS_CONFIG0_TOG_CH2_NUM_MASK) |
| #define GIS_CONFIG0_TOG_CH3_MAPPING_MASK 0x7000000u |
| #define GIS_CONFIG0_TOG_CH3_MAPPING_SHIFT 24 |
| #define GIS_CONFIG0_TOG_CH3_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH3_MAPPING_SHIFT))&GIS_CONFIG0_TOG_CH3_MAPPING_MASK) |
| #define GIS_CONFIG0_TOG_CH3_NUM_MASK 0x38000000u |
| #define GIS_CONFIG0_TOG_CH3_NUM_SHIFT 27 |
| #define GIS_CONFIG0_TOG_CH3_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG0_TOG_CH3_NUM_SHIFT))&GIS_CONFIG0_TOG_CH3_NUM_MASK) |
| /* CONFIG1 Bit Fields */ |
| #define GIS_CONFIG1_CH4_MAPPING_MASK 0x7u |
| #define GIS_CONFIG1_CH4_MAPPING_SHIFT 0 |
| #define GIS_CONFIG1_CH4_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH4_MAPPING_SHIFT))&GIS_CONFIG1_CH4_MAPPING_MASK) |
| #define GIS_CONFIG1_CH4_NUM_MASK 0x38u |
| #define GIS_CONFIG1_CH4_NUM_SHIFT 3 |
| #define GIS_CONFIG1_CH4_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH4_NUM_SHIFT))&GIS_CONFIG1_CH4_NUM_MASK) |
| #define GIS_CONFIG1_CH5_MAPPING_MASK 0x700u |
| #define GIS_CONFIG1_CH5_MAPPING_SHIFT 8 |
| #define GIS_CONFIG1_CH5_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH5_MAPPING_SHIFT))&GIS_CONFIG1_CH5_MAPPING_MASK) |
| #define GIS_CONFIG1_CH5_NUM_MASK 0x3800u |
| #define GIS_CONFIG1_CH5_NUM_SHIFT 11 |
| #define GIS_CONFIG1_CH5_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CH5_NUM_SHIFT))&GIS_CONFIG1_CH5_NUM_MASK) |
| /* CONFIG1_SET Bit Fields */ |
| #define GIS_CONFIG1_SET_CH4_MAPPING_MASK 0x7u |
| #define GIS_CONFIG1_SET_CH4_MAPPING_SHIFT 0 |
| #define GIS_CONFIG1_SET_CH4_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH4_MAPPING_SHIFT))&GIS_CONFIG1_SET_CH4_MAPPING_MASK) |
| #define GIS_CONFIG1_SET_CH4_NUM_MASK 0x38u |
| #define GIS_CONFIG1_SET_CH4_NUM_SHIFT 3 |
| #define GIS_CONFIG1_SET_CH4_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH4_NUM_SHIFT))&GIS_CONFIG1_SET_CH4_NUM_MASK) |
| #define GIS_CONFIG1_SET_CH5_MAPPING_MASK 0x700u |
| #define GIS_CONFIG1_SET_CH5_MAPPING_SHIFT 8 |
| #define GIS_CONFIG1_SET_CH5_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH5_MAPPING_SHIFT))&GIS_CONFIG1_SET_CH5_MAPPING_MASK) |
| #define GIS_CONFIG1_SET_CH5_NUM_MASK 0x3800u |
| #define GIS_CONFIG1_SET_CH5_NUM_SHIFT 11 |
| #define GIS_CONFIG1_SET_CH5_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_SET_CH5_NUM_SHIFT))&GIS_CONFIG1_SET_CH5_NUM_MASK) |
| /* CONFIG1_CLR Bit Fields */ |
| #define GIS_CONFIG1_CLR_CH4_MAPPING_MASK 0x7u |
| #define GIS_CONFIG1_CLR_CH4_MAPPING_SHIFT 0 |
| #define GIS_CONFIG1_CLR_CH4_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH4_MAPPING_SHIFT))&GIS_CONFIG1_CLR_CH4_MAPPING_MASK) |
| #define GIS_CONFIG1_CLR_CH4_NUM_MASK 0x38u |
| #define GIS_CONFIG1_CLR_CH4_NUM_SHIFT 3 |
| #define GIS_CONFIG1_CLR_CH4_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH4_NUM_SHIFT))&GIS_CONFIG1_CLR_CH4_NUM_MASK) |
| #define GIS_CONFIG1_CLR_CH5_MAPPING_MASK 0x700u |
| #define GIS_CONFIG1_CLR_CH5_MAPPING_SHIFT 8 |
| #define GIS_CONFIG1_CLR_CH5_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH5_MAPPING_SHIFT))&GIS_CONFIG1_CLR_CH5_MAPPING_MASK) |
| #define GIS_CONFIG1_CLR_CH5_NUM_MASK 0x3800u |
| #define GIS_CONFIG1_CLR_CH5_NUM_SHIFT 11 |
| #define GIS_CONFIG1_CLR_CH5_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_CLR_CH5_NUM_SHIFT))&GIS_CONFIG1_CLR_CH5_NUM_MASK) |
| /* CONFIG1_TOG Bit Fields */ |
| #define GIS_CONFIG1_TOG_CH4_MAPPING_MASK 0x7u |
| #define GIS_CONFIG1_TOG_CH4_MAPPING_SHIFT 0 |
| #define GIS_CONFIG1_TOG_CH4_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH4_MAPPING_SHIFT))&GIS_CONFIG1_TOG_CH4_MAPPING_MASK) |
| #define GIS_CONFIG1_TOG_CH4_NUM_MASK 0x38u |
| #define GIS_CONFIG1_TOG_CH4_NUM_SHIFT 3 |
| #define GIS_CONFIG1_TOG_CH4_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH4_NUM_SHIFT))&GIS_CONFIG1_TOG_CH4_NUM_MASK) |
| #define GIS_CONFIG1_TOG_CH5_MAPPING_MASK 0x700u |
| #define GIS_CONFIG1_TOG_CH5_MAPPING_SHIFT 8 |
| #define GIS_CONFIG1_TOG_CH5_MAPPING(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH5_MAPPING_SHIFT))&GIS_CONFIG1_TOG_CH5_MAPPING_MASK) |
| #define GIS_CONFIG1_TOG_CH5_NUM_MASK 0x3800u |
| #define GIS_CONFIG1_TOG_CH5_NUM_SHIFT 11 |
| #define GIS_CONFIG1_TOG_CH5_NUM(x) (((uint32_t)(((uint32_t)(x))<<GIS_CONFIG1_TOG_CH5_NUM_SHIFT))&GIS_CONFIG1_TOG_CH5_NUM_MASK) |
| /* FB0 Bit Fields */ |
| #define GIS_FB0_ADDR_MASK 0xFFFFFFFFu |
| #define GIS_FB0_ADDR_SHIFT 0 |
| #define GIS_FB0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_FB0_ADDR_SHIFT))&GIS_FB0_ADDR_MASK) |
| /* FB1 Bit Fields */ |
| #define GIS_FB1_ADDR_MASK 0xFFFFFFFFu |
| #define GIS_FB1_ADDR_SHIFT 0 |
| #define GIS_FB1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_FB1_ADDR_SHIFT))&GIS_FB1_ADDR_MASK) |
| /* PXP_FB0 Bit Fields */ |
| #define GIS_PXP_FB0_ADDR_MASK 0xFFFFFFFFu |
| #define GIS_PXP_FB0_ADDR_SHIFT 0 |
| #define GIS_PXP_FB0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_PXP_FB0_ADDR_SHIFT))&GIS_PXP_FB0_ADDR_MASK) |
| /* PXP_FB1 Bit Fields */ |
| #define GIS_PXP_FB1_ADDR_MASK 0xFFFFFFFFu |
| #define GIS_PXP_FB1_ADDR_SHIFT 0 |
| #define GIS_PXP_FB1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_PXP_FB1_ADDR_SHIFT))&GIS_PXP_FB1_ADDR_MASK) |
| /* CH0_CTRL Bit Fields */ |
| #define GIS_CH0_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH0_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH0_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH0_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH0_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH0_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH0_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH0_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH0_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH0_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH0_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH0_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH0_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH0_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH0_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH0_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH0_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH0_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH0_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH0_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH0_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH0_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH0_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH0_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH0_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH0_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH0_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH0_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH0_CTRL_SET Bit Fields */ |
| #define GIS_CH0_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH0_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH0_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH0_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH0_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH0_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH0_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH0_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH0_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH0_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH0_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH0_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH0_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH0_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH0_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH0_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH0_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH0_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH0_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH0_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH0_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH0_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH0_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH0_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH0_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH0_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH0_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH0_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH0_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH0_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH0_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH0_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH0_CTRL_CLR Bit Fields */ |
| #define GIS_CH0_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH0_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH0_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH0_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH0_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH0_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH0_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH0_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH0_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH0_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH0_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH0_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH0_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH0_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH0_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH0_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH0_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH0_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH0_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH0_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH0_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH0_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH0_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH0_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH0_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH0_CTRL_TOG Bit Fields */ |
| #define GIS_CH0_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH0_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH0_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH0_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH0_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH0_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH0_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH0_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH0_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH0_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH0_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH0_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH0_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH0_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH0_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH0_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH0_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH0_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH0_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH0_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH0_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH0_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH0_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH0_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH0_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH0_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH0_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH0_ADDR0 Bit Fields */ |
| #define GIS_CH0_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_ADDR_SHIFT))&GIS_CH0_ADDR0_ADDR_MASK) |
| #define GIS_CH0_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR0_SET Bit Fields */ |
| #define GIS_CH0_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_SET_ADDR_SHIFT))&GIS_CH0_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH0_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR0_CLR Bit Fields */ |
| #define GIS_CH0_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_CLR_ADDR_SHIFT))&GIS_CH0_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH0_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR0_TOG Bit Fields */ |
| #define GIS_CH0_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR0_TOG_ADDR_SHIFT))&GIS_CH0_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH0_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH0_DATA0 Bit Fields */ |
| #define GIS_CH0_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH0_DATA0_DATA_SHIFT 0 |
| #define GIS_CH0_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA0_DATA_SHIFT))&GIS_CH0_DATA0_DATA_MASK) |
| /* CH0_ADDR1 Bit Fields */ |
| #define GIS_CH0_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_ADDR_SHIFT))&GIS_CH0_ADDR1_ADDR_MASK) |
| #define GIS_CH0_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR1_SET Bit Fields */ |
| #define GIS_CH0_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_SET_ADDR_SHIFT))&GIS_CH0_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH0_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR1_CLR Bit Fields */ |
| #define GIS_CH0_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_CLR_ADDR_SHIFT))&GIS_CH0_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH0_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR1_TOG Bit Fields */ |
| #define GIS_CH0_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR1_TOG_ADDR_SHIFT))&GIS_CH0_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH0_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH0_DATA1 Bit Fields */ |
| #define GIS_CH0_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH0_DATA1_DATA_SHIFT 0 |
| #define GIS_CH0_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA1_DATA_SHIFT))&GIS_CH0_DATA1_DATA_MASK) |
| /* CH0_ADDR2 Bit Fields */ |
| #define GIS_CH0_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_ADDR_SHIFT))&GIS_CH0_ADDR2_ADDR_MASK) |
| #define GIS_CH0_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR2_SET Bit Fields */ |
| #define GIS_CH0_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_SET_ADDR_SHIFT))&GIS_CH0_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH0_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR2_CLR Bit Fields */ |
| #define GIS_CH0_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_CLR_ADDR_SHIFT))&GIS_CH0_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH0_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR2_TOG Bit Fields */ |
| #define GIS_CH0_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR2_TOG_ADDR_SHIFT))&GIS_CH0_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH0_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH0_DATA2 Bit Fields */ |
| #define GIS_CH0_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH0_DATA2_DATA_SHIFT 0 |
| #define GIS_CH0_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA2_DATA_SHIFT))&GIS_CH0_DATA2_DATA_MASK) |
| /* CH0_ADDR3 Bit Fields */ |
| #define GIS_CH0_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_ADDR_SHIFT))&GIS_CH0_ADDR3_ADDR_MASK) |
| #define GIS_CH0_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR3_SET Bit Fields */ |
| #define GIS_CH0_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_SET_ADDR_SHIFT))&GIS_CH0_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH0_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR3_CLR Bit Fields */ |
| #define GIS_CH0_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_CLR_ADDR_SHIFT))&GIS_CH0_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH0_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH0_ADDR3_TOG Bit Fields */ |
| #define GIS_CH0_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH0_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH0_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_ADDR3_TOG_ADDR_SHIFT))&GIS_CH0_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH0_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH0_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH0_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH0_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH0_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH0_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH0_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH0_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH0_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH0_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH0_DATA3 Bit Fields */ |
| #define GIS_CH0_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH0_DATA3_DATA_SHIFT 0 |
| #define GIS_CH0_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH0_DATA3_DATA_SHIFT))&GIS_CH0_DATA3_DATA_MASK) |
| /* CH1_CTRL Bit Fields */ |
| #define GIS_CH1_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH1_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH1_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH1_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH1_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH1_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH1_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH1_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH1_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH1_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH1_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH1_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH1_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH1_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH1_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH1_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH1_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH1_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH1_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH1_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH1_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH1_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH1_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH1_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH1_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH1_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH1_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH1_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH1_CTRL_SET Bit Fields */ |
| #define GIS_CH1_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH1_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH1_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH1_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH1_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH1_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH1_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH1_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH1_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH1_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH1_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH1_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH1_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH1_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH1_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH1_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH1_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH1_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH1_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH1_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH1_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH1_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH1_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH1_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH1_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH1_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH1_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH1_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH1_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH1_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH1_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH1_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH1_CTRL_CLR Bit Fields */ |
| #define GIS_CH1_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH1_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH1_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH1_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH1_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH1_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH1_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH1_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH1_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH1_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH1_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH1_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH1_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH1_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH1_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH1_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH1_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH1_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH1_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH1_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH1_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH1_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH1_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH1_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH1_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH1_CTRL_TOG Bit Fields */ |
| #define GIS_CH1_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH1_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH1_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH1_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH1_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH1_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH1_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH1_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH1_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH1_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH1_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH1_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH1_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH1_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH1_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH1_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH1_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH1_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH1_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH1_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH1_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH1_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH1_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH1_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH1_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH1_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH1_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH1_ADDR0 Bit Fields */ |
| #define GIS_CH1_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_ADDR_SHIFT))&GIS_CH1_ADDR0_ADDR_MASK) |
| #define GIS_CH1_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR0_SET Bit Fields */ |
| #define GIS_CH1_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_SET_ADDR_SHIFT))&GIS_CH1_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH1_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR0_CLR Bit Fields */ |
| #define GIS_CH1_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_CLR_ADDR_SHIFT))&GIS_CH1_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH1_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR0_TOG Bit Fields */ |
| #define GIS_CH1_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR0_TOG_ADDR_SHIFT))&GIS_CH1_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH1_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH1_DATA0 Bit Fields */ |
| #define GIS_CH1_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH1_DATA0_DATA_SHIFT 0 |
| #define GIS_CH1_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA0_DATA_SHIFT))&GIS_CH1_DATA0_DATA_MASK) |
| /* CH1_ADDR1 Bit Fields */ |
| #define GIS_CH1_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_ADDR_SHIFT))&GIS_CH1_ADDR1_ADDR_MASK) |
| #define GIS_CH1_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR1_SET Bit Fields */ |
| #define GIS_CH1_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_SET_ADDR_SHIFT))&GIS_CH1_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH1_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR1_CLR Bit Fields */ |
| #define GIS_CH1_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_CLR_ADDR_SHIFT))&GIS_CH1_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH1_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR1_TOG Bit Fields */ |
| #define GIS_CH1_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR1_TOG_ADDR_SHIFT))&GIS_CH1_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH1_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH1_DATA1 Bit Fields */ |
| #define GIS_CH1_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH1_DATA1_DATA_SHIFT 0 |
| #define GIS_CH1_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA1_DATA_SHIFT))&GIS_CH1_DATA1_DATA_MASK) |
| /* CH1_ADDR2 Bit Fields */ |
| #define GIS_CH1_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_ADDR_SHIFT))&GIS_CH1_ADDR2_ADDR_MASK) |
| #define GIS_CH1_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR2_SET Bit Fields */ |
| #define GIS_CH1_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_SET_ADDR_SHIFT))&GIS_CH1_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH1_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR2_CLR Bit Fields */ |
| #define GIS_CH1_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_CLR_ADDR_SHIFT))&GIS_CH1_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH1_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR2_TOG Bit Fields */ |
| #define GIS_CH1_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR2_TOG_ADDR_SHIFT))&GIS_CH1_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH1_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH1_DATA2 Bit Fields */ |
| #define GIS_CH1_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH1_DATA2_DATA_SHIFT 0 |
| #define GIS_CH1_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA2_DATA_SHIFT))&GIS_CH1_DATA2_DATA_MASK) |
| /* CH1_ADDR3 Bit Fields */ |
| #define GIS_CH1_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_ADDR_SHIFT))&GIS_CH1_ADDR3_ADDR_MASK) |
| #define GIS_CH1_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR3_SET Bit Fields */ |
| #define GIS_CH1_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_SET_ADDR_SHIFT))&GIS_CH1_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH1_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR3_CLR Bit Fields */ |
| #define GIS_CH1_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_CLR_ADDR_SHIFT))&GIS_CH1_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH1_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH1_ADDR3_TOG Bit Fields */ |
| #define GIS_CH1_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH1_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH1_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_ADDR3_TOG_ADDR_SHIFT))&GIS_CH1_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH1_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH1_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH1_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH1_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH1_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH1_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH1_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH1_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH1_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH1_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH1_DATA3 Bit Fields */ |
| #define GIS_CH1_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH1_DATA3_DATA_SHIFT 0 |
| #define GIS_CH1_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH1_DATA3_DATA_SHIFT))&GIS_CH1_DATA3_DATA_MASK) |
| /* CH2_CTRL Bit Fields */ |
| #define GIS_CH2_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH2_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH2_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH2_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH2_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH2_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH2_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH2_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH2_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH2_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH2_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH2_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH2_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH2_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH2_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH2_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH2_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH2_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH2_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH2_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH2_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH2_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH2_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH2_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH2_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH2_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH2_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH2_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH2_CTRL_SET Bit Fields */ |
| #define GIS_CH2_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH2_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH2_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH2_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH2_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH2_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH2_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH2_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH2_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH2_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH2_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH2_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH2_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH2_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH2_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH2_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH2_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH2_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH2_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH2_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH2_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH2_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH2_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH2_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH2_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH2_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH2_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH2_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH2_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH2_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH2_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH2_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH2_CTRL_CLR Bit Fields */ |
| #define GIS_CH2_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH2_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH2_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH2_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH2_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH2_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH2_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH2_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH2_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH2_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH2_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH2_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH2_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH2_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH2_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH2_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH2_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH2_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH2_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH2_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH2_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH2_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH2_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH2_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH2_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH2_CTRL_TOG Bit Fields */ |
| #define GIS_CH2_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH2_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH2_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH2_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH2_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH2_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH2_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH2_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH2_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH2_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH2_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH2_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH2_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH2_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH2_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH2_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH2_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH2_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH2_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH2_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH2_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH2_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH2_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH2_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH2_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH2_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH2_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH2_ADDR0 Bit Fields */ |
| #define GIS_CH2_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_ADDR_SHIFT))&GIS_CH2_ADDR0_ADDR_MASK) |
| #define GIS_CH2_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR0_SET Bit Fields */ |
| #define GIS_CH2_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_SET_ADDR_SHIFT))&GIS_CH2_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH2_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR0_CLR Bit Fields */ |
| #define GIS_CH2_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_CLR_ADDR_SHIFT))&GIS_CH2_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH2_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR0_TOG Bit Fields */ |
| #define GIS_CH2_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR0_TOG_ADDR_SHIFT))&GIS_CH2_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH2_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH2_DATA0 Bit Fields */ |
| #define GIS_CH2_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH2_DATA0_DATA_SHIFT 0 |
| #define GIS_CH2_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA0_DATA_SHIFT))&GIS_CH2_DATA0_DATA_MASK) |
| /* CH2_ADDR1 Bit Fields */ |
| #define GIS_CH2_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_ADDR_SHIFT))&GIS_CH2_ADDR1_ADDR_MASK) |
| #define GIS_CH2_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR1_SET Bit Fields */ |
| #define GIS_CH2_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_SET_ADDR_SHIFT))&GIS_CH2_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH2_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR1_CLR Bit Fields */ |
| #define GIS_CH2_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_CLR_ADDR_SHIFT))&GIS_CH2_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH2_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR1_TOG Bit Fields */ |
| #define GIS_CH2_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR1_TOG_ADDR_SHIFT))&GIS_CH2_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH2_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH2_DATA1 Bit Fields */ |
| #define GIS_CH2_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH2_DATA1_DATA_SHIFT 0 |
| #define GIS_CH2_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA1_DATA_SHIFT))&GIS_CH2_DATA1_DATA_MASK) |
| /* CH2_ADDR2 Bit Fields */ |
| #define GIS_CH2_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_ADDR_SHIFT))&GIS_CH2_ADDR2_ADDR_MASK) |
| #define GIS_CH2_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR2_SET Bit Fields */ |
| #define GIS_CH2_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_SET_ADDR_SHIFT))&GIS_CH2_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH2_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR2_CLR Bit Fields */ |
| #define GIS_CH2_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_CLR_ADDR_SHIFT))&GIS_CH2_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH2_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR2_TOG Bit Fields */ |
| #define GIS_CH2_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR2_TOG_ADDR_SHIFT))&GIS_CH2_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH2_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH2_DATA2 Bit Fields */ |
| #define GIS_CH2_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH2_DATA2_DATA_SHIFT 0 |
| #define GIS_CH2_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA2_DATA_SHIFT))&GIS_CH2_DATA2_DATA_MASK) |
| /* CH2_ADDR3 Bit Fields */ |
| #define GIS_CH2_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_ADDR_SHIFT))&GIS_CH2_ADDR3_ADDR_MASK) |
| #define GIS_CH2_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR3_SET Bit Fields */ |
| #define GIS_CH2_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_SET_ADDR_SHIFT))&GIS_CH2_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH2_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR3_CLR Bit Fields */ |
| #define GIS_CH2_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_CLR_ADDR_SHIFT))&GIS_CH2_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH2_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH2_ADDR3_TOG Bit Fields */ |
| #define GIS_CH2_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH2_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH2_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_ADDR3_TOG_ADDR_SHIFT))&GIS_CH2_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH2_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH2_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH2_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH2_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH2_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH2_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH2_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH2_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH2_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH2_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH2_DATA3 Bit Fields */ |
| #define GIS_CH2_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH2_DATA3_DATA_SHIFT 0 |
| #define GIS_CH2_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH2_DATA3_DATA_SHIFT))&GIS_CH2_DATA3_DATA_MASK) |
| /* CH3_CTRL Bit Fields */ |
| #define GIS_CH3_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH3_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH3_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH3_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH3_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH3_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH3_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH3_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH3_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH3_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH3_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH3_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH3_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH3_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH3_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH3_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH3_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH3_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH3_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH3_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH3_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH3_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH3_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH3_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH3_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH3_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH3_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH3_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH3_CTRL_SET Bit Fields */ |
| #define GIS_CH3_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH3_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH3_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH3_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH3_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH3_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH3_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH3_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH3_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH3_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH3_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH3_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH3_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH3_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH3_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH3_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH3_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH3_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH3_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH3_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH3_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH3_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH3_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH3_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH3_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH3_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH3_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH3_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH3_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH3_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH3_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH3_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH3_CTRL_CLR Bit Fields */ |
| #define GIS_CH3_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH3_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH3_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH3_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH3_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH3_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH3_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH3_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH3_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH3_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH3_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH3_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH3_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH3_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH3_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH3_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH3_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH3_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH3_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH3_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH3_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH3_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH3_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH3_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH3_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH3_CTRL_TOG Bit Fields */ |
| #define GIS_CH3_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH3_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH3_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH3_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH3_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH3_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH3_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH3_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH3_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH3_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH3_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH3_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH3_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH3_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH3_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH3_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH3_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH3_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH3_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH3_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH3_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH3_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH3_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH3_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH3_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH3_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH3_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH3_ADDR0 Bit Fields */ |
| #define GIS_CH3_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_ADDR_SHIFT))&GIS_CH3_ADDR0_ADDR_MASK) |
| #define GIS_CH3_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR0_SET Bit Fields */ |
| #define GIS_CH3_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_SET_ADDR_SHIFT))&GIS_CH3_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH3_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR0_CLR Bit Fields */ |
| #define GIS_CH3_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_CLR_ADDR_SHIFT))&GIS_CH3_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH3_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR0_TOG Bit Fields */ |
| #define GIS_CH3_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR0_TOG_ADDR_SHIFT))&GIS_CH3_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH3_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH3_DATA0 Bit Fields */ |
| #define GIS_CH3_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH3_DATA0_DATA_SHIFT 0 |
| #define GIS_CH3_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA0_DATA_SHIFT))&GIS_CH3_DATA0_DATA_MASK) |
| /* CH3_ADDR1 Bit Fields */ |
| #define GIS_CH3_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_ADDR_SHIFT))&GIS_CH3_ADDR1_ADDR_MASK) |
| #define GIS_CH3_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR1_SET Bit Fields */ |
| #define GIS_CH3_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_SET_ADDR_SHIFT))&GIS_CH3_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH3_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR1_CLR Bit Fields */ |
| #define GIS_CH3_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_CLR_ADDR_SHIFT))&GIS_CH3_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH3_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR1_TOG Bit Fields */ |
| #define GIS_CH3_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR1_TOG_ADDR_SHIFT))&GIS_CH3_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH3_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH3_DATA1 Bit Fields */ |
| #define GIS_CH3_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH3_DATA1_DATA_SHIFT 0 |
| #define GIS_CH3_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA1_DATA_SHIFT))&GIS_CH3_DATA1_DATA_MASK) |
| /* CH3_ADDR2 Bit Fields */ |
| #define GIS_CH3_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_ADDR_SHIFT))&GIS_CH3_ADDR2_ADDR_MASK) |
| #define GIS_CH3_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR2_SET Bit Fields */ |
| #define GIS_CH3_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_SET_ADDR_SHIFT))&GIS_CH3_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH3_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR2_CLR Bit Fields */ |
| #define GIS_CH3_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_CLR_ADDR_SHIFT))&GIS_CH3_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH3_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR2_TOG Bit Fields */ |
| #define GIS_CH3_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR2_TOG_ADDR_SHIFT))&GIS_CH3_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH3_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH3_DATA2 Bit Fields */ |
| #define GIS_CH3_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH3_DATA2_DATA_SHIFT 0 |
| #define GIS_CH3_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA2_DATA_SHIFT))&GIS_CH3_DATA2_DATA_MASK) |
| /* CH3_ADDR3 Bit Fields */ |
| #define GIS_CH3_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_ADDR_SHIFT))&GIS_CH3_ADDR3_ADDR_MASK) |
| #define GIS_CH3_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR3_SET Bit Fields */ |
| #define GIS_CH3_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_SET_ADDR_SHIFT))&GIS_CH3_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH3_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR3_CLR Bit Fields */ |
| #define GIS_CH3_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_CLR_ADDR_SHIFT))&GIS_CH3_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH3_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH3_ADDR3_TOG Bit Fields */ |
| #define GIS_CH3_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH3_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH3_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_ADDR3_TOG_ADDR_SHIFT))&GIS_CH3_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH3_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH3_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH3_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH3_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH3_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH3_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH3_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH3_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH3_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH3_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH3_DATA3 Bit Fields */ |
| #define GIS_CH3_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH3_DATA3_DATA_SHIFT 0 |
| #define GIS_CH3_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH3_DATA3_DATA_SHIFT))&GIS_CH3_DATA3_DATA_MASK) |
| /* CH4_CTRL Bit Fields */ |
| #define GIS_CH4_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH4_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH4_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH4_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH4_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH4_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH4_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH4_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH4_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH4_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH4_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH4_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH4_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH4_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH4_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH4_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH4_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH4_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH4_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH4_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH4_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH4_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH4_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH4_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH4_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH4_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH4_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH4_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH4_CTRL_SET Bit Fields */ |
| #define GIS_CH4_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH4_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH4_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH4_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH4_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH4_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH4_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH4_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH4_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH4_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH4_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH4_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH4_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH4_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH4_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH4_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH4_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH4_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH4_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH4_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH4_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH4_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH4_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH4_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH4_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH4_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH4_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH4_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH4_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH4_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH4_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH4_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH4_CTRL_CLR Bit Fields */ |
| #define GIS_CH4_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH4_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH4_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH4_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH4_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH4_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH4_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH4_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH4_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH4_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH4_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH4_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH4_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH4_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH4_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH4_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH4_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH4_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH4_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH4_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH4_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH4_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH4_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH4_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH4_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH4_CTRL_TOG Bit Fields */ |
| #define GIS_CH4_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH4_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH4_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH4_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH4_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH4_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH4_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH4_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH4_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH4_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH4_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH4_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH4_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH4_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH4_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH4_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH4_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH4_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH4_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH4_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH4_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH4_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH4_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH4_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH4_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH4_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH4_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH4_ADDR0 Bit Fields */ |
| #define GIS_CH4_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_ADDR_SHIFT))&GIS_CH4_ADDR0_ADDR_MASK) |
| #define GIS_CH4_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR0_SET Bit Fields */ |
| #define GIS_CH4_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_SET_ADDR_SHIFT))&GIS_CH4_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH4_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR0_CLR Bit Fields */ |
| #define GIS_CH4_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_CLR_ADDR_SHIFT))&GIS_CH4_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH4_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR0_TOG Bit Fields */ |
| #define GIS_CH4_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR0_TOG_ADDR_SHIFT))&GIS_CH4_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH4_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH4_DATA0 Bit Fields */ |
| #define GIS_CH4_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH4_DATA0_DATA_SHIFT 0 |
| #define GIS_CH4_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA0_DATA_SHIFT))&GIS_CH4_DATA0_DATA_MASK) |
| /* CH4_ADDR1 Bit Fields */ |
| #define GIS_CH4_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_ADDR_SHIFT))&GIS_CH4_ADDR1_ADDR_MASK) |
| #define GIS_CH4_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR1_SET Bit Fields */ |
| #define GIS_CH4_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_SET_ADDR_SHIFT))&GIS_CH4_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH4_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR1_CLR Bit Fields */ |
| #define GIS_CH4_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_CLR_ADDR_SHIFT))&GIS_CH4_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH4_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR1_TOG Bit Fields */ |
| #define GIS_CH4_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR1_TOG_ADDR_SHIFT))&GIS_CH4_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH4_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH4_DATA1 Bit Fields */ |
| #define GIS_CH4_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH4_DATA1_DATA_SHIFT 0 |
| #define GIS_CH4_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA1_DATA_SHIFT))&GIS_CH4_DATA1_DATA_MASK) |
| /* CH4_ADDR2 Bit Fields */ |
| #define GIS_CH4_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_ADDR_SHIFT))&GIS_CH4_ADDR2_ADDR_MASK) |
| #define GIS_CH4_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR2_SET Bit Fields */ |
| #define GIS_CH4_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_SET_ADDR_SHIFT))&GIS_CH4_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH4_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR2_CLR Bit Fields */ |
| #define GIS_CH4_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_CLR_ADDR_SHIFT))&GIS_CH4_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH4_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR2_TOG Bit Fields */ |
| #define GIS_CH4_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR2_TOG_ADDR_SHIFT))&GIS_CH4_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH4_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH4_DATA2 Bit Fields */ |
| #define GIS_CH4_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH4_DATA2_DATA_SHIFT 0 |
| #define GIS_CH4_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA2_DATA_SHIFT))&GIS_CH4_DATA2_DATA_MASK) |
| /* CH4_ADDR3 Bit Fields */ |
| #define GIS_CH4_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_ADDR_SHIFT))&GIS_CH4_ADDR3_ADDR_MASK) |
| #define GIS_CH4_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR3_SET Bit Fields */ |
| #define GIS_CH4_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_SET_ADDR_SHIFT))&GIS_CH4_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH4_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR3_CLR Bit Fields */ |
| #define GIS_CH4_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_CLR_ADDR_SHIFT))&GIS_CH4_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH4_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH4_ADDR3_TOG Bit Fields */ |
| #define GIS_CH4_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH4_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH4_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_ADDR3_TOG_ADDR_SHIFT))&GIS_CH4_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH4_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH4_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH4_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH4_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH4_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH4_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH4_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH4_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH4_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH4_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH4_DATA3 Bit Fields */ |
| #define GIS_CH4_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH4_DATA3_DATA_SHIFT 0 |
| #define GIS_CH4_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH4_DATA3_DATA_SHIFT))&GIS_CH4_DATA3_DATA_MASK) |
| /* CH5_CTRL Bit Fields */ |
| #define GIS_CH5_CTRL_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH5_CTRL_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH5_CTRL_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD0_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CMD0_ALU_MASK 0x70u |
| #define GIS_CH5_CTRL_CMD0_ALU_SHIFT 4 |
| #define GIS_CH5_CTRL_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_CMD0_ALU_MASK) |
| #define GIS_CH5_CTRL_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH5_CTRL_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH5_CTRL_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH5_CTRL_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH5_CTRL_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD1_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH5_CTRL_CMD1_ALU_SHIFT 12 |
| #define GIS_CH5_CTRL_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_CMD1_ALU_MASK) |
| #define GIS_CH5_CTRL_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH5_CTRL_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH5_CTRL_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH5_CTRL_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH5_CTRL_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD2_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH5_CTRL_CMD2_ALU_SHIFT 20 |
| #define GIS_CH5_CTRL_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_CMD2_ALU_MASK) |
| #define GIS_CH5_CTRL_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH5_CTRL_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH5_CTRL_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH5_CTRL_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH5_CTRL_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_CMD3_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH5_CTRL_CMD3_ALU_SHIFT 28 |
| #define GIS_CH5_CTRL_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_CMD3_ALU_MASK) |
| #define GIS_CH5_CTRL_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH5_CTRL_CMD3_ACC_NEG_SHIFT 31 |
| /* CH5_CTRL_SET Bit Fields */ |
| #define GIS_CH5_CTRL_SET_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH5_CTRL_SET_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH5_CTRL_SET_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD0_OPCODE_MASK) |
| #define GIS_CH5_CTRL_SET_CMD0_ALU_MASK 0x70u |
| #define GIS_CH5_CTRL_SET_CMD0_ALU_SHIFT 4 |
| #define GIS_CH5_CTRL_SET_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD0_ALU_MASK) |
| #define GIS_CH5_CTRL_SET_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH5_CTRL_SET_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH5_CTRL_SET_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH5_CTRL_SET_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH5_CTRL_SET_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD1_OPCODE_MASK) |
| #define GIS_CH5_CTRL_SET_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH5_CTRL_SET_CMD1_ALU_SHIFT 12 |
| #define GIS_CH5_CTRL_SET_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD1_ALU_MASK) |
| #define GIS_CH5_CTRL_SET_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH5_CTRL_SET_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH5_CTRL_SET_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH5_CTRL_SET_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH5_CTRL_SET_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD2_OPCODE_MASK) |
| #define GIS_CH5_CTRL_SET_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH5_CTRL_SET_CMD2_ALU_SHIFT 20 |
| #define GIS_CH5_CTRL_SET_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD2_ALU_MASK) |
| #define GIS_CH5_CTRL_SET_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH5_CTRL_SET_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH5_CTRL_SET_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH5_CTRL_SET_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH5_CTRL_SET_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_SET_CMD3_OPCODE_MASK) |
| #define GIS_CH5_CTRL_SET_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH5_CTRL_SET_CMD3_ALU_SHIFT 28 |
| #define GIS_CH5_CTRL_SET_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_SET_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_SET_CMD3_ALU_MASK) |
| #define GIS_CH5_CTRL_SET_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH5_CTRL_SET_CMD3_ACC_NEG_SHIFT 31 |
| /* CH5_CTRL_CLR Bit Fields */ |
| #define GIS_CH5_CTRL_CLR_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH5_CTRL_CLR_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH5_CTRL_CLR_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD0_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD0_ALU_MASK 0x70u |
| #define GIS_CH5_CTRL_CLR_CMD0_ALU_SHIFT 4 |
| #define GIS_CH5_CTRL_CLR_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD0_ALU_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH5_CTRL_CLR_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH5_CTRL_CLR_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH5_CTRL_CLR_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH5_CTRL_CLR_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD1_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH5_CTRL_CLR_CMD1_ALU_SHIFT 12 |
| #define GIS_CH5_CTRL_CLR_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD1_ALU_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH5_CTRL_CLR_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH5_CTRL_CLR_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH5_CTRL_CLR_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH5_CTRL_CLR_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD2_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH5_CTRL_CLR_CMD2_ALU_SHIFT 20 |
| #define GIS_CH5_CTRL_CLR_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD2_ALU_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH5_CTRL_CLR_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH5_CTRL_CLR_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH5_CTRL_CLR_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH5_CTRL_CLR_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_CLR_CMD3_OPCODE_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH5_CTRL_CLR_CMD3_ALU_SHIFT 28 |
| #define GIS_CH5_CTRL_CLR_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_CLR_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_CLR_CMD3_ALU_MASK) |
| #define GIS_CH5_CTRL_CLR_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH5_CTRL_CLR_CMD3_ACC_NEG_SHIFT 31 |
| /* CH5_CTRL_TOG Bit Fields */ |
| #define GIS_CH5_CTRL_TOG_CMD0_OPCODE_MASK 0xFu |
| #define GIS_CH5_CTRL_TOG_CMD0_OPCODE_SHIFT 0 |
| #define GIS_CH5_CTRL_TOG_CMD0_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD0_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD0_OPCODE_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD0_ALU_MASK 0x70u |
| #define GIS_CH5_CTRL_TOG_CMD0_ALU_SHIFT 4 |
| #define GIS_CH5_CTRL_TOG_CMD0_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD0_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD0_ALU_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD0_ACC_NEG_MASK 0x80u |
| #define GIS_CH5_CTRL_TOG_CMD0_ACC_NEG_SHIFT 7 |
| #define GIS_CH5_CTRL_TOG_CMD1_OPCODE_MASK 0xF00u |
| #define GIS_CH5_CTRL_TOG_CMD1_OPCODE_SHIFT 8 |
| #define GIS_CH5_CTRL_TOG_CMD1_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD1_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD1_OPCODE_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD1_ALU_MASK 0x7000u |
| #define GIS_CH5_CTRL_TOG_CMD1_ALU_SHIFT 12 |
| #define GIS_CH5_CTRL_TOG_CMD1_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD1_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD1_ALU_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD1_ACC_NEG_MASK 0x8000u |
| #define GIS_CH5_CTRL_TOG_CMD1_ACC_NEG_SHIFT 15 |
| #define GIS_CH5_CTRL_TOG_CMD2_OPCODE_MASK 0xF0000u |
| #define GIS_CH5_CTRL_TOG_CMD2_OPCODE_SHIFT 16 |
| #define GIS_CH5_CTRL_TOG_CMD2_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD2_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD2_OPCODE_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD2_ALU_MASK 0x700000u |
| #define GIS_CH5_CTRL_TOG_CMD2_ALU_SHIFT 20 |
| #define GIS_CH5_CTRL_TOG_CMD2_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD2_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD2_ALU_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD2_ACC_NEG_MASK 0x800000u |
| #define GIS_CH5_CTRL_TOG_CMD2_ACC_NEG_SHIFT 23 |
| #define GIS_CH5_CTRL_TOG_CMD3_OPCODE_MASK 0xF000000u |
| #define GIS_CH5_CTRL_TOG_CMD3_OPCODE_SHIFT 24 |
| #define GIS_CH5_CTRL_TOG_CMD3_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD3_OPCODE_SHIFT))&GIS_CH5_CTRL_TOG_CMD3_OPCODE_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD3_ALU_MASK 0x70000000u |
| #define GIS_CH5_CTRL_TOG_CMD3_ALU_SHIFT 28 |
| #define GIS_CH5_CTRL_TOG_CMD3_ALU(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_CTRL_TOG_CMD3_ALU_SHIFT))&GIS_CH5_CTRL_TOG_CMD3_ALU_MASK) |
| #define GIS_CH5_CTRL_TOG_CMD3_ACC_NEG_MASK 0x80000000u |
| #define GIS_CH5_CTRL_TOG_CMD3_ACC_NEG_SHIFT 31 |
| /* CH5_ADDR0 Bit Fields */ |
| #define GIS_CH5_ADDR0_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR0_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR0_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_ADDR_SHIFT))&GIS_CH5_ADDR0_ADDR_MASK) |
| #define GIS_CH5_ADDR0_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR0_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR0_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR0_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR0_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR0_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR0_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR0_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR0_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR0_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR0_SET Bit Fields */ |
| #define GIS_CH5_ADDR0_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR0_SET_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR0_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_SET_ADDR_SHIFT))&GIS_CH5_ADDR0_SET_ADDR_MASK) |
| #define GIS_CH5_ADDR0_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR0_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR0_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR0_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR0_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR0_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR0_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR0_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR0_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR0_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR0_CLR Bit Fields */ |
| #define GIS_CH5_ADDR0_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR0_CLR_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR0_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_CLR_ADDR_SHIFT))&GIS_CH5_ADDR0_CLR_ADDR_MASK) |
| #define GIS_CH5_ADDR0_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR0_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR0_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR0_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR0_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR0_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR0_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR0_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR0_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR0_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR0_TOG Bit Fields */ |
| #define GIS_CH5_ADDR0_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR0_TOG_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR0_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR0_TOG_ADDR_SHIFT))&GIS_CH5_ADDR0_TOG_ADDR_MASK) |
| #define GIS_CH5_ADDR0_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR0_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR0_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR0_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR0_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR0_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR0_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR0_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR0_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR0_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH5_DATA0 Bit Fields */ |
| #define GIS_CH5_DATA0_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH5_DATA0_DATA_SHIFT 0 |
| #define GIS_CH5_DATA0_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA0_DATA_SHIFT))&GIS_CH5_DATA0_DATA_MASK) |
| /* CH5_ADDR1 Bit Fields */ |
| #define GIS_CH5_ADDR1_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR1_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR1_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_ADDR_SHIFT))&GIS_CH5_ADDR1_ADDR_MASK) |
| #define GIS_CH5_ADDR1_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR1_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR1_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR1_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR1_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR1_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR1_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR1_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR1_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR1_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR1_SET Bit Fields */ |
| #define GIS_CH5_ADDR1_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR1_SET_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR1_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_SET_ADDR_SHIFT))&GIS_CH5_ADDR1_SET_ADDR_MASK) |
| #define GIS_CH5_ADDR1_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR1_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR1_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR1_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR1_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR1_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR1_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR1_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR1_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR1_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR1_CLR Bit Fields */ |
| #define GIS_CH5_ADDR1_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR1_CLR_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR1_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_CLR_ADDR_SHIFT))&GIS_CH5_ADDR1_CLR_ADDR_MASK) |
| #define GIS_CH5_ADDR1_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR1_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR1_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR1_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR1_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR1_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR1_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR1_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR1_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR1_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR1_TOG Bit Fields */ |
| #define GIS_CH5_ADDR1_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR1_TOG_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR1_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR1_TOG_ADDR_SHIFT))&GIS_CH5_ADDR1_TOG_ADDR_MASK) |
| #define GIS_CH5_ADDR1_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR1_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR1_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR1_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR1_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR1_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR1_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR1_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR1_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR1_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH5_DATA1 Bit Fields */ |
| #define GIS_CH5_DATA1_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH5_DATA1_DATA_SHIFT 0 |
| #define GIS_CH5_DATA1_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA1_DATA_SHIFT))&GIS_CH5_DATA1_DATA_MASK) |
| /* CH5_ADDR2 Bit Fields */ |
| #define GIS_CH5_ADDR2_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR2_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_ADDR_SHIFT))&GIS_CH5_ADDR2_ADDR_MASK) |
| #define GIS_CH5_ADDR2_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR2_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR2_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR2_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR2_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR2_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR2_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR2_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR2_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR2_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR2_SET Bit Fields */ |
| #define GIS_CH5_ADDR2_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR2_SET_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR2_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_SET_ADDR_SHIFT))&GIS_CH5_ADDR2_SET_ADDR_MASK) |
| #define GIS_CH5_ADDR2_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR2_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR2_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR2_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR2_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR2_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR2_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR2_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR2_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR2_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR2_CLR Bit Fields */ |
| #define GIS_CH5_ADDR2_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR2_CLR_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR2_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_CLR_ADDR_SHIFT))&GIS_CH5_ADDR2_CLR_ADDR_MASK) |
| #define GIS_CH5_ADDR2_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR2_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR2_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR2_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR2_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR2_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR2_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR2_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR2_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR2_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR2_TOG Bit Fields */ |
| #define GIS_CH5_ADDR2_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR2_TOG_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR2_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR2_TOG_ADDR_SHIFT))&GIS_CH5_ADDR2_TOG_ADDR_MASK) |
| #define GIS_CH5_ADDR2_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR2_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR2_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR2_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR2_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR2_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR2_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR2_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR2_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR2_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH5_DATA2 Bit Fields */ |
| #define GIS_CH5_DATA2_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH5_DATA2_DATA_SHIFT 0 |
| #define GIS_CH5_DATA2_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA2_DATA_SHIFT))&GIS_CH5_DATA2_DATA_MASK) |
| /* CH5_ADDR3 Bit Fields */ |
| #define GIS_CH5_ADDR3_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR3_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR3_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_ADDR_SHIFT))&GIS_CH5_ADDR3_ADDR_MASK) |
| #define GIS_CH5_ADDR3_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR3_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR3_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR3_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR3_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR3_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR3_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR3_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR3_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR3_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR3_SET Bit Fields */ |
| #define GIS_CH5_ADDR3_SET_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR3_SET_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR3_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_SET_ADDR_SHIFT))&GIS_CH5_ADDR3_SET_ADDR_MASK) |
| #define GIS_CH5_ADDR3_SET_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR3_SET_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR3_SET_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR3_SET_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR3_SET_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR3_SET_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR3_SET_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR3_SET_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR3_SET_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR3_SET_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR3_CLR Bit Fields */ |
| #define GIS_CH5_ADDR3_CLR_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR3_CLR_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR3_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_CLR_ADDR_SHIFT))&GIS_CH5_ADDR3_CLR_ADDR_MASK) |
| #define GIS_CH5_ADDR3_CLR_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR3_CLR_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR3_CLR_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR3_CLR_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR3_CLR_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR3_CLR_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR3_CLR_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR3_CLR_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR3_CLR_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR3_CLR_LCDIF1_SEL_SHIFT 31 |
| /* CH5_ADDR3_TOG Bit Fields */ |
| #define GIS_CH5_ADDR3_TOG_ADDR_MASK 0x7FFFFFFu |
| #define GIS_CH5_ADDR3_TOG_ADDR_SHIFT 0 |
| #define GIS_CH5_ADDR3_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_ADDR3_TOG_ADDR_SHIFT))&GIS_CH5_ADDR3_TOG_ADDR_MASK) |
| #define GIS_CH5_ADDR3_TOG_CSI0_SEL_MASK 0x8000000u |
| #define GIS_CH5_ADDR3_TOG_CSI0_SEL_SHIFT 27 |
| #define GIS_CH5_ADDR3_TOG_CSI1_SEL_MASK 0x10000000u |
| #define GIS_CH5_ADDR3_TOG_CSI1_SEL_SHIFT 28 |
| #define GIS_CH5_ADDR3_TOG_PXP_SEL_MASK 0x20000000u |
| #define GIS_CH5_ADDR3_TOG_PXP_SEL_SHIFT 29 |
| #define GIS_CH5_ADDR3_TOG_LCDIF0_SEL_MASK 0x40000000u |
| #define GIS_CH5_ADDR3_TOG_LCDIF0_SEL_SHIFT 30 |
| #define GIS_CH5_ADDR3_TOG_LCDIF1_SEL_MASK 0x80000000u |
| #define GIS_CH5_ADDR3_TOG_LCDIF1_SEL_SHIFT 31 |
| /* CH5_DATA3 Bit Fields */ |
| #define GIS_CH5_DATA3_DATA_MASK 0xFFFFFFFFu |
| #define GIS_CH5_DATA3_DATA_SHIFT 0 |
| #define GIS_CH5_DATA3_DATA(x) (((uint32_t)(((uint32_t)(x))<<GIS_CH5_DATA3_DATA_SHIFT))&GIS_CH5_DATA3_DATA_MASK) |
| /* DEBUG0 Bit Fields */ |
| #define GIS_DEBUG0_CMD_STATE_MASK 0xFFu |
| #define GIS_DEBUG0_CMD_STATE_SHIFT 0 |
| #define GIS_DEBUG0_CMD_STATE(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_STATE_SHIFT))&GIS_DEBUG0_CMD_STATE_MASK) |
| #define GIS_DEBUG0_MAIN_STATE_MASK 0x3F00u |
| #define GIS_DEBUG0_MAIN_STATE_SHIFT 8 |
| #define GIS_DEBUG0_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_MAIN_STATE_SHIFT))&GIS_DEBUG0_MAIN_STATE_MASK) |
| #define GIS_DEBUG0_CHANNEL_CUR_MASK 0x3C000u |
| #define GIS_DEBUG0_CHANNEL_CUR_SHIFT 14 |
| #define GIS_DEBUG0_CHANNEL_CUR(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CHANNEL_CUR_SHIFT))&GIS_DEBUG0_CHANNEL_CUR_MASK) |
| #define GIS_DEBUG0_CMD_COUNTER_MASK 0x1C0000u |
| #define GIS_DEBUG0_CMD_COUNTER_SHIFT 18 |
| #define GIS_DEBUG0_CMD_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_COUNTER_SHIFT))&GIS_DEBUG0_CMD_COUNTER_MASK) |
| #define GIS_DEBUG0_CMD_OPCODE_MASK 0x1E00000u |
| #define GIS_DEBUG0_CMD_OPCODE_SHIFT 21 |
| #define GIS_DEBUG0_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CMD_OPCODE_SHIFT))&GIS_DEBUG0_CMD_OPCODE_MASK) |
| #define GIS_DEBUG0_PXP_BUSY_MASK 0x2000000u |
| #define GIS_DEBUG0_PXP_BUSY_SHIFT 25 |
| #define GIS_DEBUG0_PXP_IRQ_MASK 0x4000000u |
| #define GIS_DEBUG0_PXP_IRQ_SHIFT 26 |
| #define GIS_DEBUG0_CSI_IRQ_MASK 0x8000000u |
| #define GIS_DEBUG0_CSI_IRQ_SHIFT 27 |
| #define GIS_DEBUG0_CSI_FB_REG_MASK 0x30000000u |
| #define GIS_DEBUG0_CSI_FB_REG_SHIFT 28 |
| #define GIS_DEBUG0_CSI_FB_REG(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG0_CSI_FB_REG_SHIFT))&GIS_DEBUG0_CSI_FB_REG_MASK) |
| /* DEBUG1 Bit Fields */ |
| #define GIS_DEBUG1_CSI_FB_MASK 0xFFu |
| #define GIS_DEBUG1_CSI_FB_SHIFT 0 |
| #define GIS_DEBUG1_CSI_FB(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_CSI_FB_SHIFT))&GIS_DEBUG1_CSI_FB_MASK) |
| #define GIS_DEBUG1_PXP_OUT_FB_MASK 0xFF00u |
| #define GIS_DEBUG1_PXP_OUT_FB_SHIFT 8 |
| #define GIS_DEBUG1_PXP_OUT_FB(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_PXP_OUT_FB_SHIFT))&GIS_DEBUG1_PXP_OUT_FB_MASK) |
| #define GIS_DEBUG1_PXP_IN_FB_MASK 0x30000u |
| #define GIS_DEBUG1_PXP_IN_FB_SHIFT 16 |
| #define GIS_DEBUG1_PXP_IN_FB(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_PXP_IN_FB_SHIFT))&GIS_DEBUG1_PXP_IN_FB_MASK) |
| #define GIS_DEBUG1_LCDIF_FB_MASK 0xC0000u |
| #define GIS_DEBUG1_LCDIF_FB_SHIFT 18 |
| #define GIS_DEBUG1_LCDIF_FB(x) (((uint32_t)(((uint32_t)(x))<<GIS_DEBUG1_LCDIF_FB_SHIFT))&GIS_DEBUG1_LCDIF_FB_MASK) |
| /* VERSION Bit Fields */ |
| #define GIS_VERSION_STEP_MASK 0xFFFFu |
| #define GIS_VERSION_STEP_SHIFT 0 |
| #define GIS_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_STEP_SHIFT))&GIS_VERSION_STEP_MASK) |
| #define GIS_VERSION_MINOR_MASK 0xFF0000u |
| #define GIS_VERSION_MINOR_SHIFT 16 |
| #define GIS_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_MINOR_SHIFT))&GIS_VERSION_MINOR_MASK) |
| #define GIS_VERSION_MAJOR_MASK 0xFF000000u |
| #define GIS_VERSION_MAJOR_SHIFT 24 |
| #define GIS_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<GIS_VERSION_MAJOR_SHIFT))&GIS_VERSION_MAJOR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group GIS_Register_Masks */ |
| |
| /* GIS - Peripheral instance base addresses */ |
| /** Peripheral GIS base address */ |
| #define GIS_BASE (0x42204000u) |
| /** Peripheral GIS base pointer */ |
| #define GIS ((GIS_Type *)GIS_BASE) |
| #define GIS_BASE_PTR (GIS) |
| /** Array initializer of GIS peripheral base addresses */ |
| #define GIS_BASE_ADDRS { GIS_BASE } |
| /** Array initializer of GIS peripheral base pointers */ |
| #define GIS_BASE_PTRS { GIS } |
| |
| /* ---------------------------------------------------------------------------- |
| -- GIS - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GIS_Register_Accessor_Macros GIS - Register accessor macros |
| * @{ |
| */ |
| |
| /* GIS - Register instance definitions */ |
| /* GIS */ |
| #define GIS_CTRL GIS_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CTRL_SET GIS_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CTRL_CLR GIS_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CTRL_TOG GIS_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG0 GIS_CONFIG0_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG0_SET GIS_CONFIG0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG0_CLR GIS_CONFIG0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG0_TOG GIS_CONFIG0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG1 GIS_CONFIG1_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG1_SET GIS_CONFIG1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG1_CLR GIS_CONFIG1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CONFIG1_TOG GIS_CONFIG1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_FB0 GIS_FB0_REG(GIS_BASE_PTR) |
| #define GIS_FB1 GIS_FB1_REG(GIS_BASE_PTR) |
| #define GIS_PXP_FB0 GIS_PXP_FB0_REG(GIS_BASE_PTR) |
| #define GIS_PXP_FB1 GIS_PXP_FB1_REG(GIS_BASE_PTR) |
| #define GIS_CH0_CTRL GIS_CH0_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH0_CTRL_SET GIS_CH0_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH0_CTRL_CLR GIS_CH0_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH0_CTRL_TOG GIS_CH0_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR0 GIS_CH0_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR0_SET GIS_CH0_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR0_CLR GIS_CH0_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR0_TOG GIS_CH0_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH0_DATA0 GIS_CH0_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR1 GIS_CH0_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR1_SET GIS_CH0_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR1_CLR GIS_CH0_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR1_TOG GIS_CH0_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH0_DATA1 GIS_CH0_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR2 GIS_CH0_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR2_SET GIS_CH0_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR2_CLR GIS_CH0_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR2_TOG GIS_CH0_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH0_DATA2 GIS_CH0_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR3 GIS_CH0_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR3_SET GIS_CH0_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR3_CLR GIS_CH0_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH0_ADDR3_TOG GIS_CH0_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH0_DATA3 GIS_CH0_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_CH1_CTRL GIS_CH1_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH1_CTRL_SET GIS_CH1_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH1_CTRL_CLR GIS_CH1_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH1_CTRL_TOG GIS_CH1_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR0 GIS_CH1_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR0_SET GIS_CH1_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR0_CLR GIS_CH1_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR0_TOG GIS_CH1_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH1_DATA0 GIS_CH1_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR1 GIS_CH1_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR1_SET GIS_CH1_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR1_CLR GIS_CH1_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR1_TOG GIS_CH1_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH1_DATA1 GIS_CH1_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR2 GIS_CH1_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR2_SET GIS_CH1_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR2_CLR GIS_CH1_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR2_TOG GIS_CH1_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH1_DATA2 GIS_CH1_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR3 GIS_CH1_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR3_SET GIS_CH1_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR3_CLR GIS_CH1_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH1_ADDR3_TOG GIS_CH1_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH1_DATA3 GIS_CH1_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_CH2_CTRL GIS_CH2_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH2_CTRL_SET GIS_CH2_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH2_CTRL_CLR GIS_CH2_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH2_CTRL_TOG GIS_CH2_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR0 GIS_CH2_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR0_SET GIS_CH2_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR0_CLR GIS_CH2_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR0_TOG GIS_CH2_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH2_DATA0 GIS_CH2_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR1 GIS_CH2_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR1_SET GIS_CH2_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR1_CLR GIS_CH2_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR1_TOG GIS_CH2_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH2_DATA1 GIS_CH2_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR2 GIS_CH2_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR2_SET GIS_CH2_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR2_CLR GIS_CH2_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR2_TOG GIS_CH2_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH2_DATA2 GIS_CH2_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR3 GIS_CH2_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR3_SET GIS_CH2_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR3_CLR GIS_CH2_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH2_ADDR3_TOG GIS_CH2_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH2_DATA3 GIS_CH2_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_CH3_CTRL GIS_CH3_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH3_CTRL_SET GIS_CH3_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH3_CTRL_CLR GIS_CH3_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH3_CTRL_TOG GIS_CH3_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR0 GIS_CH3_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR0_SET GIS_CH3_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR0_CLR GIS_CH3_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR0_TOG GIS_CH3_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH3_DATA0 GIS_CH3_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR1 GIS_CH3_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR1_SET GIS_CH3_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR1_CLR GIS_CH3_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR1_TOG GIS_CH3_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH3_DATA1 GIS_CH3_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR2 GIS_CH3_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR2_SET GIS_CH3_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR2_CLR GIS_CH3_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR2_TOG GIS_CH3_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH3_DATA2 GIS_CH3_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR3 GIS_CH3_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR3_SET GIS_CH3_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR3_CLR GIS_CH3_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH3_ADDR3_TOG GIS_CH3_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH3_DATA3 GIS_CH3_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_CH4_CTRL GIS_CH4_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH4_CTRL_SET GIS_CH4_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH4_CTRL_CLR GIS_CH4_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH4_CTRL_TOG GIS_CH4_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR0 GIS_CH4_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR0_SET GIS_CH4_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR0_CLR GIS_CH4_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR0_TOG GIS_CH4_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH4_DATA0 GIS_CH4_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR1 GIS_CH4_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR1_SET GIS_CH4_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR1_CLR GIS_CH4_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR1_TOG GIS_CH4_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH4_DATA1 GIS_CH4_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR2 GIS_CH4_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR2_SET GIS_CH4_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR2_CLR GIS_CH4_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR2_TOG GIS_CH4_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH4_DATA2 GIS_CH4_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR3 GIS_CH4_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR3_SET GIS_CH4_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR3_CLR GIS_CH4_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH4_ADDR3_TOG GIS_CH4_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH4_DATA3 GIS_CH4_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_CH5_CTRL GIS_CH5_CTRL_REG(GIS_BASE_PTR) |
| #define GIS_CH5_CTRL_SET GIS_CH5_CTRL_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH5_CTRL_CLR GIS_CH5_CTRL_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH5_CTRL_TOG GIS_CH5_CTRL_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR0 GIS_CH5_ADDR0_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR0_SET GIS_CH5_ADDR0_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR0_CLR GIS_CH5_ADDR0_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR0_TOG GIS_CH5_ADDR0_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH5_DATA0 GIS_CH5_DATA0_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR1 GIS_CH5_ADDR1_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR1_SET GIS_CH5_ADDR1_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR1_CLR GIS_CH5_ADDR1_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR1_TOG GIS_CH5_ADDR1_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH5_DATA1 GIS_CH5_DATA1_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR2 GIS_CH5_ADDR2_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR2_SET GIS_CH5_ADDR2_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR2_CLR GIS_CH5_ADDR2_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR2_TOG GIS_CH5_ADDR2_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH5_DATA2 GIS_CH5_DATA2_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR3 GIS_CH5_ADDR3_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR3_SET GIS_CH5_ADDR3_SET_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR3_CLR GIS_CH5_ADDR3_CLR_REG(GIS_BASE_PTR) |
| #define GIS_CH5_ADDR3_TOG GIS_CH5_ADDR3_TOG_REG(GIS_BASE_PTR) |
| #define GIS_CH5_DATA3 GIS_CH5_DATA3_REG(GIS_BASE_PTR) |
| #define GIS_DEBUG0 GIS_DEBUG0_REG(GIS_BASE_PTR) |
| #define GIS_DEBUG1 GIS_DEBUG1_REG(GIS_BASE_PTR) |
| #define GIS_VERSION GIS_VERSION_REG(GIS_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group GIS_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group GIS_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ |
| __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ |
| __IO uint32_t IMR1; /**< IRQ masking register 1, offset: 0x8 */ |
| __IO uint32_t IMR2; /**< IRQ masking register 2, offset: 0xC */ |
| __IO uint32_t IMR3; /**< IRQ masking register 3, offset: 0x10 */ |
| __IO uint32_t IMR4; /**< IRQ masking register 4, offset: 0x14 */ |
| __I uint32_t ISR1; /**< IRQ status resister 1, offset: 0x18 */ |
| __I uint32_t ISR2; /**< IRQ status resister 2, offset: 0x1C */ |
| __I uint32_t ISR3; /**< IRQ status resister 3, offset: 0x20 */ |
| __I uint32_t ISR4; /**< IRQ status resister 4, offset: 0x24 */ |
| __I uint32_t A9_LPSR; /**< A9 Low Power Status Register, offset: 0x28 */ |
| __I uint32_t M4_LPSR; /**< M4 Low Power Status Register, offset: 0x2C */ |
| __I uint32_t DR; /**< GPC Debug Register, offset: 0x30 */ |
| } GPC_Type, *GPC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPC - Register accessors */ |
| #define GPC_CNTR_REG(base) ((base)->CNTR) |
| #define GPC_PGR_REG(base) ((base)->PGR) |
| #define GPC_IMR1_REG(base) ((base)->IMR1) |
| #define GPC_IMR2_REG(base) ((base)->IMR2) |
| #define GPC_IMR3_REG(base) ((base)->IMR3) |
| #define GPC_IMR4_REG(base) ((base)->IMR4) |
| #define GPC_ISR1_REG(base) ((base)->ISR1) |
| #define GPC_ISR2_REG(base) ((base)->ISR2) |
| #define GPC_ISR3_REG(base) ((base)->ISR3) |
| #define GPC_ISR4_REG(base) ((base)->ISR4) |
| #define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) |
| #define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) |
| #define GPC_DR_REG(base) ((base)->DR) |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Register_Masks GPC Register Masks |
| * @{ |
| */ |
| |
| /* CNTR Bit Fields */ |
| #define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u |
| #define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 |
| #define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u |
| #define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 |
| #define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u |
| #define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 |
| #define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u |
| #define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 |
| #define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u |
| #define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 |
| #define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u |
| #define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 |
| #define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u |
| #define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 |
| #define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u |
| #define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 |
| #define GPC_CNTR_DVFS0CR_MASK 0x10000u |
| #define GPC_CNTR_DVFS0CR_SHIFT 16 |
| #define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u |
| #define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 |
| #define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u |
| #define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 |
| #define GPC_CNTR_GPCIRQM_MASK 0x200000u |
| #define GPC_CNTR_GPCIRQM_SHIFT 21 |
| #define GPC_CNTR_L2_PGE_MASK 0x400000u |
| #define GPC_CNTR_L2_PGE_SHIFT 22 |
| /* PGR Bit Fields */ |
| #define GPC_PGR_DRCIC_MASK 0x60000000u |
| #define GPC_PGR_DRCIC_SHIFT 29 |
| #define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGR_DRCIC_SHIFT))&GPC_PGR_DRCIC_MASK) |
| /* IMR1 Bit Fields */ |
| #define GPC_IMR1_IMR1_MASK 0xFFFFFFFFu |
| #define GPC_IMR1_IMR1_SHIFT 0 |
| #define GPC_IMR1_IMR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_IMR1_SHIFT))&GPC_IMR1_IMR1_MASK) |
| /* IMR2 Bit Fields */ |
| #define GPC_IMR2_IMR2_MASK 0xFFFFFFFFu |
| #define GPC_IMR2_IMR2_SHIFT 0 |
| #define GPC_IMR2_IMR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_IMR2_SHIFT))&GPC_IMR2_IMR2_MASK) |
| /* IMR3 Bit Fields */ |
| #define GPC_IMR3_IMR3_MASK 0xFFFFFFFFu |
| #define GPC_IMR3_IMR3_SHIFT 0 |
| #define GPC_IMR3_IMR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_IMR3_SHIFT))&GPC_IMR3_IMR3_MASK) |
| /* IMR4 Bit Fields */ |
| #define GPC_IMR4_IMR4_MASK 0xFFFFFFFFu |
| #define GPC_IMR4_IMR4_SHIFT 0 |
| #define GPC_IMR4_IMR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_IMR4_SHIFT))&GPC_IMR4_IMR4_MASK) |
| /* ISR1 Bit Fields */ |
| #define GPC_ISR1_ISR1_MASK 0xFFFFFFFFu |
| #define GPC_ISR1_ISR1_SHIFT 0 |
| #define GPC_ISR1_ISR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_ISR1_SHIFT))&GPC_ISR1_ISR1_MASK) |
| /* ISR2 Bit Fields */ |
| #define GPC_ISR2_ISR2_MASK 0xFFFFFFFFu |
| #define GPC_ISR2_ISR2_SHIFT 0 |
| #define GPC_ISR2_ISR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_ISR2_SHIFT))&GPC_ISR2_ISR2_MASK) |
| /* ISR3 Bit Fields */ |
| #define GPC_ISR3_ISR3_MASK 0xFFFFFFFFu |
| #define GPC_ISR3_ISR3_SHIFT 0 |
| #define GPC_ISR3_ISR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_ISR3_SHIFT))&GPC_ISR3_ISR3_MASK) |
| /* ISR4 Bit Fields */ |
| #define GPC_ISR4_ISR4_MASK 0xFFFFFFFFu |
| #define GPC_ISR4_ISR4_SHIFT 0 |
| #define GPC_ISR4_ISR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_ISR4_SHIFT))&GPC_ISR4_ISR4_MASK) |
| /* A9_LPSR Bit Fields */ |
| #define GPC_A9_LPSR_A9_STANDBY_WFI_MASK 0x1u |
| #define GPC_A9_LPSR_A9_STANDBY_WFI_SHIFT 0 |
| #define GPC_A9_LPSR_A9_SCU_IDLE_MASK 0x10u |
| #define GPC_A9_LPSR_A9_SCU_IDLE_SHIFT 4 |
| #define GPC_A9_LPSR_A9_L2CC_IDLE_MASK 0x20u |
| #define GPC_A9_LPSR_A9_L2CC_IDLE_SHIFT 5 |
| #define GPC_A9_LPSR_A9_CLK_ENABLE_MASK 0x40u |
| #define GPC_A9_LPSR_A9_CLK_ENABLE_SHIFT 6 |
| #define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_MASK 0x80u |
| #define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_SHIFT 7 |
| #define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_MASK 0x100u |
| #define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_SHIFT 8 |
| #define GPC_A9_LPSR_A9_DBG_ACK_MASK 0x200u |
| #define GPC_A9_LPSR_A9_DBG_ACK_SHIFT 9 |
| #define GPC_A9_LPSR_A9_RST_MASK 0x400u |
| #define GPC_A9_LPSR_A9_RST_SHIFT 10 |
| /* M4_LPSR Bit Fields */ |
| #define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_MASK 0x1u |
| #define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_SHIFT 0 |
| #define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_MASK 0x2u |
| #define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_SHIFT 1 |
| #define GPC_M4_LPSR_M4_GATE_HCLK_MASK 0x4u |
| #define GPC_M4_LPSR_M4_GATE_HCLK_SHIFT 2 |
| #define GPC_M4_LPSR_M4_SLEEP_DEEP_MASK 0x8u |
| #define GPC_M4_LPSR_M4_SLEEP_DEEP_SHIFT 3 |
| #define GPC_M4_LPSR_M4_SLEEPING_MASK 0x10u |
| #define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 |
| #define GPC_M4_LPSR_M4_LOCKUP_MASK 0x20u |
| #define GPC_M4_LPSR_M4_LOCKUP_SHIFT 5 |
| #define GPC_M4_LPSR_M4_HALTED_MASK 0x40u |
| #define GPC_M4_LPSR_M4_HALTED_SHIFT 6 |
| #define GPC_M4_LPSR_M4_PLATFORM_RESET_B_MASK 0x80u |
| #define GPC_M4_LPSR_M4_PLATFORM_RESET_B_SHIFT 7 |
| #define GPC_M4_LPSR_M4_CORE_RESET_B_MASK 0x100u |
| #define GPC_M4_LPSR_M4_CORE_RESET_B_SHIFT 8 |
| /* DR Bit Fields */ |
| #define GPC_DR_PCIE_PHY_RESET_B_MASK 0x1u |
| #define GPC_DR_PCIE_PHY_RESET_B_SHIFT 0 |
| #define GPC_DR_PCIE_PHY_ISO_MASK 0x2u |
| #define GPC_DR_PCIE_PHY_ISO_SHIFT 1 |
| #define GPC_DR_MEGA_RESET_B_MASK 0x4u |
| #define GPC_DR_MEGA_RESET_B_SHIFT 2 |
| #define GPC_DR_MEGA_SWITCH_B_MASK 0x8u |
| #define GPC_DR_MEGA_SWITCH_B_SHIFT 3 |
| #define GPC_DR_MEGA_ISO_MASK 0x10u |
| #define GPC_DR_MEGA_ISO_SHIFT 4 |
| #define GPC_DR_GPC_PUP_ACK_MASK 0x20u |
| #define GPC_DR_GPC_PUP_ACK_SHIFT 5 |
| #define GPC_DR_GPC_PDN_ACK_MASK 0x40u |
| #define GPC_DR_GPC_PDN_ACK_SHIFT 6 |
| #define GPC_DR_GPC_DISP_RESET_B_MASK 0x80u |
| #define GPC_DR_GPC_DISP_RESET_B_SHIFT 7 |
| #define GPC_DR_GPC_DISP_SWITCH_B_MASK 0x100u |
| #define GPC_DR_GPC_DISP_SWITCH_B_SHIFT 8 |
| #define GPC_DR_GPC_DISP_ISO_MASK 0x200u |
| #define GPC_DR_GPC_DISP_ISO_SHIFT 9 |
| #define GPC_DR_GPC_GPU_RESET_B_MASK 0x400u |
| #define GPC_DR_GPC_GPU_RESET_B_SHIFT 10 |
| #define GPC_DR_GPC_GPU_SWITCH_B_MASK 0x800u |
| #define GPC_DR_GPC_GPU_SWITCH_B_SHIFT 11 |
| #define GPC_DR_GPC_GPU_ISO_MASK 0x1000u |
| #define GPC_DR_GPC_GPU_ISO_SHIFT 12 |
| #define GPC_DR_GPC_L2SOC_ISO_MASK 0x2000u |
| #define GPC_DR_GPC_L2SOC_ISO_SHIFT 13 |
| #define GPC_DR_GPC_L2CPU_ISO_MASK 0x4000u |
| #define GPC_DR_GPC_L2CPU_ISO_SHIFT 14 |
| #define GPC_DR_GPC_L2_SWITCH_B_MASK 0x8000u |
| #define GPC_DR_GPC_L2_SWITCH_B_SHIFT 15 |
| #define GPC_DR_GPC_CPU_RESET_B_MASK 0x10000u |
| #define GPC_DR_GPC_CPU_RESET_B_SHIFT 16 |
| #define GPC_DR_GPC_CPU_SWITCH_B_MASK 0x20000u |
| #define GPC_DR_GPC_CPU_SWITCH_B_SHIFT 17 |
| #define GPC_DR_GPC_CPU_ISO_MASK 0x40000u |
| #define GPC_DR_GPC_CPU_ISO_SHIFT 18 |
| #define GPC_DR_IPG_STOP_MASK 0x80000u |
| #define GPC_DR_IPG_STOP_SHIFT 19 |
| #define GPC_DR_IPG_WAIT_MASK 0x100000u |
| #define GPC_DR_IPG_WAIT_SHIFT 20 |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Register_Masks */ |
| |
| /* GPC - Peripheral instance base addresses */ |
| /** Peripheral GPC base address */ |
| #define GPC_BASE (0x420DC000u) |
| /** Peripheral GPC base pointer */ |
| #define GPC ((GPC_Type *)GPC_BASE) |
| #define GPC_BASE_PTR (GPC) |
| /** Array initializer of GPC peripheral base addresses */ |
| #define GPC_BASE_ADDRS { GPC_BASE } |
| /** Array initializer of GPC peripheral base pointers */ |
| #define GPC_BASE_PTRS { GPC } |
| /** Interrupt vectors for the GPC peripheral type */ |
| #define GPC_IRQS { GPC_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPC - Register instance definitions */ |
| /* GPC */ |
| #define GPC_CNTR GPC_CNTR_REG(GPC_BASE_PTR) |
| #define GPC_PGR GPC_PGR_REG(GPC_BASE_PTR) |
| #define GPC_IMR1 GPC_IMR1_REG(GPC_BASE_PTR) |
| #define GPC_IMR2 GPC_IMR2_REG(GPC_BASE_PTR) |
| #define GPC_IMR3 GPC_IMR3_REG(GPC_BASE_PTR) |
| #define GPC_IMR4 GPC_IMR4_REG(GPC_BASE_PTR) |
| #define GPC_ISR1 GPC_ISR1_REG(GPC_BASE_PTR) |
| #define GPC_ISR2 GPC_ISR2_REG(GPC_BASE_PTR) |
| #define GPC_ISR3 GPC_ISR3_REG(GPC_BASE_PTR) |
| #define GPC_ISR4 GPC_ISR4_REG(GPC_BASE_PTR) |
| #define GPC_A9_LPSR GPC_A9_LPSR_REG(GPC_BASE_PTR) |
| #define GPC_M4_LPSR GPC_M4_LPSR_REG(GPC_BASE_PTR) |
| #define GPC_DR GPC_DR_REG(GPC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group GPC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPIO - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ |
| __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ |
| __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ |
| __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ |
| __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ |
| __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ |
| __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ |
| __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ |
| } GPIO_Type, *GPIO_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPIO - Register accessors */ |
| #define GPIO_DR_REG(base) ((base)->DR) |
| #define GPIO_GDIR_REG(base) ((base)->GDIR) |
| #define GPIO_PSR_REG(base) ((base)->PSR) |
| #define GPIO_ICR1_REG(base) ((base)->ICR1) |
| #define GPIO_ICR2_REG(base) ((base)->ICR2) |
| #define GPIO_IMR_REG(base) ((base)->IMR) |
| #define GPIO_ISR_REG(base) ((base)->ISR) |
| #define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Register_Masks GPIO Register Masks |
| * @{ |
| */ |
| |
| /* DR Bit Fields */ |
| #define GPIO_DR_DR_MASK 0xFFFFFFFFu |
| #define GPIO_DR_DR_SHIFT 0 |
| #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_DR_DR_SHIFT))&GPIO_DR_DR_MASK) |
| /* GDIR Bit Fields */ |
| #define GPIO_GDIR_GDIR_MASK 0xFFFFFFFFu |
| #define GPIO_GDIR_GDIR_SHIFT 0 |
| #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_GDIR_GDIR_SHIFT))&GPIO_GDIR_GDIR_MASK) |
| /* PSR Bit Fields */ |
| #define GPIO_PSR_PSR_MASK 0xFFFFFFFFu |
| #define GPIO_PSR_PSR_SHIFT 0 |
| #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSR_PSR_SHIFT))&GPIO_PSR_PSR_MASK) |
| /* ICR1 Bit Fields */ |
| #define GPIO_ICR1_ICR0_MASK 0x3u |
| #define GPIO_ICR1_ICR0_SHIFT 0 |
| #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK) |
| #define GPIO_ICR1_ICR1_MASK 0xCu |
| #define GPIO_ICR1_ICR1_SHIFT 2 |
| #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR1_SHIFT))&GPIO_ICR1_ICR1_MASK) |
| #define GPIO_ICR1_ICR2_MASK 0x30u |
| #define GPIO_ICR1_ICR2_SHIFT 4 |
| #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR2_SHIFT))&GPIO_ICR1_ICR2_MASK) |
| #define GPIO_ICR1_ICR3_MASK 0xC0u |
| #define GPIO_ICR1_ICR3_SHIFT 6 |
| #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR3_SHIFT))&GPIO_ICR1_ICR3_MASK) |
| #define GPIO_ICR1_ICR4_MASK 0x300u |
| #define GPIO_ICR1_ICR4_SHIFT 8 |
| #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR4_SHIFT))&GPIO_ICR1_ICR4_MASK) |
| #define GPIO_ICR1_ICR5_MASK 0xC00u |
| #define GPIO_ICR1_ICR5_SHIFT 10 |
| #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR5_SHIFT))&GPIO_ICR1_ICR5_MASK) |
| #define GPIO_ICR1_ICR6_MASK 0x3000u |
| #define GPIO_ICR1_ICR6_SHIFT 12 |
| #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR6_SHIFT))&GPIO_ICR1_ICR6_MASK) |
| #define GPIO_ICR1_ICR7_MASK 0xC000u |
| #define GPIO_ICR1_ICR7_SHIFT 14 |
| #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR7_SHIFT))&GPIO_ICR1_ICR7_MASK) |
| #define GPIO_ICR1_ICR8_MASK 0x30000u |
| #define GPIO_ICR1_ICR8_SHIFT 16 |
| #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR8_SHIFT))&GPIO_ICR1_ICR8_MASK) |
| #define GPIO_ICR1_ICR9_MASK 0xC0000u |
| #define GPIO_ICR1_ICR9_SHIFT 18 |
| #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR9_SHIFT))&GPIO_ICR1_ICR9_MASK) |
| #define GPIO_ICR1_ICR10_MASK 0x300000u |
| #define GPIO_ICR1_ICR10_SHIFT 20 |
| #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR10_SHIFT))&GPIO_ICR1_ICR10_MASK) |
| #define GPIO_ICR1_ICR11_MASK 0xC00000u |
| #define GPIO_ICR1_ICR11_SHIFT 22 |
| #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR11_SHIFT))&GPIO_ICR1_ICR11_MASK) |
| #define GPIO_ICR1_ICR12_MASK 0x3000000u |
| #define GPIO_ICR1_ICR12_SHIFT 24 |
| #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR12_SHIFT))&GPIO_ICR1_ICR12_MASK) |
| #define GPIO_ICR1_ICR13_MASK 0xC000000u |
| #define GPIO_ICR1_ICR13_SHIFT 26 |
| #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR13_SHIFT))&GPIO_ICR1_ICR13_MASK) |
| #define GPIO_ICR1_ICR14_MASK 0x30000000u |
| #define GPIO_ICR1_ICR14_SHIFT 28 |
| #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR14_SHIFT))&GPIO_ICR1_ICR14_MASK) |
| #define GPIO_ICR1_ICR15_MASK 0xC0000000u |
| #define GPIO_ICR1_ICR15_SHIFT 30 |
| #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR15_SHIFT))&GPIO_ICR1_ICR15_MASK) |
| /* ICR2 Bit Fields */ |
| #define GPIO_ICR2_ICR16_MASK 0x3u |
| #define GPIO_ICR2_ICR16_SHIFT 0 |
| #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR16_SHIFT))&GPIO_ICR2_ICR16_MASK) |
| #define GPIO_ICR2_ICR17_MASK 0xCu |
| #define GPIO_ICR2_ICR17_SHIFT 2 |
| #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR17_SHIFT))&GPIO_ICR2_ICR17_MASK) |
| #define GPIO_ICR2_ICR18_MASK 0x30u |
| #define GPIO_ICR2_ICR18_SHIFT 4 |
| #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR18_SHIFT))&GPIO_ICR2_ICR18_MASK) |
| #define GPIO_ICR2_ICR19_MASK 0xC0u |
| #define GPIO_ICR2_ICR19_SHIFT 6 |
| #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR19_SHIFT))&GPIO_ICR2_ICR19_MASK) |
| #define GPIO_ICR2_ICR20_MASK 0x300u |
| #define GPIO_ICR2_ICR20_SHIFT 8 |
| #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR20_SHIFT))&GPIO_ICR2_ICR20_MASK) |
| #define GPIO_ICR2_ICR21_MASK 0xC00u |
| #define GPIO_ICR2_ICR21_SHIFT 10 |
| #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR21_SHIFT))&GPIO_ICR2_ICR21_MASK) |
| #define GPIO_ICR2_ICR22_MASK 0x3000u |
| #define GPIO_ICR2_ICR22_SHIFT 12 |
| #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR22_SHIFT))&GPIO_ICR2_ICR22_MASK) |
| #define GPIO_ICR2_ICR23_MASK 0xC000u |
| #define GPIO_ICR2_ICR23_SHIFT 14 |
| #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR23_SHIFT))&GPIO_ICR2_ICR23_MASK) |
| #define GPIO_ICR2_ICR24_MASK 0x30000u |
| #define GPIO_ICR2_ICR24_SHIFT 16 |
| #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR24_SHIFT))&GPIO_ICR2_ICR24_MASK) |
| #define GPIO_ICR2_ICR25_MASK 0xC0000u |
| #define GPIO_ICR2_ICR25_SHIFT 18 |
| #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR25_SHIFT))&GPIO_ICR2_ICR25_MASK) |
| #define GPIO_ICR2_ICR26_MASK 0x300000u |
| #define GPIO_ICR2_ICR26_SHIFT 20 |
| #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR26_SHIFT))&GPIO_ICR2_ICR26_MASK) |
| #define GPIO_ICR2_ICR27_MASK 0xC00000u |
| #define GPIO_ICR2_ICR27_SHIFT 22 |
| #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR27_SHIFT))&GPIO_ICR2_ICR27_MASK) |
| #define GPIO_ICR2_ICR28_MASK 0x3000000u |
| #define GPIO_ICR2_ICR28_SHIFT 24 |
| #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR28_SHIFT))&GPIO_ICR2_ICR28_MASK) |
| #define GPIO_ICR2_ICR29_MASK 0xC000000u |
| #define GPIO_ICR2_ICR29_SHIFT 26 |
| #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR29_SHIFT))&GPIO_ICR2_ICR29_MASK) |
| #define GPIO_ICR2_ICR30_MASK 0x30000000u |
| #define GPIO_ICR2_ICR30_SHIFT 28 |
| #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR30_SHIFT))&GPIO_ICR2_ICR30_MASK) |
| #define GPIO_ICR2_ICR31_MASK 0xC0000000u |
| #define GPIO_ICR2_ICR31_SHIFT 30 |
| #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR31_SHIFT))&GPIO_ICR2_ICR31_MASK) |
| /* IMR Bit Fields */ |
| #define GPIO_IMR_IMR_MASK 0xFFFFFFFFu |
| #define GPIO_IMR_IMR_SHIFT 0 |
| #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_IMR_IMR_SHIFT))&GPIO_IMR_IMR_MASK) |
| /* ISR Bit Fields */ |
| #define GPIO_ISR_ISR_MASK 0xFFFFFFFFu |
| #define GPIO_ISR_ISR_SHIFT 0 |
| #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ISR_ISR_SHIFT))&GPIO_ISR_ISR_MASK) |
| /* EDGE_SEL Bit Fields */ |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK 0xFFFFFFFFu |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT 0 |
| #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT))&GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Register_Masks */ |
| |
| /* GPIO - Peripheral instance base addresses */ |
| /** Peripheral GPIO1 base address */ |
| #define GPIO1_BASE (0x4209C000u) |
| /** Peripheral GPIO1 base pointer */ |
| #define GPIO1 ((GPIO_Type *)GPIO1_BASE) |
| #define GPIO1_BASE_PTR (GPIO1) |
| /** Peripheral GPIO2 base address */ |
| #define GPIO2_BASE (0x420A0000u) |
| /** Peripheral GPIO2 base pointer */ |
| #define GPIO2 ((GPIO_Type *)GPIO2_BASE) |
| #define GPIO2_BASE_PTR (GPIO2) |
| /** Peripheral GPIO3 base address */ |
| #define GPIO3_BASE (0x420A4000u) |
| /** Peripheral GPIO3 base pointer */ |
| #define GPIO3 ((GPIO_Type *)GPIO3_BASE) |
| #define GPIO3_BASE_PTR (GPIO3) |
| /** Peripheral GPIO4 base address */ |
| #define GPIO4_BASE (0x420A8000u) |
| /** Peripheral GPIO4 base pointer */ |
| #define GPIO4 ((GPIO_Type *)GPIO4_BASE) |
| #define GPIO4_BASE_PTR (GPIO4) |
| /** Peripheral GPIO5 base address */ |
| #define GPIO5_BASE (0x420AC000u) |
| /** Peripheral GPIO5 base pointer */ |
| #define GPIO5 ((GPIO_Type *)GPIO5_BASE) |
| #define GPIO5_BASE_PTR (GPIO5) |
| /** Peripheral GPIO6 base address */ |
| #define GPIO6_BASE (0x420B0000u) |
| /** Peripheral GPIO6 base pointer */ |
| #define GPIO6 ((GPIO_Type *)GPIO6_BASE) |
| #define GPIO6_BASE_PTR (GPIO6) |
| /** Peripheral GPIO7 base address */ |
| #define GPIO7_BASE (0x420B4000u) |
| /** Peripheral GPIO7 base pointer */ |
| #define GPIO7 ((GPIO_Type *)GPIO7_BASE) |
| #define GPIO7_BASE_PTR (GPIO7) |
| /** Array initializer of GPIO peripheral base addresses */ |
| #define GPIO_BASE_ADDRS { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE } |
| /** Array initializer of GPIO peripheral base pointers */ |
| #define GPIO_BASE_PTRS { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7 } |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPIO - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPIO - Register instance definitions */ |
| /* GPIO1 */ |
| #define GPIO1_DR GPIO_DR_REG(GPIO1_BASE_PTR) |
| #define GPIO1_GDIR GPIO_GDIR_REG(GPIO1_BASE_PTR) |
| #define GPIO1_PSR GPIO_PSR_REG(GPIO1_BASE_PTR) |
| #define GPIO1_ICR1 GPIO_ICR1_REG(GPIO1_BASE_PTR) |
| #define GPIO1_ICR2 GPIO_ICR2_REG(GPIO1_BASE_PTR) |
| #define GPIO1_IMR GPIO_IMR_REG(GPIO1_BASE_PTR) |
| #define GPIO1_ISR GPIO_ISR_REG(GPIO1_BASE_PTR) |
| #define GPIO1_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO1_BASE_PTR) |
| /* GPIO2 */ |
| #define GPIO2_DR GPIO_DR_REG(GPIO2_BASE_PTR) |
| #define GPIO2_GDIR GPIO_GDIR_REG(GPIO2_BASE_PTR) |
| #define GPIO2_PSR GPIO_PSR_REG(GPIO2_BASE_PTR) |
| #define GPIO2_ICR1 GPIO_ICR1_REG(GPIO2_BASE_PTR) |
| #define GPIO2_ICR2 GPIO_ICR2_REG(GPIO2_BASE_PTR) |
| #define GPIO2_IMR GPIO_IMR_REG(GPIO2_BASE_PTR) |
| #define GPIO2_ISR GPIO_ISR_REG(GPIO2_BASE_PTR) |
| #define GPIO2_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO2_BASE_PTR) |
| /* GPIO3 */ |
| #define GPIO3_DR GPIO_DR_REG(GPIO3_BASE_PTR) |
| #define GPIO3_GDIR GPIO_GDIR_REG(GPIO3_BASE_PTR) |
| #define GPIO3_PSR GPIO_PSR_REG(GPIO3_BASE_PTR) |
| #define GPIO3_ICR1 GPIO_ICR1_REG(GPIO3_BASE_PTR) |
| #define GPIO3_ICR2 GPIO_ICR2_REG(GPIO3_BASE_PTR) |
| #define GPIO3_IMR GPIO_IMR_REG(GPIO3_BASE_PTR) |
| #define GPIO3_ISR GPIO_ISR_REG(GPIO3_BASE_PTR) |
| #define GPIO3_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO3_BASE_PTR) |
| /* GPIO4 */ |
| #define GPIO4_DR GPIO_DR_REG(GPIO4_BASE_PTR) |
| #define GPIO4_GDIR GPIO_GDIR_REG(GPIO4_BASE_PTR) |
| #define GPIO4_PSR GPIO_PSR_REG(GPIO4_BASE_PTR) |
| #define GPIO4_ICR1 GPIO_ICR1_REG(GPIO4_BASE_PTR) |
| #define GPIO4_ICR2 GPIO_ICR2_REG(GPIO4_BASE_PTR) |
| #define GPIO4_IMR GPIO_IMR_REG(GPIO4_BASE_PTR) |
| #define GPIO4_ISR GPIO_ISR_REG(GPIO4_BASE_PTR) |
| #define GPIO4_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO4_BASE_PTR) |
| /* GPIO5 */ |
| #define GPIO5_DR GPIO_DR_REG(GPIO5_BASE_PTR) |
| #define GPIO5_GDIR GPIO_GDIR_REG(GPIO5_BASE_PTR) |
| #define GPIO5_PSR GPIO_PSR_REG(GPIO5_BASE_PTR) |
| #define GPIO5_ICR1 GPIO_ICR1_REG(GPIO5_BASE_PTR) |
| #define GPIO5_ICR2 GPIO_ICR2_REG(GPIO5_BASE_PTR) |
| #define GPIO5_IMR GPIO_IMR_REG(GPIO5_BASE_PTR) |
| #define GPIO5_ISR GPIO_ISR_REG(GPIO5_BASE_PTR) |
| #define GPIO5_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO5_BASE_PTR) |
| /* GPIO6 */ |
| #define GPIO6_DR GPIO_DR_REG(GPIO6_BASE_PTR) |
| #define GPIO6_GDIR GPIO_GDIR_REG(GPIO6_BASE_PTR) |
| #define GPIO6_PSR GPIO_PSR_REG(GPIO6_BASE_PTR) |
| #define GPIO6_ICR1 GPIO_ICR1_REG(GPIO6_BASE_PTR) |
| #define GPIO6_ICR2 GPIO_ICR2_REG(GPIO6_BASE_PTR) |
| #define GPIO6_IMR GPIO_IMR_REG(GPIO6_BASE_PTR) |
| #define GPIO6_ISR GPIO_ISR_REG(GPIO6_BASE_PTR) |
| #define GPIO6_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO6_BASE_PTR) |
| /* GPIO7 */ |
| #define GPIO7_DR GPIO_DR_REG(GPIO7_BASE_PTR) |
| #define GPIO7_GDIR GPIO_GDIR_REG(GPIO7_BASE_PTR) |
| #define GPIO7_PSR GPIO_PSR_REG(GPIO7_BASE_PTR) |
| #define GPIO7_ICR1 GPIO_ICR1_REG(GPIO7_BASE_PTR) |
| #define GPIO7_ICR2 GPIO_ICR2_REG(GPIO7_BASE_PTR) |
| #define GPIO7_IMR GPIO_IMR_REG(GPIO7_BASE_PTR) |
| #define GPIO7_ISR GPIO_ISR_REG(GPIO7_BASE_PTR) |
| #define GPIO7_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO7_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group GPIO_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPMI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ |
| __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ |
| __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ |
| __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ |
| __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ |
| __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ |
| __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ |
| __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ |
| __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ |
| __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ |
| __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ |
| __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ |
| __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ |
| uint8_t RESERVED_7[12]; |
| __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ |
| uint8_t RESERVED_8[12]; |
| __I uint32_t DEBUG; /**< GPMI Debug Information Register Description, offset: 0xC0 */ |
| uint8_t RESERVED_9[12]; |
| __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ |
| uint8_t RESERVED_11[12]; |
| __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ |
| uint8_t RESERVED_14[12]; |
| __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ |
| uint8_t RESERVED_15[12]; |
| __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ |
| } GPMI_Type, *GPMI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPMI - Register accessors */ |
| #define GPMI_CTRL0_REG(base) ((base)->CTRL0) |
| #define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) |
| #define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) |
| #define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) |
| #define GPMI_COMPARE_REG(base) ((base)->COMPARE) |
| #define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) |
| #define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) |
| #define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) |
| #define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) |
| #define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) |
| #define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) |
| #define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) |
| #define GPMI_CTRL1_REG(base) ((base)->CTRL1) |
| #define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) |
| #define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) |
| #define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) |
| #define GPMI_TIMING0_REG(base) ((base)->TIMING0) |
| #define GPMI_TIMING1_REG(base) ((base)->TIMING1) |
| #define GPMI_TIMING2_REG(base) ((base)->TIMING2) |
| #define GPMI_DATA_REG(base) ((base)->DATA) |
| #define GPMI_STAT_REG(base) ((base)->STAT) |
| #define GPMI_DEBUG_REG(base) ((base)->DEBUG) |
| #define GPMI_VERSION_REG(base) ((base)->VERSION) |
| #define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) |
| #define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) |
| #define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REG(base) ((base)->WRITE_DDR_DLL_CTRL) |
| #define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) |
| #define GPMI_WRITE_DDR_DLL_STS_REG(base) ((base)->WRITE_DDR_DLL_STS) |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Register_Masks GPMI Register Masks |
| * @{ |
| */ |
| |
| /* CTRL0 Bit Fields */ |
| #define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu |
| #define GPMI_CTRL0_XFER_COUNT_SHIFT 0 |
| #define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_XFER_COUNT_SHIFT))&GPMI_CTRL0_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_ADDRESS_INCREMENT_MASK 0x10000u |
| #define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT 16 |
| #define GPMI_CTRL0_ADDRESS_MASK 0xE0000u |
| #define GPMI_CTRL0_ADDRESS_SHIFT 17 |
| #define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_ADDRESS_SHIFT))&GPMI_CTRL0_ADDRESS_MASK) |
| #define GPMI_CTRL0_CS_MASK 0x700000u |
| #define GPMI_CTRL0_CS_SHIFT 20 |
| #define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CS_SHIFT))&GPMI_CTRL0_CS_MASK) |
| #define GPMI_CTRL0_WORD_LENGTH_MASK 0x800000u |
| #define GPMI_CTRL0_WORD_LENGTH_SHIFT 23 |
| #define GPMI_CTRL0_COMMAND_MODE_MASK 0x3000000u |
| #define GPMI_CTRL0_COMMAND_MODE_SHIFT 24 |
| #define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_COMMAND_MODE_SHIFT))&GPMI_CTRL0_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_UDMA_MASK 0x4000000u |
| #define GPMI_CTRL0_UDMA_SHIFT 26 |
| #define GPMI_CTRL0_LOCK_CS_MASK 0x8000000u |
| #define GPMI_CTRL0_LOCK_CS_SHIFT 27 |
| #define GPMI_CTRL0_DEV_IRQ_EN_MASK 0x10000000u |
| #define GPMI_CTRL0_DEV_IRQ_EN_SHIFT 28 |
| #define GPMI_CTRL0_RUN_MASK 0x20000000u |
| #define GPMI_CTRL0_RUN_SHIFT 29 |
| #define GPMI_CTRL0_CLKGATE_MASK 0x40000000u |
| #define GPMI_CTRL0_CLKGATE_SHIFT 30 |
| #define GPMI_CTRL0_SFTRST_MASK 0x80000000u |
| #define GPMI_CTRL0_SFTRST_SHIFT 31 |
| /* CTRL0_SET Bit Fields */ |
| #define GPMI_CTRL0_SET_XFER_COUNT_MASK 0xFFFFu |
| #define GPMI_CTRL0_SET_XFER_COUNT_SHIFT 0 |
| #define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_XFER_COUNT_SHIFT))&GPMI_CTRL0_SET_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK 0x10000u |
| #define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT 16 |
| #define GPMI_CTRL0_SET_ADDRESS_MASK 0xE0000u |
| #define GPMI_CTRL0_SET_ADDRESS_SHIFT 17 |
| #define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_ADDRESS_SHIFT))&GPMI_CTRL0_SET_ADDRESS_MASK) |
| #define GPMI_CTRL0_SET_CS_MASK 0x700000u |
| #define GPMI_CTRL0_SET_CS_SHIFT 20 |
| #define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_CS_SHIFT))&GPMI_CTRL0_SET_CS_MASK) |
| #define GPMI_CTRL0_SET_WORD_LENGTH_MASK 0x800000u |
| #define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT 23 |
| #define GPMI_CTRL0_SET_COMMAND_MODE_MASK 0x3000000u |
| #define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT 24 |
| #define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_COMMAND_MODE_SHIFT))&GPMI_CTRL0_SET_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_SET_UDMA_MASK 0x4000000u |
| #define GPMI_CTRL0_SET_UDMA_SHIFT 26 |
| #define GPMI_CTRL0_SET_LOCK_CS_MASK 0x8000000u |
| #define GPMI_CTRL0_SET_LOCK_CS_SHIFT 27 |
| #define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK 0x10000000u |
| #define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT 28 |
| #define GPMI_CTRL0_SET_RUN_MASK 0x20000000u |
| #define GPMI_CTRL0_SET_RUN_SHIFT 29 |
| #define GPMI_CTRL0_SET_CLKGATE_MASK 0x40000000u |
| #define GPMI_CTRL0_SET_CLKGATE_SHIFT 30 |
| #define GPMI_CTRL0_SET_SFTRST_MASK 0x80000000u |
| #define GPMI_CTRL0_SET_SFTRST_SHIFT 31 |
| /* CTRL0_CLR Bit Fields */ |
| #define GPMI_CTRL0_CLR_XFER_COUNT_MASK 0xFFFFu |
| #define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT 0 |
| #define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_XFER_COUNT_SHIFT))&GPMI_CTRL0_CLR_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK 0x10000u |
| #define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT 16 |
| #define GPMI_CTRL0_CLR_ADDRESS_MASK 0xE0000u |
| #define GPMI_CTRL0_CLR_ADDRESS_SHIFT 17 |
| #define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_ADDRESS_SHIFT))&GPMI_CTRL0_CLR_ADDRESS_MASK) |
| #define GPMI_CTRL0_CLR_CS_MASK 0x700000u |
| #define GPMI_CTRL0_CLR_CS_SHIFT 20 |
| #define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_CS_SHIFT))&GPMI_CTRL0_CLR_CS_MASK) |
| #define GPMI_CTRL0_CLR_WORD_LENGTH_MASK 0x800000u |
| #define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT 23 |
| #define GPMI_CTRL0_CLR_COMMAND_MODE_MASK 0x3000000u |
| #define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT 24 |
| #define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT))&GPMI_CTRL0_CLR_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_CLR_UDMA_MASK 0x4000000u |
| #define GPMI_CTRL0_CLR_UDMA_SHIFT 26 |
| #define GPMI_CTRL0_CLR_LOCK_CS_MASK 0x8000000u |
| #define GPMI_CTRL0_CLR_LOCK_CS_SHIFT 27 |
| #define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK 0x10000000u |
| #define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT 28 |
| #define GPMI_CTRL0_CLR_RUN_MASK 0x20000000u |
| #define GPMI_CTRL0_CLR_RUN_SHIFT 29 |
| #define GPMI_CTRL0_CLR_CLKGATE_MASK 0x40000000u |
| #define GPMI_CTRL0_CLR_CLKGATE_SHIFT 30 |
| #define GPMI_CTRL0_CLR_SFTRST_MASK 0x80000000u |
| #define GPMI_CTRL0_CLR_SFTRST_SHIFT 31 |
| /* CTRL0_TOG Bit Fields */ |
| #define GPMI_CTRL0_TOG_XFER_COUNT_MASK 0xFFFFu |
| #define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT 0 |
| #define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_XFER_COUNT_SHIFT))&GPMI_CTRL0_TOG_XFER_COUNT_MASK) |
| #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK 0x10000u |
| #define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT 16 |
| #define GPMI_CTRL0_TOG_ADDRESS_MASK 0xE0000u |
| #define GPMI_CTRL0_TOG_ADDRESS_SHIFT 17 |
| #define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_ADDRESS_SHIFT))&GPMI_CTRL0_TOG_ADDRESS_MASK) |
| #define GPMI_CTRL0_TOG_CS_MASK 0x700000u |
| #define GPMI_CTRL0_TOG_CS_SHIFT 20 |
| #define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_CS_SHIFT))&GPMI_CTRL0_TOG_CS_MASK) |
| #define GPMI_CTRL0_TOG_WORD_LENGTH_MASK 0x800000u |
| #define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT 23 |
| #define GPMI_CTRL0_TOG_COMMAND_MODE_MASK 0x3000000u |
| #define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT 24 |
| #define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT))&GPMI_CTRL0_TOG_COMMAND_MODE_MASK) |
| #define GPMI_CTRL0_TOG_UDMA_MASK 0x4000000u |
| #define GPMI_CTRL0_TOG_UDMA_SHIFT 26 |
| #define GPMI_CTRL0_TOG_LOCK_CS_MASK 0x8000000u |
| #define GPMI_CTRL0_TOG_LOCK_CS_SHIFT 27 |
| #define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK 0x10000000u |
| #define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT 28 |
| #define GPMI_CTRL0_TOG_RUN_MASK 0x20000000u |
| #define GPMI_CTRL0_TOG_RUN_SHIFT 29 |
| #define GPMI_CTRL0_TOG_CLKGATE_MASK 0x40000000u |
| #define GPMI_CTRL0_TOG_CLKGATE_SHIFT 30 |
| #define GPMI_CTRL0_TOG_SFTRST_MASK 0x80000000u |
| #define GPMI_CTRL0_TOG_SFTRST_SHIFT 31 |
| /* COMPARE Bit Fields */ |
| #define GPMI_COMPARE_REFERENCE_MASK 0xFFFFu |
| #define GPMI_COMPARE_REFERENCE_SHIFT 0 |
| #define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_REFERENCE_SHIFT))&GPMI_COMPARE_REFERENCE_MASK) |
| #define GPMI_COMPARE_MASK_MASK 0xFFFF0000u |
| #define GPMI_COMPARE_MASK_SHIFT 16 |
| #define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_MASK_SHIFT))&GPMI_COMPARE_MASK_MASK) |
| /* ECCCTRL Bit Fields */ |
| #define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1FFu |
| #define GPMI_ECCCTRL_BUFFER_MASK_SHIFT 0 |
| #define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK 0x800u |
| #define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT 11 |
| #define GPMI_ECCCTRL_ENABLE_ECC_MASK 0x1000u |
| #define GPMI_ECCCTRL_ENABLE_ECC_SHIFT 12 |
| #define GPMI_ECCCTRL_ECC_CMD_MASK 0x6000u |
| #define GPMI_ECCCTRL_ECC_CMD_SHIFT 13 |
| #define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_ECC_CMD_SHIFT))&GPMI_ECCCTRL_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_RSVD2_MASK 0x8000u |
| #define GPMI_ECCCTRL_RSVD2_SHIFT 15 |
| #define GPMI_ECCCTRL_HANDLE_MASK 0xFFFF0000u |
| #define GPMI_ECCCTRL_HANDLE_SHIFT 16 |
| #define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_HANDLE_SHIFT))&GPMI_ECCCTRL_HANDLE_MASK) |
| /* ECCCTRL_SET Bit Fields */ |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK 0x1FFu |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT 0 |
| #define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK 0x800u |
| #define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT 11 |
| #define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK 0x1000u |
| #define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT 12 |
| #define GPMI_ECCCTRL_SET_ECC_CMD_MASK 0x6000u |
| #define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT 13 |
| #define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_ECC_CMD_SHIFT))&GPMI_ECCCTRL_SET_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_SET_RSVD2_MASK 0x8000u |
| #define GPMI_ECCCTRL_SET_RSVD2_SHIFT 15 |
| #define GPMI_ECCCTRL_SET_HANDLE_MASK 0xFFFF0000u |
| #define GPMI_ECCCTRL_SET_HANDLE_SHIFT 16 |
| #define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_HANDLE_SHIFT))&GPMI_ECCCTRL_SET_HANDLE_MASK) |
| /* ECCCTRL_CLR Bit Fields */ |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK 0x1FFu |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT 0 |
| #define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK 0x800u |
| #define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT 11 |
| #define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK 0x1000u |
| #define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT 12 |
| #define GPMI_ECCCTRL_CLR_ECC_CMD_MASK 0x6000u |
| #define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT 13 |
| #define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT))&GPMI_ECCCTRL_CLR_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_CLR_RSVD2_MASK 0x8000u |
| #define GPMI_ECCCTRL_CLR_RSVD2_SHIFT 15 |
| #define GPMI_ECCCTRL_CLR_HANDLE_MASK 0xFFFF0000u |
| #define GPMI_ECCCTRL_CLR_HANDLE_SHIFT 16 |
| #define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_HANDLE_SHIFT))&GPMI_ECCCTRL_CLR_HANDLE_MASK) |
| /* ECCCTRL_TOG Bit Fields */ |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK 0x1FFu |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT 0 |
| #define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK 0x800u |
| #define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT 11 |
| #define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK 0x1000u |
| #define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT 12 |
| #define GPMI_ECCCTRL_TOG_ECC_CMD_MASK 0x6000u |
| #define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT 13 |
| #define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT))&GPMI_ECCCTRL_TOG_ECC_CMD_MASK) |
| #define GPMI_ECCCTRL_TOG_RSVD2_MASK 0x8000u |
| #define GPMI_ECCCTRL_TOG_RSVD2_SHIFT 15 |
| #define GPMI_ECCCTRL_TOG_HANDLE_MASK 0xFFFF0000u |
| #define GPMI_ECCCTRL_TOG_HANDLE_SHIFT 16 |
| #define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_HANDLE_SHIFT))&GPMI_ECCCTRL_TOG_HANDLE_MASK) |
| /* ECCCOUNT Bit Fields */ |
| #define GPMI_ECCCOUNT_COUNT_MASK 0xFFFFu |
| #define GPMI_ECCCOUNT_COUNT_SHIFT 0 |
| #define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_COUNT_SHIFT))&GPMI_ECCCOUNT_COUNT_MASK) |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK 0xFF0000u |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT 16 |
| #define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT))&GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK) |
| /* PAYLOAD Bit Fields */ |
| #define GPMI_PAYLOAD_RSVD0_MASK 0x3u |
| #define GPMI_PAYLOAD_RSVD0_SHIFT 0 |
| #define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_RSVD0_SHIFT))&GPMI_PAYLOAD_RSVD0_MASK) |
| #define GPMI_PAYLOAD_ADDRESS_MASK 0xFFFFFFFCu |
| #define GPMI_PAYLOAD_ADDRESS_SHIFT 2 |
| #define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_ADDRESS_SHIFT))&GPMI_PAYLOAD_ADDRESS_MASK) |
| /* AUXILIARY Bit Fields */ |
| #define GPMI_AUXILIARY_RSVD0_MASK 0x3u |
| #define GPMI_AUXILIARY_RSVD0_SHIFT 0 |
| #define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_RSVD0_SHIFT))&GPMI_AUXILIARY_RSVD0_MASK) |
| #define GPMI_AUXILIARY_ADDRESS_MASK 0xFFFFFFFCu |
| #define GPMI_AUXILIARY_ADDRESS_SHIFT 2 |
| #define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_ADDRESS_SHIFT))&GPMI_AUXILIARY_ADDRESS_MASK) |
| /* CTRL1 Bit Fields */ |
| #define GPMI_CTRL1_GPMI_MODE_MASK 0x1u |
| #define GPMI_CTRL1_GPMI_MODE_SHIFT 0 |
| #define GPMI_CTRL1_CAMERA_MODE_MASK 0x2u |
| #define GPMI_CTRL1_CAMERA_MODE_SHIFT 1 |
| #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK 0x4u |
| #define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT 2 |
| #define GPMI_CTRL1_DEV_RESET_MASK 0x8u |
| #define GPMI_CTRL1_DEV_RESET_SHIFT 3 |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 |
| #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK 0x80u |
| #define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT 7 |
| #define GPMI_CTRL1_BURST_EN_MASK 0x100u |
| #define GPMI_CTRL1_BURST_EN_SHIFT 8 |
| #define GPMI_CTRL1_TIMEOUT_IRQ_MASK 0x200u |
| #define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT 9 |
| #define GPMI_CTRL1_DEV_IRQ_MASK 0x400u |
| #define GPMI_CTRL1_DEV_IRQ_SHIFT 10 |
| #define GPMI_CTRL1_DMA2ECC_MODE_MASK 0x800u |
| #define GPMI_CTRL1_DMA2ECC_MODE_SHIFT 11 |
| #define GPMI_CTRL1_RDN_DELAY_MASK 0xF000u |
| #define GPMI_CTRL1_RDN_DELAY_SHIFT 12 |
| #define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_RDN_DELAY_SHIFT))&GPMI_CTRL1_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_HALF_PERIOD_MASK 0x10000u |
| #define GPMI_CTRL1_HALF_PERIOD_SHIFT 16 |
| #define GPMI_CTRL1_DLL_ENABLE_MASK 0x20000u |
| #define GPMI_CTRL1_DLL_ENABLE_SHIFT 17 |
| #define GPMI_CTRL1_BCH_MODE_MASK 0x40000u |
| #define GPMI_CTRL1_BCH_MODE_SHIFT 18 |
| #define GPMI_CTRL1_GANGED_RDYBUSY_MASK 0x80000u |
| #define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT 19 |
| #define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK 0x100000u |
| #define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT 20 |
| #define GPMI_CTRL1_TEST_TRIGGER_MASK 0x200000u |
| #define GPMI_CTRL1_TEST_TRIGGER_SHIFT 21 |
| #define GPMI_CTRL1_WRN_DLY_SEL_MASK 0xC00000u |
| #define GPMI_CTRL1_WRN_DLY_SEL_SHIFT 22 |
| #define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_DECOUPLE_CS_MASK 0x1000000u |
| #define GPMI_CTRL1_DECOUPLE_CS_SHIFT 24 |
| #define GPMI_CTRL1_SSYNCMODE_MASK 0x2000000u |
| #define GPMI_CTRL1_SSYNCMODE_SHIFT 25 |
| #define GPMI_CTRL1_UPDATE_CS_MASK 0x4000000u |
| #define GPMI_CTRL1_UPDATE_CS_SHIFT 26 |
| #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK 0x8000000u |
| #define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT 27 |
| #define GPMI_CTRL1_TOGGLE_MODE_MASK 0x10000000u |
| #define GPMI_CTRL1_TOGGLE_MODE_SHIFT 28 |
| #define GPMI_CTRL1_WRITE_CLK_STOP_MASK 0x20000000u |
| #define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT 29 |
| #define GPMI_CTRL1_SSYNC_CLK_STOP_MASK 0x40000000u |
| #define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT 30 |
| #define GPMI_CTRL1_DEV_CLK_STOP_MASK 0x80000000u |
| #define GPMI_CTRL1_DEV_CLK_STOP_SHIFT 31 |
| /* CTRL1_SET Bit Fields */ |
| #define GPMI_CTRL1_SET_GPMI_MODE_MASK 0x1u |
| #define GPMI_CTRL1_SET_GPMI_MODE_SHIFT 0 |
| #define GPMI_CTRL1_SET_CAMERA_MODE_MASK 0x2u |
| #define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT 1 |
| #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK 0x4u |
| #define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT 2 |
| #define GPMI_CTRL1_SET_DEV_RESET_MASK 0x8u |
| #define GPMI_CTRL1_SET_DEV_RESET_SHIFT 3 |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 |
| #define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK 0x80u |
| #define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT 7 |
| #define GPMI_CTRL1_SET_BURST_EN_MASK 0x100u |
| #define GPMI_CTRL1_SET_BURST_EN_SHIFT 8 |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK 0x200u |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT 9 |
| #define GPMI_CTRL1_SET_DEV_IRQ_MASK 0x400u |
| #define GPMI_CTRL1_SET_DEV_IRQ_SHIFT 10 |
| #define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK 0x800u |
| #define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT 11 |
| #define GPMI_CTRL1_SET_RDN_DELAY_MASK 0xF000u |
| #define GPMI_CTRL1_SET_RDN_DELAY_SHIFT 12 |
| #define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_RDN_DELAY_SHIFT))&GPMI_CTRL1_SET_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_SET_HALF_PERIOD_MASK 0x10000u |
| #define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT 16 |
| #define GPMI_CTRL1_SET_DLL_ENABLE_MASK 0x20000u |
| #define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT 17 |
| #define GPMI_CTRL1_SET_BCH_MODE_MASK 0x40000u |
| #define GPMI_CTRL1_SET_BCH_MODE_SHIFT 18 |
| #define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK 0x80000u |
| #define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT 19 |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK 0x100000u |
| #define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT 20 |
| #define GPMI_CTRL1_SET_TEST_TRIGGER_MASK 0x200000u |
| #define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT 21 |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK 0xC00000u |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT 22 |
| #define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_SET_DECOUPLE_CS_MASK 0x1000000u |
| #define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT 24 |
| #define GPMI_CTRL1_SET_SSYNCMODE_MASK 0x2000000u |
| #define GPMI_CTRL1_SET_SSYNCMODE_SHIFT 25 |
| #define GPMI_CTRL1_SET_UPDATE_CS_MASK 0x4000000u |
| #define GPMI_CTRL1_SET_UPDATE_CS_SHIFT 26 |
| #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK 0x8000000u |
| #define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT 27 |
| #define GPMI_CTRL1_SET_TOGGLE_MODE_MASK 0x10000000u |
| #define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT 28 |
| #define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK 0x20000000u |
| #define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT 29 |
| #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK 0x40000000u |
| #define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT 30 |
| #define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK 0x80000000u |
| #define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT 31 |
| /* CTRL1_CLR Bit Fields */ |
| #define GPMI_CTRL1_CLR_GPMI_MODE_MASK 0x1u |
| #define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT 0 |
| #define GPMI_CTRL1_CLR_CAMERA_MODE_MASK 0x2u |
| #define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT 1 |
| #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK 0x4u |
| #define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT 2 |
| #define GPMI_CTRL1_CLR_DEV_RESET_MASK 0x8u |
| #define GPMI_CTRL1_CLR_DEV_RESET_SHIFT 3 |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK 0x80u |
| #define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT 7 |
| #define GPMI_CTRL1_CLR_BURST_EN_MASK 0x100u |
| #define GPMI_CTRL1_CLR_BURST_EN_SHIFT 8 |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK 0x200u |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT 9 |
| #define GPMI_CTRL1_CLR_DEV_IRQ_MASK 0x400u |
| #define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT 10 |
| #define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK 0x800u |
| #define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT 11 |
| #define GPMI_CTRL1_CLR_RDN_DELAY_MASK 0xF000u |
| #define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT 12 |
| #define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_RDN_DELAY_SHIFT))&GPMI_CTRL1_CLR_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_CLR_HALF_PERIOD_MASK 0x10000u |
| #define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT 16 |
| #define GPMI_CTRL1_CLR_DLL_ENABLE_MASK 0x20000u |
| #define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT 17 |
| #define GPMI_CTRL1_CLR_BCH_MODE_MASK 0x40000u |
| #define GPMI_CTRL1_CLR_BCH_MODE_SHIFT 18 |
| #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK 0x80000u |
| #define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT 19 |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK 0x100000u |
| #define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT 20 |
| #define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK 0x200000u |
| #define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT 21 |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK 0xC00000u |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT 22 |
| #define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK 0x1000000u |
| #define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT 24 |
| #define GPMI_CTRL1_CLR_SSYNCMODE_MASK 0x2000000u |
| #define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT 25 |
| #define GPMI_CTRL1_CLR_UPDATE_CS_MASK 0x4000000u |
| #define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT 26 |
| #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK 0x8000000u |
| #define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT 27 |
| #define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK 0x10000000u |
| #define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT 28 |
| #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK 0x20000000u |
| #define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT 29 |
| #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK 0x40000000u |
| #define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT 30 |
| #define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK 0x80000000u |
| #define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT 31 |
| /* CTRL1_TOG Bit Fields */ |
| #define GPMI_CTRL1_TOG_GPMI_MODE_MASK 0x1u |
| #define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT 0 |
| #define GPMI_CTRL1_TOG_CAMERA_MODE_MASK 0x2u |
| #define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT 1 |
| #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK 0x4u |
| #define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT 2 |
| #define GPMI_CTRL1_TOG_DEV_RESET_MASK 0x8u |
| #define GPMI_CTRL1_TOG_DEV_RESET_SHIFT 3 |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK 0x80u |
| #define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT 7 |
| #define GPMI_CTRL1_TOG_BURST_EN_MASK 0x100u |
| #define GPMI_CTRL1_TOG_BURST_EN_SHIFT 8 |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK 0x200u |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT 9 |
| #define GPMI_CTRL1_TOG_DEV_IRQ_MASK 0x400u |
| #define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT 10 |
| #define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK 0x800u |
| #define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT 11 |
| #define GPMI_CTRL1_TOG_RDN_DELAY_MASK 0xF000u |
| #define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT 12 |
| #define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_RDN_DELAY_SHIFT))&GPMI_CTRL1_TOG_RDN_DELAY_MASK) |
| #define GPMI_CTRL1_TOG_HALF_PERIOD_MASK 0x10000u |
| #define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT 16 |
| #define GPMI_CTRL1_TOG_DLL_ENABLE_MASK 0x20000u |
| #define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT 17 |
| #define GPMI_CTRL1_TOG_BCH_MODE_MASK 0x40000u |
| #define GPMI_CTRL1_TOG_BCH_MODE_SHIFT 18 |
| #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK 0x80000u |
| #define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT 19 |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK 0x100000u |
| #define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT 20 |
| #define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK 0x200000u |
| #define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT 21 |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK 0xC00000u |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT 22 |
| #define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) |
| #define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK 0x1000000u |
| #define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT 24 |
| #define GPMI_CTRL1_TOG_SSYNCMODE_MASK 0x2000000u |
| #define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT 25 |
| #define GPMI_CTRL1_TOG_UPDATE_CS_MASK 0x4000000u |
| #define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT 26 |
| #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK 0x8000000u |
| #define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT 27 |
| #define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK 0x10000000u |
| #define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT 28 |
| #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK 0x20000000u |
| #define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT 29 |
| #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK 0x40000000u |
| #define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT 30 |
| #define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK 0x80000000u |
| #define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT 31 |
| /* TIMING0 Bit Fields */ |
| #define GPMI_TIMING0_DATA_SETUP_MASK 0xFFu |
| #define GPMI_TIMING0_DATA_SETUP_SHIFT 0 |
| #define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_SETUP_SHIFT))&GPMI_TIMING0_DATA_SETUP_MASK) |
| #define GPMI_TIMING0_DATA_HOLD_MASK 0xFF00u |
| #define GPMI_TIMING0_DATA_HOLD_SHIFT 8 |
| #define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_HOLD_SHIFT))&GPMI_TIMING0_DATA_HOLD_MASK) |
| #define GPMI_TIMING0_ADDRESS_SETUP_MASK 0xFF0000u |
| #define GPMI_TIMING0_ADDRESS_SETUP_SHIFT 16 |
| #define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_ADDRESS_SETUP_SHIFT))&GPMI_TIMING0_ADDRESS_SETUP_MASK) |
| #define GPMI_TIMING0_RSVD1_MASK 0xFF000000u |
| #define GPMI_TIMING0_RSVD1_SHIFT 24 |
| #define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_RSVD1_SHIFT))&GPMI_TIMING0_RSVD1_MASK) |
| /* TIMING1 Bit Fields */ |
| #define GPMI_TIMING1_RSVD1_MASK 0xFFFFu |
| #define GPMI_TIMING1_RSVD1_SHIFT 0 |
| #define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_RSVD1_SHIFT))&GPMI_TIMING1_RSVD1_MASK) |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK 0xFFFF0000u |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT 16 |
| #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT))&GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) |
| /* TIMING2 Bit Fields */ |
| #define GPMI_TIMING2_DATA_PAUSE_MASK 0xFu |
| #define GPMI_TIMING2_DATA_PAUSE_SHIFT 0 |
| #define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_DATA_PAUSE_SHIFT))&GPMI_TIMING2_DATA_PAUSE_MASK) |
| #define GPMI_TIMING2_CMDADD_PAUSE_MASK 0xF0u |
| #define GPMI_TIMING2_CMDADD_PAUSE_SHIFT 4 |
| #define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CMDADD_PAUSE_SHIFT))&GPMI_TIMING2_CMDADD_PAUSE_MASK) |
| #define GPMI_TIMING2_POSTAMBLE_DELAY_MASK 0xF00u |
| #define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT 8 |
| #define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT))&GPMI_TIMING2_POSTAMBLE_DELAY_MASK) |
| #define GPMI_TIMING2_PREAMBLE_DELAY_MASK 0xF000u |
| #define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT 12 |
| #define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_PREAMBLE_DELAY_SHIFT))&GPMI_TIMING2_PREAMBLE_DELAY_MASK) |
| #define GPMI_TIMING2_CE_DELAY_MASK 0x1F0000u |
| #define GPMI_TIMING2_CE_DELAY_SHIFT 16 |
| #define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CE_DELAY_SHIFT))&GPMI_TIMING2_CE_DELAY_MASK) |
| #define GPMI_TIMING2_RSVD0_MASK 0xE00000u |
| #define GPMI_TIMING2_RSVD0_SHIFT 21 |
| #define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_RSVD0_SHIFT))&GPMI_TIMING2_RSVD0_MASK) |
| #define GPMI_TIMING2_READ_LATENCY_MASK 0x7000000u |
| #define GPMI_TIMING2_READ_LATENCY_SHIFT 24 |
| #define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_READ_LATENCY_SHIFT))&GPMI_TIMING2_READ_LATENCY_MASK) |
| #define GPMI_TIMING2_TCR_MASK 0x18000000u |
| #define GPMI_TIMING2_TCR_SHIFT 27 |
| #define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TCR_SHIFT))&GPMI_TIMING2_TCR_MASK) |
| #define GPMI_TIMING2_TRPSTH_MASK 0xE0000000u |
| #define GPMI_TIMING2_TRPSTH_SHIFT 29 |
| #define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TRPSTH_SHIFT))&GPMI_TIMING2_TRPSTH_MASK) |
| /* DATA Bit Fields */ |
| #define GPMI_DATA_DATA_MASK 0xFFFFFFFFu |
| #define GPMI_DATA_DATA_SHIFT 0 |
| #define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DATA_DATA_SHIFT))&GPMI_DATA_DATA_MASK) |
| /* STAT Bit Fields */ |
| #define GPMI_STAT_PRESENT_MASK 0x1u |
| #define GPMI_STAT_PRESENT_SHIFT 0 |
| #define GPMI_STAT_FIFO_FULL_MASK 0x2u |
| #define GPMI_STAT_FIFO_FULL_SHIFT 1 |
| #define GPMI_STAT_FIFO_EMPTY_MASK 0x4u |
| #define GPMI_STAT_FIFO_EMPTY_SHIFT 2 |
| #define GPMI_STAT_INVALID_BUFFER_MASK_MASK 0x8u |
| #define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT 3 |
| #define GPMI_STAT_ATA_IRQ_MASK 0x10u |
| #define GPMI_STAT_ATA_IRQ_SHIFT 4 |
| #define GPMI_STAT_RSVD1_MASK 0xE0u |
| #define GPMI_STAT_RSVD1_SHIFT 5 |
| #define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RSVD1_SHIFT))&GPMI_STAT_RSVD1_MASK) |
| #define GPMI_STAT_DEV0_ERROR_MASK 0x100u |
| #define GPMI_STAT_DEV0_ERROR_SHIFT 8 |
| #define GPMI_STAT_DEV1_ERROR_MASK 0x200u |
| #define GPMI_STAT_DEV1_ERROR_SHIFT 9 |
| #define GPMI_STAT_DEV2_ERROR_MASK 0x400u |
| #define GPMI_STAT_DEV2_ERROR_SHIFT 10 |
| #define GPMI_STAT_DEV3_ERROR_MASK 0x800u |
| #define GPMI_STAT_DEV3_ERROR_SHIFT 11 |
| #define GPMI_STAT_DEV4_ERROR_MASK 0x1000u |
| #define GPMI_STAT_DEV4_ERROR_SHIFT 12 |
| #define GPMI_STAT_DEV5_ERROR_MASK 0x2000u |
| #define GPMI_STAT_DEV5_ERROR_SHIFT 13 |
| #define GPMI_STAT_DEV6_ERROR_MASK 0x4000u |
| #define GPMI_STAT_DEV6_ERROR_SHIFT 14 |
| #define GPMI_STAT_DEV7_ERROR_MASK 0x8000u |
| #define GPMI_STAT_DEV7_ERROR_SHIFT 15 |
| #define GPMI_STAT_RDY_TIMEOUT_MASK 0xFF0000u |
| #define GPMI_STAT_RDY_TIMEOUT_SHIFT 16 |
| #define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RDY_TIMEOUT_SHIFT))&GPMI_STAT_RDY_TIMEOUT_MASK) |
| #define GPMI_STAT_READY_BUSY_MASK 0xFF000000u |
| #define GPMI_STAT_READY_BUSY_SHIFT 24 |
| #define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_READY_BUSY_SHIFT))&GPMI_STAT_READY_BUSY_MASK) |
| /* DEBUG Bit Fields */ |
| #define GPMI_DEBUG_CMD_END_MASK 0xFFu |
| #define GPMI_DEBUG_CMD_END_SHIFT 0 |
| #define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_CMD_END_SHIFT))&GPMI_DEBUG_CMD_END_MASK) |
| #define GPMI_DEBUG_DMAREQ_MASK 0xFF00u |
| #define GPMI_DEBUG_DMAREQ_SHIFT 8 |
| #define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMAREQ_SHIFT))&GPMI_DEBUG_DMAREQ_MASK) |
| #define GPMI_DEBUG_DMA_SENSE_MASK 0xFF0000u |
| #define GPMI_DEBUG_DMA_SENSE_SHIFT 16 |
| #define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMA_SENSE_SHIFT))&GPMI_DEBUG_DMA_SENSE_MASK) |
| #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK 0xFF000000u |
| #define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT 24 |
| #define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT))&GPMI_DEBUG_WAIT_FOR_READY_END_MASK) |
| /* VERSION Bit Fields */ |
| #define GPMI_VERSION_STEP_MASK 0xFFFFu |
| #define GPMI_VERSION_STEP_SHIFT 0 |
| #define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_STEP_SHIFT))&GPMI_VERSION_STEP_MASK) |
| #define GPMI_VERSION_MINOR_MASK 0xFF0000u |
| #define GPMI_VERSION_MINOR_SHIFT 16 |
| #define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MINOR_SHIFT))&GPMI_VERSION_MINOR_MASK) |
| #define GPMI_VERSION_MAJOR_MASK 0xFF000000u |
| #define GPMI_VERSION_MAJOR_SHIFT 24 |
| #define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MAJOR_SHIFT))&GPMI_VERSION_MAJOR_MASK) |
| /* DEBUG2 Bit Fields */ |
| #define GPMI_DEBUG2_RDN_TAP_MASK 0x3Fu |
| #define GPMI_DEBUG2_RDN_TAP_SHIFT 0 |
| #define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RDN_TAP_SHIFT))&GPMI_DEBUG2_RDN_TAP_MASK) |
| #define GPMI_DEBUG2_UPDATE_WINDOW_MASK 0x40u |
| #define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT 6 |
| #define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK 0x80u |
| #define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT 7 |
| #define GPMI_DEBUG2_SYND2GPMI_READY_MASK 0x100u |
| #define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT 8 |
| #define GPMI_DEBUG2_SYND2GPMI_VALID_MASK 0x200u |
| #define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT 9 |
| #define GPMI_DEBUG2_GPMI2SYND_READY_MASK 0x400u |
| #define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT 10 |
| #define GPMI_DEBUG2_GPMI2SYND_VALID_MASK 0x800u |
| #define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT 11 |
| #define GPMI_DEBUG2_SYND2GPMI_BE_MASK 0xF000u |
| #define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT 12 |
| #define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_SYND2GPMI_BE_SHIFT))&GPMI_DEBUG2_SYND2GPMI_BE_MASK) |
| #define GPMI_DEBUG2_MAIN_STATE_MASK 0xF0000u |
| #define GPMI_DEBUG2_MAIN_STATE_SHIFT 16 |
| #define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_MAIN_STATE_SHIFT))&GPMI_DEBUG2_MAIN_STATE_MASK) |
| #define GPMI_DEBUG2_PIN_STATE_MASK 0x700000u |
| #define GPMI_DEBUG2_PIN_STATE_SHIFT 20 |
| #define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_PIN_STATE_SHIFT))&GPMI_DEBUG2_PIN_STATE_MASK) |
| #define GPMI_DEBUG2_BUSY_MASK 0x800000u |
| #define GPMI_DEBUG2_BUSY_SHIFT 23 |
| #define GPMI_DEBUG2_UDMA_STATE_MASK 0xF000000u |
| #define GPMI_DEBUG2_UDMA_STATE_SHIFT 24 |
| #define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_UDMA_STATE_SHIFT))&GPMI_DEBUG2_UDMA_STATE_MASK) |
| #define GPMI_DEBUG2_RSVD1_MASK 0xF0000000u |
| #define GPMI_DEBUG2_RSVD1_SHIFT 28 |
| #define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RSVD1_SHIFT))&GPMI_DEBUG2_RSVD1_MASK) |
| /* DEBUG3 Bit Fields */ |
| #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xFFFFu |
| #define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT 0 |
| #define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT))&GPMI_DEBUG3_DEV_WORD_CNTR_MASK) |
| #define GPMI_DEBUG3_APB_WORD_CNTR_MASK 0xFFFF0000u |
| #define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT 16 |
| #define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_APB_WORD_CNTR_SHIFT))&GPMI_DEBUG3_APB_WORD_CNTR_MASK) |
| /* READ_DDR_DLL_CTRL Bit Fields */ |
| #define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK 0x1u |
| #define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT 0 |
| #define GPMI_READ_DDR_DLL_CTRL_RESET_MASK 0x2u |
| #define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT 1 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK 0x80u |
| #define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7 |
| #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK 0x100u |
| #define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT 8 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK 0xC0000u |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT 18 |
| #define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 |
| #define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 |
| #define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /* WRITE_DDR_DLL_CTRL Bit Fields */ |
| #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK 0x1u |
| #define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT 0 |
| #define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK 0x2u |
| #define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT 1 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK 0x80u |
| #define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7 |
| #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK 0x100u |
| #define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT 8 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK 0xC0000u |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT 18 |
| #define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 |
| #define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 |
| #define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /* READ_DDR_DLL_STS Bit Fields */ |
| #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK 0x1u |
| #define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT 0 |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK 0x1FEu |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT 1 |
| #define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) |
| #define GPMI_READ_DDR_DLL_STS_RSVD0_MASK 0xFE00u |
| #define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT 9 |
| #define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD0_MASK) |
| #define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK 0x10000u |
| #define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT 16 |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK 0x1FE0000u |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT 17 |
| #define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) |
| #define GPMI_READ_DDR_DLL_STS_RSVD1_MASK 0xFE000000u |
| #define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT 25 |
| #define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD1_MASK) |
| /* WRITE_DDR_DLL_STS Bit Fields */ |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK 0x1u |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT 0 |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK 0x1FEu |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT 1 |
| #define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK 0xFE00u |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT 9 |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK 0x10000u |
| #define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT 16 |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK 0x1FE0000u |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT 17 |
| #define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK 0xFE000000u |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT 25 |
| #define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Register_Masks */ |
| |
| /* GPMI - Peripheral instance base addresses */ |
| /** Peripheral GPMI base address */ |
| #define GPMI_BASE (0x41806000u) |
| /** Peripheral GPMI base pointer */ |
| #define GPMI ((GPMI_Type *)GPMI_BASE) |
| #define GPMI_BASE_PTR (GPMI) |
| /** Array initializer of GPMI peripheral base addresses */ |
| #define GPMI_BASE_ADDRS { GPMI_BASE } |
| /** Array initializer of GPMI peripheral base pointers */ |
| #define GPMI_BASE_PTRS { GPMI } |
| /** Interrupt vectors for the GPMI peripheral type */ |
| #define GPMI_IRQS { GPMI_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPMI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPMI - Register instance definitions */ |
| /* GPMI */ |
| #define GPMI_CTRL0 GPMI_CTRL0_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL0_SET GPMI_CTRL0_SET_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL0_CLR GPMI_CTRL0_CLR_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL0_TOG GPMI_CTRL0_TOG_REG(GPMI_BASE_PTR) |
| #define GPMI_COMPARE GPMI_COMPARE_REG(GPMI_BASE_PTR) |
| #define GPMI_ECCCTRL GPMI_ECCCTRL_REG(GPMI_BASE_PTR) |
| #define GPMI_ECCCTRL_SET GPMI_ECCCTRL_SET_REG(GPMI_BASE_PTR) |
| #define GPMI_ECCCTRL_CLR GPMI_ECCCTRL_CLR_REG(GPMI_BASE_PTR) |
| #define GPMI_ECCCTRL_TOG GPMI_ECCCTRL_TOG_REG(GPMI_BASE_PTR) |
| #define GPMI_ECCCOUNT GPMI_ECCCOUNT_REG(GPMI_BASE_PTR) |
| #define GPMI_PAYLOAD GPMI_PAYLOAD_REG(GPMI_BASE_PTR) |
| #define GPMI_AUXILIARY GPMI_AUXILIARY_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL1 GPMI_CTRL1_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL1_SET GPMI_CTRL1_SET_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL1_CLR GPMI_CTRL1_CLR_REG(GPMI_BASE_PTR) |
| #define GPMI_CTRL1_TOG GPMI_CTRL1_TOG_REG(GPMI_BASE_PTR) |
| #define GPMI_TIMING0 GPMI_TIMING0_REG(GPMI_BASE_PTR) |
| #define GPMI_TIMING1 GPMI_TIMING1_REG(GPMI_BASE_PTR) |
| #define GPMI_TIMING2 GPMI_TIMING2_REG(GPMI_BASE_PTR) |
| #define GPMI_DATA GPMI_DATA_REG(GPMI_BASE_PTR) |
| #define GPMI_STAT GPMI_STAT_REG(GPMI_BASE_PTR) |
| #define GPMI_DEBUG GPMI_DEBUG_REG(GPMI_BASE_PTR) |
| #define GPMI_VERSION GPMI_VERSION_REG(GPMI_BASE_PTR) |
| #define GPMI_DEBUG2 GPMI_DEBUG2_REG(GPMI_BASE_PTR) |
| #define GPMI_DEBUG3 GPMI_DEBUG3_REG(GPMI_BASE_PTR) |
| #define GPMI_READ_DDR_DLL_CTRL GPMI_READ_DDR_DLL_CTRL_REG(GPMI_BASE_PTR) |
| #define GPMI_WRITE_DDR_DLL_CTRL GPMI_WRITE_DDR_DLL_CTRL_REG(GPMI_BASE_PTR) |
| #define GPMI_READ_DDR_DLL_STS GPMI_READ_DDR_DLL_STS_REG(GPMI_BASE_PTR) |
| #define GPMI_WRITE_DDR_DLL_STS GPMI_WRITE_DDR_DLL_STS_REG(GPMI_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group GPMI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** GPT - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ |
| __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ |
| __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ |
| __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ |
| __IO uint32_t OCR1; /**< GPT Output Compare Register 1, offset: 0x10 */ |
| __IO uint32_t OCR2; /**< GPT Output Compare Register 2, offset: 0x14 */ |
| __IO uint32_t OCR3; /**< GPT Output Compare Register 3, offset: 0x18 */ |
| __I uint32_t ICR1; /**< GPT Input Capture Register 1, offset: 0x1C */ |
| __I uint32_t ICR2; /**< GPT Input Capture Register 2, offset: 0x20 */ |
| __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ |
| } GPT_Type, *GPT_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPT - Register accessors */ |
| #define GPT_CR_REG(base) ((base)->CR) |
| #define GPT_PR_REG(base) ((base)->PR) |
| #define GPT_SR_REG(base) ((base)->SR) |
| #define GPT_IR_REG(base) ((base)->IR) |
| #define GPT_OCR1_REG(base) ((base)->OCR1) |
| #define GPT_OCR2_REG(base) ((base)->OCR2) |
| #define GPT_OCR3_REG(base) ((base)->OCR3) |
| #define GPT_ICR1_REG(base) ((base)->ICR1) |
| #define GPT_ICR2_REG(base) ((base)->ICR2) |
| #define GPT_CNT_REG(base) ((base)->CNT) |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Register_Masks GPT Register Masks |
| * @{ |
| */ |
| |
| /* CR Bit Fields */ |
| #define GPT_CR_EN_MASK 0x1u |
| #define GPT_CR_EN_SHIFT 0 |
| #define GPT_CR_ENMOD_MASK 0x2u |
| #define GPT_CR_ENMOD_SHIFT 1 |
| #define GPT_CR_DBGEN_MASK 0x4u |
| #define GPT_CR_DBGEN_SHIFT 2 |
| #define GPT_CR_WAITEN_MASK 0x8u |
| #define GPT_CR_WAITEN_SHIFT 3 |
| #define GPT_CR_DOZEEN_MASK 0x10u |
| #define GPT_CR_DOZEEN_SHIFT 4 |
| #define GPT_CR_STOPEN_MASK 0x20u |
| #define GPT_CR_STOPEN_SHIFT 5 |
| #define GPT_CR_CLKSRC_MASK 0x1C0u |
| #define GPT_CR_CLKSRC_SHIFT 6 |
| #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_CLKSRC_SHIFT))&GPT_CR_CLKSRC_MASK) |
| #define GPT_CR_FRR_MASK 0x200u |
| #define GPT_CR_FRR_SHIFT 9 |
| #define GPT_CR_EN_24M_MASK 0x400u |
| #define GPT_CR_EN_24M_SHIFT 10 |
| #define GPT_CR_SWR_MASK 0x8000u |
| #define GPT_CR_SWR_SHIFT 15 |
| #define GPT_CR_IM1_MASK 0x30000u |
| #define GPT_CR_IM1_SHIFT 16 |
| #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM1_SHIFT))&GPT_CR_IM1_MASK) |
| #define GPT_CR_IM2_MASK 0xC0000u |
| #define GPT_CR_IM2_SHIFT 18 |
| #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM2_SHIFT))&GPT_CR_IM2_MASK) |
| #define GPT_CR_OM1_MASK 0x700000u |
| #define GPT_CR_OM1_SHIFT 20 |
| #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM1_SHIFT))&GPT_CR_OM1_MASK) |
| #define GPT_CR_OM2_MASK 0x3800000u |
| #define GPT_CR_OM2_SHIFT 23 |
| #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM2_SHIFT))&GPT_CR_OM2_MASK) |
| #define GPT_CR_OM3_MASK 0x1C000000u |
| #define GPT_CR_OM3_SHIFT 26 |
| #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM3_SHIFT))&GPT_CR_OM3_MASK) |
| #define GPT_CR_FO1_MASK 0x20000000u |
| #define GPT_CR_FO1_SHIFT 29 |
| #define GPT_CR_FO2_MASK 0x40000000u |
| #define GPT_CR_FO2_SHIFT 30 |
| #define GPT_CR_FO3_MASK 0x80000000u |
| #define GPT_CR_FO3_SHIFT 31 |
| /* PR Bit Fields */ |
| #define GPT_PR_PRESCALER_MASK 0xFFFu |
| #define GPT_PR_PRESCALER_SHIFT 0 |
| #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER_SHIFT))&GPT_PR_PRESCALER_MASK) |
| #define GPT_PR_PRESCALER24M_MASK 0xF000u |
| #define GPT_PR_PRESCALER24M_SHIFT 12 |
| #define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER24M_SHIFT))&GPT_PR_PRESCALER24M_MASK) |
| /* SR Bit Fields */ |
| #define GPT_SR_OF1_MASK 0x1u |
| #define GPT_SR_OF1_SHIFT 0 |
| #define GPT_SR_OF2_MASK 0x2u |
| #define GPT_SR_OF2_SHIFT 1 |
| #define GPT_SR_OF3_MASK 0x4u |
| #define GPT_SR_OF3_SHIFT 2 |
| #define GPT_SR_IF1_MASK 0x8u |
| #define GPT_SR_IF1_SHIFT 3 |
| #define GPT_SR_IF2_MASK 0x10u |
| #define GPT_SR_IF2_SHIFT 4 |
| #define GPT_SR_ROV_MASK 0x20u |
| #define GPT_SR_ROV_SHIFT 5 |
| /* IR Bit Fields */ |
| #define GPT_IR_OF1IE_MASK 0x1u |
| #define GPT_IR_OF1IE_SHIFT 0 |
| #define GPT_IR_OF2IE_MASK 0x2u |
| #define GPT_IR_OF2IE_SHIFT 1 |
| #define GPT_IR_OF3IE_MASK 0x4u |
| #define GPT_IR_OF3IE_SHIFT 2 |
| #define GPT_IR_IF1IE_MASK 0x8u |
| #define GPT_IR_IF1IE_SHIFT 3 |
| #define GPT_IR_IF2IE_MASK 0x10u |
| #define GPT_IR_IF2IE_SHIFT 4 |
| #define GPT_IR_ROVIE_MASK 0x20u |
| #define GPT_IR_ROVIE_SHIFT 5 |
| /* OCR1 Bit Fields */ |
| #define GPT_OCR1_COMP_MASK 0xFFFFFFFFu |
| #define GPT_OCR1_COMP_SHIFT 0 |
| #define GPT_OCR1_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR1_COMP_SHIFT))&GPT_OCR1_COMP_MASK) |
| /* OCR2 Bit Fields */ |
| #define GPT_OCR2_COMP_MASK 0xFFFFFFFFu |
| #define GPT_OCR2_COMP_SHIFT 0 |
| #define GPT_OCR2_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR2_COMP_SHIFT))&GPT_OCR2_COMP_MASK) |
| /* OCR3 Bit Fields */ |
| #define GPT_OCR3_COMP_MASK 0xFFFFFFFFu |
| #define GPT_OCR3_COMP_SHIFT 0 |
| #define GPT_OCR3_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR3_COMP_SHIFT))&GPT_OCR3_COMP_MASK) |
| /* ICR1 Bit Fields */ |
| #define GPT_ICR1_CAPT_MASK 0xFFFFFFFFu |
| #define GPT_ICR1_CAPT_SHIFT 0 |
| #define GPT_ICR1_CAPT(x) (((uint32_t)(((uint32_t)(x))<<GPT_ICR1_CAPT_SHIFT))&GPT_ICR1_CAPT_MASK) |
| /* ICR2 Bit Fields */ |
| #define GPT_ICR2_CAPT_MASK 0xFFFFFFFFu |
| #define GPT_ICR2_CAPT_SHIFT 0 |
| #define GPT_ICR2_CAPT(x) (((uint32_t)(((uint32_t)(x))<<GPT_ICR2_CAPT_SHIFT))&GPT_ICR2_CAPT_MASK) |
| /* CNT Bit Fields */ |
| #define GPT_CNT_COUNT_MASK 0xFFFFFFFFu |
| #define GPT_CNT_COUNT_SHIFT 0 |
| #define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPT_CNT_COUNT_SHIFT))&GPT_CNT_COUNT_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Register_Masks */ |
| |
| /* GPT - Peripheral instance base addresses */ |
| /** Peripheral GPT base address */ |
| #define GPT_BASE (0x42098000u) |
| /** Peripheral GPT base pointer */ |
| #define GPT ((GPT_Type *)GPT_BASE) |
| #define GPT_BASE_PTR (GPT) |
| /** Array initializer of GPT peripheral base addresses */ |
| #define GPT_BASE_ADDRS { GPT_BASE } |
| /** Array initializer of GPT peripheral base pointers */ |
| #define GPT_BASE_PTRS { GPT } |
| /** Interrupt vectors for the GPT peripheral type */ |
| #define GPT_IRQS { GPT_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- GPT - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros |
| * @{ |
| */ |
| |
| /* GPT - Register instance definitions */ |
| /* GPT */ |
| #define GPT_CR GPT_CR_REG(GPT_BASE_PTR) |
| #define GPT_PR GPT_PR_REG(GPT_BASE_PTR) |
| #define GPT_SR GPT_SR_REG(GPT_BASE_PTR) |
| #define GPT_IR GPT_IR_REG(GPT_BASE_PTR) |
| #define GPT_OCR1 GPT_OCR1_REG(GPT_BASE_PTR) |
| #define GPT_OCR2 GPT_OCR2_REG(GPT_BASE_PTR) |
| #define GPT_OCR3 GPT_OCR3_REG(GPT_BASE_PTR) |
| #define GPT_ICR1 GPT_ICR1_REG(GPT_BASE_PTR) |
| #define GPT_ICR2 GPT_ICR2_REG(GPT_BASE_PTR) |
| #define GPT_CNT GPT_CNT_REG(GPT_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group GPT_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** I2C - Register Layout Typedef */ |
| typedef struct { |
| __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ |
| uint8_t RESERVED_0[2]; |
| __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ |
| uint8_t RESERVED_1[2]; |
| __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ |
| uint8_t RESERVED_2[2]; |
| __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ |
| uint8_t RESERVED_3[2]; |
| __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ |
| } I2C_Type, *I2C_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros |
| * @{ |
| */ |
| |
| /* I2C - Register accessors */ |
| #define I2C_IADR_REG(base) ((base)->IADR) |
| #define I2C_IFDR_REG(base) ((base)->IFDR) |
| #define I2C_I2CR_REG(base) ((base)->I2CR) |
| #define I2C_I2SR_REG(base) ((base)->I2SR) |
| #define I2C_I2DR_REG(base) ((base)->I2DR) |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Register_Masks I2C Register Masks |
| * @{ |
| */ |
| |
| /* IADR Bit Fields */ |
| #define I2C_IADR_ADR_MASK 0xFEu |
| #define I2C_IADR_ADR_SHIFT 1 |
| #define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<<I2C_IADR_ADR_SHIFT))&I2C_IADR_ADR_MASK) |
| /* IFDR Bit Fields */ |
| #define I2C_IFDR_IC_MASK 0x3Fu |
| #define I2C_IFDR_IC_SHIFT 0 |
| #define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x))<<I2C_IFDR_IC_SHIFT))&I2C_IFDR_IC_MASK) |
| /* I2CR Bit Fields */ |
| #define I2C_I2CR_RSTA_MASK 0x4u |
| #define I2C_I2CR_RSTA_SHIFT 2 |
| #define I2C_I2CR_TXAK_MASK 0x8u |
| #define I2C_I2CR_TXAK_SHIFT 3 |
| #define I2C_I2CR_MTX_MASK 0x10u |
| #define I2C_I2CR_MTX_SHIFT 4 |
| #define I2C_I2CR_MSTA_MASK 0x20u |
| #define I2C_I2CR_MSTA_SHIFT 5 |
| #define I2C_I2CR_IIEN_MASK 0x40u |
| #define I2C_I2CR_IIEN_SHIFT 6 |
| #define I2C_I2CR_IEN_MASK 0x80u |
| #define I2C_I2CR_IEN_SHIFT 7 |
| /* I2SR Bit Fields */ |
| #define I2C_I2SR_RXAK_MASK 0x1u |
| #define I2C_I2SR_RXAK_SHIFT 0 |
| #define I2C_I2SR_IIF_MASK 0x2u |
| #define I2C_I2SR_IIF_SHIFT 1 |
| #define I2C_I2SR_SRW_MASK 0x4u |
| #define I2C_I2SR_SRW_SHIFT 2 |
| #define I2C_I2SR_IAL_MASK 0x10u |
| #define I2C_I2SR_IAL_SHIFT 4 |
| #define I2C_I2SR_IBB_MASK 0x20u |
| #define I2C_I2SR_IBB_SHIFT 5 |
| #define I2C_I2SR_IAAS_MASK 0x40u |
| #define I2C_I2SR_IAAS_SHIFT 6 |
| #define I2C_I2SR_ICF_MASK 0x80u |
| #define I2C_I2SR_ICF_SHIFT 7 |
| /* I2DR Bit Fields */ |
| #define I2C_I2DR_DATA_MASK 0xFFu |
| #define I2C_I2DR_DATA_SHIFT 0 |
| #define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x))<<I2C_I2DR_DATA_SHIFT))&I2C_I2DR_DATA_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Register_Masks */ |
| |
| /* I2C - Peripheral instance base addresses */ |
| /** Peripheral I2C1 base address */ |
| #define I2C1_BASE (0x421A0000u) |
| /** Peripheral I2C1 base pointer */ |
| #define I2C1 ((I2C_Type *)I2C1_BASE) |
| #define I2C1_BASE_PTR (I2C1) |
| /** Peripheral I2C2 base address */ |
| #define I2C2_BASE (0x421A4000u) |
| /** Peripheral I2C2 base pointer */ |
| #define I2C2 ((I2C_Type *)I2C2_BASE) |
| #define I2C2_BASE_PTR (I2C2) |
| /** Peripheral I2C3 base address */ |
| #define I2C3_BASE (0x421A8000u) |
| /** Peripheral I2C3 base pointer */ |
| #define I2C3 ((I2C_Type *)I2C3_BASE) |
| #define I2C3_BASE_PTR (I2C3) |
| /** Peripheral I2C4 base address */ |
| #define I2C4_BASE (0x421F8000u) |
| /** Peripheral I2C4 base pointer */ |
| #define I2C4 ((I2C_Type *)I2C4_BASE) |
| #define I2C4_BASE_PTR (I2C4) |
| /** Array initializer of I2C peripheral base addresses */ |
| #define I2C_BASE_ADDRS { I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } |
| /** Array initializer of I2C peripheral base pointers */ |
| #define I2C_BASE_PTRS { I2C1, I2C2, I2C3, I2C4 } |
| /** Interrupt vectors for the I2C peripheral type */ |
| #define I2C_IRQS { I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2C - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros |
| * @{ |
| */ |
| |
| /* I2C - Register instance definitions */ |
| /* I2C1 */ |
| #define I2C1_IADR I2C_IADR_REG(I2C1_BASE_PTR) |
| #define I2C1_IFDR I2C_IFDR_REG(I2C1_BASE_PTR) |
| #define I2C1_I2CR I2C_I2CR_REG(I2C1_BASE_PTR) |
| #define I2C1_I2SR I2C_I2SR_REG(I2C1_BASE_PTR) |
| #define I2C1_I2DR I2C_I2DR_REG(I2C1_BASE_PTR) |
| /* I2C2 */ |
| #define I2C2_IADR I2C_IADR_REG(I2C2_BASE_PTR) |
| #define I2C2_IFDR I2C_IFDR_REG(I2C2_BASE_PTR) |
| #define I2C2_I2CR I2C_I2CR_REG(I2C2_BASE_PTR) |
| #define I2C2_I2SR I2C_I2SR_REG(I2C2_BASE_PTR) |
| #define I2C2_I2DR I2C_I2DR_REG(I2C2_BASE_PTR) |
| /* I2C3 */ |
| #define I2C3_IADR I2C_IADR_REG(I2C3_BASE_PTR) |
| #define I2C3_IFDR I2C_IFDR_REG(I2C3_BASE_PTR) |
| #define I2C3_I2CR I2C_I2CR_REG(I2C3_BASE_PTR) |
| #define I2C3_I2SR I2C_I2SR_REG(I2C3_BASE_PTR) |
| #define I2C3_I2DR I2C_I2DR_REG(I2C3_BASE_PTR) |
| /* I2C4 */ |
| #define I2C4_IADR I2C_IADR_REG(I2C4_BASE_PTR) |
| #define I2C4_IFDR I2C_IFDR_REG(I2C4_BASE_PTR) |
| #define I2C4_I2CR I2C_I2CR_REG(I2C4_BASE_PTR) |
| #define I2C4_I2SR I2C_I2SR_REG(I2C4_BASE_PTR) |
| #define I2C4_I2DR I2C_I2DR_REG(I2C4_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group I2C_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** I2S - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ |
| __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ |
| __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ |
| __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ |
| __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ |
| __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ |
| uint8_t RESERVED_0[8]; |
| __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ |
| uint8_t RESERVED_1[28]; |
| __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ |
| uint8_t RESERVED_2[28]; |
| __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ |
| uint8_t RESERVED_3[28]; |
| __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ |
| __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ |
| __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ |
| __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ |
| __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ |
| __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ |
| uint8_t RESERVED_4[8]; |
| __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ |
| uint8_t RESERVED_5[28]; |
| __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ |
| uint8_t RESERVED_6[28]; |
| __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ |
| } I2S_Type, *I2S_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros |
| * @{ |
| */ |
| |
| /* I2S - Register accessors */ |
| #define I2S_TCSR_REG(base) ((base)->TCSR) |
| #define I2S_TCR1_REG(base) ((base)->TCR1) |
| #define I2S_TCR2_REG(base) ((base)->TCR2) |
| #define I2S_TCR3_REG(base) ((base)->TCR3) |
| #define I2S_TCR4_REG(base) ((base)->TCR4) |
| #define I2S_TCR5_REG(base) ((base)->TCR5) |
| #define I2S_TDR_REG(base,index) ((base)->TDR[index]) |
| #define I2S_TFR_REG(base,index) ((base)->TFR[index]) |
| #define I2S_TMR_REG(base) ((base)->TMR) |
| #define I2S_RCSR_REG(base) ((base)->RCSR) |
| #define I2S_RCR1_REG(base) ((base)->RCR1) |
| #define I2S_RCR2_REG(base) ((base)->RCR2) |
| #define I2S_RCR3_REG(base) ((base)->RCR3) |
| #define I2S_RCR4_REG(base) ((base)->RCR4) |
| #define I2S_RCR5_REG(base) ((base)->RCR5) |
| #define I2S_RDR_REG(base,index) ((base)->RDR[index]) |
| #define I2S_RFR_REG(base,index) ((base)->RFR[index]) |
| #define I2S_RMR_REG(base) ((base)->RMR) |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Register_Masks I2S Register Masks |
| * @{ |
| */ |
| |
| /* TCSR Bit Fields */ |
| #define I2S_TCSR_FRDE_MASK 0x1u |
| #define I2S_TCSR_FRDE_SHIFT 0 |
| #define I2S_TCSR_FWDE_MASK 0x2u |
| #define I2S_TCSR_FWDE_SHIFT 1 |
| #define I2S_TCSR_FRIE_MASK 0x100u |
| #define I2S_TCSR_FRIE_SHIFT 8 |
| #define I2S_TCSR_FWIE_MASK 0x200u |
| #define I2S_TCSR_FWIE_SHIFT 9 |
| #define I2S_TCSR_FEIE_MASK 0x400u |
| #define I2S_TCSR_FEIE_SHIFT 10 |
| #define I2S_TCSR_SEIE_MASK 0x800u |
| #define I2S_TCSR_SEIE_SHIFT 11 |
| #define I2S_TCSR_WSIE_MASK 0x1000u |
| #define I2S_TCSR_WSIE_SHIFT 12 |
| #define I2S_TCSR_FRF_MASK 0x10000u |
| #define I2S_TCSR_FRF_SHIFT 16 |
| #define I2S_TCSR_FWF_MASK 0x20000u |
| #define I2S_TCSR_FWF_SHIFT 17 |
| #define I2S_TCSR_FEF_MASK 0x40000u |
| #define I2S_TCSR_FEF_SHIFT 18 |
| #define I2S_TCSR_SEF_MASK 0x80000u |
| #define I2S_TCSR_SEF_SHIFT 19 |
| #define I2S_TCSR_WSF_MASK 0x100000u |
| #define I2S_TCSR_WSF_SHIFT 20 |
| #define I2S_TCSR_SR_MASK 0x1000000u |
| #define I2S_TCSR_SR_SHIFT 24 |
| #define I2S_TCSR_FR_MASK 0x2000000u |
| #define I2S_TCSR_FR_SHIFT 25 |
| #define I2S_TCSR_BCE_MASK 0x10000000u |
| #define I2S_TCSR_BCE_SHIFT 28 |
| #define I2S_TCSR_DBGE_MASK 0x20000000u |
| #define I2S_TCSR_DBGE_SHIFT 29 |
| #define I2S_TCSR_STOPE_MASK 0x40000000u |
| #define I2S_TCSR_STOPE_SHIFT 30 |
| #define I2S_TCSR_TE_MASK 0x80000000u |
| #define I2S_TCSR_TE_SHIFT 31 |
| /* TCR1 Bit Fields */ |
| #define I2S_TCR1_TFW_MASK 0x1Fu |
| #define I2S_TCR1_TFW_SHIFT 0 |
| #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) |
| /* TCR2 Bit Fields */ |
| #define I2S_TCR2_DIV_MASK 0xFFu |
| #define I2S_TCR2_DIV_SHIFT 0 |
| #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) |
| #define I2S_TCR2_BCD_MASK 0x1000000u |
| #define I2S_TCR2_BCD_SHIFT 24 |
| #define I2S_TCR2_BCP_MASK 0x2000000u |
| #define I2S_TCR2_BCP_SHIFT 25 |
| #define I2S_TCR2_MSEL_MASK 0xC000000u |
| #define I2S_TCR2_MSEL_SHIFT 26 |
| #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) |
| #define I2S_TCR2_BCI_MASK 0x10000000u |
| #define I2S_TCR2_BCI_SHIFT 28 |
| #define I2S_TCR2_BCS_MASK 0x20000000u |
| #define I2S_TCR2_BCS_SHIFT 29 |
| #define I2S_TCR2_SYNC_MASK 0xC0000000u |
| #define I2S_TCR2_SYNC_SHIFT 30 |
| #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) |
| /* TCR3 Bit Fields */ |
| #define I2S_TCR3_WDFL_MASK 0x1Fu |
| #define I2S_TCR3_WDFL_SHIFT 0 |
| #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) |
| #define I2S_TCR3_TCE_MASK 0x10000u |
| #define I2S_TCR3_TCE_SHIFT 16 |
| /* TCR4 Bit Fields */ |
| #define I2S_TCR4_FSD_MASK 0x1u |
| #define I2S_TCR4_FSD_SHIFT 0 |
| #define I2S_TCR4_FSP_MASK 0x2u |
| #define I2S_TCR4_FSP_SHIFT 1 |
| #define I2S_TCR4_FSE_MASK 0x8u |
| #define I2S_TCR4_FSE_SHIFT 3 |
| #define I2S_TCR4_MF_MASK 0x10u |
| #define I2S_TCR4_MF_SHIFT 4 |
| #define I2S_TCR4_SYWD_MASK 0x1F00u |
| #define I2S_TCR4_SYWD_SHIFT 8 |
| #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) |
| #define I2S_TCR4_FRSZ_MASK 0x1F0000u |
| #define I2S_TCR4_FRSZ_SHIFT 16 |
| #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) |
| /* TCR5 Bit Fields */ |
| #define I2S_TCR5_FBT_MASK 0x1F00u |
| #define I2S_TCR5_FBT_SHIFT 8 |
| #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) |
| #define I2S_TCR5_W0W_MASK 0x1F0000u |
| #define I2S_TCR5_W0W_SHIFT 16 |
| #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) |
| #define I2S_TCR5_WNW_MASK 0x1F000000u |
| #define I2S_TCR5_WNW_SHIFT 24 |
| #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) |
| /* TDR Bit Fields */ |
| #define I2S_TDR_TDR_MASK 0xFFFFFFFFu |
| #define I2S_TDR_TDR_SHIFT 0 |
| #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) |
| /* TFR Bit Fields */ |
| #define I2S_TFR_RFP_MASK 0x3Fu |
| #define I2S_TFR_RFP_SHIFT 0 |
| #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) |
| #define I2S_TFR_WFP_MASK 0x3F0000u |
| #define I2S_TFR_WFP_SHIFT 16 |
| #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) |
| /* TMR Bit Fields */ |
| #define I2S_TMR_TWM_MASK 0xFFFFFFFFu |
| #define I2S_TMR_TWM_SHIFT 0 |
| #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) |
| /* RCSR Bit Fields */ |
| #define I2S_RCSR_FRDE_MASK 0x1u |
| #define I2S_RCSR_FRDE_SHIFT 0 |
| #define I2S_RCSR_FWDE_MASK 0x2u |
| #define I2S_RCSR_FWDE_SHIFT 1 |
| #define I2S_RCSR_FRIE_MASK 0x100u |
| #define I2S_RCSR_FRIE_SHIFT 8 |
| #define I2S_RCSR_FWIE_MASK 0x200u |
| #define I2S_RCSR_FWIE_SHIFT 9 |
| #define I2S_RCSR_FEIE_MASK 0x400u |
| #define I2S_RCSR_FEIE_SHIFT 10 |
| #define I2S_RCSR_SEIE_MASK 0x800u |
| #define I2S_RCSR_SEIE_SHIFT 11 |
| #define I2S_RCSR_WSIE_MASK 0x1000u |
| #define I2S_RCSR_WSIE_SHIFT 12 |
| #define I2S_RCSR_FRF_MASK 0x10000u |
| #define I2S_RCSR_FRF_SHIFT 16 |
| #define I2S_RCSR_FWF_MASK 0x20000u |
| #define I2S_RCSR_FWF_SHIFT 17 |
| #define I2S_RCSR_FEF_MASK 0x40000u |
| #define I2S_RCSR_FEF_SHIFT 18 |
| #define I2S_RCSR_SEF_MASK 0x80000u |
| #define I2S_RCSR_SEF_SHIFT 19 |
| #define I2S_RCSR_WSF_MASK 0x100000u |
| #define I2S_RCSR_WSF_SHIFT 20 |
| #define I2S_RCSR_SR_MASK 0x1000000u |
| #define I2S_RCSR_SR_SHIFT 24 |
| #define I2S_RCSR_FR_MASK 0x2000000u |
| #define I2S_RCSR_FR_SHIFT 25 |
| #define I2S_RCSR_BCE_MASK 0x10000000u |
| #define I2S_RCSR_BCE_SHIFT 28 |
| #define I2S_RCSR_DBGE_MASK 0x20000000u |
| #define I2S_RCSR_DBGE_SHIFT 29 |
| #define I2S_RCSR_STOPE_MASK 0x40000000u |
| #define I2S_RCSR_STOPE_SHIFT 30 |
| #define I2S_RCSR_RE_MASK 0x80000000u |
| #define I2S_RCSR_RE_SHIFT 31 |
| /* RCR1 Bit Fields */ |
| #define I2S_RCR1_RFW_MASK 0x1Fu |
| #define I2S_RCR1_RFW_SHIFT 0 |
| #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) |
| /* RCR2 Bit Fields */ |
| #define I2S_RCR2_DIV_MASK 0xFFu |
| #define I2S_RCR2_DIV_SHIFT 0 |
| #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) |
| #define I2S_RCR2_BCD_MASK 0x1000000u |
| #define I2S_RCR2_BCD_SHIFT 24 |
| #define I2S_RCR2_BCP_MASK 0x2000000u |
| #define I2S_RCR2_BCP_SHIFT 25 |
| #define I2S_RCR2_MSEL_MASK 0xC000000u |
| #define I2S_RCR2_MSEL_SHIFT 26 |
| #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) |
| #define I2S_RCR2_BCI_MASK 0x10000000u |
| #define I2S_RCR2_BCI_SHIFT 28 |
| #define I2S_RCR2_BCS_MASK 0x20000000u |
| #define I2S_RCR2_BCS_SHIFT 29 |
| #define I2S_RCR2_SYNC_MASK 0xC0000000u |
| #define I2S_RCR2_SYNC_SHIFT 30 |
| #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) |
| /* RCR3 Bit Fields */ |
| #define I2S_RCR3_WDFL_MASK 0x1Fu |
| #define I2S_RCR3_WDFL_SHIFT 0 |
| #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) |
| #define I2S_RCR3_RCE_MASK 0x10000u |
| #define I2S_RCR3_RCE_SHIFT 16 |
| /* RCR4 Bit Fields */ |
| #define I2S_RCR4_FSD_MASK 0x1u |
| #define I2S_RCR4_FSD_SHIFT 0 |
| #define I2S_RCR4_FSP_MASK 0x2u |
| #define I2S_RCR4_FSP_SHIFT 1 |
| #define I2S_RCR4_FSE_MASK 0x8u |
| #define I2S_RCR4_FSE_SHIFT 3 |
| #define I2S_RCR4_MF_MASK 0x10u |
| #define I2S_RCR4_MF_SHIFT 4 |
| #define I2S_RCR4_SYWD_MASK 0x1F00u |
| #define I2S_RCR4_SYWD_SHIFT 8 |
| #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) |
| #define I2S_RCR4_FRSZ_MASK 0x1F0000u |
| #define I2S_RCR4_FRSZ_SHIFT 16 |
| #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) |
| /* RCR5 Bit Fields */ |
| #define I2S_RCR5_FBT_MASK 0x1F00u |
| #define I2S_RCR5_FBT_SHIFT 8 |
| #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) |
| #define I2S_RCR5_W0W_MASK 0x1F0000u |
| #define I2S_RCR5_W0W_SHIFT 16 |
| #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) |
| #define I2S_RCR5_WNW_MASK 0x1F000000u |
| #define I2S_RCR5_WNW_SHIFT 24 |
| #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) |
| /* RDR Bit Fields */ |
| #define I2S_RDR_RDR_MASK 0xFFFFFFFFu |
| #define I2S_RDR_RDR_SHIFT 0 |
| #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) |
| /* RFR Bit Fields */ |
| #define I2S_RFR_RFP_MASK 0x3Fu |
| #define I2S_RFR_RFP_SHIFT 0 |
| #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) |
| #define I2S_RFR_WFP_MASK 0x3F0000u |
| #define I2S_RFR_WFP_SHIFT 16 |
| #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) |
| /* RMR Bit Fields */ |
| #define I2S_RMR_RWM_MASK 0xFFFFFFFFu |
| #define I2S_RMR_RWM_SHIFT 0 |
| #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Register_Masks */ |
| |
| /* I2S - Peripheral instance base addresses */ |
| /** Peripheral I2S1 base address */ |
| #define I2S1_BASE (0x421D4000u) |
| /** Peripheral I2S1 base pointer */ |
| #define I2S1 ((I2S_Type *)I2S1_BASE) |
| #define I2S1_BASE_PTR (I2S1) |
| /** Peripheral I2S2 base address */ |
| #define I2S2_BASE (0x421DC000u) |
| /** Peripheral I2S2 base pointer */ |
| #define I2S2 ((I2S_Type *)I2S2_BASE) |
| #define I2S2_BASE_PTR (I2S2) |
| /** Array initializer of I2S peripheral base addresses */ |
| #define I2S_BASE_ADDRS { I2S1_BASE, I2S2_BASE } |
| /** Array initializer of I2S peripheral base pointers */ |
| #define I2S_BASE_PTRS { I2S1, I2S2 } |
| /** Interrupt vectors for the I2S peripheral type */ |
| #define SAI_IRQS { SAI1_IRQn, SAI2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- I2S - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros |
| * @{ |
| */ |
| |
| /* I2S - Register instance definitions */ |
| /* I2S1 */ |
| #define I2S1_TCSR I2S_TCSR_REG(I2S1_BASE_PTR) |
| #define I2S1_TCR1 I2S_TCR1_REG(I2S1_BASE_PTR) |
| #define I2S1_TCR2 I2S_TCR2_REG(I2S1_BASE_PTR) |
| #define I2S1_TCR3 I2S_TCR3_REG(I2S1_BASE_PTR) |
| #define I2S1_TCR4 I2S_TCR4_REG(I2S1_BASE_PTR) |
| #define I2S1_TCR5 I2S_TCR5_REG(I2S1_BASE_PTR) |
| #define I2S1_TDR0 I2S_TDR_REG(I2S1_BASE_PTR,0) |
| #define I2S1_TFR0 I2S_TFR_REG(I2S1_BASE_PTR,0) |
| #define I2S1_TMR I2S_TMR_REG(I2S1_BASE_PTR) |
| #define I2S1_RCSR I2S_RCSR_REG(I2S1_BASE_PTR) |
| #define I2S1_RCR1 I2S_RCR1_REG(I2S1_BASE_PTR) |
| #define I2S1_RCR2 I2S_RCR2_REG(I2S1_BASE_PTR) |
| #define I2S1_RCR3 I2S_RCR3_REG(I2S1_BASE_PTR) |
| #define I2S1_RCR4 I2S_RCR4_REG(I2S1_BASE_PTR) |
| #define I2S1_RCR5 I2S_RCR5_REG(I2S1_BASE_PTR) |
| #define I2S1_RDR0 I2S_RDR_REG(I2S1_BASE_PTR,0) |
| #define I2S1_RFR0 I2S_RFR_REG(I2S1_BASE_PTR,0) |
| #define I2S1_RMR I2S_RMR_REG(I2S1_BASE_PTR) |
| /* I2S2 */ |
| #define I2S2_TCSR I2S_TCSR_REG(I2S2_BASE_PTR) |
| #define I2S2_TCR1 I2S_TCR1_REG(I2S2_BASE_PTR) |
| #define I2S2_TCR2 I2S_TCR2_REG(I2S2_BASE_PTR) |
| #define I2S2_TCR3 I2S_TCR3_REG(I2S2_BASE_PTR) |
| #define I2S2_TCR4 I2S_TCR4_REG(I2S2_BASE_PTR) |
| #define I2S2_TCR5 I2S_TCR5_REG(I2S2_BASE_PTR) |
| #define I2S2_TDR0 I2S_TDR_REG(I2S2_BASE_PTR,0) |
| #define I2S2_TFR0 I2S_TFR_REG(I2S2_BASE_PTR,0) |
| #define I2S2_TMR I2S_TMR_REG(I2S2_BASE_PTR) |
| #define I2S2_RCSR I2S_RCSR_REG(I2S2_BASE_PTR) |
| #define I2S2_RCR1 I2S_RCR1_REG(I2S2_BASE_PTR) |
| #define I2S2_RCR2 I2S_RCR2_REG(I2S2_BASE_PTR) |
| #define I2S2_RCR3 I2S_RCR3_REG(I2S2_BASE_PTR) |
| #define I2S2_RCR4 I2S_RCR4_REG(I2S2_BASE_PTR) |
| #define I2S2_RCR5 I2S_RCR5_REG(I2S2_BASE_PTR) |
| #define I2S2_RDR0 I2S_RDR_REG(I2S2_BASE_PTR,0) |
| #define I2S2_RFR0 I2S_RFR_REG(I2S2_BASE_PTR,0) |
| #define I2S2_RMR I2S_RMR_REG(I2S2_BASE_PTR) |
| /* I2S - Register array accessors */ |
| #define I2S1_TDR(index) I2S_TDR_REG(I2S1_BASE_PTR,index) |
| #define I2S2_TDR(index) I2S_TDR_REG(I2S2_BASE_PTR,index) |
| #define I2S1_TFR(index) I2S_TFR_REG(I2S1_BASE_PTR,index) |
| #define I2S2_TFR(index) I2S_TFR_REG(I2S2_BASE_PTR,index) |
| #define I2S1_RDR(index) I2S_RDR_REG(I2S1_BASE_PTR,index) |
| #define I2S2_RDR(index) I2S_RDR_REG(I2S2_BASE_PTR,index) |
| #define I2S1_RFR(index) I2S_RFR_REG(I2S1_BASE_PTR,index) |
| #define I2S2_RFR(index) I2S_RFR_REG(I2S2_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group I2S_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** IOMUXC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[20]; |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO00; /**< Pad Mux Register, offset: 0x14 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO01; /**< Pad Mux Register, offset: 0x18 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO02; /**< Pad Mux Register, offset: 0x1C */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO03; /**< Pad Mux Register, offset: 0x20 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO04; /**< Pad Mux Register, offset: 0x24 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO05; /**< Pad Mux Register, offset: 0x28 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO06; /**< Pad Mux Register, offset: 0x2C */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO07; /**< Pad Mux Register, offset: 0x30 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO08; /**< Pad Mux Register, offset: 0x34 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO09; /**< Pad Mux Register, offset: 0x38 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO10; /**< Pad Mux Register, offset: 0x3C */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO11; /**< Pad Mux Register, offset: 0x40 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO12; /**< Pad Mux Register, offset: 0x44 */ |
| __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO13; /**< Pad Mux Register, offset: 0x48 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA00; /**< Pad Mux Register, offset: 0x4C */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA01; /**< Pad Mux Register, offset: 0x50 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA02; /**< Pad Mux Register, offset: 0x54 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA03; /**< Pad Mux Register, offset: 0x58 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA04; /**< Pad Mux Register, offset: 0x5C */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA05; /**< Pad Mux Register, offset: 0x60 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA06; /**< Pad Mux Register, offset: 0x64 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_DATA07; /**< Pad Mux Register, offset: 0x68 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_HSYNC; /**< Pad Mux Register, offset: 0x6C */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_MCLK; /**< Pad Mux Register, offset: 0x70 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_PIXCLK; /**< Pad Mux Register, offset: 0x74 */ |
| __IO uint32_t SW_MUX_CTL_PAD_CSI_VSYNC; /**< Pad Mux Register, offset: 0x78 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_COL; /**< Pad Mux Register, offset: 0x7C */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_CRS; /**< Pad Mux Register, offset: 0x80 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_MDC; /**< Pad Mux Register, offset: 0x84 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_MDIO; /**< Pad Mux Register, offset: 0x88 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_RX_CLK; /**< Pad Mux Register, offset: 0x8C */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET1_TX_CLK; /**< Pad Mux Register, offset: 0x90 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET2_COL; /**< Pad Mux Register, offset: 0x94 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET2_CRS; /**< Pad Mux Register, offset: 0x98 */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET2_RX_CLK; /**< Pad Mux Register, offset: 0x9C */ |
| __IO uint32_t SW_MUX_CTL_PAD_ENET2_TX_CLK; /**< Pad Mux Register, offset: 0xA0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_COL0; /**< Pad Mux Register, offset: 0xA4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_COL1; /**< Pad Mux Register, offset: 0xA8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_COL2; /**< Pad Mux Register, offset: 0xAC */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_COL3; /**< Pad Mux Register, offset: 0xB0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_COL4; /**< Pad Mux Register, offset: 0xB4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_ROW0; /**< Pad Mux Register, offset: 0xB8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_ROW1; /**< Pad Mux Register, offset: 0xBC */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_ROW2; /**< Pad Mux Register, offset: 0xC0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_ROW3; /**< Pad Mux Register, offset: 0xC4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_KEY_ROW4; /**< Pad Mux Register, offset: 0xC8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_CLK; /**< Pad Mux Register, offset: 0xCC */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA00; /**< Pad Mux Register, offset: 0xD0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA01; /**< Pad Mux Register, offset: 0xD4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA02; /**< Pad Mux Register, offset: 0xD8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA03; /**< Pad Mux Register, offset: 0xDC */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA04; /**< Pad Mux Register, offset: 0xE0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA05; /**< Pad Mux Register, offset: 0xE4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA06; /**< Pad Mux Register, offset: 0xE8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA07; /**< Pad Mux Register, offset: 0xEC */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA08; /**< Pad Mux Register, offset: 0xF0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA09; /**< Pad Mux Register, offset: 0xF4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA10; /**< Pad Mux Register, offset: 0xF8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA11; /**< Pad Mux Register, offset: 0xFC */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA12; /**< Pad Mux Register, offset: 0x100 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA13; /**< Pad Mux Register, offset: 0x104 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA14; /**< Pad Mux Register, offset: 0x108 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA15; /**< Pad Mux Register, offset: 0x10C */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA16; /**< Pad Mux Register, offset: 0x110 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA17; /**< Pad Mux Register, offset: 0x114 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA18; /**< Pad Mux Register, offset: 0x118 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA19; /**< Pad Mux Register, offset: 0x11C */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA20; /**< Pad Mux Register, offset: 0x120 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA21; /**< Pad Mux Register, offset: 0x124 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA22; /**< Pad Mux Register, offset: 0x128 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_DATA23; /**< Pad Mux Register, offset: 0x12C */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_ENABLE; /**< Pad Mux Register, offset: 0x130 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_HSYNC; /**< Pad Mux Register, offset: 0x134 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_RESET; /**< Pad Mux Register, offset: 0x138 */ |
| __IO uint32_t SW_MUX_CTL_PAD_LCD1_VSYNC; /**< Pad Mux Register, offset: 0x13C */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_ALE; /**< Pad Mux Register, offset: 0x140 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_CE0_B; /**< Pad Mux Register, offset: 0x144 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_CE1_B; /**< Pad Mux Register, offset: 0x148 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_CLE; /**< Pad Mux Register, offset: 0x14C */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA00; /**< Pad Mux Register, offset: 0x150 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA01; /**< Pad Mux Register, offset: 0x154 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA02; /**< Pad Mux Register, offset: 0x158 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA03; /**< Pad Mux Register, offset: 0x15C */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA04; /**< Pad Mux Register, offset: 0x160 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA05; /**< Pad Mux Register, offset: 0x164 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA06; /**< Pad Mux Register, offset: 0x168 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_DATA07; /**< Pad Mux Register, offset: 0x16C */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_RE_B; /**< Pad Mux Register, offset: 0x170 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_READY_B; /**< Pad Mux Register, offset: 0x174 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_WE_B; /**< Pad Mux Register, offset: 0x178 */ |
| __IO uint32_t SW_MUX_CTL_PAD_NAND_WP_B; /**< Pad Mux Register, offset: 0x17C */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA0; /**< Pad Mux Register, offset: 0x180 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA1; /**< Pad Mux Register, offset: 0x184 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA2; /**< Pad Mux Register, offset: 0x188 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_DATA3; /**< Pad Mux Register, offset: 0x18C */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_DQS; /**< Pad Mux Register, offset: 0x190 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_SCLK; /**< Pad Mux Register, offset: 0x194 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_SS0_B; /**< Pad Mux Register, offset: 0x198 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1A_SS1_B; /**< Pad Mux Register, offset: 0x19C */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA0; /**< Pad Mux Register, offset: 0x1A0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA1; /**< Pad Mux Register, offset: 0x1A4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA2; /**< Pad Mux Register, offset: 0x1A8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_DATA3; /**< Pad Mux Register, offset: 0x1AC */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_DQS; /**< Pad Mux Register, offset: 0x1B0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_SCLK; /**< Pad Mux Register, offset: 0x1B4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_SS0_B; /**< Pad Mux Register, offset: 0x1B8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_QSPI1B_SS1_B; /**< Pad Mux Register, offset: 0x1BC */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RD0; /**< Pad Mux Register, offset: 0x1C0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RD1; /**< Pad Mux Register, offset: 0x1C4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RD2; /**< Pad Mux Register, offset: 0x1C8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RD3; /**< Pad Mux Register, offset: 0x1CC */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RX_CTL; /**< Pad Mux Register, offset: 0x1D0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_RXC; /**< Pad Mux Register, offset: 0x1D4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TD0; /**< Pad Mux Register, offset: 0x1D8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TD1; /**< Pad Mux Register, offset: 0x1DC */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TD2; /**< Pad Mux Register, offset: 0x1E0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TD3; /**< Pad Mux Register, offset: 0x1E4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TX_CTL; /**< Pad Mux Register, offset: 0x1E8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII1_TXC; /**< Pad Mux Register, offset: 0x1EC */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RD0; /**< Pad Mux Register, offset: 0x1F0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RD1; /**< Pad Mux Register, offset: 0x1F4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RD2; /**< Pad Mux Register, offset: 0x1F8 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RD3; /**< Pad Mux Register, offset: 0x1FC */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RX_CTL; /**< Pad Mux Register, offset: 0x200 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_RXC; /**< Pad Mux Register, offset: 0x204 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TD0; /**< Pad Mux Register, offset: 0x208 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TD1; /**< Pad Mux Register, offset: 0x20C */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TD2; /**< Pad Mux Register, offset: 0x210 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TD3; /**< Pad Mux Register, offset: 0x214 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TX_CTL; /**< Pad Mux Register, offset: 0x218 */ |
| __IO uint32_t SW_MUX_CTL_PAD_RGMII2_TXC; /**< Pad Mux Register, offset: 0x21C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_CLK; /**< Pad Mux Register, offset: 0x220 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_CMD; /**< Pad Mux Register, offset: 0x224 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA0; /**< Pad Mux Register, offset: 0x228 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA1; /**< Pad Mux Register, offset: 0x22C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA2; /**< Pad Mux Register, offset: 0x230 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA3; /**< Pad Mux Register, offset: 0x234 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_CLK; /**< Pad Mux Register, offset: 0x238 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_CMD; /**< Pad Mux Register, offset: 0x23C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA0; /**< Pad Mux Register, offset: 0x240 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA1; /**< Pad Mux Register, offset: 0x244 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA2; /**< Pad Mux Register, offset: 0x248 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA3; /**< Pad Mux Register, offset: 0x24C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_CLK; /**< Pad Mux Register, offset: 0x250 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_CMD; /**< Pad Mux Register, offset: 0x254 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA0; /**< Pad Mux Register, offset: 0x258 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA1; /**< Pad Mux Register, offset: 0x25C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA2; /**< Pad Mux Register, offset: 0x260 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA3; /**< Pad Mux Register, offset: 0x264 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA4; /**< Pad Mux Register, offset: 0x268 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA5; /**< Pad Mux Register, offset: 0x26C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA6; /**< Pad Mux Register, offset: 0x270 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA7; /**< Pad Mux Register, offset: 0x274 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_CLK; /**< Pad Mux Register, offset: 0x278 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_CMD; /**< Pad Mux Register, offset: 0x27C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA0; /**< Pad Mux Register, offset: 0x280 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA1; /**< Pad Mux Register, offset: 0x284 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA2; /**< Pad Mux Register, offset: 0x288 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA3; /**< Pad Mux Register, offset: 0x28C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA4; /**< Pad Mux Register, offset: 0x290 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA5; /**< Pad Mux Register, offset: 0x294 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA6; /**< Pad Mux Register, offset: 0x298 */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_DATA7; /**< Pad Mux Register, offset: 0x29C */ |
| __IO uint32_t SW_MUX_CTL_PAD_SD4_RESET_B; /**< Pad Mux Register, offset: 0x2A0 */ |
| __IO uint32_t SW_MUX_CTL_PAD_USB_H_DATA; /**< Pad Mux Register, offset: 0x2A4 */ |
| __IO uint32_t SW_MUX_CTL_PAD_USB_H_STROBE; /**< Pad Mux Register, offset: 0x2A8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR00; /**< Pad Control Register, offset: 0x2AC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR01; /**< Pad Control Register, offset: 0x2B0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR02; /**< Pad Control Register, offset: 0x2B4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR03; /**< Pad Control Register, offset: 0x2B8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR04; /**< Pad Control Register, offset: 0x2BC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR05; /**< Pad Control Register, offset: 0x2C0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR06; /**< Pad Control Register, offset: 0x2C4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR07; /**< Pad Control Register, offset: 0x2C8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR08; /**< Pad Control Register, offset: 0x2CC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR09; /**< Pad Control Register, offset: 0x2D0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR10; /**< Pad Control Register, offset: 0x2D4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR11; /**< Pad Control Register, offset: 0x2D8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR12; /**< Pad Control Register, offset: 0x2DC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR13; /**< Pad Control Register, offset: 0x2E0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR14; /**< Pad Control Register, offset: 0x2E4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ADDR15; /**< Pad Control Register, offset: 0x2E8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_DQM0; /**< Pad Control Register, offset: 0x2EC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_DQM1; /**< Pad Control Register, offset: 0x2F0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_DQM2; /**< Pad Control Register, offset: 0x2F4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_DQM3; /**< Pad Control Register, offset: 0x2F8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_RAS_B; /**< Pad Control Register, offset: 0x2FC */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_CAS_B; /**< Pad Control Register, offset: 0x300 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_CS0_B; /**< Pad Control Register, offset: 0x304 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_CS1_B; /**< Pad Control Register, offset: 0x308 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDWE_B; /**< Pad Control Register, offset: 0x30C */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ODT0; /**< Pad Control Register, offset: 0x310 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_ODT1; /**< Pad Control Register, offset: 0x314 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDBA0; /**< Pad Control Register, offset: 0x318 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDBA1; /**< Pad Control Register, offset: 0x31C */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDBA2; /**< Pad Control Register, offset: 0x320 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDCKE0; /**< Pad Control Register, offset: 0x324 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDCKE1; /**< Pad Control Register, offset: 0x328 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDCLK0_P; /**< Pad Control Register, offset: 0x32C */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDQS0_P; /**< Pad Control Register, offset: 0x330 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDQS1_P; /**< Pad Control Register, offset: 0x334 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDQS2_P; /**< Pad Control Register, offset: 0x338 */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_SDQS3_P; /**< Pad Control Register, offset: 0x33C */ |
| __IO uint32_t SW_PAD_CTL_PAD_DRAM_RESET; /**< Pad Control Register, offset: 0x340 */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_MOD; /**< Pad Control Register, offset: 0x344 */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_TCK; /**< Pad Control Register, offset: 0x348 */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_TDI; /**< Pad Control Register, offset: 0x34C */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_TDO; /**< Pad Control Register, offset: 0x350 */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_TMS; /**< Pad Control Register, offset: 0x354 */ |
| __IO uint32_t SW_PAD_CTL_PAD_JTAG_TRST_B; /**< Pad Control Register, offset: 0x358 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO00; /**< Pad Control Register, offset: 0x35C */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO01; /**< Pad Control Register, offset: 0x360 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO02; /**< Pad Control Register, offset: 0x364 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO03; /**< Pad Control Register, offset: 0x368 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO04; /**< Pad Control Register, offset: 0x36C */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO05; /**< Pad Control Register, offset: 0x370 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO06; /**< Pad Control Register, offset: 0x374 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO07; /**< Pad Control Register, offset: 0x378 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO08; /**< Pad Control Register, offset: 0x37C */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO09; /**< Pad Control Register, offset: 0x380 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO10; /**< Pad Control Register, offset: 0x384 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO11; /**< Pad Control Register, offset: 0x388 */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO12; /**< Pad Control Register, offset: 0x38C */ |
| __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO13; /**< Pad Control Register, offset: 0x390 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA00; /**< Pad Control Register, offset: 0x394 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA01; /**< Pad Control Register, offset: 0x398 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA02; /**< Pad Control Register, offset: 0x39C */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA03; /**< Pad Control Register, offset: 0x3A0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA04; /**< Pad Control Register, offset: 0x3A4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA05; /**< Pad Control Register, offset: 0x3A8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA06; /**< Pad Control Register, offset: 0x3AC */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_DATA07; /**< Pad Control Register, offset: 0x3B0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_HSYNC; /**< Pad Control Register, offset: 0x3B4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_MCLK; /**< Pad Control Register, offset: 0x3B8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_PIXCLK; /**< Pad Control Register, offset: 0x3BC */ |
| __IO uint32_t SW_PAD_CTL_PAD_CSI_VSYNC; /**< Pad Control Register, offset: 0x3C0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_COL; /**< Pad Control Register, offset: 0x3C4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_CRS; /**< Pad Control Register, offset: 0x3C8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_MDC; /**< Pad Control Register, offset: 0x3CC */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_MDIO; /**< Pad Control Register, offset: 0x3D0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_RX_CLK; /**< Pad Control Register, offset: 0x3D4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK; /**< Pad Control Register, offset: 0x3D8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET2_COL; /**< Pad Control Register, offset: 0x3DC */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET2_CRS; /**< Pad Control Register, offset: 0x3E0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET2_RX_CLK; /**< Pad Control Register, offset: 0x3E4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_ENET2_TX_CLK; /**< Pad Control Register, offset: 0x3E8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_COL0; /**< Pad Control Register, offset: 0x3EC */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_COL1; /**< Pad Control Register, offset: 0x3F0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_COL2; /**< Pad Control Register, offset: 0x3F4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_COL3; /**< Pad Control Register, offset: 0x3F8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_COL4; /**< Pad Control Register, offset: 0x3FC */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_ROW0; /**< Pad Control Register, offset: 0x400 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_ROW1; /**< Pad Control Register, offset: 0x404 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_ROW2; /**< Pad Control Register, offset: 0x408 */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_ROW3; /**< Pad Control Register, offset: 0x40C */ |
| __IO uint32_t SW_PAD_CTL_PAD_KEY_ROW4; /**< Pad Control Register, offset: 0x410 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_CLK; /**< Pad Control Register, offset: 0x414 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA00; /**< Pad Control Register, offset: 0x418 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA01; /**< Pad Control Register, offset: 0x41C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA02; /**< Pad Control Register, offset: 0x420 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA03; /**< Pad Control Register, offset: 0x424 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA04; /**< Pad Control Register, offset: 0x428 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA05; /**< Pad Control Register, offset: 0x42C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA06; /**< Pad Control Register, offset: 0x430 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA07; /**< Pad Control Register, offset: 0x434 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA08; /**< Pad Control Register, offset: 0x438 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA09; /**< Pad Control Register, offset: 0x43C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA10; /**< Pad Control Register, offset: 0x440 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA11; /**< Pad Control Register, offset: 0x444 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA12; /**< Pad Control Register, offset: 0x448 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA13; /**< Pad Control Register, offset: 0x44C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA14; /**< Pad Control Register, offset: 0x450 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA15; /**< Pad Control Register, offset: 0x454 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA16; /**< Pad Control Register, offset: 0x458 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA17; /**< Pad Control Register, offset: 0x45C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA18; /**< Pad Control Register, offset: 0x460 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA19; /**< Pad Control Register, offset: 0x464 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA20; /**< Pad Control Register, offset: 0x468 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA21; /**< Pad Control Register, offset: 0x46C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA22; /**< Pad Control Register, offset: 0x470 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_DATA23; /**< Pad Control Register, offset: 0x474 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_ENABLE; /**< Pad Control Register, offset: 0x478 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_HSYNC; /**< Pad Control Register, offset: 0x47C */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_RESET; /**< Pad Control Register, offset: 0x480 */ |
| __IO uint32_t SW_PAD_CTL_PAD_LCD1_VSYNC; /**< Pad Control Register, offset: 0x484 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_ALE; /**< Pad Control Register, offset: 0x488 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_CE0_B; /**< Pad Control Register, offset: 0x48C */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_CE1_B; /**< Pad Control Register, offset: 0x490 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_CLE; /**< Pad Control Register, offset: 0x494 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA00; /**< Pad Control Register, offset: 0x498 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA01; /**< Pad Control Register, offset: 0x49C */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA02; /**< Pad Control Register, offset: 0x4A0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA03; /**< Pad Control Register, offset: 0x4A4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA04; /**< Pad Control Register, offset: 0x4A8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA05; /**< Pad Control Register, offset: 0x4AC */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA06; /**< Pad Control Register, offset: 0x4B0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_DATA07; /**< Pad Control Register, offset: 0x4B4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_RE_B; /**< Pad Control Register, offset: 0x4B8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_READY_B; /**< Pad Control Register, offset: 0x4BC */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_WE_B; /**< Pad Control Register, offset: 0x4C0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_NAND_WP_B; /**< Pad Control Register, offset: 0x4C4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA0; /**< Pad Control Register, offset: 0x4C8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA1; /**< Pad Control Register, offset: 0x4CC */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA2; /**< Pad Control Register, offset: 0x4D0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_DATA3; /**< Pad Control Register, offset: 0x4D4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_DQS; /**< Pad Control Register, offset: 0x4D8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_SCLK; /**< Pad Control Register, offset: 0x4DC */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_SS0_B; /**< Pad Control Register, offset: 0x4E0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1A_SS1_B; /**< Pad Control Register, offset: 0x4E4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA0; /**< Pad Control Register, offset: 0x4E8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA1; /**< Pad Control Register, offset: 0x4EC */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA2; /**< Pad Control Register, offset: 0x4F0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_DATA3; /**< Pad Control Register, offset: 0x4F4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_DQS; /**< Pad Control Register, offset: 0x4F8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_SCLK; /**< Pad Control Register, offset: 0x4FC */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_SS0_B; /**< Pad Control Register, offset: 0x500 */ |
| __IO uint32_t SW_PAD_CTL_PAD_QSPI1B_SS1_B; /**< Pad Control Register, offset: 0x504 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RD0; /**< Pad Control Register, offset: 0x508 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RD1; /**< Pad Control Register, offset: 0x50C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RD2; /**< Pad Control Register, offset: 0x510 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RD3; /**< Pad Control Register, offset: 0x514 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RX_CTL; /**< Pad Control Register, offset: 0x518 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_RXC; /**< Pad Control Register, offset: 0x51C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TD0; /**< Pad Control Register, offset: 0x520 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TD1; /**< Pad Control Register, offset: 0x524 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TD2; /**< Pad Control Register, offset: 0x528 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TD3; /**< Pad Control Register, offset: 0x52C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TX_CTL; /**< Pad Control Register, offset: 0x530 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII1_TXC; /**< Pad Control Register, offset: 0x534 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RD0; /**< Pad Control Register, offset: 0x538 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RD1; /**< Pad Control Register, offset: 0x53C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RD2; /**< Pad Control Register, offset: 0x540 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RD3; /**< Pad Control Register, offset: 0x544 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RX_CTL; /**< Pad Control Register, offset: 0x548 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_RXC; /**< Pad Control Register, offset: 0x54C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TD0; /**< Pad Control Register, offset: 0x550 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TD1; /**< Pad Control Register, offset: 0x554 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TD2; /**< Pad Control Register, offset: 0x558 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TD3; /**< Pad Control Register, offset: 0x55C */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TX_CTL; /**< Pad Control Register, offset: 0x560 */ |
| __IO uint32_t SW_PAD_CTL_PAD_RGMII2_TXC; /**< Pad Control Register, offset: 0x564 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_CLK; /**< Pad Control Register, offset: 0x568 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_CMD; /**< Pad Control Register, offset: 0x56C */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA0; /**< Pad Control Register, offset: 0x570 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA1; /**< Pad Control Register, offset: 0x574 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA2; /**< Pad Control Register, offset: 0x578 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA3; /**< Pad Control Register, offset: 0x57C */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_CLK; /**< Pad Control Register, offset: 0x580 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_CMD; /**< Pad Control Register, offset: 0x584 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA0; /**< Pad Control Register, offset: 0x588 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA1; /**< Pad Control Register, offset: 0x58C */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA2; /**< Pad Control Register, offset: 0x590 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA3; /**< Pad Control Register, offset: 0x594 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_CLK; /**< Pad Control Register, offset: 0x598 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_CMD; /**< Pad Control Register, offset: 0x59C */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA0; /**< Pad Control Register, offset: 0x5A0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA1; /**< Pad Control Register, offset: 0x5A4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA2; /**< Pad Control Register, offset: 0x5A8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA3; /**< Pad Control Register, offset: 0x5AC */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA4; /**< Pad Control Register, offset: 0x5B0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA5; /**< Pad Control Register, offset: 0x5B4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA6; /**< Pad Control Register, offset: 0x5B8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA7; /**< Pad Control Register, offset: 0x5BC */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_CLK; /**< Pad Control Register, offset: 0x5C0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_CMD; /**< Pad Control Register, offset: 0x5C4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA0; /**< Pad Control Register, offset: 0x5C8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA1; /**< Pad Control Register, offset: 0x5CC */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA2; /**< Pad Control Register, offset: 0x5D0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA3; /**< Pad Control Register, offset: 0x5D4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA4; /**< Pad Control Register, offset: 0x5D8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA5; /**< Pad Control Register, offset: 0x5DC */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA6; /**< Pad Control Register, offset: 0x5E0 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_DATA7; /**< Pad Control Register, offset: 0x5E4 */ |
| __IO uint32_t SW_PAD_CTL_PAD_SD4_RESET_B; /**< Pad Control Register, offset: 0x5E8 */ |
| __IO uint32_t SW_PAD_CTL_PAD_USB_H_DATA; /**< Pad Control Register, offset: 0x5EC */ |
| __IO uint32_t SW_PAD_CTL_PAD_USB_H_STROBE; /**< Pad Control Register, offset: 0x5F0 */ |
| __IO uint32_t SW_PAD_CTL_GRP_ADDDS; /**< Pad Group Control Register, offset: 0x5F4 */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDRMODE_CTL; /**< Pad Group Control Register, offset: 0x5F8 */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDRPKE; /**< Pad Group Control Register, offset: 0x5FC */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDRPK; /**< Pad Group Control Register, offset: 0x600 */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDRHYS; /**< Pad Group Control Register, offset: 0x604 */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDRMODE; /**< Pad Group Control Register, offset: 0x608 */ |
| __IO uint32_t SW_PAD_CTL_GRP_B0DS; /**< Pad Group Control Register, offset: 0x60C */ |
| __IO uint32_t SW_PAD_CTL_GRP_B1DS; /**< Pad Group Control Register, offset: 0x610 */ |
| __IO uint32_t SW_PAD_CTL_GRP_CTLDS; /**< Pad Group Control Register, offset: 0x614 */ |
| __IO uint32_t SW_PAD_CTL_GRP_DDR_TYPE; /**< Pad Group Control Register, offset: 0x618 */ |
| __IO uint32_t SW_PAD_CTL_GRP_B2DS; /**< Pad Group Control Register, offset: 0x61C */ |
| __IO uint32_t SW_PAD_CTL_GRP_B3DS; /**< Pad Group Control Register, offset: 0x620 */ |
| __IO uint32_t ANATOP_USB_OTG_ID_SELECT_INPUT; /**< Select Input Register, offset: 0x624 */ |
| __IO uint32_t ANATOP_USB_UH1_ID_SELECT_INPUT; /**< Select Input Register, offset: 0x628 */ |
| __IO uint32_t AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x62C */ |
| __IO uint32_t AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x630 */ |
| __IO uint32_t AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x634 */ |
| __IO uint32_t AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x638 */ |
| __IO uint32_t AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x63C */ |
| __IO uint32_t AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x640 */ |
| __IO uint32_t AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x644 */ |
| __IO uint32_t AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x648 */ |
| __IO uint32_t AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x64C */ |
| __IO uint32_t AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x650 */ |
| __IO uint32_t AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x654 */ |
| __IO uint32_t AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x658 */ |
| __IO uint32_t AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x65C */ |
| __IO uint32_t AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x660 */ |
| __IO uint32_t AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x664 */ |
| __IO uint32_t AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x668 */ |
| __IO uint32_t AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x66C */ |
| __IO uint32_t AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x670 */ |
| __IO uint32_t AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x674 */ |
| __IO uint32_t AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x678 */ |
| __IO uint32_t AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x67C */ |
| __IO uint32_t AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x680 */ |
| __IO uint32_t AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x684 */ |
| __IO uint32_t AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT; /**< Select Input Register, offset: 0x688 */ |
| __IO uint32_t CAN1_IPP_IND_CANRX_SELECT_INPUT; /**< Select Input Register, offset: 0x68C */ |
| __IO uint32_t CAN2_IPP_IND_CANRX_SELECT_INPUT; /**< Select Input Register, offset: 0x690 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT; /**< Select Input Register, offset: 0x69C */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_0; /**< Select Input Register, offset: 0x6A0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_1; /**< Select Input Register, offset: 0x6A4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_2; /**< Select Input Register, offset: 0x6A8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_3; /**< Select Input Register, offset: 0x6AC */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_4; /**< Select Input Register, offset: 0x6B0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_5; /**< Select Input Register, offset: 0x6B4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_6; /**< Select Input Register, offset: 0x6B8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_7; /**< Select Input Register, offset: 0x6BC */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_8; /**< Select Input Register, offset: 0x6C0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_9; /**< Select Input Register, offset: 0x6C4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_11; /**< Select Input Register, offset: 0x6C8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_12; /**< Select Input Register, offset: 0x6CC */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_13; /**< Select Input Register, offset: 0x6D0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_14; /**< Select Input Register, offset: 0x6D4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_15; /**< Select Input Register, offset: 0x6D8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_16; /**< Select Input Register, offset: 0x6DC */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_17; /**< Select Input Register, offset: 0x6E0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_18; /**< Select Input Register, offset: 0x6E4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_19; /**< Select Input Register, offset: 0x6E8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_20; /**< Select Input Register, offset: 0x6EC */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_21; /**< Select Input Register, offset: 0x6F0 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_22; /**< Select Input Register, offset: 0x6F4 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_23; /**< Select Input Register, offset: 0x6F8 */ |
| __IO uint32_t CSI1_IPP_CSI_D_SELECT_INPUT_10; /**< Select Input Register, offset: 0x6FC */ |
| __IO uint32_t CSI1_IPP_CSI_HSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x700 */ |
| __IO uint32_t CSI1_IPP_CSI_PIXCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x704 */ |
| __IO uint32_t CSI1_IPP_CSI_VSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x708 */ |
| __IO uint32_t CSI1_TVDECODER_IN_FIELD_SELECT_INPUT; /**< Select Input Register, offset: 0x70C */ |
| __IO uint32_t ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x710 */ |
| __IO uint32_t ECSPI1_IPP_IND_MISO_SELECT_INPUT; /**< Select Input Register, offset: 0x714 */ |
| __IO uint32_t ECSPI1_IPP_IND_MOSI_SELECT_INPUT; /**< Select Input Register, offset: 0x718 */ |
| __IO uint32_t ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0; /**< Select Input Register, offset: 0x71C */ |
| __IO uint32_t ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x720 */ |
| __IO uint32_t ECSPI2_IPP_IND_MISO_SELECT_INPUT; /**< Select Input Register, offset: 0x724 */ |
| __IO uint32_t ECSPI2_IPP_IND_MOSI_SELECT_INPUT; /**< Select Input Register, offset: 0x728 */ |
| __IO uint32_t ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0; /**< Select Input Register, offset: 0x72C */ |
| __IO uint32_t ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x730 */ |
| __IO uint32_t ECSPI3_IPP_IND_MISO_SELECT_INPUT; /**< Select Input Register, offset: 0x734 */ |
| __IO uint32_t ECSPI3_IPP_IND_MOSI_SELECT_INPUT; /**< Select Input Register, offset: 0x738 */ |
| __IO uint32_t ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0; /**< Select Input Register, offset: 0x73C */ |
| __IO uint32_t ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x740 */ |
| __IO uint32_t ECSPI4_IPP_IND_MISO_SELECT_INPUT; /**< Select Input Register, offset: 0x744 */ |
| __IO uint32_t ECSPI4_IPP_IND_MOSI_SELECT_INPUT; /**< Select Input Register, offset: 0x748 */ |
| __IO uint32_t ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0; /**< Select Input Register, offset: 0x74C */ |
| __IO uint32_t ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x750 */ |
| __IO uint32_t ECSPI5_IPP_IND_MISO_SELECT_INPUT; /**< Select Input Register, offset: 0x754 */ |
| __IO uint32_t ECSPI5_IPP_IND_MOSI_SELECT_INPUT; /**< Select Input Register, offset: 0x758 */ |
| __IO uint32_t ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0; /**< Select Input Register, offset: 0x75C */ |
| __IO uint32_t ENET1_IPG_CLK_RMII_SELECT_INPUT; /**< Select Input Register, offset: 0x760 */ |
| __IO uint32_t ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT; /**< Select Input Register, offset: 0x764 */ |
| __IO uint32_t ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x768 */ |
| __IO uint32_t ENET2_IPG_CLK_RMII_SELECT_INPUT; /**< Select Input Register, offset: 0x76C */ |
| __IO uint32_t ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT; /**< Select Input Register, offset: 0x770 */ |
| __IO uint32_t ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x774 */ |
| __IO uint32_t ESAI_IPP_IND_FSR_SELECT_INPUT; /**< Select Input Register, offset: 0x778 */ |
| __IO uint32_t ESAI_IPP_IND_FST_SELECT_INPUT; /**< Select Input Register, offset: 0x77C */ |
| __IO uint32_t ESAI_IPP_IND_HCKR_SELECT_INPUT; /**< Select Input Register, offset: 0x780 */ |
| __IO uint32_t ESAI_IPP_IND_HCKT_SELECT_INPUT; /**< Select Input Register, offset: 0x784 */ |
| __IO uint32_t ESAI_IPP_IND_SCKR_SELECT_INPUT; /**< Select Input Register, offset: 0x788 */ |
| __IO uint32_t ESAI_IPP_IND_SCKT_SELECT_INPUT; /**< Select Input Register, offset: 0x78C */ |
| __IO uint32_t ESAI_IPP_IND_SDO0_SELECT_INPUT; /**< Select Input Register, offset: 0x790 */ |
| __IO uint32_t ESAI_IPP_IND_SDO1_SELECT_INPUT; /**< Select Input Register, offset: 0x794 */ |
| __IO uint32_t ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT; /**< Select Input Register, offset: 0x798 */ |
| __IO uint32_t ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT; /**< Select Input Register, offset: 0x79C */ |
| __IO uint32_t ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT; /**< Select Input Register, offset: 0x7A0 */ |
| __IO uint32_t ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT; /**< Select Input Register, offset: 0x7A4 */ |
| __IO uint32_t I2C1_IPP_SCL_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7A8 */ |
| __IO uint32_t I2C1_IPP_SDA_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7AC */ |
| __IO uint32_t I2C2_IPP_SCL_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7B0 */ |
| __IO uint32_t I2C2_IPP_SDA_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7B4 */ |
| __IO uint32_t I2C3_IPP_SCL_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7B8 */ |
| __IO uint32_t I2C3_IPP_SDA_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7BC */ |
| __IO uint32_t I2C4_IPP_SCL_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7C0 */ |
| __IO uint32_t I2C4_IPP_SDA_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7C4 */ |
| __IO uint32_t KPP_IPP_IND_COL_SELECT_INPUT_5; /**< Select Input Register, offset: 0x7C8 */ |
| __IO uint32_t KPP_IPP_IND_COL_SELECT_INPUT_6; /**< Select Input Register, offset: 0x7CC */ |
| __IO uint32_t KPP_IPP_IND_COL_SELECT_INPUT_7; /**< Select Input Register, offset: 0x7D0 */ |
| __IO uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_5; /**< Select Input Register, offset: 0x7D4 */ |
| __IO uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_6; /**< Select Input Register, offset: 0x7D8 */ |
| __IO uint32_t KPP_IPP_IND_ROW_SELECT_INPUT_7; /**< Select Input Register, offset: 0x7DC */ |
| __IO uint32_t LCD1_BUSY_SELECT_INPUT; /**< Select Input Register, offset: 0x7E0 */ |
| __IO uint32_t LCD2_BUSY_SELECT_INPUT; /**< Select Input Register, offset: 0x7E4 */ |
| __IO uint32_t MLB_MLB_CLK_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7E8 */ |
| __IO uint32_t MLB_MLB_DATA_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7EC */ |
| __IO uint32_t MLB_MLB_SIG_IN_SELECT_INPUT; /**< Select Input Register, offset: 0x7F0 */ |
| __IO uint32_t SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x7F4 */ |
| __IO uint32_t SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0; /**< Select Input Register, offset: 0x7F8 */ |
| __IO uint32_t SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x7FC */ |
| __IO uint32_t SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x800 */ |
| __IO uint32_t SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x804 */ |
| __IO uint32_t SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x808 */ |
| __IO uint32_t SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0; /**< Select Input Register, offset: 0x80C */ |
| __IO uint32_t SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x810 */ |
| __IO uint32_t SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT; /**< Select Input Register, offset: 0x814 */ |
| __IO uint32_t SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT; /**< Select Input Register, offset: 0x818 */ |
| __IO uint32_t SDMA_EVENTS_SELECT_INPUT_14; /**< Select Input Register, offset: 0x81C */ |
| __IO uint32_t SDMA_EVENTS_SELECT_INPUT_15; /**< Select Input Register, offset: 0x820 */ |
| __IO uint32_t SPDIF_SPDIF_IN1_SELECT_INPUT; /**< Select Input Register, offset: 0x824 */ |
| __IO uint32_t SPDIF_TX_CLK2_SELECT_INPUT; /**< Select Input Register, offset: 0x828 */ |
| __IO uint32_t UART1_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x82C */ |
| __IO uint32_t UART1_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x830 */ |
| __IO uint32_t UART2_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x834 */ |
| __IO uint32_t UART2_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x838 */ |
| __IO uint32_t UART3_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x83C */ |
| __IO uint32_t UART3_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x840 */ |
| __IO uint32_t UART4_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x844 */ |
| __IO uint32_t UART4_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x848 */ |
| __IO uint32_t UART5_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x84C */ |
| __IO uint32_t UART5_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x850 */ |
| __IO uint32_t UART6_IPP_UART_RTS_B_SELECT_INPUT; /**< Select Input Register, offset: 0x854 */ |
| __IO uint32_t UART6_IPP_UART_RXD_MUX_SELECT_INPUT; /**< Select Input Register, offset: 0x858 */ |
| __IO uint32_t USB_IPP_IND_OTG2_OC_SELECT_INPUT; /**< Select Input Register, offset: 0x85C */ |
| __IO uint32_t USB_IPP_IND_OTG_OC_SELECT_INPUT; /**< Select Input Register, offset: 0x860 */ |
| __IO uint32_t USDHC1_IPP_CARD_DET_SELECT_INPUT; /**< Select Input Register, offset: 0x864 */ |
| __IO uint32_t USDHC1_IPP_WP_ON_SELECT_INPUT; /**< Select Input Register, offset: 0x868 */ |
| __IO uint32_t USDHC2_IPP_CARD_DET_SELECT_INPUT; /**< Select Input Register, offset: 0x86C */ |
| __IO uint32_t USDHC2_IPP_WP_ON_SELECT_INPUT; /**< Select Input Register, offset: 0x870 */ |
| __IO uint32_t USDHC4_IPP_CARD_DET_SELECT_INPUT; /**< Select Input Register, offset: 0x874 */ |
| __IO uint32_t USDHC4_IPP_WP_ON_SELECT_INPUT; /**< Select Input Register, offset: 0x878 */ |
| } IOMUXC_Type, *IOMUXC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros |
| * @{ |
| */ |
| |
| /* IOMUXC - Register accessors */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO00) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA00) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA01) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA02) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA03) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA04) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA05) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA06) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA07) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_HSYNC) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_MCLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_PIXCLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_VSYNC) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDC) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDIO) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_COL) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_CRS) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_RX_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_TX_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL0) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL1) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL2) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL3) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL4) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW0) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW1) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW2) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW3) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW4) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA00) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA01) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA02) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA03) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA04) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA05) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA06) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA07) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA08) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA09) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA10) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA11) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA12) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA13) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA14) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA15) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA16) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA17) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA18) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA19) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA20) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA21) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA22) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA23) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_ENABLE) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_HSYNC) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_RESET) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_VSYNC) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_ALE) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE0_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE1_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CLE) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA00) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA01) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA02) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA03) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA04) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA05) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA06) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA07) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_RE_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_READY_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WE_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WP_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DQS) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SCLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS0_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS1_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DQS) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SCLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS0_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS1_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD0) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD1) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD2) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD3) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RX_CTL) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RXC) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD0) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD1) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD2) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD3) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TX_CTL) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TXC) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD0) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD1) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD2) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD3) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RX_CTL) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RXC) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD0) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD1) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD2) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD3) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TX_CTL) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TXC) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CLK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CMD) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA0) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA1) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA2) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA3) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA4) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA5) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA6) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA7) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_RESET_B) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_DATA) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_STROBE) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR00) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR01) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR02) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR03) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR04) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR06) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR07) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR08) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR09) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR10) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR11) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR12) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR13) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR14) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR15) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM0) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM1) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM3) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RAS_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CAS_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS0_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS1_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDWE_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT0) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT1) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE0) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE1) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCLK0_P) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS0_P) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS1_P) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS2_P) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RESET) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA00) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA01) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA02) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA03) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA04) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA05) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA06) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA07) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_HSYNC) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_MCLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_PIXCLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_VSYNC) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDC) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDIO) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_COL) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_CRS) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_RX_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_TX_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL0) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL1) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL2) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL3) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL4) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW0) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW1) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW2) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW3) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW4) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA00) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA01) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA02) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA03) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA04) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA05) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA06) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA07) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA08) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA09) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA10) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA11) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA12) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA13) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA14) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA15) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA16) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA17) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA18) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA19) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA20) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA21) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA22) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA23) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_ENABLE) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_HSYNC) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_RESET) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_VSYNC) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_ALE) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE0_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE1_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CLE) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA00) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA01) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA02) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA03) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA04) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA05) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA06) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA07) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_RE_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_READY_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WE_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WP_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DQS) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SCLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS0_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS1_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DQS) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SCLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS0_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS1_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD0) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD1) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD2) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD3) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RX_CTL) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RXC) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD0) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD1) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD2) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD3) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TX_CTL) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TXC) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD0) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD1) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD2) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD3) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RX_CTL) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RXC) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD0) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD1) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD2) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD3) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TX_CTL) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TXC) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CLK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CMD) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA0) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA1) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA2) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA3) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA4) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA5) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA6) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA7) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_RESET_B) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_DATA) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_STROBE) |
| #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(base) ((base)->SW_PAD_CTL_GRP_ADDDS) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE_CTL) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPKE) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPK) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(base) ((base)->SW_PAD_CTL_GRP_DDRHYS) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE) |
| #define IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(base) ((base)->SW_PAD_CTL_GRP_B0DS) |
| #define IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(base) ((base)->SW_PAD_CTL_GRP_B1DS) |
| #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(base) ((base)->SW_PAD_CTL_GRP_CTLDS) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(base) ((base)->SW_PAD_CTL_GRP_DDR_TYPE) |
| #define IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(base) ((base)->SW_PAD_CTL_GRP_B2DS) |
| #define IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(base) ((base)->SW_PAD_CTL_GRP_B3DS) |
| #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_OTG_ID_SELECT_INPUT) |
| #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_UH1_ID_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT) |
| #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT) |
| #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN1_IPP_IND_CANRX_SELECT_INPUT) |
| #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN2_IPP_IND_CANRX_SELECT_INPUT) |
| #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_0) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_1) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_2) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_3) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_4) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_5) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_6) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_7) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_8) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_9) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_11) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_12) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_13) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_14) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_15) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_16) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_17) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_18) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_19) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_20) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_21) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_22) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_23) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_10) |
| #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_HSYNC_SELECT_INPUT) |
| #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_PIXCLK_SELECT_INPUT) |
| #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_VSYNC_SELECT_INPUT) |
| #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(base) ((base)->CSI1_TVDECODER_IN_FIELD_SELECT_INPUT) |
| #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MISO_SELECT_INPUT) |
| #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MOSI_SELECT_INPUT) |
| #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0) |
| #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MISO_SELECT_INPUT) |
| #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MOSI_SELECT_INPUT) |
| #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0) |
| #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MISO_SELECT_INPUT) |
| #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MOSI_SELECT_INPUT) |
| #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0) |
| #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MISO_SELECT_INPUT) |
| #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MOSI_SELECT_INPUT) |
| #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0) |
| #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MISO_SELECT_INPUT) |
| #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MOSI_SELECT_INPUT) |
| #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0) |
| #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET1_IPG_CLK_RMII_SELECT_INPUT) |
| #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT) |
| #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT) |
| #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET2_IPG_CLK_RMII_SELECT_INPUT) |
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT) |
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FSR_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FST_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKR_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKT_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKR_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKT_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO0_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO1_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT) |
| #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT) |
| #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SCL_IN_SELECT_INPUT) |
| #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SDA_IN_SELECT_INPUT) |
| #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SCL_IN_SELECT_INPUT) |
| #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SDA_IN_SELECT_INPUT) |
| #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SCL_IN_SELECT_INPUT) |
| #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SDA_IN_SELECT_INPUT) |
| #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SCL_IN_SELECT_INPUT) |
| #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SDA_IN_SELECT_INPUT) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_5) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_6) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_7) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_5) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_6) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_7) |
| #define IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(base) ((base)->LCD1_BUSY_SELECT_INPUT) |
| #define IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(base) ((base)->LCD2_BUSY_SELECT_INPUT) |
| #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_CLK_IN_SELECT_INPUT) |
| #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_DATA_IN_SELECT_INPUT) |
| #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_SIG_IN_SELECT_INPUT) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT) |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT) |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT) |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT) |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT) |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_14) |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_15) |
| #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(base) ((base)->SPDIF_SPDIF_IN1_SELECT_INPUT) |
| #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(base) ((base)->SPDIF_TX_CLK2_SELECT_INPUT) |
| #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RTS_B_SELECT_INPUT) |
| #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RXD_MUX_SELECT_INPUT) |
| #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG2_OC_SELECT_INPUT) |
| #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG_OC_SELECT_INPUT) |
| #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_CARD_DET_SELECT_INPUT) |
| #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_WP_ON_SELECT_INPUT) |
| #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_CARD_DET_SELECT_INPUT) |
| #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_WP_ON_SELECT_INPUT) |
| #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_CARD_DET_SELECT_INPUT) |
| #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_WP_ON_SELECT_INPUT) |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks |
| * @{ |
| */ |
| |
| /* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO01 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO02 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO03 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO04 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO05 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO06 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO07 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO09 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO10 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO11 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO12 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_GPIO1_IO13 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA00 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA01 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA02 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA03 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA04 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA05 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA06 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_DATA07 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_HSYNC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_MCLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_PIXCLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_CSI_VSYNC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_COL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_CRS Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_MDC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_MDIO Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_RX_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET1_TX_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET2_COL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET2_CRS Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET2_RX_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_ENET2_TX_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_COL0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_COL1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_COL2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_COL3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_COL4 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_ROW0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_ROW1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_ROW2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_ROW3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_KEY_ROW4 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA00 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA01 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA02 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA03 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA04 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA05 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA06 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA07 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA08 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA09 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA10 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA11 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA12 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA13 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA14 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA15 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA16 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA17 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA18 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA19 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA20 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA21 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA22 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_DATA23 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_ENABLE Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_HSYNC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_RESET Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_LCD1_VSYNC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_ALE Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_CE0_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_CE1_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_CLE Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA00 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA01 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA02 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA03 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA04 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA05 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA06 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_DATA07 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_RE_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_READY_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_WE_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_NAND_WP_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_DQS Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_SCLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_SS0_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1A_SS1_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_DQS Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_SCLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_SS0_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_QSPI1B_SS1_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RD0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RD1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RD2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RD3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RX_CTL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_RXC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TD0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TD1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TD2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TD3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TX_CTL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII1_TXC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RD0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RD1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RD2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RD3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RX_CTL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_RXC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TD0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TD1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TD2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TD3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TX_CTL Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_RGMII2_TXC Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_CMD Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD1_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_CMD Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD2_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_CMD Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA4 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA5 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA6 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD3_DATA7 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_CLK Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_CMD Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA0 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA1 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA2 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA3 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA4 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA5 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA6 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_DATA7 Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_SD4_RESET_B Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_USB_H_DATA Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_SION_SHIFT 4 |
| /* SW_MUX_CTL_PAD_USB_H_STROBE Bit Fields */ |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_MASK 0x7u |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_SHIFT 0 |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_MUX_MODE_MASK) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_SION_MASK 0x10u |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_SION_SHIFT 4 |
| /* SW_PAD_CTL_PAD_DRAM_ADDR00 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR01 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR02 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR03 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR04 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR05 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR06 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR07 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR08 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR09 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR10 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR11 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR12 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR13 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR14 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ADDR15 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_DQM0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_DQM1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_DQM2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_DQM3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_RAS_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_CAS_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_CS0_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_CS1_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDWE_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ODT0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_ODT1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDBA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDBA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDBA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDCKE0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDCKE1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDCLK0_P Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_MASK 0x3000000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_SHIFT 24 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_DO_TRIM_PADN_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDQS0_P Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_MASK 0x3000000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_SHIFT 24 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_DO_TRIM_PADN_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDQS1_P Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_MASK 0x3000000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_SHIFT 24 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_DO_TRIM_PADN_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDQS2_P Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_MASK 0x3000000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_SHIFT 24 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_DO_TRIM_PADN_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_SDQS3_P Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_MASK 0x3000000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_SHIFT 24 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_DO_TRIM_PADN_MASK) |
| /* SW_PAD_CTL_PAD_DRAM_RESET Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_JTAG_MOD Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_JTAG_TCK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_JTAG_TDI Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_JTAG_TDO Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_JTAG_TMS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_JTAG_TRST_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO00 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO01 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO02 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO03 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO04 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO05 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO06 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO07 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO08 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO09 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO10 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO11 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO12 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_GPIO1_IO13 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA00 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA01 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA02 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA03 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA04 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA05 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA06 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_DATA07 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_HSYNC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_MCLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_PIXCLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_CSI_VSYNC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_COL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_CRS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_MDC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_MDIO Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_RX_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET1_TX_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET2_COL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET2_CRS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET2_RX_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_ENET2_TX_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_COL0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_COL1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_COL2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_COL3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_COL4 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_ROW0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_ROW1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_ROW2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_ROW3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_KEY_ROW4 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA00 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA01 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA02 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA03 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA04 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA05 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA06 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA07 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA08 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA09 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA10 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA11 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA12 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA13 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA14 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA15 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA16 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA17 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA18 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA19 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA20 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA21 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA22 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_DATA23 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_ENABLE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_HSYNC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_RESET Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_LCD1_VSYNC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_ALE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_CE0_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_CE1_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_CLE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA00 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA01 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA02 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA03 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA04 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA05 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA06 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_DATA07 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_RE_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_READY_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_WE_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_NAND_WP_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_DQS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_SCLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_SS0_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1A_SS1_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_DQS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_SCLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_SS0_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_QSPI1B_SS1_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RD0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RD1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RD2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RD3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RX_CTL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_RXC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TD0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TD1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TD2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TD3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TX_CTL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII1_TXC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RD0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RD1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RD2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RD3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RX_CTL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_RXC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TD0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TD1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TD2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TD3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TX_CTL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_RGMII2_TXC Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_CMD Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD1_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_CMD Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD2_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD3_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_CMD Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA4 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA5 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA6 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD3_DATA7 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_LVE_MASK 0x400000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_LVE_SHIFT 22 |
| /* SW_PAD_CTL_PAD_SD4_CLK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_CMD Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA0 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA1 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA2 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA3 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA4 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA5 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA6 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_DATA7 Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_SD4_RESET_B Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SRE_MASK 0x1u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SRE_SHIFT 0 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_MASK 0xC0u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_SHIFT 6 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_SPEED_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_ODE_MASK 0x800u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_ODE_SHIFT 11 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_HYS_SHIFT 16 |
| /* SW_PAD_CTL_PAD_USB_H_DATA Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_DO_TRIM_MASK) |
| /* SW_PAD_CTL_PAD_USB_H_STROBE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DSE_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_MASK 0x700u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_SHIFT 8 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_ODT_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PKE_SHIFT 12 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUE_SHIFT 13 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_MASK 0xC000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_SHIFT 14 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_PUS_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_HYS_SHIFT 16 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_INPUT_SHIFT 17 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DDR_SEL_MASK) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_MASK 0x300000u |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_SHIFT 20 |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_DO_TRIM_MASK) |
| /* SW_PAD_CTL_GRP_ADDDS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_ADDDS_DSE_MASK) |
| /* SW_PAD_CTL_GRP_DDRMODE_CTL Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_DDR_INPUT_SHIFT 17 |
| /* SW_PAD_CTL_GRP_DDRPKE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_MASK 0x1000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_PKE_SHIFT 12 |
| /* SW_PAD_CTL_GRP_DDRPK Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_MASK 0x2000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPK_PUE_SHIFT 13 |
| /* SW_PAD_CTL_GRP_DDRHYS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_MASK 0x10000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_HYS_SHIFT 16 |
| /* SW_PAD_CTL_GRP_DDRMODE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_MASK 0x20000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_DDR_INPUT_SHIFT 17 |
| /* SW_PAD_CTL_GRP_B0DS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B0DS_DSE_MASK) |
| /* SW_PAD_CTL_GRP_B1DS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B1DS_DSE_MASK) |
| /* SW_PAD_CTL_GRP_CTLDS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_CTLDS_DSE_MASK) |
| /* SW_PAD_CTL_GRP_DDR_TYPE Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_MASK 0xC0000u |
| #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_SHIFT 18 |
| #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_DDR_SEL_MASK) |
| /* SW_PAD_CTL_GRP_B2DS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B2DS_DSE_MASK) |
| /* SW_PAD_CTL_GRP_B3DS Bit Fields */ |
| #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_MASK 0x38u |
| #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_SHIFT 3 |
| #define IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_GRP_B3DS_DSE_MASK) |
| /* ANATOP_USB_OTG_ID_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_DAISY_MASK) |
| /* ANATOP_USB_UH1_ID_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| /* AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_DAISY_MASK) |
| /* AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_DAISY_MASK) |
| /* CAN1_IPP_IND_CANRX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK) |
| /* CAN2_IPP_IND_CANRX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_DAISY_MASK) |
| /* CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_DAISY_MASK) |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_1 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_2 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_3 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_4 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_5 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_6 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_7 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_8 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_9 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_11 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_12 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_13 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_14 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_15 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_16 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_17 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_18 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_19 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_20 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_21 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_22 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_23 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_D_SELECT_INPUT_10 Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_HSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_PIXCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* CSI1_IPP_CSI_VSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* CSI1_TVDECODER_IN_FIELD_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI1_IPP_IND_MISO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI1_IPP_IND_MOSI_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI2_IPP_IND_MISO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI2_IPP_IND_MOSI_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI3_IPP_IND_MISO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI3_IPP_IND_MOSI_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI4_IPP_IND_MISO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI4_IPP_IND_MOSI_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI5_IPP_IND_MISO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI5_IPP_IND_MOSI_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* ENET1_IPG_CLK_RMII_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK) |
| /* ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ENET2_IPG_CLK_RMII_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_DAISY_MASK) |
| /* ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* ESAI_IPP_IND_FSR_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_FST_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_HCKR_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_HCKT_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SCKR_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SCKT_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO0_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO1_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_DAISY_MASK) |
| /* ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK) |
| /* I2C1_IPP_SCL_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* I2C1_IPP_SDA_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| /* I2C2_IPP_SCL_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK) |
| /* I2C2_IPP_SDA_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK) |
| /* I2C3_IPP_SCL_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK) |
| /* I2C3_IPP_SDA_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK) |
| /* I2C4_IPP_SCL_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_MASK) |
| /* I2C4_IPP_SDA_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK) |
| /* KPP_IPP_IND_COL_SELECT_INPUT_5 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_DAISY_SHIFT 0 |
| /* KPP_IPP_IND_COL_SELECT_INPUT_6 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_DAISY_SHIFT 0 |
| /* KPP_IPP_IND_COL_SELECT_INPUT_7 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_DAISY_SHIFT 0 |
| /* KPP_IPP_IND_ROW_SELECT_INPUT_5 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_DAISY_SHIFT 0 |
| /* KPP_IPP_IND_ROW_SELECT_INPUT_6 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_DAISY_SHIFT 0 |
| /* KPP_IPP_IND_ROW_SELECT_INPUT_7 Bit Fields */ |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_DAISY_MASK 0x1u |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_DAISY_SHIFT 0 |
| /* LCD1_BUSY_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_LCD1_BUSY_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_LCD1_BUSY_SELECT_INPUT_DAISY_SHIFT 0 |
| /* LCD2_BUSY_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_LCD2_BUSY_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_LCD2_BUSY_SELECT_INPUT_DAISY_SHIFT 0 |
| /* MLB_MLB_CLK_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_DAISY_MASK) |
| /* MLB_MLB_DATA_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_DAISY_MASK) |
| /* MLB_MLB_SIG_IN_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_DAISY_MASK) |
| /* SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 Bit Fields */ |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_MASK 0x1u |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_DAISY_SHIFT 0 |
| /* SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_DAISY_SHIFT 0 |
| /* SDMA_EVENTS_SELECT_INPUT_14 Bit Fields */ |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_MASK 0x3u |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_SHIFT 0 |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_DAISY_MASK) |
| /* SDMA_EVENTS_SELECT_INPUT_15 Bit Fields */ |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_DAISY_MASK 0x1u |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_DAISY_SHIFT 0 |
| /* SPDIF_SPDIF_IN1_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_MASK 0x7u |
| #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_MASK) |
| /* SPDIF_TX_CLK2_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_DAISY_SHIFT 0 |
| /* UART1_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART1_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* UART2_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART2_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* UART3_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u |
| #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART3_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u |
| #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* UART4_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART4_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u |
| #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* UART5_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART5_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* UART6_IPP_UART_RTS_B_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_DAISY_MASK) |
| /* UART6_IPP_UART_RXD_MUX_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK 0x7u |
| #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY_MASK) |
| /* USB_IPP_IND_OTG2_OC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_DAISY_MASK) |
| /* USB_IPP_IND_OTG_OC_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_MASK 0x3u |
| #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_SHIFT 0 |
| #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_DAISY_MASK) |
| /* USDHC1_IPP_CARD_DET_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0 |
| /* USDHC1_IPP_WP_ON_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0 |
| /* USDHC2_IPP_CARD_DET_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0 |
| /* USDHC2_IPP_WP_ON_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0 |
| /* USDHC4_IPP_CARD_DET_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_DAISY_SHIFT 0 |
| /* USDHC4_IPP_WP_ON_SELECT_INPUT Bit Fields */ |
| #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_DAISY_MASK 0x1u |
| #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_DAISY_SHIFT 0 |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Register_Masks */ |
| |
| /* IOMUXC - Peripheral instance base addresses */ |
| /** Peripheral IOMUXC base address */ |
| #define IOMUXC_BASE (0x420E0000u) |
| /** Peripheral IOMUXC base pointer */ |
| #define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) |
| #define IOMUXC_BASE_PTR (IOMUXC) |
| /** Array initializer of IOMUXC peripheral base addresses */ |
| #define IOMUXC_BASE_ADDRS { IOMUXC_BASE } |
| /** Array initializer of IOMUXC peripheral base pointers */ |
| #define IOMUXC_BASE_PTRS { IOMUXC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros |
| * @{ |
| */ |
| |
| /* IOMUXC - Register instance definitions */ |
| /* IOMUXC */ |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23 IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3 IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3 IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3 IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3 IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3 IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23 IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3 IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3 IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3 IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3 IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3 IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_ADDDS IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRPK IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_B0DS IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_B1DS IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_CTLDS IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_B2DS IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SW_PAD_CTL_GRP_B3DS IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10 IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7 IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7 IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_LCD1_BUSY_SELECT_INPUT IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_LCD2_BUSY_SELECT_INPUT IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14 IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15 IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| #define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(IOMUXC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** IOMUXC_GPR - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ |
| __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ |
| __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ |
| __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ |
| __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ |
| __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ |
| __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ |
| __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ |
| __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ |
| __IO uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ |
| __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ |
| __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ |
| __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ |
| __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ |
| } IOMUXC_GPR_Type, *IOMUXC_GPR_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros |
| * @{ |
| */ |
| |
| /* IOMUXC_GPR - Register accessors */ |
| #define IOMUXC_GPR_GPR0_REG(base) ((base)->GPR0) |
| #define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) |
| #define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) |
| #define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) |
| #define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) |
| #define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) |
| #define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) |
| #define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) |
| #define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) |
| #define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) |
| #define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) |
| #define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) |
| #define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) |
| #define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks |
| * @{ |
| */ |
| |
| /* GPR0 Bit Fields */ |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK 0x80u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT 7 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK 0x100u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT 8 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK 0x200u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT 9 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK 0x400u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT 10 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK 0x800u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT 11 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK 0x1000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT 12 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK 0x2000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT 13 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK 0x4000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT 14 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK 0x8000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT 15 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK 0x10000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT 16 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK 0x20000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT 17 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK 0x40000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT 18 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK 0x80000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT 19 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK 0x100000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT 20 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK 0x200000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT 21 |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK 0x400000u |
| #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT 22 |
| /* GPR1 Bit Fields */ |
| #define IOMUXC_GPR_GPR1_ACT_CS0_MASK 0x1u |
| #define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT 0 |
| #define IOMUXC_GPR_GPR1_ADDRS0_MASK 0x6u |
| #define IOMUXC_GPR_GPR1_ADDRS0_SHIFT 1 |
| #define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_ADDRS0_MASK) |
| #define IOMUXC_GPR_GPR1_ACT_CS1_MASK 0x8u |
| #define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT 3 |
| #define IOMUXC_GPR_GPR1_ADDRS1_MASK 0x30u |
| #define IOMUXC_GPR_GPR1_ADDRS1_SHIFT 4 |
| #define IOMUXC_GPR_GPR1_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_ADDRS1_MASK) |
| #define IOMUXC_GPR_GPR1_ACT_CS2_MASK 0x40u |
| #define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT 6 |
| #define IOMUXC_GPR_GPR1_ADDRS2_MASK 0x180u |
| #define IOMUXC_GPR_GPR1_ADDRS2_SHIFT 7 |
| #define IOMUXC_GPR_GPR1_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_ADDRS2_MASK) |
| #define IOMUXC_GPR_GPR1_ACT_CS3_MASK 0x200u |
| #define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT 9 |
| #define IOMUXC_GPR_GPR1_ADDRS3_MASK 0xC00u |
| #define IOMUXC_GPR_GPR1_ADDRS3_SHIFT 10 |
| #define IOMUXC_GPR_GPR1_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_ADDRS3_MASK) |
| #define IOMUXC_GPR_GPR1_GINT_MASK 0x1000u |
| #define IOMUXC_GPR_GPR1_GINT_SHIFT 12 |
| #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK 0x2000u |
| #define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT 13 |
| #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK 0x4000u |
| #define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT 14 |
| #define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK 0x8000u |
| #define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT 15 |
| #define IOMUXC_GPR_GPR1_ADD_DS_MASK 0x10000u |
| #define IOMUXC_GPR_GPR1_ADD_DS_SHIFT 16 |
| #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK 0x20000u |
| #define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT 17 |
| #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK 0x40000u |
| #define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT 18 |
| #define IOMUXC_GPR_GPR1_VADC_SW_RST_MASK 0x80000u |
| #define IOMUXC_GPR_GPR1_VADC_SW_RST_SHIFT 19 |
| #define IOMUXC_GPR_GPR1_VDEC_SW_RST_MASK 0x100000u |
| #define IOMUXC_GPR_GPR1_VDEC_SW_RST_SHIFT 20 |
| #define IOMUXC_GPR_GPR1_EXC_MON_MASK 0x400000u |
| #define IOMUXC_GPR_GPR1_EXC_MON_SHIFT 22 |
| #define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK 0x800000u |
| #define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT 23 |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_APB_DBG_EN_MASK 0x1000000u |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_APB_DBG_EN_SHIFT 24 |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_ATB_EN_MASK 0x2000000u |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_ATB_EN_SHIFT 25 |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_AHB_EN_MASK 0x4000000u |
| #define IOMUXC_GPR_GPR1_ARMA9_CLK_AHB_EN_SHIFT 26 |
| #define IOMUXC_GPR_GPR1_ARMA9_IPG_CLK_EN_MASK 0x8000000u |
| #define IOMUXC_GPR_GPR1_ARMA9_IPG_CLK_EN_SHIFT 27 |
| /* GPR2 Bit Fields */ |
| #define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK 0x1u |
| #define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT 0 |
| #define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK 0x2u |
| #define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT 1 |
| #define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK 0x4u |
| #define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT 2 |
| #define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK 0x8u |
| #define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT 3 |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK 0x10u |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT 4 |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK 0x20u |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT 5 |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK 0x40u |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT 6 |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK 0x80u |
| #define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT 7 |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK 0x100u |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT 8 |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK 0x200u |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT 9 |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK 0x400u |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT 10 |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK 0x800u |
| #define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT 11 |
| #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK 0x1000u |
| #define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT 12 |
| #define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK 0x2000u |
| #define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT 13 |
| #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK 0x4000u |
| #define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT 14 |
| #define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK 0x8000u |
| #define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT 15 |
| #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK 0x8000000u |
| #define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT 27 |
| #define IOMUXC_GPR_GPR2_DRAM_RESET_MASK 0x10000000u |
| #define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT 28 |
| #define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK 0x20000000u |
| #define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT 29 |
| #define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK 0x40000000u |
| #define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT 30 |
| #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK 0x80000000u |
| #define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT 31 |
| /* GPR3 Bit Fields */ |
| #define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK 0xFu |
| #define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT 0 |
| #define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) |
| #define IOMUXC_GPR_GPR3_OCRAM_S_CTL_MASK 0xF0u |
| #define IOMUXC_GPR_GPR3_OCRAM_S_CTL_SHIFT 4 |
| #define IOMUXC_GPR_GPR3_OCRAM_S_CTL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_S_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_S_CTL_MASK) |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL_MASK 0xF00u |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL_SHIFT 8 |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_CTL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_L2_CTL_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_L2_CTL_MASK) |
| #define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK 0x2000u |
| #define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT 13 |
| #define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK 0xF0000u |
| #define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT 16 |
| #define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) |
| #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS_MASK 0xF00000u |
| #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS_SHIFT 20 |
| #define IOMUXC_GPR_GPR3_OCRAM_S_STATUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_S_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_S_STATUS_MASK) |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_MASK 0xF000000u |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_SHIFT 24 |
| #define IOMUXC_GPR_GPR3_OCRAM_L2_STATUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_SHIFT))&IOMUXC_GPR_GPR3_OCRAM_L2_STATUS_MASK) |
| /* GPR4 Bit Fields */ |
| #define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK 0x1u |
| #define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT 0 |
| #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK 0x2u |
| #define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT 1 |
| #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK 0x4u |
| #define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT 2 |
| #define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK 0x8u |
| #define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT 3 |
| #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK 0x10u |
| #define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT 4 |
| #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK 0x20u |
| #define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT 5 |
| #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK 0x40u |
| #define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT 6 |
| #define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK 0x10000u |
| #define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT 16 |
| #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK 0x20000u |
| #define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT 17 |
| #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK 0x40000u |
| #define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT 18 |
| #define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK 0x80000u |
| #define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT 19 |
| #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK 0x100000u |
| #define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT 20 |
| #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK 0x200000u |
| #define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT 21 |
| #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK 0x400000u |
| #define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT 22 |
| #define IOMUXC_GPR_GPR4_L2_CLK_STOP_MASK 0x20000000u |
| #define IOMUXC_GPR_GPR4_L2_CLK_STOP_SHIFT 29 |
| #define IOMUXC_GPR_GPR4_ARM_WFI_MASK 0x40000000u |
| #define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT 30 |
| #define IOMUXC_GPR_GPR4_ARM_WFE_MASK 0x80000000u |
| #define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT 31 |
| /* GPR5 Bit Fields */ |
| #define IOMUXC_GPR_GPR5_SVADC_TEST_GPR1_MASK 0x1u |
| #define IOMUXC_GPR_GPR5_SVADC_TEST_GPR1_SHIFT 0 |
| #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC1_CTRL_MASK 0x2u |
| #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC1_CTRL_SHIFT 1 |
| #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC2_CTRL_MASK 0x4u |
| #define IOMUXC_GPR_GPR5_DISP_MUX_DCIC2_CTRL_SHIFT 2 |
| #define IOMUXC_GPR_GPR5_DISP_MUX_LDB_CTRL_MASK 0x8u |
| #define IOMUXC_GPR_GPR5_DISP_MUX_LDB_CTRL_SHIFT 3 |
| #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_MASK 0x30u |
| #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_SHIFT 4 |
| #define IOMUXC_GPR_GPR5_CSI1_MUX_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_SHIFT))&IOMUXC_GPR_GPR5_CSI1_MUX_CTRL_MASK) |
| #define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK 0x40u |
| #define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT 6 |
| #define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK 0x80u |
| #define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT 7 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_MASK 0x300u |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_SHIFT 8 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI1_MASK) |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_MASK 0xC00u |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_SHIFT 10 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI2_MASK) |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_MASK 0x3000u |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_SHIFT 12 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF1_MASK) |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_MASK 0xC000u |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_SHIFT 14 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF2_MASK) |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK 0x30000u |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT 16 |
| #define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT))&IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK) |
| #define IOMUXC_GPR_GPR5_PCIE_PERST_MASK 0x40000u |
| #define IOMUXC_GPR_GPR5_PCIE_PERST_SHIFT 18 |
| #define IOMUXC_GPR_GPR5_PCIE_BTNRST_MASK 0x80000u |
| #define IOMUXC_GPR_GPR5_PCIE_BTNRST_SHIFT 19 |
| #define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK 0x100000u |
| #define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT 20 |
| #define IOMUXC_GPR_GPR5_LCDIF1_CSI_VSYNC_SEL_MASK 0x200000u |
| #define IOMUXC_GPR_GPR5_LCDIF1_CSI_VSYNC_SEL_SHIFT 21 |
| #define IOMUXC_GPR_GPR5_LCDIF2_CSI_VSYNC_SEL_MASK 0x400000u |
| #define IOMUXC_GPR_GPR5_LCDIF2_CSI_VSYNC_SEL_SHIFT 22 |
| #define IOMUXC_GPR_GPR5_VADC_TEST_GPR3_MASK 0x800000u |
| #define IOMUXC_GPR_GPR5_VADC_TEST_GPR3_SHIFT 23 |
| #define IOMUXC_GPR_GPR5_VADC_TEST_6SX_GPR5_MASK 0x1000000u |
| #define IOMUXC_GPR_GPR5_VADC_TEST_6SX_GPR5_SHIFT 24 |
| #define IOMUXC_GPR_GPR5_VADC_TEST_GPR2_MASK 0x2000000u |
| #define IOMUXC_GPR_GPR5_VADC_TEST_GPR2_SHIFT 25 |
| #define IOMUXC_GPR_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK 0x4000000u |
| #define IOMUXC_GPR_GPR5_VADC_TO_CSI_CAPTURE_EN_SHIFT 26 |
| #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_MASK 0x18000000u |
| #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_SHIFT 27 |
| #define IOMUXC_GPR_GPR5_CSI2_MUX_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_SHIFT))&IOMUXC_GPR_GPR5_CSI2_MUX_CTRL_MASK) |
| #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT_MASK 0x20000000u |
| #define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT_SHIFT 29 |
| #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK 0x40000000u |
| #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT 30 |
| #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK 0x80000000u |
| #define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT 31 |
| /* GPR6 Bit Fields */ |
| #define IOMUXC_GPR_GPR6_CH0_MODE_MASK 0x3u |
| #define IOMUXC_GPR_GPR6_CH0_MODE_SHIFT 0 |
| #define IOMUXC_GPR_GPR6_CH0_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_CH0_MODE_SHIFT))&IOMUXC_GPR_GPR6_CH0_MODE_MASK) |
| #define IOMUXC_GPR_GPR6_DATA_WIDTH_CH0_MASK 0x20u |
| #define IOMUXC_GPR_GPR6_DATA_WIDTH_CH0_SHIFT 5 |
| #define IOMUXC_GPR_GPR6_BIT_MAPPING_CH0_MASK 0x40u |
| #define IOMUXC_GPR_GPR6_BIT_MAPPING_CH0_SHIFT 6 |
| #define IOMUXC_GPR_GPR6_LCDIF_VS_POLARITY_MASK 0x200u |
| #define IOMUXC_GPR_GPR6_LCDIF_VS_POLARITY_SHIFT 9 |
| #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_MASK 0x70000u |
| #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_SHIFT 16 |
| #define IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_SHIFT))&IOMUXC_GPR_GPR6_LVDS_CLK_SHIFT_MASK) |
| #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_MASK 0x300000u |
| #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_SHIFT 20 |
| #define IOMUXC_GPR_GPR6_COUNTER_RESET_VAL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_SHIFT))&IOMUXC_GPR_GPR6_COUNTER_RESET_VAL_MASK) |
| /* GPR7 Bit Fields */ |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_MASK 0x3u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_SHIFT 0 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_RX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_MASK 0xCu |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_SHIFT 2 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_ESAI_TX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_MASK 0x30u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_SHIFT 4 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_RX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_MASK 0xC0u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_SHIFT 6 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI1_TX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_MASK 0x300u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_SHIFT 8 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_RX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_MASK 0xC00u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_SHIFT 10 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI2_TX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_MASK 0x3000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_SHIFT 12 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_RX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_MASK 0xC000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_SHIFT 14 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SSI3_TX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_MASK 0x30000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_SHIFT 16 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_SHIFT))&IOMUXC_GPR_GPR7_ASRC_SEL_SPDIF_TX_MASK) |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_1_MASK 0x40000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_1_SHIFT 18 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_4_MASK 0x80000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_4_SHIFT 19 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_9_MASK 0x100000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_9_SHIFT 20 |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_C_MASK 0x200000u |
| #define IOMUXC_GPR_GPR7_ASRC_SEL_CLK_C_SHIFT 21 |
| /* GPR8 Bit Fields */ |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_MASK 0x3Fu |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_SHIFT 0 |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN1_MASK) |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK 0xFC0u |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT 6 |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK) |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK 0x3F000u |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT 12 |
| #define IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK) |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_MASK 0x1FC0000u |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_SHIFT 18 |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_SWING_FULL_MASK) |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_MASK 0xFE000000u |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_SHIFT 25 |
| #define IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_SHIFT))&IOMUXC_GPR_GPR8_PCS_TX_SWING_LOW_MASK) |
| /* GPR9 Bit Fields */ |
| #define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK 0x1u |
| #define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT 0 |
| /* GPR10 Bit Fields */ |
| #define IOMUXC_GPR_GPR10_DBG_EN_MASK 0x1u |
| #define IOMUXC_GPR_GPR10_DBG_EN_SHIFT 0 |
| #define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK 0x2u |
| #define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT 1 |
| #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK 0x4u |
| #define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT 2 |
| #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_EN_MASK 0x8u |
| #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_EN_SHIFT 3 |
| #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_MASK 0x3F0u |
| #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_SHIFT 4 |
| #define IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_L2_TZ_ADDR_MASK) |
| #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK 0x400u |
| #define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT 10 |
| #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK 0xF800u |
| #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT 11 |
| #define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) |
| /* GPR11 Bit Fields */ |
| #define IOMUXC_GPR_GPR11_OCRAM_L2_EN_MASK 0x2u |
| #define IOMUXC_GPR_GPR11_OCRAM_L2_EN_SHIFT 1 |
| #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_MASK 0x400u |
| #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_EN_SHIFT 10 |
| #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK 0x1800u |
| #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT 11 |
| #define IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_SHIFT))&IOMUXC_GPR_GPR11_OCRAM_S_TZ_ADDR_MASK) |
| /* GPR12 Bit Fields */ |
| #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ_MASK 0x7u |
| #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ_SHIFT 0 |
| #define IOMUXC_GPR_GPR12_PCIE_RX0_EQ(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIE_RX0_EQ_SHIFT))&IOMUXC_GPR_GPR12_PCIE_RX0_EQ_MASK) |
| #define IOMUXC_GPR_GPR12_LOS_LEVEL_MASK 0x1F0u |
| #define IOMUXC_GPR_GPR12_LOS_LEVEL_SHIFT 4 |
| #define IOMUXC_GPR_GPR12_LOS_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_LOS_LEVEL_SHIFT))&IOMUXC_GPR_GPR12_LOS_LEVEL_MASK) |
| #define IOMUXC_GPR_GPR12_APPS_PM_XMT_PME_MASK 0x200u |
| #define IOMUXC_GPR_GPR12_APPS_PM_XMT_PME_SHIFT 9 |
| #define IOMUXC_GPR_GPR12_APP_LTSSM_ENABLE_MASK 0x400u |
| #define IOMUXC_GPR_GPR12_APP_LTSSM_ENABLE_SHIFT 10 |
| #define IOMUXC_GPR_GPR12_APP_INIT_RST_MASK 0x800u |
| #define IOMUXC_GPR_GPR12_APP_INIT_RST_SHIFT 11 |
| #define IOMUXC_GPR_GPR12_DEVICE_TYPE_MASK 0xF000u |
| #define IOMUXC_GPR_GPR12_DEVICE_TYPE_SHIFT 12 |
| #define IOMUXC_GPR_GPR12_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_DEVICE_TYPE_MASK) |
| #define IOMUXC_GPR_GPR12_APPS_PM_XMT_TURNOFF_MASK 0x10000u |
| #define IOMUXC_GPR_GPR12_APPS_PM_XMT_TURNOFF_SHIFT 16 |
| #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u |
| #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_SHIFT 17 |
| #define IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_DIAG_STATUS_BUS_SELECT_MASK) |
| #define IOMUXC_GPR_GPR12_PCIe_CTL_7_MASK 0xE00000u |
| #define IOMUXC_GPR_GPR12_PCIe_CTL_7_SHIFT 21 |
| #define IOMUXC_GPR_GPR12_PCIe_CTL_7(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_PCIe_CTL_7_SHIFT))&IOMUXC_GPR_GPR12_PCIe_CTL_7_MASK) |
| #define IOMUXC_GPR_GPR12_SYS_INT_MASK 0x1000000u |
| #define IOMUXC_GPR_GPR12_SYS_INT_SHIFT 24 |
| #define IOMUXC_GPR_GPR12_APP_REQ_ENTR_L1_MASK 0x2000000u |
| #define IOMUXC_GPR_GPR12_APP_REQ_ENTR_L1_SHIFT 25 |
| #define IOMUXC_GPR_GPR12_APP_REQ_EXIT_L1_MASK 0x4000000u |
| #define IOMUXC_GPR_GPR12_APP_REQ_EXIT_L1_SHIFT 26 |
| #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK 0x8000000u |
| #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT 27 |
| #define IOMUXC_GPR_GPR12_APP_READY_ENTR_L23_MASK 0x10000000u |
| #define IOMUXC_GPR_GPR12_APP_READY_ENTR_L23_SHIFT 28 |
| #define IOMUXC_GPR_GPR12_APP_CLK_REQ_N_MASK 0x20000000u |
| #define IOMUXC_GPR_GPR12_APP_CLK_REQ_N_SHIFT 29 |
| #define IOMUXC_GPR_GPR12_TEST_POWERDOWN_MASK 0x40000000u |
| #define IOMUXC_GPR_GPR12_TEST_POWERDOWN_SHIFT 30 |
| #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN_MASK 0x80000000u |
| #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN_SHIFT 31 |
| /* GPR13 Bit Fields */ |
| #define IOMUXC_GPR_GPR13_USDHC_RD_CACHE_VAL_MASK 0x1u |
| #define IOMUXC_GPR_GPR13_USDHC_RD_CACHE_VAL_SHIFT 0 |
| #define IOMUXC_GPR_GPR13_USDHC_WR_CACHE_VAL_MASK 0x2u |
| #define IOMUXC_GPR_GPR13_USDHC_WR_CACHE_VAL_SHIFT 1 |
| #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_VAL_MASK 0x4u |
| #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_VAL_SHIFT 2 |
| #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_VAL_MASK 0x8u |
| #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_VAL_SHIFT 3 |
| #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_VAL_MASK 0x10u |
| #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_VAL_SHIFT 4 |
| #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_VAL_MASK 0x20u |
| #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_VAL_SHIFT 5 |
| #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_VAL_MASK 0x40u |
| #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_VAL_SHIFT 6 |
| #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_VAL_MASK 0x80u |
| #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_VAL_SHIFT 7 |
| #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_SEL_MASK 0x100u |
| #define IOMUXC_GPR_GPR13_PXP_RD_CACHE_SEL_SHIFT 8 |
| #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_SEL_MASK 0x200u |
| #define IOMUXC_GPR_GPR13_PXP_WR_CACHE_SEL_SHIFT 9 |
| #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_SEL_MASK 0x400u |
| #define IOMUXC_GPR_GPR13_PCIE_RD_CACHE_SEL_SHIFT 10 |
| #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_SEL_MASK 0x800u |
| #define IOMUXC_GPR_GPR13_PCIE_WR_CACHE_SEL_SHIFT 11 |
| #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_SEL_MASK 0x1000u |
| #define IOMUXC_GPR_GPR13_LCDIF1_RD_CACHE_SEL_SHIFT 12 |
| #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_SEL_MASK 0x2000u |
| #define IOMUXC_GPR_GPR13_LCDIF2_RD_CACHE_SEL_SHIFT 13 |
| #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE_MASK 0x4000u |
| #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_LNKRST_DISABLE_SHIFT 14 |
| #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_PERST_DISABLE_MASK 0x8000u |
| #define IOMUXC_GPR_GPR13_GPR_PCIE_CLK_RST_FIX_PERST_DISABLE_SHIFT 15 |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Register_Masks */ |
| |
| /* IOMUXC_GPR - Peripheral instance base addresses */ |
| /** Peripheral IOMUXC_GPR base address */ |
| #define IOMUXC_GPR_BASE (0x420E4000u) |
| /** Peripheral IOMUXC_GPR base pointer */ |
| #define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) |
| #define IOMUXC_GPR_BASE_PTR (IOMUXC_GPR) |
| /** Array initializer of IOMUXC_GPR peripheral base addresses */ |
| #define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } |
| /** Array initializer of IOMUXC_GPR peripheral base pointers */ |
| #define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } |
| |
| /* ---------------------------------------------------------------------------- |
| -- IOMUXC_GPR - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros |
| * @{ |
| */ |
| |
| /* IOMUXC_GPR - Register instance definitions */ |
| /* IOMUXC_GPR */ |
| #define IOMUXC_GPR_GPR0 IOMUXC_GPR_GPR0_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR1 IOMUXC_GPR_GPR1_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR2 IOMUXC_GPR_GPR2_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR3 IOMUXC_GPR_GPR3_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR4 IOMUXC_GPR_GPR4_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR5 IOMUXC_GPR_GPR5_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR6 IOMUXC_GPR_GPR6_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR7 IOMUXC_GPR_GPR7_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR8 IOMUXC_GPR_GPR8_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR9 IOMUXC_GPR_GPR9_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR10 IOMUXC_GPR_GPR10_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR11 IOMUXC_GPR_GPR11_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR12 IOMUXC_GPR_GPR12_REG(IOMUXC_GPR_BASE_PTR) |
| #define IOMUXC_GPR_GPR13 IOMUXC_GPR_GPR13_REG(IOMUXC_GPR_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group IOMUXC_GPR_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- KPP Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** KPP - Register Layout Typedef */ |
| typedef struct { |
| __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ |
| __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ |
| __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ |
| __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ |
| } KPP_Type, *KPP_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- KPP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros |
| * @{ |
| */ |
| |
| /* KPP - Register accessors */ |
| #define KPP_KPCR_REG(base) ((base)->KPCR) |
| #define KPP_KPSR_REG(base) ((base)->KPSR) |
| #define KPP_KDDR_REG(base) ((base)->KDDR) |
| #define KPP_KPDR_REG(base) ((base)->KPDR) |
| |
| /*! |
| * @} |
| */ /* end of group KPP_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- KPP Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup KPP_Register_Masks KPP Register Masks |
| * @{ |
| */ |
| |
| /* KPCR Bit Fields */ |
| #define KPP_KPCR_KRE_MASK 0xFFu |
| #define KPP_KPCR_KRE_SHIFT 0 |
| #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KRE_SHIFT))&KPP_KPCR_KRE_MASK) |
| #define KPP_KPCR_KCO_MASK 0xFF00u |
| #define KPP_KPCR_KCO_SHIFT 8 |
| #define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KCO_SHIFT))&KPP_KPCR_KCO_MASK) |
| /* KPSR Bit Fields */ |
| #define KPP_KPSR_KPKD_MASK 0x1u |
| #define KPP_KPSR_KPKD_SHIFT 0 |
| #define KPP_KPSR_KPKR_MASK 0x2u |
| #define KPP_KPSR_KPKR_SHIFT 1 |
| #define KPP_KPSR_KDSC_MASK 0x4u |
| #define KPP_KPSR_KDSC_SHIFT 2 |
| #define KPP_KPSR_KRSS_MASK 0x8u |
| #define KPP_KPSR_KRSS_SHIFT 3 |
| #define KPP_KPSR_KDIE_MASK 0x100u |
| #define KPP_KPSR_KDIE_SHIFT 8 |
| #define KPP_KPSR_KRIE_MASK 0x200u |
| #define KPP_KPSR_KRIE_SHIFT 9 |
| /* KDDR Bit Fields */ |
| #define KPP_KDDR_KRDD_MASK 0xFFu |
| #define KPP_KDDR_KRDD_SHIFT 0 |
| #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KRDD_SHIFT))&KPP_KDDR_KRDD_MASK) |
| #define KPP_KDDR_KCDD_MASK 0xFF00u |
| #define KPP_KDDR_KCDD_SHIFT 8 |
| #define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KCDD_SHIFT))&KPP_KDDR_KCDD_MASK) |
| /* KPDR Bit Fields */ |
| #define KPP_KPDR_KRD_MASK 0xFFu |
| #define KPP_KPDR_KRD_SHIFT 0 |
| #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KRD_SHIFT))&KPP_KPDR_KRD_MASK) |
| #define KPP_KPDR_KCD_MASK 0xFF00u |
| #define KPP_KPDR_KCD_SHIFT 8 |
| #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KCD_SHIFT))&KPP_KPDR_KCD_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group KPP_Register_Masks */ |
| |
| /* KPP - Peripheral instance base addresses */ |
| /** Peripheral KPP base address */ |
| #define KPP_BASE (0x420B8000u) |
| /** Peripheral KPP base pointer */ |
| #define KPP ((KPP_Type *)KPP_BASE) |
| #define KPP_BASE_PTR (KPP) |
| /** Array initializer of KPP peripheral base addresses */ |
| #define KPP_BASE_ADDRS { KPP_BASE } |
| /** Array initializer of KPP peripheral base pointers */ |
| #define KPP_BASE_PTRS { KPP } |
| /** Interrupt vectors for the KPP peripheral type */ |
| #define KPP_IRQS { KPP_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- KPP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros |
| * @{ |
| */ |
| |
| /* KPP - Register instance definitions */ |
| /* KPP */ |
| #define KPP_KPCR KPP_KPCR_REG(KPP_BASE_PTR) |
| #define KPP_KPSR KPP_KPSR_REG(KPP_BASE_PTR) |
| #define KPP_KDDR KPP_KDDR_REG(KPP_BASE_PTR) |
| #define KPP_KPDR KPP_KPDR_REG(KPP_BASE_PTR) |
| /*! |
| * @} |
| */ /* end of group KPP_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group KPP_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LCDIF - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t RL; /**< eLCDIF General Control Register, offset: 0x0 */ |
| __IO uint32_t RL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ |
| __IO uint32_t RL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ |
| __IO uint32_t RL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ |
| __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ |
| __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ |
| __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ |
| __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ |
| __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ |
| __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ |
| __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ |
| __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ |
| __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ |
| __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ |
| __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ |
| __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ |
| __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ |
| uint8_t RESERVED_22[12]; |
| __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ |
| uint8_t RESERVED_23[12]; |
| __I uint32_t VERSION; /**< LCD Interface Version Register, offset: 0x1C0 */ |
| uint8_t RESERVED_24[12]; |
| __I uint32_t DEBUG0; /**< LCD Interface Debug0 Register, offset: 0x1D0 */ |
| uint8_t RESERVED_25[12]; |
| __I uint32_t DEBUG1; /**< LCD Interface Debug1 Register, offset: 0x1E0 */ |
| uint8_t RESERVED_26[12]; |
| __I uint32_t DEBUG2; /**< LCD Interface Debug2 Register, offset: 0x1F0 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ |
| uint8_t RESERVED_28[12]; |
| __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ |
| uint8_t RESERVED_29[12]; |
| __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ |
| uint8_t RESERVED_30[12]; |
| __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ |
| uint8_t RESERVED_31[12]; |
| __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ |
| uint8_t RESERVED_32[12]; |
| __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ |
| uint8_t RESERVED_33[12]; |
| __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ |
| uint8_t RESERVED_34[12]; |
| __IO uint32_t DEBUG3; /**< eLCDIF Interface Debug3 Register, offset: 0x270 */ |
| uint8_t RESERVED_35[12]; |
| __IO uint32_t DEBUG4; /**< LCD Interface Debug4 , offset: 0x280 */ |
| uint8_t RESERVED_36[12]; |
| __IO uint32_t DEBUG5; /**< LCD Interface Debug5 , offset: 0x290 */ |
| } LCDIF_Type, *LCDIF_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros |
| * @{ |
| */ |
| |
| /* LCDIF - Register accessors */ |
| #define LCDIF_RL_REG(base) ((base)->RL) |
| #define LCDIF_RL_SET_REG(base) ((base)->RL_SET) |
| #define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) |
| #define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) |
| #define LCDIF_CTRL1_REG(base) ((base)->CTRL1) |
| #define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) |
| #define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) |
| #define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) |
| #define LCDIF_CTRL2_REG(base) ((base)->CTRL2) |
| #define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) |
| #define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) |
| #define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) |
| #define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) |
| #define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) |
| #define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) |
| #define LCDIF_TIMING_REG(base) ((base)->TIMING) |
| #define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) |
| #define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) |
| #define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) |
| #define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) |
| #define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) |
| #define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) |
| #define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) |
| #define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) |
| #define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) |
| #define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) |
| #define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) |
| #define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) |
| #define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) |
| #define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) |
| #define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) |
| #define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) |
| #define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) |
| #define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) |
| #define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) |
| #define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) |
| #define LCDIF_DATA_REG(base) ((base)->DATA) |
| #define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) |
| #define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) |
| #define LCDIF_STAT_REG(base) ((base)->STAT) |
| #define LCDIF_VERSION_REG(base) ((base)->VERSION) |
| #define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) |
| #define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) |
| #define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) |
| #define LCDIF_THRES_REG(base) ((base)->THRES) |
| #define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) |
| #define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) |
| #define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) |
| #define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) |
| #define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) |
| #define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) |
| #define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) |
| #define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) |
| #define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Register_Masks LCDIF Register Masks |
| * @{ |
| */ |
| |
| /* RL Bit Fields */ |
| #define LCDIF_RL_RUN_MASK 0x1u |
| #define LCDIF_RL_RUN_SHIFT 0 |
| #define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u |
| #define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 |
| #define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u |
| #define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 |
| #define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u |
| #define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 |
| #define LCDIF_RL_RSRVD0_MASK 0x10u |
| #define LCDIF_RL_RSRVD0_SHIFT 4 |
| #define LCDIF_RL_MASTER_MASK 0x20u |
| #define LCDIF_RL_MASTER_SHIFT 5 |
| #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u |
| #define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 |
| #define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u |
| #define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 |
| #define LCDIF_RL_WORD_LENGTH_MASK 0x300u |
| #define LCDIF_RL_WORD_LENGTH_SHIFT 8 |
| #define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_WORD_LENGTH_SHIFT))&LCDIF_RL_WORD_LENGTH_MASK) |
| #define LCDIF_RL_LCD_DATABUS_WIDTH_MASK 0xC00u |
| #define LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT 10 |
| #define LCDIF_RL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_RL_CSC_DATA_SWIZZLE_MASK 0x3000u |
| #define LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT 12 |
| #define LCDIF_RL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_INPUT_DATA_SWIZZLE_MASK 0xC000u |
| #define LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT 14 |
| #define LCDIF_RL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_DATA_SELECT_MASK 0x10000u |
| #define LCDIF_RL_DATA_SELECT_SHIFT 16 |
| #define LCDIF_RL_DOTCLK_MODE_MASK 0x20000u |
| #define LCDIF_RL_DOTCLK_MODE_SHIFT 17 |
| #define LCDIF_RL_VSYNC_MODE_MASK 0x40000u |
| #define LCDIF_RL_VSYNC_MODE_SHIFT 18 |
| #define LCDIF_RL_BYPASS_COUNT_MASK 0x80000u |
| #define LCDIF_RL_BYPASS_COUNT_SHIFT 19 |
| #define LCDIF_RL_DVI_MODE_MASK 0x100000u |
| #define LCDIF_RL_DVI_MODE_SHIFT 20 |
| #define LCDIF_RL_SHIFT_NUM_BITS_MASK 0x3E00000u |
| #define LCDIF_RL_SHIFT_NUM_BITS_SHIFT 21 |
| #define LCDIF_RL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_RL_DATA_SHIFT_DIR_MASK 0x4000000u |
| #define LCDIF_RL_DATA_SHIFT_DIR_SHIFT 26 |
| #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u |
| #define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_SHIFT 27 |
| #define LCDIF_RL_READ_WRITEB_MASK 0x10000000u |
| #define LCDIF_RL_READ_WRITEB_SHIFT 28 |
| #define LCDIF_RL_YCBCR422_INPUT_MASK 0x20000000u |
| #define LCDIF_RL_YCBCR422_INPUT_SHIFT 29 |
| #define LCDIF_RL_CLKGATE_MASK 0x40000000u |
| #define LCDIF_RL_CLKGATE_SHIFT 30 |
| #define LCDIF_RL_SFTRST_MASK 0x80000000u |
| #define LCDIF_RL_SFTRST_SHIFT 31 |
| /* RL_SET Bit Fields */ |
| #define LCDIF_RL_SET_RUN_MASK 0x1u |
| #define LCDIF_RL_SET_RUN_SHIFT 0 |
| #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_MASK 0x2u |
| #define LCDIF_RL_SET_DATA_FORMAT_24_BIT_SHIFT 1 |
| #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_MASK 0x4u |
| #define LCDIF_RL_SET_DATA_FORMAT_18_BIT_SHIFT 2 |
| #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_MASK 0x8u |
| #define LCDIF_RL_SET_DATA_FORMAT_16_BIT_SHIFT 3 |
| #define LCDIF_RL_SET_RSRVD0_MASK 0x10u |
| #define LCDIF_RL_SET_RSRVD0_SHIFT 4 |
| #define LCDIF_RL_SET_MASTER_MASK 0x20u |
| #define LCDIF_RL_SET_MASTER_SHIFT 5 |
| #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_MASK 0x40u |
| #define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_SHIFT 6 |
| #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_MASK 0x80u |
| #define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_SHIFT 7 |
| #define LCDIF_RL_SET_WORD_LENGTH_MASK 0x300u |
| #define LCDIF_RL_SET_WORD_LENGTH_SHIFT 8 |
| #define LCDIF_RL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_WORD_LENGTH_SHIFT))&LCDIF_RL_SET_WORD_LENGTH_MASK) |
| #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK 0xC00u |
| #define LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT 10 |
| #define LCDIF_RL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK 0x3000u |
| #define LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT 12 |
| #define LCDIF_RL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK 0xC000u |
| #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT 14 |
| #define LCDIF_RL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_SET_DATA_SELECT_MASK 0x10000u |
| #define LCDIF_RL_SET_DATA_SELECT_SHIFT 16 |
| #define LCDIF_RL_SET_DOTCLK_MODE_MASK 0x20000u |
| #define LCDIF_RL_SET_DOTCLK_MODE_SHIFT 17 |
| #define LCDIF_RL_SET_VSYNC_MODE_MASK 0x40000u |
| #define LCDIF_RL_SET_VSYNC_MODE_SHIFT 18 |
| #define LCDIF_RL_SET_BYPASS_COUNT_MASK 0x80000u |
| #define LCDIF_RL_SET_BYPASS_COUNT_SHIFT 19 |
| #define LCDIF_RL_SET_DVI_MODE_MASK 0x100000u |
| #define LCDIF_RL_SET_DVI_MODE_SHIFT 20 |
| #define LCDIF_RL_SET_SHIFT_NUM_BITS_MASK 0x3E00000u |
| #define LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT 21 |
| #define LCDIF_RL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SET_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_RL_SET_DATA_SHIFT_DIR_MASK 0x4000000u |
| #define LCDIF_RL_SET_DATA_SHIFT_DIR_SHIFT 26 |
| #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u |
| #define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT 27 |
| #define LCDIF_RL_SET_READ_WRITEB_MASK 0x10000000u |
| #define LCDIF_RL_SET_READ_WRITEB_SHIFT 28 |
| #define LCDIF_RL_SET_YCBCR422_INPUT_MASK 0x20000000u |
| #define LCDIF_RL_SET_YCBCR422_INPUT_SHIFT 29 |
| #define LCDIF_RL_SET_CLKGATE_MASK 0x40000000u |
| #define LCDIF_RL_SET_CLKGATE_SHIFT 30 |
| #define LCDIF_RL_SET_SFTRST_MASK 0x80000000u |
| #define LCDIF_RL_SET_SFTRST_SHIFT 31 |
| /* RL_CLR Bit Fields */ |
| #define LCDIF_RL_CLR_RUN_MASK 0x1u |
| #define LCDIF_RL_CLR_RUN_SHIFT 0 |
| #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_MASK 0x2u |
| #define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_SHIFT 1 |
| #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_MASK 0x4u |
| #define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_SHIFT 2 |
| #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_MASK 0x8u |
| #define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_SHIFT 3 |
| #define LCDIF_RL_CLR_RSRVD0_MASK 0x10u |
| #define LCDIF_RL_CLR_RSRVD0_SHIFT 4 |
| #define LCDIF_RL_CLR_MASTER_MASK 0x20u |
| #define LCDIF_RL_CLR_MASTER_SHIFT 5 |
| #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_MASK 0x40u |
| #define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT 6 |
| #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_MASK 0x80u |
| #define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_SHIFT 7 |
| #define LCDIF_RL_CLR_WORD_LENGTH_MASK 0x300u |
| #define LCDIF_RL_CLR_WORD_LENGTH_SHIFT 8 |
| #define LCDIF_RL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_WORD_LENGTH_SHIFT))&LCDIF_RL_CLR_WORD_LENGTH_MASK) |
| #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK 0xC00u |
| #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT 10 |
| #define LCDIF_RL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK 0x3000u |
| #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT 12 |
| #define LCDIF_RL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK 0xC000u |
| #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT 14 |
| #define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_CLR_DATA_SELECT_MASK 0x10000u |
| #define LCDIF_RL_CLR_DATA_SELECT_SHIFT 16 |
| #define LCDIF_RL_CLR_DOTCLK_MODE_MASK 0x20000u |
| #define LCDIF_RL_CLR_DOTCLK_MODE_SHIFT 17 |
| #define LCDIF_RL_CLR_VSYNC_MODE_MASK 0x40000u |
| #define LCDIF_RL_CLR_VSYNC_MODE_SHIFT 18 |
| #define LCDIF_RL_CLR_BYPASS_COUNT_MASK 0x80000u |
| #define LCDIF_RL_CLR_BYPASS_COUNT_SHIFT 19 |
| #define LCDIF_RL_CLR_DVI_MODE_MASK 0x100000u |
| #define LCDIF_RL_CLR_DVI_MODE_SHIFT 20 |
| #define LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK 0x3E00000u |
| #define LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT 21 |
| #define LCDIF_RL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_RL_CLR_DATA_SHIFT_DIR_MASK 0x4000000u |
| #define LCDIF_RL_CLR_DATA_SHIFT_DIR_SHIFT 26 |
| #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u |
| #define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT 27 |
| #define LCDIF_RL_CLR_READ_WRITEB_MASK 0x10000000u |
| #define LCDIF_RL_CLR_READ_WRITEB_SHIFT 28 |
| #define LCDIF_RL_CLR_YCBCR422_INPUT_MASK 0x20000000u |
| #define LCDIF_RL_CLR_YCBCR422_INPUT_SHIFT 29 |
| #define LCDIF_RL_CLR_CLKGATE_MASK 0x40000000u |
| #define LCDIF_RL_CLR_CLKGATE_SHIFT 30 |
| #define LCDIF_RL_CLR_SFTRST_MASK 0x80000000u |
| #define LCDIF_RL_CLR_SFTRST_SHIFT 31 |
| /* RL_TOG Bit Fields */ |
| #define LCDIF_RL_TOG_RUN_MASK 0x1u |
| #define LCDIF_RL_TOG_RUN_SHIFT 0 |
| #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_MASK 0x2u |
| #define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_SHIFT 1 |
| #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_MASK 0x4u |
| #define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_SHIFT 2 |
| #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_MASK 0x8u |
| #define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_SHIFT 3 |
| #define LCDIF_RL_TOG_RSRVD0_MASK 0x10u |
| #define LCDIF_RL_TOG_RSRVD0_SHIFT 4 |
| #define LCDIF_RL_TOG_MASTER_MASK 0x20u |
| #define LCDIF_RL_TOG_MASTER_SHIFT 5 |
| #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_MASK 0x40u |
| #define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT 6 |
| #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_MASK 0x80u |
| #define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_SHIFT 7 |
| #define LCDIF_RL_TOG_WORD_LENGTH_MASK 0x300u |
| #define LCDIF_RL_TOG_WORD_LENGTH_SHIFT 8 |
| #define LCDIF_RL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_WORD_LENGTH_SHIFT))&LCDIF_RL_TOG_WORD_LENGTH_MASK) |
| #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK 0xC00u |
| #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT 10 |
| #define LCDIF_RL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK) |
| #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK 0x3000u |
| #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT 12 |
| #define LCDIF_RL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK 0xC000u |
| #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT 14 |
| #define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_RL_TOG_DATA_SELECT_MASK 0x10000u |
| #define LCDIF_RL_TOG_DATA_SELECT_SHIFT 16 |
| #define LCDIF_RL_TOG_DOTCLK_MODE_MASK 0x20000u |
| #define LCDIF_RL_TOG_DOTCLK_MODE_SHIFT 17 |
| #define LCDIF_RL_TOG_VSYNC_MODE_MASK 0x40000u |
| #define LCDIF_RL_TOG_VSYNC_MODE_SHIFT 18 |
| #define LCDIF_RL_TOG_BYPASS_COUNT_MASK 0x80000u |
| #define LCDIF_RL_TOG_BYPASS_COUNT_SHIFT 19 |
| #define LCDIF_RL_TOG_DVI_MODE_MASK 0x100000u |
| #define LCDIF_RL_TOG_DVI_MODE_SHIFT 20 |
| #define LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK 0x3E00000u |
| #define LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT 21 |
| #define LCDIF_RL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK) |
| #define LCDIF_RL_TOG_DATA_SHIFT_DIR_MASK 0x4000000u |
| #define LCDIF_RL_TOG_DATA_SHIFT_DIR_SHIFT 26 |
| #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u |
| #define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT 27 |
| #define LCDIF_RL_TOG_READ_WRITEB_MASK 0x10000000u |
| #define LCDIF_RL_TOG_READ_WRITEB_SHIFT 28 |
| #define LCDIF_RL_TOG_YCBCR422_INPUT_MASK 0x20000000u |
| #define LCDIF_RL_TOG_YCBCR422_INPUT_SHIFT 29 |
| #define LCDIF_RL_TOG_CLKGATE_MASK 0x40000000u |
| #define LCDIF_RL_TOG_CLKGATE_SHIFT 30 |
| #define LCDIF_RL_TOG_SFTRST_MASK 0x80000000u |
| #define LCDIF_RL_TOG_SFTRST_SHIFT 31 |
| /* CTRL1 Bit Fields */ |
| #define LCDIF_CTRL1_RESET_MASK 0x1u |
| #define LCDIF_CTRL1_RESET_SHIFT 0 |
| #define LCDIF_CTRL1_MODE86_MASK 0x2u |
| #define LCDIF_CTRL1_MODE86_SHIFT 1 |
| #define LCDIF_CTRL1_BUSY_ENABLE_MASK 0x4u |
| #define LCDIF_CTRL1_BUSY_ENABLE_SHIFT 2 |
| #define LCDIF_CTRL1_RSRVD0_MASK 0xF8u |
| #define LCDIF_CTRL1_RSRVD0_SHIFT 3 |
| #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD0_SHIFT))&LCDIF_CTRL1_RSRVD0_MASK) |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK 0x100u |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT 8 |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK 0x200u |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT 9 |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK 0x400u |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT 10 |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK 0x800u |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT 11 |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK 0x1000u |
| #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT 12 |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u |
| #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK 0x4000u |
| #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT 14 |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK 0x8000u |
| #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT 15 |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK 0xF0000u |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT 16 |
| #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u |
| #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 |
| #define LCDIF_CTRL1_FIFO_CLEAR_MASK 0x200000u |
| #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT 21 |
| #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u |
| #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 |
| #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK 0x800000u |
| #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT 23 |
| #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK 0x1000000u |
| #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT 24 |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK 0x2000000u |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT 25 |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK 0x4000000u |
| #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT 26 |
| #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK 0x8000000u |
| #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT 27 |
| #define LCDIF_CTRL1_RSRVD1_MASK 0xF0000000u |
| #define LCDIF_CTRL1_RSRVD1_SHIFT 28 |
| #define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD1_SHIFT))&LCDIF_CTRL1_RSRVD1_MASK) |
| /* CTRL1_SET Bit Fields */ |
| #define LCDIF_CTRL1_SET_RESET_MASK 0x1u |
| #define LCDIF_CTRL1_SET_RESET_SHIFT 0 |
| #define LCDIF_CTRL1_SET_MODE86_MASK 0x2u |
| #define LCDIF_CTRL1_SET_MODE86_SHIFT 1 |
| #define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK 0x4u |
| #define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT 2 |
| #define LCDIF_CTRL1_SET_RSRVD0_MASK 0xF8u |
| #define LCDIF_CTRL1_SET_RSRVD0_SHIFT 3 |
| #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD0_SHIFT))&LCDIF_CTRL1_SET_RSRVD0_MASK) |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK 0x100u |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT 8 |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK 0x200u |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT 9 |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK 0x400u |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT 10 |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK 0x800u |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT 11 |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK 0x1000u |
| #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT 12 |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u |
| #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK 0x4000u |
| #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT 14 |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK 0x8000u |
| #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT 15 |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK 0xF0000u |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT 16 |
| #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u |
| #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 |
| #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK 0x200000u |
| #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT 21 |
| #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u |
| #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 |
| #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK 0x800000u |
| #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT 23 |
| #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK 0x1000000u |
| #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT 24 |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK 0x2000000u |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT 25 |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK 0x4000000u |
| #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT 26 |
| #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK 0x8000000u |
| #define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT 27 |
| #define LCDIF_CTRL1_SET_RSRVD1_MASK 0xF0000000u |
| #define LCDIF_CTRL1_SET_RSRVD1_SHIFT 28 |
| #define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD1_SHIFT))&LCDIF_CTRL1_SET_RSRVD1_MASK) |
| /* CTRL1_CLR Bit Fields */ |
| #define LCDIF_CTRL1_CLR_RESET_MASK 0x1u |
| #define LCDIF_CTRL1_CLR_RESET_SHIFT 0 |
| #define LCDIF_CTRL1_CLR_MODE86_MASK 0x2u |
| #define LCDIF_CTRL1_CLR_MODE86_SHIFT 1 |
| #define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK 0x4u |
| #define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT 2 |
| #define LCDIF_CTRL1_CLR_RSRVD0_MASK 0xF8u |
| #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT 3 |
| #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK) |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK 0x100u |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT 8 |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK 0x200u |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT 9 |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK 0x400u |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT 10 |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK 0x800u |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT 11 |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK 0x1000u |
| #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT 12 |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u |
| #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK 0x4000u |
| #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT 14 |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK 0x8000u |
| #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT 15 |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK 0xF0000u |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT 16 |
| #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u |
| #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 |
| #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK 0x200000u |
| #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT 21 |
| #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u |
| #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 |
| #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK 0x800000u |
| #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT 23 |
| #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK 0x1000000u |
| #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT 24 |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK 0x2000000u |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT 25 |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK 0x4000000u |
| #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT 26 |
| #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK 0x8000000u |
| #define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT 27 |
| #define LCDIF_CTRL1_CLR_RSRVD1_MASK 0xF0000000u |
| #define LCDIF_CTRL1_CLR_RSRVD1_SHIFT 28 |
| #define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD1_SHIFT))&LCDIF_CTRL1_CLR_RSRVD1_MASK) |
| /* CTRL1_TOG Bit Fields */ |
| #define LCDIF_CTRL1_TOG_RESET_MASK 0x1u |
| #define LCDIF_CTRL1_TOG_RESET_SHIFT 0 |
| #define LCDIF_CTRL1_TOG_MODE86_MASK 0x2u |
| #define LCDIF_CTRL1_TOG_MODE86_SHIFT 1 |
| #define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK 0x4u |
| #define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT 2 |
| #define LCDIF_CTRL1_TOG_RSRVD0_MASK 0xF8u |
| #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT 3 |
| #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD0_SHIFT))&LCDIF_CTRL1_TOG_RSRVD0_MASK) |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK 0x100u |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT 8 |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK 0x200u |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT 9 |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK 0x400u |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT 10 |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK 0x800u |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT 11 |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK 0x1000u |
| #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT 12 |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u |
| #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK 0x4000u |
| #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT 14 |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK 0x8000u |
| #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT 15 |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK 0xF0000u |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT 16 |
| #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) |
| #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u |
| #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 |
| #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK 0x200000u |
| #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT 21 |
| #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u |
| #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 |
| #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK 0x800000u |
| #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT 23 |
| #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK 0x1000000u |
| #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT 24 |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK 0x2000000u |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT 25 |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK 0x4000000u |
| #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT 26 |
| #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK 0x8000000u |
| #define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT 27 |
| #define LCDIF_CTRL1_TOG_RSRVD1_MASK 0xF0000000u |
| #define LCDIF_CTRL1_TOG_RSRVD1_SHIFT 28 |
| #define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD1_SHIFT))&LCDIF_CTRL1_TOG_RSRVD1_MASK) |
| /* CTRL2 Bit Fields */ |
| #define LCDIF_CTRL2_RSRVD0_MASK 0x1u |
| #define LCDIF_CTRL2_RSRVD0_SHIFT 0 |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK 0xEu |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT 1 |
| #define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 |
| #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_RSRVD1_MASK 0x80u |
| #define LCDIF_CTRL2_RSRVD1_SHIFT 7 |
| #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK 0x100u |
| #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT 8 |
| #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u |
| #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 |
| #define LCDIF_CTRL2_READ_PACK_DIR_MASK 0x400u |
| #define LCDIF_CTRL2_READ_PACK_DIR_SHIFT 10 |
| #define LCDIF_CTRL2_RSRVD2_MASK 0x800u |
| #define LCDIF_CTRL2_RSRVD2_SHIFT 11 |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK 0x7000u |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT 12 |
| #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_RSRVD3_MASK 0x8000u |
| #define LCDIF_CTRL2_RSRVD3_SHIFT 15 |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK 0x70000u |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT 16 |
| #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_RSRVD4_MASK 0x80000u |
| #define LCDIF_CTRL2_RSRVD4_SHIFT 19 |
| #define LCDIF_CTRL2_BURST_LEN_8_MASK 0x100000u |
| #define LCDIF_CTRL2_BURST_LEN_8_SHIFT 20 |
| #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK 0xE00000u |
| #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT 21 |
| #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_RSRVD5_MASK 0xFF000000u |
| #define LCDIF_CTRL2_RSRVD5_SHIFT 24 |
| #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_RSRVD5_SHIFT))&LCDIF_CTRL2_RSRVD5_MASK) |
| /* CTRL2_SET Bit Fields */ |
| #define LCDIF_CTRL2_SET_RSRVD0_MASK 0x1u |
| #define LCDIF_CTRL2_SET_RSRVD0_SHIFT 0 |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK 0xEu |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT 1 |
| #define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 |
| #define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD1_MASK 0x80u |
| #define LCDIF_CTRL2_SET_RSRVD1_SHIFT 7 |
| #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK 0x100u |
| #define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT 8 |
| #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u |
| #define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 |
| #define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK 0x400u |
| #define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT 10 |
| #define LCDIF_CTRL2_SET_RSRVD2_MASK 0x800u |
| #define LCDIF_CTRL2_SET_RSRVD2_SHIFT 11 |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK 0x7000u |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT 12 |
| #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD3_MASK 0x8000u |
| #define LCDIF_CTRL2_SET_RSRVD3_SHIFT 15 |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK 0x70000u |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT 16 |
| #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD4_MASK 0x80000u |
| #define LCDIF_CTRL2_SET_RSRVD4_SHIFT 19 |
| #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK 0x100000u |
| #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT 20 |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK 0xE00000u |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT 21 |
| #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_SET_RSRVD5_MASK 0xFF000000u |
| #define LCDIF_CTRL2_SET_RSRVD5_SHIFT 24 |
| #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_RSRVD5_SHIFT))&LCDIF_CTRL2_SET_RSRVD5_MASK) |
| /* CTRL2_CLR Bit Fields */ |
| #define LCDIF_CTRL2_CLR_RSRVD0_MASK 0x1u |
| #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT 0 |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK 0xEu |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT 1 |
| #define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 |
| #define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD1_MASK 0x80u |
| #define LCDIF_CTRL2_CLR_RSRVD1_SHIFT 7 |
| #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK 0x100u |
| #define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT 8 |
| #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u |
| #define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 |
| #define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK 0x400u |
| #define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT 10 |
| #define LCDIF_CTRL2_CLR_RSRVD2_MASK 0x800u |
| #define LCDIF_CTRL2_CLR_RSRVD2_SHIFT 11 |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK 0x7000u |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT 12 |
| #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD3_MASK 0x8000u |
| #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT 15 |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK 0x70000u |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT 16 |
| #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD4_MASK 0x80000u |
| #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT 19 |
| #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK 0x100000u |
| #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT 20 |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK 0xE00000u |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT 21 |
| #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_CLR_RSRVD5_MASK 0xFF000000u |
| #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT 24 |
| #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_RSRVD5_SHIFT))&LCDIF_CTRL2_CLR_RSRVD5_MASK) |
| /* CTRL2_TOG Bit Fields */ |
| #define LCDIF_CTRL2_TOG_RSRVD0_MASK 0x1u |
| #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT 0 |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK 0xEu |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT 1 |
| #define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 |
| #define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD1_MASK 0x80u |
| #define LCDIF_CTRL2_TOG_RSRVD1_SHIFT 7 |
| #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK 0x100u |
| #define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT 8 |
| #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u |
| #define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 |
| #define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK 0x400u |
| #define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT 10 |
| #define LCDIF_CTRL2_TOG_RSRVD2_MASK 0x800u |
| #define LCDIF_CTRL2_TOG_RSRVD2_SHIFT 11 |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK 0x7000u |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT 12 |
| #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD3_MASK 0x8000u |
| #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT 15 |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK 0x70000u |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT 16 |
| #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD4_MASK 0x80000u |
| #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT 19 |
| #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK 0x100000u |
| #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT 20 |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK 0xE00000u |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT 21 |
| #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) |
| #define LCDIF_CTRL2_TOG_RSRVD5_MASK 0xFF000000u |
| #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT 24 |
| #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK) |
| /* TRANSFER_COUNT Bit Fields */ |
| #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK 0xFFFFu |
| #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT 0 |
| #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_H_COUNT_MASK) |
| #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK 0xFFFF0000u |
| #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT 16 |
| #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_V_COUNT_MASK) |
| /* CUR_BUF Bit Fields */ |
| #define LCDIF_CUR_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define LCDIF_CUR_BUF_ADDR_SHIFT 0 |
| #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CUR_BUF_ADDR_SHIFT))&LCDIF_CUR_BUF_ADDR_MASK) |
| /* NEXT_BUF Bit Fields */ |
| #define LCDIF_NEXT_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define LCDIF_NEXT_BUF_ADDR_SHIFT 0 |
| #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_NEXT_BUF_ADDR_SHIFT))&LCDIF_NEXT_BUF_ADDR_MASK) |
| /* TIMING Bit Fields */ |
| #define LCDIF_TIMING_DATA_SETUP_MASK 0xFFu |
| #define LCDIF_TIMING_DATA_SETUP_SHIFT 0 |
| #define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_SETUP_SHIFT))&LCDIF_TIMING_DATA_SETUP_MASK) |
| #define LCDIF_TIMING_DATA_HOLD_MASK 0xFF00u |
| #define LCDIF_TIMING_DATA_HOLD_SHIFT 8 |
| #define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_HOLD_SHIFT))&LCDIF_TIMING_DATA_HOLD_MASK) |
| #define LCDIF_TIMING_CMD_SETUP_MASK 0xFF0000u |
| #define LCDIF_TIMING_CMD_SETUP_SHIFT 16 |
| #define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_SETUP_SHIFT))&LCDIF_TIMING_CMD_SETUP_MASK) |
| #define LCDIF_TIMING_CMD_HOLD_MASK 0xFF000000u |
| #define LCDIF_TIMING_CMD_HOLD_SHIFT 24 |
| #define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_HOLD_SHIFT))&LCDIF_TIMING_CMD_HOLD_MASK) |
| /* VDCTRL0 Bit Fields */ |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT 0 |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK 0x40000u |
| #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT 18 |
| #define LCDIF_VDCTRL0_HALF_LINE_MASK 0x80000u |
| #define LCDIF_VDCTRL0_HALF_LINE_SHIFT 19 |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u |
| #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 |
| #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK 0x200000u |
| #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT 21 |
| #define LCDIF_VDCTRL0_RSRVD1_MASK 0xC00000u |
| #define LCDIF_VDCTRL0_RSRVD1_SHIFT 22 |
| #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD1_SHIFT))&LCDIF_VDCTRL0_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_ENABLE_POL_MASK 0x1000000u |
| #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT 24 |
| #define LCDIF_VDCTRL0_DOTCLK_POL_MASK 0x2000000u |
| #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT 25 |
| #define LCDIF_VDCTRL0_HSYNC_POL_MASK 0x4000000u |
| #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT 26 |
| #define LCDIF_VDCTRL0_VSYNC_POL_MASK 0x8000000u |
| #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT 27 |
| #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK 0x10000000u |
| #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT 28 |
| #define LCDIF_VDCTRL0_VSYNC_OEB_MASK 0x20000000u |
| #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT 29 |
| #define LCDIF_VDCTRL0_RSRVD2_MASK 0xC0000000u |
| #define LCDIF_VDCTRL0_RSRVD2_SHIFT 30 |
| #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD2_SHIFT))&LCDIF_VDCTRL0_RSRVD2_MASK) |
| /* VDCTRL0_SET Bit Fields */ |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT 0 |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK 0x40000u |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT 18 |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK 0x80000u |
| #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT 19 |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u |
| #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 |
| #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK 0x200000u |
| #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT 21 |
| #define LCDIF_VDCTRL0_SET_RSRVD1_MASK 0xC00000u |
| #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT 22 |
| #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD1_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK 0x1000000u |
| #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT 24 |
| #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK 0x2000000u |
| #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT 25 |
| #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK 0x4000000u |
| #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT 26 |
| #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK 0x8000000u |
| #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT 27 |
| #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK 0x10000000u |
| #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT 28 |
| #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK 0x20000000u |
| #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT 29 |
| #define LCDIF_VDCTRL0_SET_RSRVD2_MASK 0xC0000000u |
| #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT 30 |
| #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD2_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD2_MASK) |
| /* VDCTRL0_CLR Bit Fields */ |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT 0 |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK 0x40000u |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT 18 |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK 0x80000u |
| #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT 19 |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK 0x200000u |
| #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT 21 |
| #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK 0xC00000u |
| #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT 22 |
| #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK 0x1000000u |
| #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT 24 |
| #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK 0x2000000u |
| #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT 25 |
| #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK 0x4000000u |
| #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT 26 |
| #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK 0x8000000u |
| #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT 27 |
| #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK 0x10000000u |
| #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT 28 |
| #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK 0x20000000u |
| #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT 29 |
| #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK 0xC0000000u |
| #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT 30 |
| #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD2_MASK) |
| /* VDCTRL0_TOG Bit Fields */ |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT 0 |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK 0x40000u |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT 18 |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK 0x80000u |
| #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT 19 |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK 0x200000u |
| #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT 21 |
| #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK 0xC00000u |
| #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT 22 |
| #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD1_MASK) |
| #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK 0x1000000u |
| #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT 24 |
| #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK 0x2000000u |
| #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT 25 |
| #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK 0x4000000u |
| #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT 26 |
| #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK 0x8000000u |
| #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT 27 |
| #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK 0x10000000u |
| #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT 28 |
| #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK 0x20000000u |
| #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT 29 |
| #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK 0xC0000000u |
| #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT 30 |
| #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD2_MASK) |
| /* VDCTRL1 Bit Fields */ |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xFFFFFFFFu |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT 0 |
| #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) |
| /* VDCTRL2 Bit Fields */ |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT 0 |
| #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK 0xFFFC0000u |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT 18 |
| #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) |
| /* VDCTRL3 Bit Fields */ |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK 0xFFFFu |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT 0 |
| #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK 0xFFF0000u |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT 16 |
| #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) |
| #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK 0x10000000u |
| #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT 28 |
| #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK 0x20000000u |
| #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT 29 |
| #define LCDIF_VDCTRL3_RSRVD0_MASK 0xC0000000u |
| #define LCDIF_VDCTRL3_RSRVD0_SHIFT 30 |
| #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK) |
| /* VDCTRL4 Bit Fields */ |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3FFFFu |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT 0 |
| #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT))&LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) |
| #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK 0x40000u |
| #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT 18 |
| #define LCDIF_VDCTRL4_RSRVD0_MASK 0x1FF80000u |
| #define LCDIF_VDCTRL4_RSRVD0_SHIFT 19 |
| #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_RSRVD0_SHIFT))&LCDIF_VDCTRL4_RSRVD0_MASK) |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK 0xE0000000u |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT 29 |
| #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT))&LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) |
| /* DVICTRL0 Bit Fields */ |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK 0xFFFu |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT 0 |
| #define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT))&LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) |
| #define LCDIF_DVICTRL0_RSRVD0_MASK 0xF000u |
| #define LCDIF_DVICTRL0_RSRVD0_SHIFT 12 |
| #define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD0_SHIFT))&LCDIF_DVICTRL0_RSRVD0_MASK) |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK 0xFFF0000u |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT 16 |
| #define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT))&LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) |
| #define LCDIF_DVICTRL0_RSRVD1_MASK 0xF0000000u |
| #define LCDIF_DVICTRL0_RSRVD1_SHIFT 28 |
| #define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD1_SHIFT))&LCDIF_DVICTRL0_RSRVD1_MASK) |
| /* DVICTRL1 Bit Fields */ |
| #define LCDIF_DVICTRL1_F2_START_LINE_MASK 0x3FFu |
| #define LCDIF_DVICTRL1_F2_START_LINE_SHIFT 0 |
| #define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F2_START_LINE_SHIFT))&LCDIF_DVICTRL1_F2_START_LINE_MASK) |
| #define LCDIF_DVICTRL1_F1_END_LINE_MASK 0xFFC00u |
| #define LCDIF_DVICTRL1_F1_END_LINE_SHIFT 10 |
| #define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_END_LINE_SHIFT))&LCDIF_DVICTRL1_F1_END_LINE_MASK) |
| #define LCDIF_DVICTRL1_F1_START_LINE_MASK 0x3FF00000u |
| #define LCDIF_DVICTRL1_F1_START_LINE_SHIFT 20 |
| #define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_START_LINE_SHIFT))&LCDIF_DVICTRL1_F1_START_LINE_MASK) |
| #define LCDIF_DVICTRL1_RSRVD0_MASK 0xC0000000u |
| #define LCDIF_DVICTRL1_RSRVD0_SHIFT 30 |
| #define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_RSRVD0_SHIFT))&LCDIF_DVICTRL1_RSRVD0_MASK) |
| /* DVICTRL2 Bit Fields */ |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK 0x3FFu |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT 0 |
| #define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK 0xFFC00u |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT 10 |
| #define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) |
| #define LCDIF_DVICTRL2_F2_END_LINE_MASK 0x3FF00000u |
| #define LCDIF_DVICTRL2_F2_END_LINE_SHIFT 20 |
| #define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_F2_END_LINE_SHIFT))&LCDIF_DVICTRL2_F2_END_LINE_MASK) |
| #define LCDIF_DVICTRL2_RSRVD0_MASK 0xC0000000u |
| #define LCDIF_DVICTRL2_RSRVD0_SHIFT 30 |
| #define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_RSRVD0_SHIFT))&LCDIF_DVICTRL2_RSRVD0_MASK) |
| /* DVICTRL3 Bit Fields */ |
| #define LCDIF_DVICTRL3_V_LINES_CNT_MASK 0x3FFu |
| #define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT 0 |
| #define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V_LINES_CNT_SHIFT))&LCDIF_DVICTRL3_V_LINES_CNT_MASK) |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK 0xFFC00u |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT 10 |
| #define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK 0x3FF00000u |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT 20 |
| #define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) |
| #define LCDIF_DVICTRL3_RSRVD0_MASK 0xC0000000u |
| #define LCDIF_DVICTRL3_RSRVD0_SHIFT 30 |
| #define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_RSRVD0_SHIFT))&LCDIF_DVICTRL3_RSRVD0_MASK) |
| /* DVICTRL4 Bit Fields */ |
| #define LCDIF_DVICTRL4_H_FILL_CNT_MASK 0xFFu |
| #define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT 0 |
| #define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_H_FILL_CNT_SHIFT))&LCDIF_DVICTRL4_H_FILL_CNT_MASK) |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK 0xFF00u |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT 8 |
| #define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK 0xFF0000u |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT 16 |
| #define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK 0xFF000000u |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT 24 |
| #define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) |
| /* CSC_COEFF0 Bit Fields */ |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK 0x3u |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT 0 |
| #define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT))&LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) |
| #define LCDIF_CSC_COEFF0_RSRVD0_MASK 0xFFFCu |
| #define LCDIF_CSC_COEFF0_RSRVD0_SHIFT 2 |
| #define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD0_SHIFT))&LCDIF_CSC_COEFF0_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF0_C0_MASK 0x3FF0000u |
| #define LCDIF_CSC_COEFF0_C0_SHIFT 16 |
| #define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_C0_SHIFT))&LCDIF_CSC_COEFF0_C0_MASK) |
| #define LCDIF_CSC_COEFF0_RSRVD1_MASK 0xFC000000u |
| #define LCDIF_CSC_COEFF0_RSRVD1_SHIFT 26 |
| #define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD1_SHIFT))&LCDIF_CSC_COEFF0_RSRVD1_MASK) |
| /* CSC_COEFF1 Bit Fields */ |
| #define LCDIF_CSC_COEFF1_C1_MASK 0x3FFu |
| #define LCDIF_CSC_COEFF1_C1_SHIFT 0 |
| #define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C1_SHIFT))&LCDIF_CSC_COEFF1_C1_MASK) |
| #define LCDIF_CSC_COEFF1_RSRVD0_MASK 0xFC00u |
| #define LCDIF_CSC_COEFF1_RSRVD0_SHIFT 10 |
| #define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD0_SHIFT))&LCDIF_CSC_COEFF1_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF1_C2_MASK 0x3FF0000u |
| #define LCDIF_CSC_COEFF1_C2_SHIFT 16 |
| #define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C2_SHIFT))&LCDIF_CSC_COEFF1_C2_MASK) |
| #define LCDIF_CSC_COEFF1_RSRVD1_MASK 0xFC000000u |
| #define LCDIF_CSC_COEFF1_RSRVD1_SHIFT 26 |
| #define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD1_SHIFT))&LCDIF_CSC_COEFF1_RSRVD1_MASK) |
| /* CSC_COEFF2 Bit Fields */ |
| #define LCDIF_CSC_COEFF2_C3_MASK 0x3FFu |
| #define LCDIF_CSC_COEFF2_C3_SHIFT 0 |
| #define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C3_SHIFT))&LCDIF_CSC_COEFF2_C3_MASK) |
| #define LCDIF_CSC_COEFF2_RSRVD0_MASK 0xFC00u |
| #define LCDIF_CSC_COEFF2_RSRVD0_SHIFT 10 |
| #define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD0_SHIFT))&LCDIF_CSC_COEFF2_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF2_C4_MASK 0x3FF0000u |
| #define LCDIF_CSC_COEFF2_C4_SHIFT 16 |
| #define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C4_SHIFT))&LCDIF_CSC_COEFF2_C4_MASK) |
| #define LCDIF_CSC_COEFF2_RSRVD1_MASK 0xFC000000u |
| #define LCDIF_CSC_COEFF2_RSRVD1_SHIFT 26 |
| #define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD1_SHIFT))&LCDIF_CSC_COEFF2_RSRVD1_MASK) |
| /* CSC_COEFF3 Bit Fields */ |
| #define LCDIF_CSC_COEFF3_C5_MASK 0x3FFu |
| #define LCDIF_CSC_COEFF3_C5_SHIFT 0 |
| #define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C5_SHIFT))&LCDIF_CSC_COEFF3_C5_MASK) |
| #define LCDIF_CSC_COEFF3_RSRVD0_MASK 0xFC00u |
| #define LCDIF_CSC_COEFF3_RSRVD0_SHIFT 10 |
| #define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD0_SHIFT))&LCDIF_CSC_COEFF3_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF3_C6_MASK 0x3FF0000u |
| #define LCDIF_CSC_COEFF3_C6_SHIFT 16 |
| #define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C6_SHIFT))&LCDIF_CSC_COEFF3_C6_MASK) |
| #define LCDIF_CSC_COEFF3_RSRVD1_MASK 0xFC000000u |
| #define LCDIF_CSC_COEFF3_RSRVD1_SHIFT 26 |
| #define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD1_SHIFT))&LCDIF_CSC_COEFF3_RSRVD1_MASK) |
| /* CSC_COEFF4 Bit Fields */ |
| #define LCDIF_CSC_COEFF4_C7_MASK 0x3FFu |
| #define LCDIF_CSC_COEFF4_C7_SHIFT 0 |
| #define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C7_SHIFT))&LCDIF_CSC_COEFF4_C7_MASK) |
| #define LCDIF_CSC_COEFF4_RSRVD0_MASK 0xFC00u |
| #define LCDIF_CSC_COEFF4_RSRVD0_SHIFT 10 |
| #define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD0_SHIFT))&LCDIF_CSC_COEFF4_RSRVD0_MASK) |
| #define LCDIF_CSC_COEFF4_C8_MASK 0x3FF0000u |
| #define LCDIF_CSC_COEFF4_C8_SHIFT 16 |
| #define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C8_SHIFT))&LCDIF_CSC_COEFF4_C8_MASK) |
| #define LCDIF_CSC_COEFF4_RSRVD1_MASK 0xFC000000u |
| #define LCDIF_CSC_COEFF4_RSRVD1_SHIFT 26 |
| #define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD1_SHIFT))&LCDIF_CSC_COEFF4_RSRVD1_MASK) |
| /* CSC_OFFSET Bit Fields */ |
| #define LCDIF_CSC_OFFSET_Y_OFFSET_MASK 0x1FFu |
| #define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT 0 |
| #define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_Y_OFFSET_MASK) |
| #define LCDIF_CSC_OFFSET_RSRVD0_MASK 0xFE00u |
| #define LCDIF_CSC_OFFSET_RSRVD0_SHIFT 9 |
| #define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD0_SHIFT))&LCDIF_CSC_OFFSET_RSRVD0_MASK) |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK 0x1FF0000u |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT 16 |
| #define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) |
| #define LCDIF_CSC_OFFSET_RSRVD1_MASK 0xFE000000u |
| #define LCDIF_CSC_OFFSET_RSRVD1_SHIFT 25 |
| #define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD1_SHIFT))&LCDIF_CSC_OFFSET_RSRVD1_MASK) |
| /* CSC_LIMIT Bit Fields */ |
| #define LCDIF_CSC_LIMIT_Y_MAX_MASK 0xFFu |
| #define LCDIF_CSC_LIMIT_Y_MAX_SHIFT 0 |
| #define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MAX_SHIFT))&LCDIF_CSC_LIMIT_Y_MAX_MASK) |
| #define LCDIF_CSC_LIMIT_Y_MIN_MASK 0xFF00u |
| #define LCDIF_CSC_LIMIT_Y_MIN_SHIFT 8 |
| #define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MIN_SHIFT))&LCDIF_CSC_LIMIT_Y_MIN_MASK) |
| #define LCDIF_CSC_LIMIT_CBCR_MAX_MASK 0xFF0000u |
| #define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT 16 |
| #define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MAX_MASK) |
| #define LCDIF_CSC_LIMIT_CBCR_MIN_MASK 0xFF000000u |
| #define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT 24 |
| #define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MIN_MASK) |
| /* DATA Bit Fields */ |
| #define LCDIF_DATA_DATA_ZERO_MASK 0xFFu |
| #define LCDIF_DATA_DATA_ZERO_SHIFT 0 |
| #define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ZERO_SHIFT))&LCDIF_DATA_DATA_ZERO_MASK) |
| #define LCDIF_DATA_DATA_ONE_MASK 0xFF00u |
| #define LCDIF_DATA_DATA_ONE_SHIFT 8 |
| #define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ONE_SHIFT))&LCDIF_DATA_DATA_ONE_MASK) |
| #define LCDIF_DATA_DATA_TWO_MASK 0xFF0000u |
| #define LCDIF_DATA_DATA_TWO_SHIFT 16 |
| #define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_TWO_SHIFT))&LCDIF_DATA_DATA_TWO_MASK) |
| #define LCDIF_DATA_DATA_THREE_MASK 0xFF000000u |
| #define LCDIF_DATA_DATA_THREE_SHIFT 24 |
| #define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_THREE_SHIFT))&LCDIF_DATA_DATA_THREE_MASK) |
| /* BM_ERROR_STAT Bit Fields */ |
| #define LCDIF_BM_ERROR_STAT_ADDR_MASK 0xFFFFFFFFu |
| #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT 0 |
| #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_BM_ERROR_STAT_ADDR_SHIFT))&LCDIF_BM_ERROR_STAT_ADDR_MASK) |
| /* CRC_STAT Bit Fields */ |
| #define LCDIF_CRC_STAT_CRC_VALUE_MASK 0xFFFFFFFFu |
| #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT 0 |
| #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CRC_STAT_CRC_VALUE_SHIFT))&LCDIF_CRC_STAT_CRC_VALUE_MASK) |
| /* STAT Bit Fields */ |
| #define LCDIF_STAT_LFIFO_COUNT_MASK 0x1FFu |
| #define LCDIF_STAT_LFIFO_COUNT_SHIFT 0 |
| #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_LFIFO_COUNT_SHIFT))&LCDIF_STAT_LFIFO_COUNT_MASK) |
| #define LCDIF_STAT_RSRVD0_MASK 0xFFFE00u |
| #define LCDIF_STAT_RSRVD0_SHIFT 9 |
| #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_RSRVD0_SHIFT))&LCDIF_STAT_RSRVD0_MASK) |
| #define LCDIF_STAT_DVI_CURRENT_FIELD_MASK 0x1000000u |
| #define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT 24 |
| #define LCDIF_STAT_BUSY_MASK 0x2000000u |
| #define LCDIF_STAT_BUSY_SHIFT 25 |
| #define LCDIF_STAT_TXFIFO_EMPTY_MASK 0x4000000u |
| #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT 26 |
| #define LCDIF_STAT_TXFIFO_FULL_MASK 0x8000000u |
| #define LCDIF_STAT_TXFIFO_FULL_SHIFT 27 |
| #define LCDIF_STAT_LFIFO_EMPTY_MASK 0x10000000u |
| #define LCDIF_STAT_LFIFO_EMPTY_SHIFT 28 |
| #define LCDIF_STAT_LFIFO_FULL_MASK 0x20000000u |
| #define LCDIF_STAT_LFIFO_FULL_SHIFT 29 |
| #define LCDIF_STAT_PRESENT_MASK 0x80000000u |
| #define LCDIF_STAT_PRESENT_SHIFT 31 |
| /* VERSION Bit Fields */ |
| #define LCDIF_VERSION_STEP_MASK 0xFFFFu |
| #define LCDIF_VERSION_STEP_SHIFT 0 |
| #define LCDIF_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_STEP_SHIFT))&LCDIF_VERSION_STEP_MASK) |
| #define LCDIF_VERSION_MINOR_MASK 0xFF0000u |
| #define LCDIF_VERSION_MINOR_SHIFT 16 |
| #define LCDIF_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MINOR_SHIFT))&LCDIF_VERSION_MINOR_MASK) |
| #define LCDIF_VERSION_MAJOR_MASK 0xFF000000u |
| #define LCDIF_VERSION_MAJOR_SHIFT 24 |
| #define LCDIF_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MAJOR_SHIFT))&LCDIF_VERSION_MAJOR_MASK) |
| /* DEBUG0 Bit Fields */ |
| #define LCDIF_DEBUG0_MST_WORDS_MASK 0xFu |
| #define LCDIF_DEBUG0_MST_WORDS_SHIFT 0 |
| #define LCDIF_DEBUG0_MST_WORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_WORDS_SHIFT))&LCDIF_DEBUG0_MST_WORDS_MASK) |
| #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK 0x1F0u |
| #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT 4 |
| #define LCDIF_DEBUG0_MST_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK) |
| #define LCDIF_DEBUG0_MST_AVALID_MASK 0x200u |
| #define LCDIF_DEBUG0_MST_AVALID_SHIFT 9 |
| #define LCDIF_DEBUG0_CUR_REQ_STATE_MASK 0xC00u |
| #define LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT 10 |
| #define LCDIF_DEBUG0_CUR_REQ_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG0_CUR_REQ_STATE_MASK) |
| #define LCDIF_DEBUG0_PXP_B1_DONE_MASK 0x1000u |
| #define LCDIF_DEBUG0_PXP_B1_DONE_SHIFT 12 |
| #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_MASK 0x2000u |
| #define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_SHIFT 13 |
| #define LCDIF_DEBUG0_PXP_B0_DONE_MASK 0x4000u |
| #define LCDIF_DEBUG0_PXP_B0_DONE_SHIFT 14 |
| #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_MASK 0x8000u |
| #define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_SHIFT 15 |
| #define LCDIF_DEBUG0_CUR_STATE_MASK 0x7F0000u |
| #define LCDIF_DEBUG0_CUR_STATE_SHIFT 16 |
| #define LCDIF_DEBUG0_CUR_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_STATE_SHIFT))&LCDIF_DEBUG0_CUR_STATE_MASK) |
| #define LCDIF_DEBUG0_EMPTY_WORD_MASK 0x800000u |
| #define LCDIF_DEBUG0_EMPTY_WORD_SHIFT 23 |
| #define LCDIF_DEBUG0_CUR_FRAME_TX_MASK 0x1000000u |
| #define LCDIF_DEBUG0_CUR_FRAME_TX_SHIFT 24 |
| #define LCDIF_DEBUG0_VSYNC_MASK 0x2000000u |
| #define LCDIF_DEBUG0_VSYNC_SHIFT 25 |
| #define LCDIF_DEBUG0_HSYNC_MASK 0x4000000u |
| #define LCDIF_DEBUG0_HSYNC_SHIFT 26 |
| #define LCDIF_DEBUG0_ENABLE_MASK 0x8000000u |
| #define LCDIF_DEBUG0_ENABLE_SHIFT 27 |
| #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_MASK 0x20000000u |
| #define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_SHIFT 29 |
| #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_MASK 0x40000000u |
| #define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_SHIFT 30 |
| #define LCDIF_DEBUG0_STREAMING_END_DETECTED_MASK 0x80000000u |
| #define LCDIF_DEBUG0_STREAMING_END_DETECTED_SHIFT 31 |
| /* DEBUG1 Bit Fields */ |
| #define LCDIF_DEBUG1_V_DATA_COUNT_MASK 0xFFFFu |
| #define LCDIF_DEBUG1_V_DATA_COUNT_SHIFT 0 |
| #define LCDIF_DEBUG1_V_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_V_DATA_COUNT_MASK) |
| #define LCDIF_DEBUG1_H_DATA_COUNT_MASK 0xFFFF0000u |
| #define LCDIF_DEBUG1_H_DATA_COUNT_SHIFT 16 |
| #define LCDIF_DEBUG1_H_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_H_DATA_COUNT_MASK) |
| /* DEBUG2 Bit Fields */ |
| #define LCDIF_DEBUG2_MST_ADDRESS_MASK 0xFFFFFFFFu |
| #define LCDIF_DEBUG2_MST_ADDRESS_SHIFT 0 |
| #define LCDIF_DEBUG2_MST_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG2_MST_ADDRESS_SHIFT))&LCDIF_DEBUG2_MST_ADDRESS_MASK) |
| /* THRES Bit Fields */ |
| #define LCDIF_THRES_PANIC_MASK 0x1FFu |
| #define LCDIF_THRES_PANIC_SHIFT 0 |
| #define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_PANIC_SHIFT))&LCDIF_THRES_PANIC_MASK) |
| #define LCDIF_THRES_RSRVD1_MASK 0xFE00u |
| #define LCDIF_THRES_RSRVD1_SHIFT 9 |
| #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD1_SHIFT))&LCDIF_THRES_RSRVD1_MASK) |
| #define LCDIF_THRES_FASTCLOCK_MASK 0x1FF0000u |
| #define LCDIF_THRES_FASTCLOCK_SHIFT 16 |
| #define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_FASTCLOCK_SHIFT))&LCDIF_THRES_FASTCLOCK_MASK) |
| #define LCDIF_THRES_RSRVD2_MASK 0xFE000000u |
| #define LCDIF_THRES_RSRVD2_SHIFT 25 |
| #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD2_SHIFT))&LCDIF_THRES_RSRVD2_MASK) |
| /* AS_CTRL Bit Fields */ |
| #define LCDIF_AS_CTRL_AS_ENABLE_MASK 0x1u |
| #define LCDIF_AS_CTRL_AS_ENABLE_SHIFT 0 |
| #define LCDIF_AS_CTRL_ALPHA_CTRL_MASK 0x6u |
| #define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT 1 |
| #define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT))&LCDIF_AS_CTRL_ALPHA_CTRL_MASK) |
| #define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u |
| #define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 |
| #define LCDIF_AS_CTRL_FORMAT_MASK 0xF0u |
| #define LCDIF_AS_CTRL_FORMAT_SHIFT 4 |
| #define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_FORMAT_SHIFT))&LCDIF_AS_CTRL_FORMAT_MASK) |
| #define LCDIF_AS_CTRL_ALPHA_MASK 0xFF00u |
| #define LCDIF_AS_CTRL_ALPHA_SHIFT 8 |
| #define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_SHIFT))&LCDIF_AS_CTRL_ALPHA_MASK) |
| #define LCDIF_AS_CTRL_ROP_MASK 0xF0000u |
| #define LCDIF_AS_CTRL_ROP_SHIFT 16 |
| #define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ROP_SHIFT))&LCDIF_AS_CTRL_ROP_MASK) |
| #define LCDIF_AS_CTRL_ALPHA_INVERT_MASK 0x100000u |
| #define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT 20 |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK 0x600000u |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT 21 |
| #define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) |
| #define LCDIF_AS_CTRL_PS_DISABLE_MASK 0x800000u |
| #define LCDIF_AS_CTRL_PS_DISABLE_SHIFT 23 |
| #define LCDIF_AS_CTRL_RVDS1_MASK 0x7000000u |
| #define LCDIF_AS_CTRL_RVDS1_SHIFT 24 |
| #define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_RVDS1_SHIFT))&LCDIF_AS_CTRL_RVDS1_MASK) |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK 0x8000000u |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT 27 |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK 0x10000000u |
| #define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT 28 |
| #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK 0x20000000u |
| #define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT 29 |
| #define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK 0x40000000u |
| #define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT 30 |
| #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK 0x80000000u |
| #define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT 31 |
| /* AS_BUF Bit Fields */ |
| #define LCDIF_AS_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define LCDIF_AS_BUF_ADDR_SHIFT 0 |
| #define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_BUF_ADDR_SHIFT))&LCDIF_AS_BUF_ADDR_MASK) |
| /* AS_NEXT_BUF Bit Fields */ |
| #define LCDIF_AS_NEXT_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define LCDIF_AS_NEXT_BUF_ADDR_SHIFT 0 |
| #define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_NEXT_BUF_ADDR_SHIFT))&LCDIF_AS_NEXT_BUF_ADDR_MASK) |
| /* AS_CLRKEYLOW Bit Fields */ |
| #define LCDIF_AS_CLRKEYLOW_PIXEL_MASK 0xFFFFFFu |
| #define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT 0 |
| #define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT))&LCDIF_AS_CLRKEYLOW_PIXEL_MASK) |
| #define LCDIF_AS_CLRKEYLOW_RSVD1_MASK 0xFF000000u |
| #define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT 24 |
| #define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT))&LCDIF_AS_CLRKEYLOW_RSVD1_MASK) |
| /* AS_CLRKEYHIGH Bit Fields */ |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK 0xFFFFFFu |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT 0 |
| #define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT))&LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK 0xFF000000u |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT 24 |
| #define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT))&LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) |
| /* SYNC_DELAY Bit Fields */ |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK 0xFFFFu |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT 0 |
| #define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK 0xFFFF0000u |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT 16 |
| #define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) |
| /* DEBUG3 Bit Fields */ |
| #define LCDIF_DEBUG3_MST_WORDS_MASK 0xFu |
| #define LCDIF_DEBUG3_MST_WORDS_SHIFT 0 |
| #define LCDIF_DEBUG3_MST_WORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_WORDS_SHIFT))&LCDIF_DEBUG3_MST_WORDS_MASK) |
| #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK 0x1F0u |
| #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT 4 |
| #define LCDIF_DEBUG3_MST_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK) |
| #define LCDIF_DEBUG3_MST_AVALID_MASK 0x200u |
| #define LCDIF_DEBUG3_MST_AVALID_SHIFT 9 |
| #define LCDIF_DEBUG3_CUR_REQ_STATE_MASK 0xC00u |
| #define LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT 10 |
| #define LCDIF_DEBUG3_CUR_REQ_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG3_CUR_REQ_STATE_MASK) |
| #define LCDIF_DEBUG3_RSVD0_MASK 0xFFFFF000u |
| #define LCDIF_DEBUG3_RSVD0_SHIFT 12 |
| #define LCDIF_DEBUG3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_RSVD0_SHIFT))&LCDIF_DEBUG3_RSVD0_MASK) |
| /* DEBUG4 Bit Fields */ |
| #define LCDIF_DEBUG4_V_DATA_COUNT_MASK 0xFFFFu |
| #define LCDIF_DEBUG4_V_DATA_COUNT_SHIFT 0 |
| #define LCDIF_DEBUG4_V_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_V_DATA_COUNT_MASK) |
| #define LCDIF_DEBUG4_H_DATA_COUNT_MASK 0xFFFF0000u |
| #define LCDIF_DEBUG4_H_DATA_COUNT_SHIFT 16 |
| #define LCDIF_DEBUG4_H_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_H_DATA_COUNT_MASK) |
| /* DEBUG5 Bit Fields */ |
| #define LCDIF_DEBUG5_MST_ADDRESS_MASK 0xFFFFFFFFu |
| #define LCDIF_DEBUG5_MST_ADDRESS_SHIFT 0 |
| #define LCDIF_DEBUG5_MST_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG5_MST_ADDRESS_SHIFT))&LCDIF_DEBUG5_MST_ADDRESS_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Register_Masks */ |
| |
| /* LCDIF - Peripheral instance base addresses */ |
| /** Peripheral LCDIF1 base address */ |
| #define LCDIF1_BASE (0x42220000u) |
| /** Peripheral LCDIF1 base pointer */ |
| #define LCDIF1 ((LCDIF_Type *)LCDIF1_BASE) |
| #define LCDIF1_BASE_PTR (LCDIF1) |
| /** Peripheral LCDIF2 base address */ |
| #define LCDIF2_BASE (0x42224000u) |
| /** Peripheral LCDIF2 base pointer */ |
| #define LCDIF2 ((LCDIF_Type *)LCDIF2_BASE) |
| #define LCDIF2_BASE_PTR (LCDIF2) |
| /** Array initializer of LCDIF peripheral base addresses */ |
| #define LCDIF_BASE_ADDRS { LCDIF1_BASE, LCDIF2_BASE } |
| /** Array initializer of LCDIF peripheral base pointers */ |
| #define LCDIF_BASE_PTRS { LCDIF1, LCDIF2 } |
| /** Interrupt vectors for the LCDIF peripheral type */ |
| #define LCDIF_IRQS { LCDIF1_IRQn, LCDIF2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- LCDIF - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros |
| * @{ |
| */ |
| |
| /* LCDIF - Register instance definitions */ |
| /* LCDIF1 */ |
| #define LCDIF1_RL LCDIF_RL_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_RL_SET LCDIF_RL_SET_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_RL_CLR LCDIF_RL_CLR_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_RL_TOG LCDIF_RL_TOG_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL1 LCDIF_CTRL1_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL1_SET LCDIF_CTRL1_SET_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL1_CLR LCDIF_CTRL1_CLR_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL1_TOG LCDIF_CTRL1_TOG_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL2 LCDIF_CTRL2_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL2_SET LCDIF_CTRL2_SET_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL2_CLR LCDIF_CTRL2_CLR_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CTRL2_TOG LCDIF_CTRL2_TOG_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_TRANSFER_COUNT LCDIF_TRANSFER_COUNT_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CUR_BUF LCDIF_CUR_BUF_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_NEXT_BUF LCDIF_NEXT_BUF_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_TIMING LCDIF_TIMING_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL0 LCDIF_VDCTRL0_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL0_SET LCDIF_VDCTRL0_SET_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL0_CLR LCDIF_VDCTRL0_CLR_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL0_TOG LCDIF_VDCTRL0_TOG_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL1 LCDIF_VDCTRL1_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL2 LCDIF_VDCTRL2_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL3 LCDIF_VDCTRL3_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VDCTRL4 LCDIF_VDCTRL4_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DVICTRL0 LCDIF_DVICTRL0_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DVICTRL1 LCDIF_DVICTRL1_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DVICTRL2 LCDIF_DVICTRL2_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DVICTRL3 LCDIF_DVICTRL3_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DVICTRL4 LCDIF_DVICTRL4_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_COEFF0 LCDIF_CSC_COEFF0_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_COEFF1 LCDIF_CSC_COEFF1_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_COEFF2 LCDIF_CSC_COEFF2_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_COEFF3 LCDIF_CSC_COEFF3_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_COEFF4 LCDIF_CSC_COEFF4_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_OFFSET LCDIF_CSC_OFFSET_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CSC_LIMIT LCDIF_CSC_LIMIT_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DATA LCDIF_DATA_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_BM_ERROR_STAT LCDIF_BM_ERROR_STAT_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_CRC_STAT LCDIF_CRC_STAT_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_STAT LCDIF_STAT_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_VERSION LCDIF_VERSION_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG0 LCDIF_DEBUG0_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG1 LCDIF_DEBUG1_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG2 LCDIF_DEBUG2_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_THRES LCDIF_THRES_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_AS_CTRL LCDIF_AS_CTRL_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_AS_BUF LCDIF_AS_BUF_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_AS_NEXT_BUF LCDIF_AS_NEXT_BUF_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_AS_CLRKEYLOW LCDIF_AS_CLRKEYLOW_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_AS_CLRKEYHIGH LCDIF_AS_CLRKEYHIGH_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_SYNC_DELAY LCDIF_SYNC_DELAY_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG3 LCDIF_DEBUG3_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG4 LCDIF_DEBUG4_REG(LCDIF1_BASE_PTR) |
| #define LCDIF1_DEBUG5 LCDIF_DEBUG5_REG(LCDIF1_BASE_PTR) |
| /* LCDIF2 */ |
| #define LCDIF2_RL LCDIF_RL_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_RL_SET LCDIF_RL_SET_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_RL_CLR LCDIF_RL_CLR_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_RL_TOG LCDIF_RL_TOG_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL1 LCDIF_CTRL1_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL1_SET LCDIF_CTRL1_SET_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL1_CLR LCDIF_CTRL1_CLR_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL1_TOG LCDIF_CTRL1_TOG_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL2 LCDIF_CTRL2_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL2_SET LCDIF_CTRL2_SET_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL2_CLR LCDIF_CTRL2_CLR_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CTRL2_TOG LCDIF_CTRL2_TOG_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_TRANSFER_COUNT LCDIF_TRANSFER_COUNT_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CUR_BUF LCDIF_CUR_BUF_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_NEXT_BUF LCDIF_NEXT_BUF_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_TIMING LCDIF_TIMING_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL0 LCDIF_VDCTRL0_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL0_SET LCDIF_VDCTRL0_SET_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL0_CLR LCDIF_VDCTRL0_CLR_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL0_TOG LCDIF_VDCTRL0_TOG_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL1 LCDIF_VDCTRL1_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL2 LCDIF_VDCTRL2_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL3 LCDIF_VDCTRL3_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VDCTRL4 LCDIF_VDCTRL4_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DVICTRL0 LCDIF_DVICTRL0_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DVICTRL1 LCDIF_DVICTRL1_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DVICTRL2 LCDIF_DVICTRL2_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DVICTRL3 LCDIF_DVICTRL3_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DVICTRL4 LCDIF_DVICTRL4_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_COEFF0 LCDIF_CSC_COEFF0_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_COEFF1 LCDIF_CSC_COEFF1_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_COEFF2 LCDIF_CSC_COEFF2_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_COEFF3 LCDIF_CSC_COEFF3_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_COEFF4 LCDIF_CSC_COEFF4_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_OFFSET LCDIF_CSC_OFFSET_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CSC_LIMIT LCDIF_CSC_LIMIT_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DATA LCDIF_DATA_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_BM_ERROR_STAT LCDIF_BM_ERROR_STAT_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_CRC_STAT LCDIF_CRC_STAT_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_STAT LCDIF_STAT_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_VERSION LCDIF_VERSION_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG0 LCDIF_DEBUG0_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG1 LCDIF_DEBUG1_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG2 LCDIF_DEBUG2_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_THRES LCDIF_THRES_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_AS_CTRL LCDIF_AS_CTRL_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_AS_BUF LCDIF_AS_BUF_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_AS_NEXT_BUF LCDIF_AS_NEXT_BUF_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_AS_CLRKEYLOW LCDIF_AS_CLRKEYLOW_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_AS_CLRKEYHIGH LCDIF_AS_CLRKEYHIGH_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_SYNC_DELAY LCDIF_SYNC_DELAY_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG3 LCDIF_DEBUG3_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG4 LCDIF_DEBUG4_REG(LCDIF2_BASE_PTR) |
| #define LCDIF2_DEBUG5 LCDIF_DEBUG5_REG(LCDIF2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group LCDIF_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- LDB Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LDB_Peripheral_Access_Layer LDB Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LDB - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< LDB Control Register, offset: 0x0 */ |
| } LDB_Type, *LDB_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LDB - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LDB_Register_Accessor_Macros LDB - Register accessor macros |
| * @{ |
| */ |
| |
| /* LDB - Register accessors */ |
| #define LDB_CTRL_REG(base) ((base)->CTRL) |
| |
| /*! |
| * @} |
| */ /* end of group LDB_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- LDB Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LDB_Register_Masks LDB Register Masks |
| * @{ |
| */ |
| |
| /* CTRL Bit Fields */ |
| #define LDB_CTRL_ch0_mode_MASK 0x3u |
| #define LDB_CTRL_ch0_mode_SHIFT 0 |
| #define LDB_CTRL_ch0_mode(x) (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_ch0_mode_SHIFT))&LDB_CTRL_ch0_mode_MASK) |
| #define LDB_CTRL_data_width_ch0_MASK 0x20u |
| #define LDB_CTRL_data_width_ch0_SHIFT 5 |
| #define LDB_CTRL_bit_mapping_ch0_MASK 0x40u |
| #define LDB_CTRL_bit_mapping_ch0_SHIFT 6 |
| #define LDB_CTRL_lcdif1_vs_polarity_MASK 0x200u |
| #define LDB_CTRL_lcdif1_vs_polarity_SHIFT 9 |
| #define LDB_CTRL_lvds_clk_shift_MASK 0x70000u |
| #define LDB_CTRL_lvds_clk_shift_SHIFT 16 |
| #define LDB_CTRL_lvds_clk_shift(x) (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_lvds_clk_shift_SHIFT))&LDB_CTRL_lvds_clk_shift_MASK) |
| #define LDB_CTRL_counter_reset_val_MASK 0x300000u |
| #define LDB_CTRL_counter_reset_val_SHIFT 20 |
| #define LDB_CTRL_counter_reset_val(x) (((uint32_t)(((uint32_t)(x))<<LDB_CTRL_counter_reset_val_SHIFT))&LDB_CTRL_counter_reset_val_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group LDB_Register_Masks */ |
| |
| /* LDB - Peripheral instance base addresses */ |
| /** Peripheral LDB base address */ |
| #define LDB_BASE (0x420E0014u) |
| /** Peripheral LDB base pointer */ |
| #define LDB ((LDB_Type *)LDB_BASE) |
| #define LDB_BASE_PTR (LDB) |
| /** Array initializer of LDB peripheral base addresses */ |
| #define LDB_BASE_ADDRS { LDB_BASE } |
| /** Array initializer of LDB peripheral base pointers */ |
| #define LDB_BASE_PTRS { LDB } |
| |
| /* ---------------------------------------------------------------------------- |
| -- LDB - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LDB_Register_Accessor_Macros LDB - Register accessor macros |
| * @{ |
| */ |
| |
| /* LDB - Register instance definitions */ |
| /* LDB */ |
| #define LDB_CTRL LDB_CTRL_REG(LDB_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group LDB_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group LDB_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- LMEM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** LMEM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ |
| __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ |
| __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ |
| __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ |
| uint8_t RESERVED_0[2032]; |
| __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ |
| __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ |
| __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ |
| __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ |
| } LMEM_Type, *LMEM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- LMEM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros |
| * @{ |
| */ |
| |
| /* LMEM - Register accessors */ |
| #define LMEM_PCCCR_REG(base) ((base)->PCCCR) |
| #define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) |
| #define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) |
| #define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) |
| #define LMEM_PSCCR_REG(base) ((base)->PSCCR) |
| #define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) |
| #define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) |
| #define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Register_Accessor_Macros */ |
| /* ---------------------------------------------------------------------------- |
| -- LMEM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Register_Masks LMEM Register Masks |
| * @{ |
| */ |
| |
| /* PCCCR Bit Fields */ |
| #define LMEM_PCCCR_ENCACHE_MASK 0x1u |
| #define LMEM_PCCCR_ENCACHE_SHIFT 0 |
| #define LMEM_PCCCR_ENWRBUF_MASK 0x2u |
| #define LMEM_PCCCR_ENWRBUF_SHIFT 1 |
| #define LMEM_PCCCR_PCCR2_MASK 0x4u |
| #define LMEM_PCCCR_PCCR2_SHIFT 2 |
| #define LMEM_PCCCR_PCCR3_MASK 0x8u |
| #define LMEM_PCCCR_PCCR3_SHIFT 3 |
| #define LMEM_PCCCR_INVW0_MASK 0x1000000u |
| #define LMEM_PCCCR_INVW0_SHIFT 24 |
| #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u |
| #define LMEM_PCCCR_PUSHW0_SHIFT 25 |
| #define LMEM_PCCCR_INVW1_MASK 0x4000000u |
| #define LMEM_PCCCR_INVW1_SHIFT 26 |
| #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u |
| #define LMEM_PCCCR_PUSHW1_SHIFT 27 |
| #define LMEM_PCCCR_GO_MASK 0x80000000u |
| #define LMEM_PCCCR_GO_SHIFT 31 |
| /* PCCLCR Bit Fields */ |
| #define LMEM_PCCLCR_LGO_MASK 0x1u |
| #define LMEM_PCCLCR_LGO_SHIFT 0 |
| #define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu |
| #define LMEM_PCCLCR_CACHEADDR_SHIFT 2 |
| #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK) |
| #define LMEM_PCCLCR_WSEL_MASK 0x4000u |
| #define LMEM_PCCLCR_WSEL_SHIFT 14 |
| #define LMEM_PCCLCR_TDSEL_MASK 0x10000u |
| #define LMEM_PCCLCR_TDSEL_SHIFT 16 |
| #define LMEM_PCCLCR_LCIVB_MASK 0x100000u |
| #define LMEM_PCCLCR_LCIVB_SHIFT 20 |
| #define LMEM_PCCLCR_LCIMB_MASK 0x200000u |
| #define LMEM_PCCLCR_LCIMB_SHIFT 21 |
| #define LMEM_PCCLCR_LCWAY_MASK 0x400000u |
| #define LMEM_PCCLCR_LCWAY_SHIFT 22 |
| #define LMEM_PCCLCR_LCMD_MASK 0x3000000u |
| #define LMEM_PCCLCR_LCMD_SHIFT 24 |
| #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK) |
| #define LMEM_PCCLCR_LADSEL_MASK 0x4000000u |
| #define LMEM_PCCLCR_LADSEL_SHIFT 26 |
| #define LMEM_PCCLCR_LACC_MASK 0x8000000u |
| #define LMEM_PCCLCR_LACC_SHIFT 27 |
| /* PCCSAR Bit Fields */ |
| #define LMEM_PCCSAR_LGO_MASK 0x1u |
| #define LMEM_PCCSAR_LGO_SHIFT 0 |
| #define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu |
| #define LMEM_PCCSAR_PHYADDR_SHIFT 2 |
| #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK) |
| /* PCCCVR Bit Fields */ |
| #define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu |
| #define LMEM_PCCCVR_DATA_SHIFT 0 |
| #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK) |
| /* PSCCR Bit Fields */ |
| #define LMEM_PSCCR_ENCACHE_MASK 0x1u |
| #define LMEM_PSCCR_ENCACHE_SHIFT 0 |
| #define LMEM_PSCCR_ENWRBUF_MASK 0x2u |
| #define LMEM_PSCCR_ENWRBUF_SHIFT 1 |
| #define LMEM_PSCCR_INVW0_MASK 0x1000000u |
| #define LMEM_PSCCR_INVW0_SHIFT 24 |
| #define LMEM_PSCCR_PUSHW0_MASK 0x2000000u |
| #define LMEM_PSCCR_PUSHW0_SHIFT 25 |
| #define LMEM_PSCCR_INVW1_MASK 0x4000000u |
| #define LMEM_PSCCR_INVW1_SHIFT 26 |
| #define LMEM_PSCCR_PUSHW1_MASK 0x8000000u |
| #define LMEM_PSCCR_PUSHW1_SHIFT 27 |
| #define LMEM_PSCCR_GO_MASK 0x80000000u |
| #define LMEM_PSCCR_GO_SHIFT 31 |
| /* PSCLCR Bit Fields */ |
| #define LMEM_PSCLCR_LGO_MASK 0x1u |
| #define LMEM_PSCLCR_LGO_SHIFT 0 |
| #define LMEM_PSCLCR_CACHEADDR_MASK 0x1FFCu |
| #define LMEM_PSCLCR_CACHEADDR_SHIFT 2 |
| #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK) |
| #define LMEM_PSCLCR_WSEL_MASK 0x4000u |
| #define LMEM_PSCLCR_WSEL_SHIFT 14 |
| #define LMEM_PSCLCR_TDSEL_MASK 0x10000u |
| #define LMEM_PSCLCR_TDSEL_SHIFT 16 |
| #define LMEM_PSCLCR_LCIVB_MASK 0x100000u |
| #define LMEM_PSCLCR_LCIVB_SHIFT 20 |
| #define LMEM_PSCLCR_LCIMB_MASK 0x200000u |
| #define LMEM_PSCLCR_LCIMB_SHIFT 21 |
| #define LMEM_PSCLCR_LCWAY_MASK 0x400000u |
| #define LMEM_PSCLCR_LCWAY_SHIFT 22 |
| #define LMEM_PSCLCR_LCMD_MASK 0x3000000u |
| #define LMEM_PSCLCR_LCMD_SHIFT 24 |
| #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK) |
| #define LMEM_PSCLCR_LADSEL_MASK 0x4000000u |
| #define LMEM_PSCLCR_LADSEL_SHIFT 26 |
| #define LMEM_PSCLCR_LACC_MASK 0x8000000u |
| #define LMEM_PSCLCR_LACC_SHIFT 27 |
| /* PSCSAR Bit Fields */ |
| #define LMEM_PSCSAR_LGO_MASK 0x1u |
| #define LMEM_PSCSAR_LGO_SHIFT 0 |
| #define LMEM_PSCSAR_PHYADDR_MASK 0xFFFFFFFCu |
| #define LMEM_PSCSAR_PHYADDR_SHIFT 2 |
| #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK) |
| /* PSCCVR Bit Fields */ |
| #define LMEM_PSCCVR_DATA_MASK 0xFFFFFFFFu |
| #define LMEM_PSCCVR_DATA_SHIFT 0 |
| #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Register_Masks */ |
| |
| /* LMEM - Peripheral instance base addresses */ |
| /** Peripheral LMEM base address */ |
| #define LMEM_BASE (0xE0082000u) |
| /** Peripheral LMEM base pointer */ |
| #define LMEM ((LMEM_Type *)LMEM_BASE) |
| #define LMEM_BASE_PTR (LMEM) |
| /** Array initializer of LMEM peripheral base addresses */ |
| #define LMEM_BASE_ADDRS { LMEM_BASE } |
| /** Array initializer of LMEM peripheral base pointers */ |
| #define LMEM_BASE_PTRS { LMEM } |
| |
| /* ---------------------------------------------------------------------------- |
| -- LMEM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros |
| * @{ |
| */ |
| |
| /* LMEM - Register instance definitions */ |
| /* LMEM */ |
| #define LMEM_PCCCR LMEM_PCCCR_REG(LMEM_BASE_PTR) |
| #define LMEM_PCCLCR LMEM_PCCLCR_REG(LMEM_BASE_PTR) |
| #define LMEM_PCCSAR LMEM_PCCSAR_REG(LMEM_BASE_PTR) |
| #define LMEM_PCCCVR LMEM_PCCCVR_REG(LMEM_BASE_PTR) |
| #define LMEM_PSCCR LMEM_PSCCR_REG(LMEM_BASE_PTR) |
| #define LMEM_PSCLCR LMEM_PSCLCR_REG(LMEM_BASE_PTR) |
| #define LMEM_PSCSAR LMEM_PSCSAR_REG(LMEM_BASE_PTR) |
| #define LMEM_PSCCVR LMEM_PSCCVR_REG(LMEM_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group LMEM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MCM - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[8]; |
| __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ |
| __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ |
| uint8_t RESERVED_1[20]; |
| __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ |
| __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ |
| __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ |
| } MCM_Type, *MCM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros |
| * @{ |
| */ |
| |
| /* MCM - Register accessors */ |
| #define MCM_PLASC_REG(base) ((base)->PLASC) |
| #define MCM_PLAMC_REG(base) ((base)->PLAMC) |
| #define MCM_FADR_REG(base) ((base)->FADR) |
| #define MCM_FATR_REG(base) ((base)->FATR) |
| #define MCM_FDR_REG(base) ((base)->FDR) |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Register_Masks MCM Register Masks |
| * @{ |
| */ |
| |
| /* PLASC Bit Fields */ |
| #define MCM_PLASC_ASC_MASK 0xFFu |
| #define MCM_PLASC_ASC_SHIFT 0 |
| #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) |
| /* PLAMC Bit Fields */ |
| #define MCM_PLAMC_AMC_MASK 0xFFu |
| #define MCM_PLAMC_AMC_SHIFT 0 |
| #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) |
| /* FADR Bit Fields */ |
| #define MCM_FADR_ADDRESS_MASK 0xFFFFFFFFu |
| #define MCM_FADR_ADDRESS_SHIFT 0 |
| #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<MCM_FADR_ADDRESS_SHIFT))&MCM_FADR_ADDRESS_MASK) |
| /* FATR Bit Fields */ |
| #define MCM_FATR_BEDA_MASK 0x1u |
| #define MCM_FATR_BEDA_SHIFT 0 |
| #define MCM_FATR_BEMD_MASK 0x2u |
| #define MCM_FATR_BEMD_SHIFT 1 |
| #define MCM_FATR_BESZ_MASK 0x30u |
| #define MCM_FATR_BESZ_SHIFT 4 |
| #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK) |
| #define MCM_FATR_BEWT_MASK 0x80u |
| #define MCM_FATR_BEWT_SHIFT 7 |
| #define MCM_FATR_BEMN_MASK 0xF00u |
| #define MCM_FATR_BEMN_SHIFT 8 |
| #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK) |
| #define MCM_FATR_BEOVR_MASK 0x80000000u |
| #define MCM_FATR_BEOVR_SHIFT 31 |
| /* FDR Bit Fields */ |
| #define MCM_FDR_DATA_MASK 0xFFFFFFFFu |
| #define MCM_FDR_DATA_SHIFT 0 |
| #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Register_Masks */ |
| |
| /* MCM - Peripheral instance base addresses */ |
| /** Peripheral MCM base address */ |
| #define MCM_BASE (0xE0000000u) |
| /** Peripheral MCM base pointer */ |
| #define MCM ((MCM_Type *)MCM_BASE) |
| #define MCM_BASE_PTR (MCM) |
| /** Array initializer of MCM peripheral base addresses */ |
| #define MCM_BASE_ADDRS { MCM_BASE } |
| /** Array initializer of MCM peripheral base pointers */ |
| #define MCM_BASE_PTRS { MCM } |
| |
| /* ---------------------------------------------------------------------------- |
| -- MCM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros |
| * @{ |
| */ |
| |
| /* MCM - Register instance definitions */ |
| /* MCM */ |
| #define MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR) |
| #define MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR) |
| #define MCM_FADR MCM_FADR_REG(MCM_BASE_PTR) |
| #define MCM_FATR MCM_FATR_REG(MCM_BASE_PTR) |
| #define MCM_FDR MCM_FDR_REG(MCM_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group MCM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MLB Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MLB_Peripheral_Access_Layer MLB Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MLB - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MLBC0; /**< MediaLB Control 0 Register, offset: 0x0 */ |
| uint8_t RESERVED_0[8]; |
| union { /* offset: 0xC */ |
| __I uint32_t MS0; /**< MediaLB Channel Status 0 Register,offset: 0xC */ |
| struct { /* offset: 0xD */ |
| uint8_t RESERVED_0[1]; |
| __I uint32_t MLBPC2; /**< MediaLB 6-pin Control 2 Register,offset: 0xD */ |
| } MLBPC2; |
| }; |
| uint8_t RESERVED_1[3]; |
| __I uint32_t MS1; /**< MediaLB Channel Status1 Register, offset: 0x14 */ |
| uint8_t RESERVED_2[8]; |
| __I uint32_t MSS; /**< MediaLB System Status Register, offset: 0x20 */ |
| __I uint32_t MSD; /**< MediaLB System Data Register, offset: 0x24 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t MIEN; /**< MediaLB Interrupt Enable Register, offset: 0x2C */ |
| uint8_t RESERVED_4[12]; |
| __I uint32_t MLBC1; /**< MediaLB Control 1 Register, offset: 0x3C */ |
| uint8_t RESERVED_5[64]; |
| __IO uint32_t HCTL; /**< HBI Control Register, offset: 0x80 */ |
| uint8_t RESERVED_6[4]; |
| __IO uint32_t HCMR0; /**< HBI Channel Mask 0 Register, offset: 0x88 */ |
| __IO uint32_t HCMR1; /**< HBI Channel Mask 1 Register, offset: 0x8C */ |
| __I uint32_t HCER0; /**< HBI Channel Error 0 Register, offset: 0x90 */ |
| __I uint32_t HCER1; /**< HBI Channel Error 1 Register, offset: 0x94 */ |
| __I uint32_t HCBR0; /**< HBI Channel Busy 0 Register, offset: 0x98 */ |
| __I uint32_t HCBR1; /**< HBI Channel Busy 1 Register, offset: 0x9C */ |
| uint8_t RESERVED_7[32]; |
| __IO uint32_t MDAT0; /**< MIF Data 0 Register, offset: 0xC0 */ |
| __IO uint32_t MDAT1; /**< MIF Data 1 Register, offset: 0xC4 */ |
| __IO uint32_t MDAT2; /**< MIF Data 2 Register, offset: 0xC8 */ |
| __IO uint32_t MDAT3; /**< MIF Data 3 Register, offset: 0xCC */ |
| __IO uint32_t MDWE0; /**< MIF Data Write Enable 0 Register, offset: 0xD0 */ |
| __IO uint32_t MDWE1; /**< MIF Data Write Enable 1 Register, offset: 0xD4 */ |
| __IO uint32_t MDWE2; /**< MIF Data Write Enable 2 Register, offset: 0xD8 */ |
| __IO uint32_t MDWE3; /**< MIF Data Write Enable 3 Register, offset: 0xDC */ |
| __I uint32_t MCTL; /**< MIF Control Register, offset: 0xE0 */ |
| __IO uint32_t MADR; /**< MIF Address Register, offset: 0xE4 */ |
| uint8_t RESERVED_8[728]; |
| __IO uint32_t ACTL; /**< AHB Control Register, offset: 0x3C0 */ |
| uint8_t RESERVED_9[12]; |
| __I uint32_t ACSR0; /**< AHB Channel Status 0 Register, offset: 0x3D0 */ |
| __I uint32_t ACSR1; /**< AHB Channel Status 1 Register, offset: 0x3D4 */ |
| __IO uint32_t ACMR0; /**< AHB Channel Mask 0 Register, offset: 0x3D8 */ |
| __IO uint32_t ACMR1; /**< AHB Channel Mask 1 Register, offset: 0x3DC */ |
| } MLB_Type, *MLB_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MLB - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MLB_Register_Accessor_Macros MLB - Register accessor macros |
| * @{ |
| */ |
| |
| /* MLB - Register accessors */ |
| #define MLB_MLBC0_REG(base) ((base)->MLBC0) |
| #define MLB_MS0_REG(base) ((base)->MS0) |
| #define MLB_MLBPC2_REG(base) ((base)->MLBPC2.MLBPC2) |
| #define MLB_MS1_REG(base) ((base)->MS1) |
| #define MLB_MSS_REG(base) ((base)->MSS) |
| #define MLB_MSD_REG(base) ((base)->MSD) |
| #define MLB_MIEN_REG(base) ((base)->MIEN) |
| #define MLB_MLBC1_REG(base) ((base)->MLBC1) |
| #define MLB_HCTL_REG(base) ((base)->HCTL) |
| #define MLB_HCMR0_REG(base) ((base)->HCMR0) |
| #define MLB_HCMR1_REG(base) ((base)->HCMR1) |
| #define MLB_HCER0_REG(base) ((base)->HCER0) |
| #define MLB_HCER1_REG(base) ((base)->HCER1) |
| #define MLB_HCBR0_REG(base) ((base)->HCBR0) |
| #define MLB_HCBR1_REG(base) ((base)->HCBR1) |
| #define MLB_MDAT0_REG(base) ((base)->MDAT0) |
| #define MLB_MDAT1_REG(base) ((base)->MDAT1) |
| #define MLB_MDAT2_REG(base) ((base)->MDAT2) |
| #define MLB_MDAT3_REG(base) ((base)->MDAT3) |
| #define MLB_MDWE0_REG(base) ((base)->MDWE0) |
| #define MLB_MDWE1_REG(base) ((base)->MDWE1) |
| #define MLB_MDWE2_REG(base) ((base)->MDWE2) |
| #define MLB_MDWE3_REG(base) ((base)->MDWE3) |
| #define MLB_MCTL_REG(base) ((base)->MCTL) |
| #define MLB_MADR_REG(base) ((base)->MADR) |
| #define MLB_ACTL_REG(base) ((base)->ACTL) |
| #define MLB_ACSR0_REG(base) ((base)->ACSR0) |
| #define MLB_ACSR1_REG(base) ((base)->ACSR1) |
| #define MLB_ACMR0_REG(base) ((base)->ACMR0) |
| #define MLB_ACMR1_REG(base) ((base)->ACMR1) |
| |
| /*! |
| * @} |
| */ /* end of group MLB_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MLB Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MLB_Register_Masks MLB Register Masks |
| * @{ |
| */ |
| |
| /* MLBC0 Bit Fields */ |
| #define MLB_MLBC0_MLBEN_MASK 0x1u |
| #define MLB_MLBC0_MLBEN_SHIFT 0 |
| #define MLB_MLBC0_MLBCLK_2_0_MASK 0x1Cu |
| #define MLB_MLBC0_MLBCLK_2_0_SHIFT 2 |
| #define MLB_MLBC0_MLBCLK_2_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MLBC0_MLBCLK_2_0_SHIFT))&MLB_MLBC0_MLBCLK_2_0_MASK) |
| #define MLB_MLBC0_MLBLK_MASK 0x80u |
| #define MLB_MLBC0_MLBLK_SHIFT 7 |
| #define MLB_MLBC0_ASYRETRY_MASK 0x1000u |
| #define MLB_MLBC0_ASYRETRY_SHIFT 12 |
| #define MLB_MLBC0_CTLRETRY_MASK 0x4000u |
| #define MLB_MLBC0_CTLRETRY_SHIFT 14 |
| #define MLB_MLBC0_FCNT_MASK 0x38000u |
| #define MLB_MLBC0_FCNT_SHIFT 15 |
| #define MLB_MLBC0_FCNT(x) (((uint32_t)(((uint32_t)(x))<<MLB_MLBC0_FCNT_SHIFT))&MLB_MLBC0_FCNT_MASK) |
| /* MS0 Bit Fields */ |
| #define MLB_MS0_MCS_31_0_MASK 0xFFFFFFFFu |
| #define MLB_MS0_MCS_31_0_SHIFT 0 |
| #define MLB_MS0_MCS_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MS0_MCS_31_0_SHIFT))&MLB_MS0_MCS_31_0_MASK) |
| /* MLBPC2 Bit Fields */ |
| #define MLB_MLBPC2_SDOPC_MASK 0x1u |
| #define MLB_MLBPC2_SDOPC_SHIFT 0 |
| #define MLB_MLBPC2_MORCD_MASK 0x7F00u |
| #define MLB_MLBPC2_MORCD_SHIFT 8 |
| #define MLB_MLBPC2_MORCD(x) (((uint32_t)(((uint32_t)(x))<<MLB_MLBPC2_MORCD_SHIFT))&MLB_MLBPC2_MORCD_MASK) |
| #define MLB_MLBPC2_MORCE_MASK 0x8000u |
| #define MLB_MLBPC2_MORCE_SHIFT 15 |
| /* MS1 Bit Fields */ |
| #define MLB_MS1_MCS_63_32_MASK 0xFFFFFFFFu |
| #define MLB_MS1_MCS_63_32_SHIFT 0 |
| #define MLB_MS1_MCS_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_MS1_MCS_63_32_SHIFT))&MLB_MS1_MCS_63_32_MASK) |
| /* MSS Bit Fields */ |
| #define MLB_MSS_RSTSYSCMD_MASK 0x1u |
| #define MLB_MSS_RSTSYSCMD_SHIFT 0 |
| #define MLB_MSS_LKSYSCMD_MASK 0x2u |
| #define MLB_MSS_LKSYSCMD_SHIFT 1 |
| #define MLB_MSS_ULKSYSCMD_MASK 0x4u |
| #define MLB_MSS_ULKSYSCMD_SHIFT 2 |
| #define MLB_MSS_CSSYSCMD_MASK 0x8u |
| #define MLB_MSS_CSSYSCMD_SHIFT 3 |
| #define MLB_MSS_SWSYSCMD_MASK 0x10u |
| #define MLB_MSS_SWSYSCMD_SHIFT 4 |
| #define MLB_MSS_SERVREQ_MASK 0x20u |
| #define MLB_MSS_SERVREQ_SHIFT 5 |
| /* MSD Bit Fields */ |
| #define MLB_MSD_SD0_7_0_MASK 0xFFu |
| #define MLB_MSD_SD0_7_0_SHIFT 0 |
| #define MLB_MSD_SD0_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD0_7_0_SHIFT))&MLB_MSD_SD0_7_0_MASK) |
| #define MLB_MSD_SD1_7_0_MASK 0xFF00u |
| #define MLB_MSD_SD1_7_0_SHIFT 8 |
| #define MLB_MSD_SD1_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD1_7_0_SHIFT))&MLB_MSD_SD1_7_0_MASK) |
| #define MLB_MSD_SD2_7_0_MASK 0xFF0000u |
| #define MLB_MSD_SD2_7_0_SHIFT 16 |
| #define MLB_MSD_SD2_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD2_7_0_SHIFT))&MLB_MSD_SD2_7_0_MASK) |
| #define MLB_MSD_SD3_7_0_MASK 0xFF000000u |
| #define MLB_MSD_SD3_7_0_SHIFT 24 |
| #define MLB_MSD_SD3_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MSD_SD3_7_0_SHIFT))&MLB_MSD_SD3_7_0_MASK) |
| /* MIEN Bit Fields */ |
| #define MLB_MIEN_ISOC_PE_MASK 0x1u |
| #define MLB_MIEN_ISOC_PE_SHIFT 0 |
| #define MLB_MIEN_ISOC_BUFO_MASK 0x2u |
| #define MLB_MIEN_ISOC_BUFO_SHIFT 1 |
| #define MLB_MIEN_SYNC_PE_MASK 0x10000u |
| #define MLB_MIEN_SYNC_PE_SHIFT 16 |
| #define MLB_MIEN_ARX_DONE_MASK 0x20000u |
| #define MLB_MIEN_ARX_DONE_SHIFT 17 |
| #define MLB_MIEN_ARX_PE_MASK 0x40000u |
| #define MLB_MIEN_ARX_PE_SHIFT 18 |
| #define MLB_MIEN_ARX_BREAK_MASK 0x80000u |
| #define MLB_MIEN_ARX_BREAK_SHIFT 19 |
| #define MLB_MIEN_ATX_DONE_MASK 0x100000u |
| #define MLB_MIEN_ATX_DONE_SHIFT 20 |
| #define MLB_MIEN_ATX_PE_MASK 0x200000u |
| #define MLB_MIEN_ATX_PE_SHIFT 21 |
| #define MLB_MIEN_ATX_BREAK_MASK 0x400000u |
| #define MLB_MIEN_ATX_BREAK_SHIFT 22 |
| #define MLB_MIEN_CRX_DONE_MASK 0x1000000u |
| #define MLB_MIEN_CRX_DONE_SHIFT 24 |
| #define MLB_MIEN_CRX_PE_MASK 0x2000000u |
| #define MLB_MIEN_CRX_PE_SHIFT 25 |
| #define MLB_MIEN_CRX_BREAK_MASK 0x4000000u |
| #define MLB_MIEN_CRX_BREAK_SHIFT 26 |
| #define MLB_MIEN_CTX_DONE_MASK 0x8000000u |
| #define MLB_MIEN_CTX_DONE_SHIFT 27 |
| #define MLB_MIEN_CTX_PE_MASK 0x10000000u |
| #define MLB_MIEN_CTX_PE_SHIFT 28 |
| #define MLB_MIEN_CTX_BREAK_MASK 0x20000000u |
| #define MLB_MIEN_CTX_BREAK_SHIFT 29 |
| /* MLBC1 Bit Fields */ |
| #define MLB_MLBC1_LOCK_MASK 0x40u |
| #define MLB_MLBC1_LOCK_SHIFT 6 |
| #define MLB_MLBC1_CLKM_MASK 0x80u |
| #define MLB_MLBC1_CLKM_SHIFT 7 |
| #define MLB_MLBC1_NDA_7_0_MASK 0xFF00u |
| #define MLB_MLBC1_NDA_7_0_SHIFT 8 |
| #define MLB_MLBC1_NDA_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MLBC1_NDA_7_0_SHIFT))&MLB_MLBC1_NDA_7_0_MASK) |
| /* HCTL Bit Fields */ |
| #define MLB_HCTL_RST0_MASK 0x1u |
| #define MLB_HCTL_RST0_SHIFT 0 |
| #define MLB_HCTL_RST1_MASK 0x2u |
| #define MLB_HCTL_RST1_SHIFT 1 |
| #define MLB_HCTL_EN_MASK 0x8000u |
| #define MLB_HCTL_EN_SHIFT 15 |
| /* HCMR0 Bit Fields */ |
| #define MLB_HCMR0_CHM_31_0_P_MASK 0xFFFFFFFFu |
| #define MLB_HCMR0_CHM_31_0_P_SHIFT 0 |
| #define MLB_HCMR0_CHM_31_0_P(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCMR0_CHM_31_0_P_SHIFT))&MLB_HCMR0_CHM_31_0_P_MASK) |
| /* HCMR1 Bit Fields */ |
| #define MLB_HCMR1_CHM_63_32_MASK 0xFFFFFFFFu |
| #define MLB_HCMR1_CHM_63_32_SHIFT 0 |
| #define MLB_HCMR1_CHM_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCMR1_CHM_63_32_SHIFT))&MLB_HCMR1_CHM_63_32_MASK) |
| /* HCER0 Bit Fields */ |
| #define MLB_HCER0_CERR_31_0_MASK 0xFFFFFFFFu |
| #define MLB_HCER0_CERR_31_0_SHIFT 0 |
| #define MLB_HCER0_CERR_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCER0_CERR_31_0_SHIFT))&MLB_HCER0_CERR_31_0_MASK) |
| /* HCER1 Bit Fields */ |
| #define MLB_HCER1_CERR_63_32_MASK 0xFFFFFFFFu |
| #define MLB_HCER1_CERR_63_32_SHIFT 0 |
| #define MLB_HCER1_CERR_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCER1_CERR_63_32_SHIFT))&MLB_HCER1_CERR_63_32_MASK) |
| /* HCBR0 Bit Fields */ |
| #define MLB_HCBR0_CHB_31_0_MASK 0xFFFFFFFFu |
| #define MLB_HCBR0_CHB_31_0_SHIFT 0 |
| #define MLB_HCBR0_CHB_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCBR0_CHB_31_0_SHIFT))&MLB_HCBR0_CHB_31_0_MASK) |
| /* HCBR1 Bit Fields */ |
| #define MLB_HCBR1_CHB_63_32_MASK 0xFFFFFFFFu |
| #define MLB_HCBR1_CHB_63_32_SHIFT 0 |
| #define MLB_HCBR1_CHB_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_HCBR1_CHB_63_32_SHIFT))&MLB_HCBR1_CHB_63_32_MASK) |
| /* MDAT0 Bit Fields */ |
| #define MLB_MDAT0_DATA_31_0_MASK 0xFFFFFFFFu |
| #define MLB_MDAT0_DATA_31_0_SHIFT 0 |
| #define MLB_MDAT0_DATA_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDAT0_DATA_31_0_SHIFT))&MLB_MDAT0_DATA_31_0_MASK) |
| /* MDAT1 Bit Fields */ |
| #define MLB_MDAT1_DATA_63_32_MASK 0xFFFFFFFFu |
| #define MLB_MDAT1_DATA_63_32_SHIFT 0 |
| #define MLB_MDAT1_DATA_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDAT1_DATA_63_32_SHIFT))&MLB_MDAT1_DATA_63_32_MASK) |
| /* MDAT2 Bit Fields */ |
| #define MLB_MDAT2_DATA_95_64_MASK 0xFFFFFFFFu |
| #define MLB_MDAT2_DATA_95_64_SHIFT 0 |
| #define MLB_MDAT2_DATA_95_64(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDAT2_DATA_95_64_SHIFT))&MLB_MDAT2_DATA_95_64_MASK) |
| /* MDAT3 Bit Fields */ |
| #define MLB_MDAT3_DATA_127_96_MASK 0xFFFFFFFFu |
| #define MLB_MDAT3_DATA_127_96_SHIFT 0 |
| #define MLB_MDAT3_DATA_127_96(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDAT3_DATA_127_96_SHIFT))&MLB_MDAT3_DATA_127_96_MASK) |
| /* MDWE0 Bit Fields */ |
| #define MLB_MDWE0_MASK_31_0_MASK 0xFFFFFFFFu |
| #define MLB_MDWE0_MASK_31_0_SHIFT 0 |
| #define MLB_MDWE0_MASK_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDWE0_MASK_31_0_SHIFT))&MLB_MDWE0_MASK_31_0_MASK) |
| /* MDWE1 Bit Fields */ |
| #define MLB_MDWE1_MASK_63_32_MASK 0xFFFFFFFFu |
| #define MLB_MDWE1_MASK_63_32_SHIFT 0 |
| #define MLB_MDWE1_MASK_63_32(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDWE1_MASK_63_32_SHIFT))&MLB_MDWE1_MASK_63_32_MASK) |
| /* MDWE2 Bit Fields */ |
| #define MLB_MDWE2_MASK_95_64_MASK 0xFFFFFFFFu |
| #define MLB_MDWE2_MASK_95_64_SHIFT 0 |
| #define MLB_MDWE2_MASK_95_64(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDWE2_MASK_95_64_SHIFT))&MLB_MDWE2_MASK_95_64_MASK) |
| /* MDWE3 Bit Fields */ |
| #define MLB_MDWE3_MASK_127_96_MASK 0xFFFFFFFFu |
| #define MLB_MDWE3_MASK_127_96_SHIFT 0 |
| #define MLB_MDWE3_MASK_127_96(x) (((uint32_t)(((uint32_t)(x))<<MLB_MDWE3_MASK_127_96_SHIFT))&MLB_MDWE3_MASK_127_96_MASK) |
| /* MCTL Bit Fields */ |
| #define MLB_MCTL_XCMP_MASK 0x1u |
| #define MLB_MCTL_XCMP_SHIFT 0 |
| /* MADR Bit Fields */ |
| #define MLB_MADR_ADDR_7_0_MASK 0xFFu |
| #define MLB_MADR_ADDR_7_0_SHIFT 0 |
| #define MLB_MADR_ADDR_7_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_MADR_ADDR_7_0_SHIFT))&MLB_MADR_ADDR_7_0_MASK) |
| #define MLB_MADR_ADDR_13_8_MASK 0x3F00u |
| #define MLB_MADR_ADDR_13_8_SHIFT 8 |
| #define MLB_MADR_ADDR_13_8(x) (((uint32_t)(((uint32_t)(x))<<MLB_MADR_ADDR_13_8_SHIFT))&MLB_MADR_ADDR_13_8_MASK) |
| #define MLB_MADR_TB_MASK 0x40000000u |
| #define MLB_MADR_TB_SHIFT 30 |
| #define MLB_MADR_WNR_MASK 0x80000000u |
| #define MLB_MADR_WNR_SHIFT 31 |
| /* ACTL Bit Fields */ |
| #define MLB_ACTL_SCE_MASK 0x1u |
| #define MLB_ACTL_SCE_SHIFT 0 |
| #define MLB_ACTL_SMX_MASK 0x2u |
| #define MLB_ACTL_SMX_SHIFT 1 |
| #define MLB_ACTL_DMA_MODE_MASK 0x4u |
| #define MLB_ACTL_DMA_MODE_SHIFT 2 |
| #define MLB_ACTL_MPB_MASK 0x10u |
| #define MLB_ACTL_MPB_SHIFT 4 |
| /* ACSR0 Bit Fields */ |
| #define MLB_ACSR0_CHS_MASK 0xFFFFFFFFu |
| #define MLB_ACSR0_CHS_SHIFT 0 |
| #define MLB_ACSR0_CHS(x) (((uint32_t)(((uint32_t)(x))<<MLB_ACSR0_CHS_SHIFT))&MLB_ACSR0_CHS_MASK) |
| /* ACSR1 Bit Fields */ |
| #define MLB_ACSR1_CHS_MASK 0xFFFFFFFFu |
| #define MLB_ACSR1_CHS_SHIFT 0 |
| #define MLB_ACSR1_CHS(x) (((uint32_t)(((uint32_t)(x))<<MLB_ACSR1_CHS_SHIFT))&MLB_ACSR1_CHS_MASK) |
| /* ACMR0 Bit Fields */ |
| #define MLB_ACMR0_CHM_31_0_MASK 0xFFFFFFFFu |
| #define MLB_ACMR0_CHM_31_0_SHIFT 0 |
| #define MLB_ACMR0_CHM_31_0(x) (((uint32_t)(((uint32_t)(x))<<MLB_ACMR0_CHM_31_0_SHIFT))&MLB_ACMR0_CHM_31_0_MASK) |
| /* ACMR1 Bit Fields */ |
| #define MLB_ACMR1_CHM_MASK 0xFFFFFFFFu |
| #define MLB_ACMR1_CHM_SHIFT 0 |
| #define MLB_ACMR1_CHM(x) (((uint32_t)(((uint32_t)(x))<<MLB_ACMR1_CHM_SHIFT))&MLB_ACMR1_CHM_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group MLB_Register_Masks */ |
| |
| /* MLB - Peripheral instance base addresses */ |
| /** Peripheral MLB base address */ |
| #define MLB_BASE (0x4218C000u) |
| /** Peripheral MLB base pointer */ |
| #define MLB ((MLB_Type *)MLB_BASE) |
| #define MLB_BASE_PTR (MLB) |
| /** Array initializer of MLB peripheral base addresses */ |
| #define MLB_BASE_ADDRS { MLB_BASE } |
| /** Array initializer of MLB peripheral base pointers */ |
| #define MLB_BASE_PTRS { MLB } |
| |
| /* ---------------------------------------------------------------------------- |
| -- MLB - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MLB_Register_Accessor_Macros MLB - Register accessor macros |
| * @{ |
| */ |
| |
| /* MLB - Register instance definitions */ |
| /* MLB */ |
| #define MLB_MLBC0 MLB_MLBC0_REG(MLB_BASE_PTR) |
| #define MLB_MS0 MLB_MS0_REG(MLB_BASE_PTR) |
| #define MLB_MLBPC2 MLB_MLBPC2_REG(MLB_BASE_PTR) |
| #define MLB_MS1 MLB_MS1_REG(MLB_BASE_PTR) |
| #define MLB_MSS MLB_MSS_REG(MLB_BASE_PTR) |
| #define MLB_MSD MLB_MSD_REG(MLB_BASE_PTR) |
| #define MLB_MIEN MLB_MIEN_REG(MLB_BASE_PTR) |
| #define MLB_MLBC1 MLB_MLBC1_REG(MLB_BASE_PTR) |
| #define MLB_HCTL MLB_HCTL_REG(MLB_BASE_PTR) |
| #define MLB_HCMR0 MLB_HCMR0_REG(MLB_BASE_PTR) |
| #define MLB_HCMR1 MLB_HCMR1_REG(MLB_BASE_PTR) |
| #define MLB_HCER0 MLB_HCER0_REG(MLB_BASE_PTR) |
| #define MLB_HCER1 MLB_HCER1_REG(MLB_BASE_PTR) |
| #define MLB_HCBR0 MLB_HCBR0_REG(MLB_BASE_PTR) |
| #define MLB_HCBR1 MLB_HCBR1_REG(MLB_BASE_PTR) |
| #define MLB_MDAT0 MLB_MDAT0_REG(MLB_BASE_PTR) |
| #define MLB_MDAT1 MLB_MDAT1_REG(MLB_BASE_PTR) |
| #define MLB_MDAT2 MLB_MDAT2_REG(MLB_BASE_PTR) |
| #define MLB_MDAT3 MLB_MDAT3_REG(MLB_BASE_PTR) |
| #define MLB_MDWE0 MLB_MDWE0_REG(MLB_BASE_PTR) |
| #define MLB_MDWE1 MLB_MDWE1_REG(MLB_BASE_PTR) |
| #define MLB_MDWE2 MLB_MDWE2_REG(MLB_BASE_PTR) |
| #define MLB_MDWE3 MLB_MDWE3_REG(MLB_BASE_PTR) |
| #define MLB_MCTL MLB_MCTL_REG(MLB_BASE_PTR) |
| #define MLB_MADR MLB_MADR_REG(MLB_BASE_PTR) |
| #define MLB_ACTL MLB_ACTL_REG(MLB_BASE_PTR) |
| #define MLB_ACSR0 MLB_ACSR0_REG(MLB_BASE_PTR) |
| #define MLB_ACSR1 MLB_ACSR1_REG(MLB_BASE_PTR) |
| #define MLB_ACMR0 MLB_ACMR0_REG(MLB_BASE_PTR) |
| #define MLB_ACMR1 MLB_ACMR1_REG(MLB_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group MLB_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group MLB_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MMDC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MMDC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ |
| __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ |
| __IO uint32_t MDOTC; /**< MMDC Core ODT Timing Control Register, offset: 0x8 */ |
| __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ |
| __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ |
| __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ |
| __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ |
| __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ |
| __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ |
| uint8_t RESERVED_0[8]; |
| __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ |
| __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ |
| __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ |
| __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ |
| __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ |
| __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ |
| uint8_t RESERVED_1[956]; |
| __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Regsiter, offset: 0x400 */ |
| __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ |
| __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ |
| __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ |
| __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ |
| __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ |
| __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ |
| __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ |
| __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ |
| __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ |
| __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ |
| __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ |
| __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ |
| __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ |
| uint8_t RESERVED_2[8]; |
| __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ |
| uint8_t RESERVED_3[956]; |
| __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ |
| __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ |
| __IO uint32_t MPWLGCR; /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */ |
| __IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */ |
| __IO uint32_t MPWLDECTRL1; /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */ |
| __I uint32_t MPWLDLST; /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */ |
| __IO uint32_t MPODTCTRL; /**< MMDC PHY ODT control register, offset: 0x818 */ |
| __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ |
| __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ |
| __IO uint32_t MPRDDQBY2DL; /**< MMDC PHY Read DQ Byte2 Delay Register, offset: 0x824 */ |
| __IO uint32_t MPRDDQBY3DL; /**< MMDC PHY Read DQ Byte3 Delay Register, offset: 0x828 */ |
| __IO uint32_t MPWRDQBY0DL; /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */ |
| __IO uint32_t MPWRDQBY1DL; /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */ |
| __IO uint32_t MPWRDQBY2DL; /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */ |
| __IO uint32_t MPWRDQBY3DL; /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */ |
| __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ |
| __IO uint32_t MPDGCTRL1; /**< MMDC PHY Read DQS Gating Control Register 1, offset: 0x840 */ |
| __I uint32_t MPDGDLST0; /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */ |
| __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ |
| __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ |
| __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ |
| __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ |
| __IO uint32_t MPSDCTRL; /**< MMDC PHY CK Control Register, offset: 0x858 */ |
| __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ |
| __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ |
| __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ |
| __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ |
| __I uint32_t MPRDDLHWST1; /**< MMDC PHY Read Delay HW Calibration Status Register 1, offset: 0x86C */ |
| __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ |
| __I uint32_t MPWRDLHWST1; /**< MMDC PHY Write Delay HW Calibration Status Register 1, offset: 0x874 */ |
| __IO uint32_t MPWLHWERR; /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */ |
| __I uint32_t MPDGHWST0; /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */ |
| __I uint32_t MPDGHWST1; /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */ |
| __I uint32_t MPDGHWST2; /**< MMDC PHY Read DQS Gating HW Status Register 2, offset: 0x884 */ |
| __I uint32_t MPDGHWST3; /**< MMDC PHY Read DQS Gating HW Status Register 3, offset: 0x888 */ |
| __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ |
| __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ |
| __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ |
| __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ |
| __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ |
| __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ |
| __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ |
| __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ |
| __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ |
| __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ |
| __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ |
| __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ |
| __IO uint32_t MPWRCADL; /**< MMDC Write CA delay-line controller, offset: 0x8BC */ |
| __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ |
| } MMDC_Type, *MMDC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MMDC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MMDC_Register_Accessor_Macros MMDC - Register accessor macros |
| * @{ |
| */ |
| |
| /* MMDC - Register accessors */ |
| #define MMDC_MDCTL_REG(base) ((base)->MDCTL) |
| #define MMDC_MDPDC_REG(base) ((base)->MDPDC) |
| #define MMDC_MDOTC_REG(base) ((base)->MDOTC) |
| #define MMDC_MDCFG0_REG(base) ((base)->MDCFG0) |
| #define MMDC_MDCFG1_REG(base) ((base)->MDCFG1) |
| #define MMDC_MDCFG2_REG(base) ((base)->MDCFG2) |
| #define MMDC_MDMISC_REG(base) ((base)->MDMISC) |
| #define MMDC_MDSCR_REG(base) ((base)->MDSCR) |
| #define MMDC_MDREF_REG(base) ((base)->MDREF) |
| #define MMDC_MDRWD_REG(base) ((base)->MDRWD) |
| #define MMDC_MDOR_REG(base) ((base)->MDOR) |
| #define MMDC_MDMRR_REG(base) ((base)->MDMRR) |
| #define MMDC_MDCFG3LP_REG(base) ((base)->MDCFG3LP) |
| #define MMDC_MDMR4_REG(base) ((base)->MDMR4) |
| #define MMDC_MDASP_REG(base) ((base)->MDASP) |
| #define MMDC_MAARCR_REG(base) ((base)->MAARCR) |
| #define MMDC_MAPSR_REG(base) ((base)->MAPSR) |
| #define MMDC_MAEXIDR0_REG(base) ((base)->MAEXIDR0) |
| #define MMDC_MAEXIDR1_REG(base) ((base)->MAEXIDR1) |
| #define MMDC_MADPCR0_REG(base) ((base)->MADPCR0) |
| #define MMDC_MADPCR1_REG(base) ((base)->MADPCR1) |
| #define MMDC_MADPSR0_REG(base) ((base)->MADPSR0) |
| #define MMDC_MADPSR1_REG(base) ((base)->MADPSR1) |
| #define MMDC_MADPSR2_REG(base) ((base)->MADPSR2) |
| #define MMDC_MADPSR3_REG(base) ((base)->MADPSR3) |
| #define MMDC_MADPSR4_REG(base) ((base)->MADPSR4) |
| #define MMDC_MADPSR5_REG(base) ((base)->MADPSR5) |
| #define MMDC_MASBS0_REG(base) ((base)->MASBS0) |
| #define MMDC_MASBS1_REG(base) ((base)->MASBS1) |
| #define MMDC_MAGENP_REG(base) ((base)->MAGENP) |
| #define MMDC_MPZQHWCTRL_REG(base) ((base)->MPZQHWCTRL) |
| #define MMDC_MPZQSWCTRL_REG(base) ((base)->MPZQSWCTRL) |
| #define MMDC_MPWLGCR_REG(base) ((base)->MPWLGCR) |
| #define MMDC_MPWLDECTRL0_REG(base) ((base)->MPWLDECTRL0) |
| #define MMDC_MPWLDECTRL1_REG(base) ((base)->MPWLDECTRL1) |
| #define MMDC_MPWLDLST_REG(base) ((base)->MPWLDLST) |
| #define MMDC_MPODTCTRL_REG(base) ((base)->MPODTCTRL) |
| #define MMDC_MPRDDQBY0DL_REG(base) ((base)->MPRDDQBY0DL) |
| #define MMDC_MPRDDQBY1DL_REG(base) ((base)->MPRDDQBY1DL) |
| #define MMDC_MPRDDQBY2DL_REG(base) ((base)->MPRDDQBY2DL) |
| #define MMDC_MPRDDQBY3DL_REG(base) ((base)->MPRDDQBY3DL) |
| #define MMDC_MPWRDQBY0DL_REG(base) ((base)->MPWRDQBY0DL) |
| #define MMDC_MPWRDQBY1DL_REG(base) ((base)->MPWRDQBY1DL) |
| #define MMDC_MPWRDQBY2DL_REG(base) ((base)->MPWRDQBY2DL) |
| #define MMDC_MPWRDQBY3DL_REG(base) ((base)->MPWRDQBY3DL) |
| #define MMDC_MPDGCTRL0_REG(base) ((base)->MPDGCTRL0) |
| #define MMDC_MPDGCTRL1_REG(base) ((base)->MPDGCTRL1) |
| #define MMDC_MPDGDLST0_REG(base) ((base)->MPDGDLST0) |
| #define MMDC_MPRDDLCTL_REG(base) ((base)->MPRDDLCTL) |
| #define MMDC_MPRDDLST_REG(base) ((base)->MPRDDLST) |
| #define MMDC_MPWRDLCTL_REG(base) ((base)->MPWRDLCTL) |
| #define MMDC_MPWRDLST_REG(base) ((base)->MPWRDLST) |
| #define MMDC_MPSDCTRL_REG(base) ((base)->MPSDCTRL) |
| #define MMDC_MPZQLP2CTL_REG(base) ((base)->MPZQLP2CTL) |
| #define MMDC_MPRDDLHWCTL_REG(base) ((base)->MPRDDLHWCTL) |
| #define MMDC_MPWRDLHWCTL_REG(base) ((base)->MPWRDLHWCTL) |
| #define MMDC_MPRDDLHWST0_REG(base) ((base)->MPRDDLHWST0) |
| #define MMDC_MPRDDLHWST1_REG(base) ((base)->MPRDDLHWST1) |
| #define MMDC_MPWRDLHWST0_REG(base) ((base)->MPWRDLHWST0) |
| #define MMDC_MPWRDLHWST1_REG(base) ((base)->MPWRDLHWST1) |
| #define MMDC_MPWLHWERR_REG(base) ((base)->MPWLHWERR) |
| #define MMDC_MPDGHWST0_REG(base) ((base)->MPDGHWST0) |
| #define MMDC_MPDGHWST1_REG(base) ((base)->MPDGHWST1) |
| #define MMDC_MPDGHWST2_REG(base) ((base)->MPDGHWST2) |
| #define MMDC_MPDGHWST3_REG(base) ((base)->MPDGHWST3) |
| #define MMDC_MPPDCMPR1_REG(base) ((base)->MPPDCMPR1) |
| #define MMDC_MPPDCMPR2_REG(base) ((base)->MPPDCMPR2) |
| #define MMDC_MPSWDAR0_REG(base) ((base)->MPSWDAR0) |
| #define MMDC_MPSWDRDR0_REG(base) ((base)->MPSWDRDR0) |
| #define MMDC_MPSWDRDR1_REG(base) ((base)->MPSWDRDR1) |
| #define MMDC_MPSWDRDR2_REG(base) ((base)->MPSWDRDR2) |
| #define MMDC_MPSWDRDR3_REG(base) ((base)->MPSWDRDR3) |
| #define MMDC_MPSWDRDR4_REG(base) ((base)->MPSWDRDR4) |
| #define MMDC_MPSWDRDR5_REG(base) ((base)->MPSWDRDR5) |
| #define MMDC_MPSWDRDR6_REG(base) ((base)->MPSWDRDR6) |
| #define MMDC_MPSWDRDR7_REG(base) ((base)->MPSWDRDR7) |
| #define MMDC_MPMUR0_REG(base) ((base)->MPMUR0) |
| #define MMDC_MPWRCADL_REG(base) ((base)->MPWRCADL) |
| #define MMDC_MPDCCR_REG(base) ((base)->MPDCCR) |
| |
| /*! |
| * @} |
| */ /* end of group MMDC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MMDC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MMDC_Register_Masks MMDC Register Masks |
| * @{ |
| */ |
| |
| /* MDCTL Bit Fields */ |
| #define MMDC_MDCTL_DSIZ_MASK 0x30000u |
| #define MMDC_MDCTL_DSIZ_SHIFT 16 |
| #define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_DSIZ_SHIFT))&MMDC_MDCTL_DSIZ_MASK) |
| #define MMDC_MDCTL_BL_MASK 0x80000u |
| #define MMDC_MDCTL_BL_SHIFT 19 |
| #define MMDC_MDCTL_COL_MASK 0x700000u |
| #define MMDC_MDCTL_COL_SHIFT 20 |
| #define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_COL_SHIFT))&MMDC_MDCTL_COL_MASK) |
| #define MMDC_MDCTL_ROW_MASK 0x7000000u |
| #define MMDC_MDCTL_ROW_SHIFT 24 |
| #define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCTL_ROW_SHIFT))&MMDC_MDCTL_ROW_MASK) |
| #define MMDC_MDCTL_SDE_1_MASK 0x40000000u |
| #define MMDC_MDCTL_SDE_1_SHIFT 30 |
| #define MMDC_MDCTL_SDE_0_MASK 0x80000000u |
| #define MMDC_MDCTL_SDE_0_SHIFT 31 |
| /* MDPDC Bit Fields */ |
| #define MMDC_MDPDC_tCKSRE_MASK 0x7u |
| #define MMDC_MDPDC_tCKSRE_SHIFT 0 |
| #define MMDC_MDPDC_tCKSRE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKSRE_SHIFT))&MMDC_MDPDC_tCKSRE_MASK) |
| #define MMDC_MDPDC_tCKSRX_MASK 0x38u |
| #define MMDC_MDPDC_tCKSRX_SHIFT 3 |
| #define MMDC_MDPDC_tCKSRX(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKSRX_SHIFT))&MMDC_MDPDC_tCKSRX_MASK) |
| #define MMDC_MDPDC_BOTH_CS_PD_MASK 0x40u |
| #define MMDC_MDPDC_BOTH_CS_PD_SHIFT 6 |
| #define MMDC_MDPDC_SLOW_PD_MASK 0x80u |
| #define MMDC_MDPDC_SLOW_PD_SHIFT 7 |
| #define MMDC_MDPDC_PWDT_0_MASK 0xF00u |
| #define MMDC_MDPDC_PWDT_0_SHIFT 8 |
| #define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PWDT_0_SHIFT))&MMDC_MDPDC_PWDT_0_MASK) |
| #define MMDC_MDPDC_PWDT_1_MASK 0xF000u |
| #define MMDC_MDPDC_PWDT_1_SHIFT 12 |
| #define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PWDT_1_SHIFT))&MMDC_MDPDC_PWDT_1_MASK) |
| #define MMDC_MDPDC_tCKE_MASK 0x70000u |
| #define MMDC_MDPDC_tCKE_SHIFT 16 |
| #define MMDC_MDPDC_tCKE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_tCKE_SHIFT))&MMDC_MDPDC_tCKE_MASK) |
| #define MMDC_MDPDC_PRCT_0_MASK 0x7000000u |
| #define MMDC_MDPDC_PRCT_0_SHIFT 24 |
| #define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PRCT_0_SHIFT))&MMDC_MDPDC_PRCT_0_MASK) |
| #define MMDC_MDPDC_PRCT_1_MASK 0x70000000u |
| #define MMDC_MDPDC_PRCT_1_SHIFT 28 |
| #define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDPDC_PRCT_1_SHIFT))&MMDC_MDPDC_PRCT_1_MASK) |
| /* MDOTC Bit Fields */ |
| #define MMDC_MDOTC_tODT_idle_off_MASK 0x1F0u |
| #define MMDC_MDOTC_tODT_idle_off_SHIFT 4 |
| #define MMDC_MDOTC_tODT_idle_off(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tODT_idle_off_SHIFT))&MMDC_MDOTC_tODT_idle_off_MASK) |
| #define MMDC_MDOTC_tODTLon_MASK 0x7000u |
| #define MMDC_MDOTC_tODTLon_SHIFT 12 |
| #define MMDC_MDOTC_tODTLon(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tODTLon_SHIFT))&MMDC_MDOTC_tODTLon_MASK) |
| #define MMDC_MDOTC_tAXPD_MASK 0xF0000u |
| #define MMDC_MDOTC_tAXPD_SHIFT 16 |
| #define MMDC_MDOTC_tAXPD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAXPD_SHIFT))&MMDC_MDOTC_tAXPD_MASK) |
| #define MMDC_MDOTC_tANPD_MASK 0xF00000u |
| #define MMDC_MDOTC_tANPD_SHIFT 20 |
| #define MMDC_MDOTC_tANPD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tANPD_SHIFT))&MMDC_MDOTC_tANPD_MASK) |
| #define MMDC_MDOTC_tAONPD_MASK 0x7000000u |
| #define MMDC_MDOTC_tAONPD_SHIFT 24 |
| #define MMDC_MDOTC_tAONPD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAONPD_SHIFT))&MMDC_MDOTC_tAONPD_MASK) |
| #define MMDC_MDOTC_tAOFPD_MASK 0x38000000u |
| #define MMDC_MDOTC_tAOFPD_SHIFT 27 |
| #define MMDC_MDOTC_tAOFPD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOTC_tAOFPD_SHIFT))&MMDC_MDOTC_tAOFPD_MASK) |
| /* MDCFG0 Bit Fields */ |
| #define MMDC_MDCFG0_tCL_MASK 0xFu |
| #define MMDC_MDCFG0_tCL_SHIFT 0 |
| #define MMDC_MDCFG0_tCL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tCL_SHIFT))&MMDC_MDCFG0_tCL_MASK) |
| #define MMDC_MDCFG0_tFAW_MASK 0x1F0u |
| #define MMDC_MDCFG0_tFAW_SHIFT 4 |
| #define MMDC_MDCFG0_tFAW(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tFAW_SHIFT))&MMDC_MDCFG0_tFAW_MASK) |
| #define MMDC_MDCFG0_tXPDLL_MASK 0x1E00u |
| #define MMDC_MDCFG0_tXPDLL_SHIFT 9 |
| #define MMDC_MDCFG0_tXPDLL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXPDLL_SHIFT))&MMDC_MDCFG0_tXPDLL_MASK) |
| #define MMDC_MDCFG0_tXP_MASK 0xE000u |
| #define MMDC_MDCFG0_tXP_SHIFT 13 |
| #define MMDC_MDCFG0_tXP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXP_SHIFT))&MMDC_MDCFG0_tXP_MASK) |
| #define MMDC_MDCFG0_tXS_MASK 0xFF0000u |
| #define MMDC_MDCFG0_tXS_SHIFT 16 |
| #define MMDC_MDCFG0_tXS(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tXS_SHIFT))&MMDC_MDCFG0_tXS_MASK) |
| #define MMDC_MDCFG0_tRFC_MASK 0xFF000000u |
| #define MMDC_MDCFG0_tRFC_SHIFT 24 |
| #define MMDC_MDCFG0_tRFC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG0_tRFC_SHIFT))&MMDC_MDCFG0_tRFC_MASK) |
| /* MDCFG1 Bit Fields */ |
| #define MMDC_MDCFG1_tCWL_MASK 0x7u |
| #define MMDC_MDCFG1_tCWL_SHIFT 0 |
| #define MMDC_MDCFG1_tCWL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tCWL_SHIFT))&MMDC_MDCFG1_tCWL_MASK) |
| #define MMDC_MDCFG1_tMRD_MASK 0x1E0u |
| #define MMDC_MDCFG1_tMRD_SHIFT 5 |
| #define MMDC_MDCFG1_tMRD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tMRD_SHIFT))&MMDC_MDCFG1_tMRD_MASK) |
| #define MMDC_MDCFG1_tWR_MASK 0xE00u |
| #define MMDC_MDCFG1_tWR_SHIFT 9 |
| #define MMDC_MDCFG1_tWR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tWR_SHIFT))&MMDC_MDCFG1_tWR_MASK) |
| #define MMDC_MDCFG1_tRPA_MASK 0x8000u |
| #define MMDC_MDCFG1_tRPA_SHIFT 15 |
| #define MMDC_MDCFG1_tRAS_MASK 0x1F0000u |
| #define MMDC_MDCFG1_tRAS_SHIFT 16 |
| #define MMDC_MDCFG1_tRAS(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRAS_SHIFT))&MMDC_MDCFG1_tRAS_MASK) |
| #define MMDC_MDCFG1_tRC_MASK 0x3E00000u |
| #define MMDC_MDCFG1_tRC_SHIFT 21 |
| #define MMDC_MDCFG1_tRC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRC_SHIFT))&MMDC_MDCFG1_tRC_MASK) |
| #define MMDC_MDCFG1_tRP_MASK 0x1C000000u |
| #define MMDC_MDCFG1_tRP_SHIFT 26 |
| #define MMDC_MDCFG1_tRP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRP_SHIFT))&MMDC_MDCFG1_tRP_MASK) |
| #define MMDC_MDCFG1_tRCD_MASK 0xE0000000u |
| #define MMDC_MDCFG1_tRCD_SHIFT 29 |
| #define MMDC_MDCFG1_tRCD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG1_tRCD_SHIFT))&MMDC_MDCFG1_tRCD_MASK) |
| /* MDCFG2 Bit Fields */ |
| #define MMDC_MDCFG2_tRRD_MASK 0x7u |
| #define MMDC_MDCFG2_tRRD_SHIFT 0 |
| #define MMDC_MDCFG2_tRRD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tRRD_SHIFT))&MMDC_MDCFG2_tRRD_MASK) |
| #define MMDC_MDCFG2_tWTR_MASK 0x38u |
| #define MMDC_MDCFG2_tWTR_SHIFT 3 |
| #define MMDC_MDCFG2_tWTR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tWTR_SHIFT))&MMDC_MDCFG2_tWTR_MASK) |
| #define MMDC_MDCFG2_tRTP_MASK 0x1C0u |
| #define MMDC_MDCFG2_tRTP_SHIFT 6 |
| #define MMDC_MDCFG2_tRTP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tRTP_SHIFT))&MMDC_MDCFG2_tRTP_MASK) |
| #define MMDC_MDCFG2_tDLLK_MASK 0x1FF0000u |
| #define MMDC_MDCFG2_tDLLK_SHIFT 16 |
| #define MMDC_MDCFG2_tDLLK(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG2_tDLLK_SHIFT))&MMDC_MDCFG2_tDLLK_MASK) |
| /* MDMISC Bit Fields */ |
| #define MMDC_MDMISC_RST_MASK 0x2u |
| #define MMDC_MDMISC_RST_SHIFT 1 |
| #define MMDC_MDMISC_DDR_TYPE_MASK 0x18u |
| #define MMDC_MDMISC_DDR_TYPE_SHIFT 3 |
| #define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_DDR_TYPE_SHIFT))&MMDC_MDMISC_DDR_TYPE_MASK) |
| #define MMDC_MDMISC_DDR_4_BANK_MASK 0x20u |
| #define MMDC_MDMISC_DDR_4_BANK_SHIFT 5 |
| #define MMDC_MDMISC_RALAT_MASK 0x1C0u |
| #define MMDC_MDMISC_RALAT_SHIFT 6 |
| #define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_RALAT_SHIFT))&MMDC_MDMISC_RALAT_MASK) |
| #define MMDC_MDMISC_MIF3_MODE_MASK 0x600u |
| #define MMDC_MDMISC_MIF3_MODE_SHIFT 9 |
| #define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_MIF3_MODE_SHIFT))&MMDC_MDMISC_MIF3_MODE_MASK) |
| #define MMDC_MDMISC_LPDDR2_S2_MASK 0x800u |
| #define MMDC_MDMISC_LPDDR2_S2_SHIFT 11 |
| #define MMDC_MDMISC_BI_ON_MASK 0x1000u |
| #define MMDC_MDMISC_BI_ON_SHIFT 12 |
| #define MMDC_MDMISC_WALAT_MASK 0x30000u |
| #define MMDC_MDMISC_WALAT_SHIFT 16 |
| #define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMISC_WALAT_SHIFT))&MMDC_MDMISC_WALAT_MASK) |
| #define MMDC_MDMISC_LHD_MASK 0x40000u |
| #define MMDC_MDMISC_LHD_SHIFT 18 |
| #define MMDC_MDMISC_ADDR_MIRROR_MASK 0x80000u |
| #define MMDC_MDMISC_ADDR_MIRROR_SHIFT 19 |
| #define MMDC_MDMISC_CALIB_PER_CS_MASK 0x100000u |
| #define MMDC_MDMISC_CALIB_PER_CS_SHIFT 20 |
| #define MMDC_MDMISC_CK1_GATING_MASK 0x200000u |
| #define MMDC_MDMISC_CK1_GATING_SHIFT 21 |
| #define MMDC_MDMISC_CS1_RDY_MASK 0x40000000u |
| #define MMDC_MDMISC_CS1_RDY_SHIFT 30 |
| #define MMDC_MDMISC_CS0_RDY_MASK 0x80000000u |
| #define MMDC_MDMISC_CS0_RDY_SHIFT 31 |
| /* MDSCR Bit Fields */ |
| #define MMDC_MDSCR_CMD_BA_MASK 0x7u |
| #define MMDC_MDSCR_CMD_BA_SHIFT 0 |
| #define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_BA_SHIFT))&MMDC_MDSCR_CMD_BA_MASK) |
| #define MMDC_MDSCR_CMD_CS_MASK 0x8u |
| #define MMDC_MDSCR_CMD_CS_SHIFT 3 |
| #define MMDC_MDSCR_CMD_MASK 0x70u |
| #define MMDC_MDSCR_CMD_SHIFT 4 |
| #define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_SHIFT))&MMDC_MDSCR_CMD_MASK) |
| #define MMDC_MDSCR_WL_EN_MASK 0x200u |
| #define MMDC_MDSCR_WL_EN_SHIFT 9 |
| #define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK 0x400u |
| #define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT 10 |
| #define MMDC_MDSCR_CON_ACK_MASK 0x4000u |
| #define MMDC_MDSCR_CON_ACK_SHIFT 14 |
| #define MMDC_MDSCR_CON_REQ_MASK 0x8000u |
| #define MMDC_MDSCR_CON_REQ_SHIFT 15 |
| #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK 0xFF0000u |
| #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT 16 |
| #define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT))&MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) |
| #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK 0xFF000000u |
| #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT 24 |
| #define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT))&MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) |
| /* MDREF Bit Fields */ |
| #define MMDC_MDREF_START_REF_MASK 0x1u |
| #define MMDC_MDREF_START_REF_SHIFT 0 |
| #define MMDC_MDREF_REFR_MASK 0x3800u |
| #define MMDC_MDREF_REFR_SHIFT 11 |
| #define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REFR_SHIFT))&MMDC_MDREF_REFR_MASK) |
| #define MMDC_MDREF_REF_SEL_MASK 0xC000u |
| #define MMDC_MDREF_REF_SEL_SHIFT 14 |
| #define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REF_SEL_SHIFT))&MMDC_MDREF_REF_SEL_MASK) |
| #define MMDC_MDREF_REF_CNT_MASK 0xFFFF0000u |
| #define MMDC_MDREF_REF_CNT_SHIFT 16 |
| #define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDREF_REF_CNT_SHIFT))&MMDC_MDREF_REF_CNT_MASK) |
| /* MDRWD Bit Fields */ |
| #define MMDC_MDRWD_RTR_DIFF_MASK 0x7u |
| #define MMDC_MDRWD_RTR_DIFF_SHIFT 0 |
| #define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTR_DIFF_SHIFT))&MMDC_MDRWD_RTR_DIFF_MASK) |
| #define MMDC_MDRWD_RTW_DIFF_MASK 0x38u |
| #define MMDC_MDRWD_RTW_DIFF_SHIFT 3 |
| #define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTW_DIFF_SHIFT))&MMDC_MDRWD_RTW_DIFF_MASK) |
| #define MMDC_MDRWD_WTW_DIFF_MASK 0x1C0u |
| #define MMDC_MDRWD_WTW_DIFF_SHIFT 6 |
| #define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_WTW_DIFF_SHIFT))&MMDC_MDRWD_WTW_DIFF_MASK) |
| #define MMDC_MDRWD_WTR_DIFF_MASK 0xE00u |
| #define MMDC_MDRWD_WTR_DIFF_SHIFT 9 |
| #define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_WTR_DIFF_SHIFT))&MMDC_MDRWD_WTR_DIFF_MASK) |
| #define MMDC_MDRWD_RTW_SAME_MASK 0x7000u |
| #define MMDC_MDRWD_RTW_SAME_SHIFT 12 |
| #define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_RTW_SAME_SHIFT))&MMDC_MDRWD_RTW_SAME_MASK) |
| #define MMDC_MDRWD_tDAI_MASK 0x1FFF0000u |
| #define MMDC_MDRWD_tDAI_SHIFT 16 |
| #define MMDC_MDRWD_tDAI(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDRWD_tDAI_SHIFT))&MMDC_MDRWD_tDAI_MASK) |
| /* MDOR Bit Fields */ |
| #define MMDC_MDOR_RST_to_CKE_MASK 0x3Fu |
| #define MMDC_MDOR_RST_to_CKE_SHIFT 0 |
| #define MMDC_MDOR_RST_to_CKE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_RST_to_CKE_SHIFT))&MMDC_MDOR_RST_to_CKE_MASK) |
| #define MMDC_MDOR_SDE_to_RST_MASK 0x3F00u |
| #define MMDC_MDOR_SDE_to_RST_SHIFT 8 |
| #define MMDC_MDOR_SDE_to_RST(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_SDE_to_RST_SHIFT))&MMDC_MDOR_SDE_to_RST_MASK) |
| #define MMDC_MDOR_tXPR_MASK 0xFF0000u |
| #define MMDC_MDOR_tXPR_SHIFT 16 |
| #define MMDC_MDOR_tXPR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDOR_tXPR_SHIFT))&MMDC_MDOR_tXPR_MASK) |
| /* MDMRR Bit Fields */ |
| #define MMDC_MDMRR_MRR_READ_DATA0_MASK 0xFFu |
| #define MMDC_MDMRR_MRR_READ_DATA0_SHIFT 0 |
| #define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA0_SHIFT))&MMDC_MDMRR_MRR_READ_DATA0_MASK) |
| #define MMDC_MDMRR_MRR_READ_DATA1_MASK 0xFF00u |
| #define MMDC_MDMRR_MRR_READ_DATA1_SHIFT 8 |
| #define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA1_SHIFT))&MMDC_MDMRR_MRR_READ_DATA1_MASK) |
| #define MMDC_MDMRR_MRR_READ_DATA2_MASK 0xFF0000u |
| #define MMDC_MDMRR_MRR_READ_DATA2_SHIFT 16 |
| #define MMDC_MDMRR_MRR_READ_DATA2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA2_SHIFT))&MMDC_MDMRR_MRR_READ_DATA2_MASK) |
| #define MMDC_MDMRR_MRR_READ_DATA3_MASK 0xFF000000u |
| #define MMDC_MDMRR_MRR_READ_DATA3_SHIFT 24 |
| #define MMDC_MDMRR_MRR_READ_DATA3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDMRR_MRR_READ_DATA3_SHIFT))&MMDC_MDMRR_MRR_READ_DATA3_MASK) |
| /* MDCFG3LP Bit Fields */ |
| #define MMDC_MDCFG3LP_tRPab_LP_MASK 0xFu |
| #define MMDC_MDCFG3LP_tRPab_LP_SHIFT 0 |
| #define MMDC_MDCFG3LP_tRPab_LP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRPab_LP_SHIFT))&MMDC_MDCFG3LP_tRPab_LP_MASK) |
| #define MMDC_MDCFG3LP_tRPpb_LP_MASK 0xF0u |
| #define MMDC_MDCFG3LP_tRPpb_LP_SHIFT 4 |
| #define MMDC_MDCFG3LP_tRPpb_LP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRPpb_LP_SHIFT))&MMDC_MDCFG3LP_tRPpb_LP_MASK) |
| #define MMDC_MDCFG3LP_tRCD_LP_MASK 0xF00u |
| #define MMDC_MDCFG3LP_tRCD_LP_SHIFT 8 |
| #define MMDC_MDCFG3LP_tRCD_LP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_tRCD_LP_SHIFT))&MMDC_MDCFG3LP_tRCD_LP_MASK) |
| #define MMDC_MDCFG3LP_RC_LP_MASK 0x3F0000u |
| #define MMDC_MDCFG3LP_RC_LP_SHIFT 16 |
| #define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDCFG3LP_RC_LP_SHIFT))&MMDC_MDCFG3LP_RC_LP_MASK) |
| /* MDMR4 Bit Fields */ |
| #define MMDC_MDMR4_UPDATE_DE_REQ_MASK 0x1u |
| #define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT 0 |
| #define MMDC_MDMR4_UPDATE_DE_ACK_MASK 0x2u |
| #define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT 1 |
| #define MMDC_MDMR4_tRCD_DE_MASK 0x10u |
| #define MMDC_MDMR4_tRCD_DE_SHIFT 4 |
| #define MMDC_MDMR4_tRC_DE_MASK 0x20u |
| #define MMDC_MDMR4_tRC_DE_SHIFT 5 |
| #define MMDC_MDMR4_tRAS_DE_MASK 0x40u |
| #define MMDC_MDMR4_tRAS_DE_SHIFT 6 |
| #define MMDC_MDMR4_tRP_DE_MASK 0x80u |
| #define MMDC_MDMR4_tRP_DE_SHIFT 7 |
| #define MMDC_MDMR4_tRRD_DE_MASK 0x100u |
| #define MMDC_MDMR4_tRRD_DE_SHIFT 8 |
| /* MDASP Bit Fields */ |
| #define MMDC_MDASP_CS0_END_MASK 0x7Fu |
| #define MMDC_MDASP_CS0_END_SHIFT 0 |
| #define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MDASP_CS0_END_SHIFT))&MMDC_MDASP_CS0_END_MASK) |
| /* MAARCR Bit Fields */ |
| #define MMDC_MAARCR_ARCR_GUARD_MASK 0xFu |
| #define MMDC_MAARCR_ARCR_GUARD_SHIFT 0 |
| #define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_GUARD_SHIFT))&MMDC_MAARCR_ARCR_GUARD_MASK) |
| #define MMDC_MAARCR_ARCR_DYN_MAX_MASK 0xF0u |
| #define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT 4 |
| #define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_DYN_MAX_SHIFT))&MMDC_MAARCR_ARCR_DYN_MAX_MASK) |
| #define MMDC_MAARCR_ARCR_DYN_JMP_MASK 0xF00u |
| #define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT 8 |
| #define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_DYN_JMP_SHIFT))&MMDC_MAARCR_ARCR_DYN_JMP_MASK) |
| #define MMDC_MAARCR_ARCR_ACC_HIT_MASK 0x70000u |
| #define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT 16 |
| #define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_ACC_HIT_SHIFT))&MMDC_MAARCR_ARCR_ACC_HIT_MASK) |
| #define MMDC_MAARCR_ARCR_PAG_HIT_MASK 0x700000u |
| #define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT 20 |
| #define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAARCR_ARCR_PAG_HIT_SHIFT))&MMDC_MAARCR_ARCR_PAG_HIT_MASK) |
| #define MMDC_MAARCR_ARCR_RCH_EN_MASK 0x1000000u |
| #define MMDC_MAARCR_ARCR_RCH_EN_SHIFT 24 |
| #define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK 0x10000000u |
| #define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT 28 |
| #define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK 0x40000000u |
| #define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT 30 |
| #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK 0x80000000u |
| #define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT 31 |
| /* MAPSR Bit Fields */ |
| #define MMDC_MAPSR_PSD_MASK 0x1u |
| #define MMDC_MAPSR_PSD_SHIFT 0 |
| #define MMDC_MAPSR_PSS_MASK 0x10u |
| #define MMDC_MAPSR_PSS_SHIFT 4 |
| #define MMDC_MAPSR_RIS_MASK 0x20u |
| #define MMDC_MAPSR_RIS_SHIFT 5 |
| #define MMDC_MAPSR_WIS_MASK 0x40u |
| #define MMDC_MAPSR_WIS_SHIFT 6 |
| #define MMDC_MAPSR_PST_MASK 0xFF00u |
| #define MMDC_MAPSR_PST_SHIFT 8 |
| #define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAPSR_PST_SHIFT))&MMDC_MAPSR_PST_MASK) |
| #define MMDC_MAPSR_LPMD_MASK 0x100000u |
| #define MMDC_MAPSR_LPMD_SHIFT 20 |
| #define MMDC_MAPSR_DVFS_MASK 0x200000u |
| #define MMDC_MAPSR_DVFS_SHIFT 21 |
| #define MMDC_MAPSR_LPACK_MASK 0x1000000u |
| #define MMDC_MAPSR_LPACK_SHIFT 24 |
| #define MMDC_MAPSR_DVACK_MASK 0x2000000u |
| #define MMDC_MAPSR_DVACK_SHIFT 25 |
| /* MAEXIDR0 Bit Fields */ |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK 0xFFFFu |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT 0 |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT))&MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK 0xFFFF0000u |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT 16 |
| #define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT))&MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) |
| /* MAEXIDR1 Bit Fields */ |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK 0xFFFFu |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT 0 |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT))&MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK 0xFFFF0000u |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT 16 |
| #define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT))&MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) |
| /* MADPCR0 Bit Fields */ |
| #define MMDC_MADPCR0_DBG_EN_MASK 0x1u |
| #define MMDC_MADPCR0_DBG_EN_SHIFT 0 |
| #define MMDC_MADPCR0_DBG_RST_MASK 0x2u |
| #define MMDC_MADPCR0_DBG_RST_SHIFT 1 |
| #define MMDC_MADPCR0_PRF_FRZ_MASK 0x4u |
| #define MMDC_MADPCR0_PRF_FRZ_SHIFT 2 |
| #define MMDC_MADPCR0_CYC_OVF_MASK 0x8u |
| #define MMDC_MADPCR0_CYC_OVF_SHIFT 3 |
| #define MMDC_MADPCR0_SBS_EN_MASK 0x100u |
| #define MMDC_MADPCR0_SBS_EN_SHIFT 8 |
| #define MMDC_MADPCR0_SBS_MASK 0x200u |
| #define MMDC_MADPCR0_SBS_SHIFT 9 |
| /* MADPCR1 Bit Fields */ |
| #define MMDC_MADPCR1_PRF_AXI_ID_MASK 0xFFFFu |
| #define MMDC_MADPCR1_PRF_AXI_ID_SHIFT 0 |
| #define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPCR1_PRF_AXI_ID_SHIFT))&MMDC_MADPCR1_PRF_AXI_ID_MASK) |
| #define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK 0xFFFF0000u |
| #define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT 16 |
| #define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPCR1_PRF_AXI_ID_MASK_SHIFT))&MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) |
| /* MADPSR0 Bit Fields */ |
| #define MMDC_MADPSR0_CYC_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR0_CYC_COUNT_SHIFT 0 |
| #define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR0_CYC_COUNT_SHIFT))&MMDC_MADPSR0_CYC_COUNT_MASK) |
| /* MADPSR1 Bit Fields */ |
| #define MMDC_MADPSR1_BUSY_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR1_BUSY_COUNT_SHIFT 0 |
| #define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR1_BUSY_COUNT_SHIFT))&MMDC_MADPSR1_BUSY_COUNT_MASK) |
| /* MADPSR2 Bit Fields */ |
| #define MMDC_MADPSR2_RD_ACC_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT 0 |
| #define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR2_RD_ACC_COUNT_SHIFT))&MMDC_MADPSR2_RD_ACC_COUNT_MASK) |
| /* MADPSR3 Bit Fields */ |
| #define MMDC_MADPSR3_WR_ACC_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT 0 |
| #define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR3_WR_ACC_COUNT_SHIFT))&MMDC_MADPSR3_WR_ACC_COUNT_MASK) |
| /* MADPSR4 Bit Fields */ |
| #define MMDC_MADPSR4_RD_BYTES_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT 0 |
| #define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT))&MMDC_MADPSR4_RD_BYTES_COUNT_MASK) |
| /* MADPSR5 Bit Fields */ |
| #define MMDC_MADPSR5_WR_BYTES_COUNT_MASK 0xFFFFFFFFu |
| #define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT 0 |
| #define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT))&MMDC_MADPSR5_WR_BYTES_COUNT_MASK) |
| /* MASBS0 Bit Fields */ |
| #define MMDC_MASBS0_SBS_ADDR_MASK 0xFFFFFFFFu |
| #define MMDC_MASBS0_SBS_ADDR_SHIFT 0 |
| #define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS0_SBS_ADDR_SHIFT))&MMDC_MASBS0_SBS_ADDR_MASK) |
| /* MASBS1 Bit Fields */ |
| #define MMDC_MASBS1_SBS_VLD_MASK 0x1u |
| #define MMDC_MASBS1_SBS_VLD_SHIFT 0 |
| #define MMDC_MASBS1_SBS_TYPE_MASK 0x2u |
| #define MMDC_MASBS1_SBS_TYPE_SHIFT 1 |
| #define MMDC_MASBS1_SBS_LOCK_MASK 0xCu |
| #define MMDC_MASBS1_SBS_LOCK_SHIFT 2 |
| #define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_LOCK_SHIFT))&MMDC_MASBS1_SBS_LOCK_MASK) |
| #define MMDC_MASBS1_SBS_PROT_MASK 0x70u |
| #define MMDC_MASBS1_SBS_PROT_SHIFT 4 |
| #define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_PROT_SHIFT))&MMDC_MASBS1_SBS_PROT_MASK) |
| #define MMDC_MASBS1_SBS_SIZE_MASK 0x380u |
| #define MMDC_MASBS1_SBS_SIZE_SHIFT 7 |
| #define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_SIZE_SHIFT))&MMDC_MASBS1_SBS_SIZE_MASK) |
| #define MMDC_MASBS1_SBS_BURST_MASK 0xC00u |
| #define MMDC_MASBS1_SBS_BURST_SHIFT 10 |
| #define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_BURST_SHIFT))&MMDC_MASBS1_SBS_BURST_MASK) |
| #define MMDC_MASBS1_SBS_BUFF_MASK 0x1000u |
| #define MMDC_MASBS1_SBS_BUFF_SHIFT 12 |
| #define MMDC_MASBS1_SBS_LEN_MASK 0xE000u |
| #define MMDC_MASBS1_SBS_LEN_SHIFT 13 |
| #define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_LEN_SHIFT))&MMDC_MASBS1_SBS_LEN_MASK) |
| #define MMDC_MASBS1_SBS_AXI_ID_MASK 0xFFFF0000u |
| #define MMDC_MASBS1_SBS_AXI_ID_SHIFT 16 |
| #define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MASBS1_SBS_AXI_ID_SHIFT))&MMDC_MASBS1_SBS_AXI_ID_MASK) |
| /* MAGENP Bit Fields */ |
| #define MMDC_MAGENP_GP31_GP0_MASK 0xFFFFFFFFu |
| #define MMDC_MAGENP_GP31_GP0_SHIFT 0 |
| #define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MAGENP_GP31_GP0_SHIFT))&MMDC_MAGENP_GP31_GP0_MASK) |
| /* MPZQHWCTRL Bit Fields */ |
| #define MMDC_MPZQHWCTRL_ZQ_MODE_MASK 0x3u |
| #define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT 0 |
| #define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT))&MMDC_MPZQHWCTRL_ZQ_MODE_MASK) |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK 0x3Cu |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT 2 |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK 0x7C0u |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT 6 |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK 0xF800u |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT 11 |
| #define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT))&MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) |
| #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK 0x10000u |
| #define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT 16 |
| #define MMDC_MPZQHWCTRL_TZQ_INIT_MASK 0xE0000u |
| #define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT 17 |
| #define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT))&MMDC_MPZQHWCTRL_TZQ_INIT_MASK) |
| #define MMDC_MPZQHWCTRL_TZQ_OPER_MASK 0x700000u |
| #define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT 20 |
| #define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT))&MMDC_MPZQHWCTRL_TZQ_OPER_MASK) |
| #define MMDC_MPZQHWCTRL_TZQ_CS_MASK 0x3800000u |
| #define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT 23 |
| #define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_TZQ_CS_SHIFT))&MMDC_MPZQHWCTRL_TZQ_CS_MASK) |
| #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK 0xF8000000u |
| #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT 27 |
| #define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT))&MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) |
| /* MPZQSWCTRL Bit Fields */ |
| #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK 0x1u |
| #define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT 0 |
| #define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK 0x2u |
| #define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT 1 |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK 0x7Cu |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT 2 |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT))&MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK 0xF80u |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT 7 |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT))&MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK 0x1000u |
| #define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT 12 |
| #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK 0x2000u |
| #define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT 13 |
| #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK 0x30000u |
| #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT 16 |
| #define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT))&MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) |
| /* MPWLGCR Bit Fields */ |
| #define MMDC_MPWLGCR_HW_WL_EN_MASK 0x1u |
| #define MMDC_MPWLGCR_HW_WL_EN_SHIFT 0 |
| #define MMDC_MPWLGCR_SW_WL_EN_MASK 0x2u |
| #define MMDC_MPWLGCR_SW_WL_EN_SHIFT 1 |
| #define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK 0x4u |
| #define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT 2 |
| #define MMDC_MPWLGCR_WL_SW_RES0_MASK 0x10u |
| #define MMDC_MPWLGCR_WL_SW_RES0_SHIFT 4 |
| #define MMDC_MPWLGCR_WL_SW_RES1_MASK 0x20u |
| #define MMDC_MPWLGCR_WL_SW_RES1_SHIFT 5 |
| #define MMDC_MPWLGCR_WL_SW_RES2_MASK 0x40u |
| #define MMDC_MPWLGCR_WL_SW_RES2_SHIFT 6 |
| #define MMDC_MPWLGCR_WL_SW_RES3_MASK 0x80u |
| #define MMDC_MPWLGCR_WL_SW_RES3_SHIFT 7 |
| #define MMDC_MPWLGCR_WL_HW_ERR0_MASK 0x100u |
| #define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT 8 |
| #define MMDC_MPWLGCR_WL_HW_ERR1_MASK 0x200u |
| #define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT 9 |
| #define MMDC_MPWLGCR_WL_HW_ERR2_MASK 0x400u |
| #define MMDC_MPWLGCR_WL_HW_ERR2_SHIFT 10 |
| #define MMDC_MPWLGCR_WL_HW_ERR3_MASK 0x800u |
| #define MMDC_MPWLGCR_WL_HW_ERR3_SHIFT 11 |
| /* MPWLDECTRL0 Bit Fields */ |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK 0x7Fu |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT 0 |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT))&MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK) |
| #define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK 0x100u |
| #define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT 8 |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK 0x600u |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT 9 |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT))&MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK) |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK 0x7F0000u |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT 16 |
| #define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT))&MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK) |
| #define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK 0x1000000u |
| #define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT 24 |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK 0x6000000u |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT 25 |
| #define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT))&MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK) |
| /* MPWLDECTRL1 Bit Fields */ |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK 0x7Fu |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT 0 |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT))&MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK) |
| #define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK 0x100u |
| #define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT 8 |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK 0x600u |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT 9 |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT))&MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK) |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK 0x7F0000u |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT 16 |
| #define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT))&MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK) |
| #define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK 0x1000000u |
| #define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT 24 |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK 0x6000000u |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT 25 |
| #define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT))&MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK) |
| /* MPWLDLST Bit Fields */ |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK 0x7Fu |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT 0 |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK) |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK 0x7F00u |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT 8 |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK) |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2_MASK 0x7F0000u |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2_SHIFT 16 |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM2_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM2_MASK) |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3_MASK 0x7F000000u |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3_SHIFT 24 |
| #define MMDC_MPWLDLST_WL_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLDLST_WL_DL_UNIT_NUM3_SHIFT))&MMDC_MPWLDLST_WL_DL_UNIT_NUM3_MASK) |
| /* MPODTCTRL Bit Fields */ |
| #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK 0x1u |
| #define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT 0 |
| #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK 0x2u |
| #define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT 1 |
| #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK 0x4u |
| #define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT 2 |
| #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK 0x8u |
| #define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT 3 |
| #define MMDC_MPODTCTRL_ODT0_INT_RES_MASK 0x70u |
| #define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT 4 |
| #define MMDC_MPODTCTRL_ODT0_INT_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT0_INT_RES_MASK) |
| #define MMDC_MPODTCTRL_ODT1_INT_RES_MASK 0x700u |
| #define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT 8 |
| #define MMDC_MPODTCTRL_ODT1_INT_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT1_INT_RES_MASK) |
| #define MMDC_MPODTCTRL_ODT2_INT_RES_MASK 0x7000u |
| #define MMDC_MPODTCTRL_ODT2_INT_RES_SHIFT 12 |
| #define MMDC_MPODTCTRL_ODT2_INT_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT2_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT2_INT_RES_MASK) |
| #define MMDC_MPODTCTRL_ODT3_INT_RES_MASK 0x70000u |
| #define MMDC_MPODTCTRL_ODT3_INT_RES_SHIFT 16 |
| #define MMDC_MPODTCTRL_ODT3_INT_RES(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPODTCTRL_ODT3_INT_RES_SHIFT))&MMDC_MPODTCTRL_ODT3_INT_RES_MASK) |
| /* MPRDDQBY0DL Bit Fields */ |
| #define MMDC_MPRDDQBY0DL_rd_dq0_del_MASK 0x7u |
| #define MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT 0 |
| #define MMDC_MPRDDQBY0DL_rd_dq0_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq0_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq0_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq1_del_MASK 0x70u |
| #define MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT 4 |
| #define MMDC_MPRDDQBY0DL_rd_dq1_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq1_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq1_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq2_del_MASK 0x700u |
| #define MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT 8 |
| #define MMDC_MPRDDQBY0DL_rd_dq2_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq2_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq2_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq3_del_MASK 0x7000u |
| #define MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT 12 |
| #define MMDC_MPRDDQBY0DL_rd_dq3_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq3_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq3_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq4_del_MASK 0x70000u |
| #define MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT 16 |
| #define MMDC_MPRDDQBY0DL_rd_dq4_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq4_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq4_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq5_del_MASK 0x700000u |
| #define MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT 20 |
| #define MMDC_MPRDDQBY0DL_rd_dq5_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq5_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq5_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq6_del_MASK 0x7000000u |
| #define MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT 24 |
| #define MMDC_MPRDDQBY0DL_rd_dq6_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq6_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq6_del_MASK) |
| #define MMDC_MPRDDQBY0DL_rd_dq7_del_MASK 0x70000000u |
| #define MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT 28 |
| #define MMDC_MPRDDQBY0DL_rd_dq7_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY0DL_rd_dq7_del_SHIFT))&MMDC_MPRDDQBY0DL_rd_dq7_del_MASK) |
| /* MPRDDQBY1DL Bit Fields */ |
| #define MMDC_MPRDDQBY1DL_rd_dq8_del_MASK 0x7u |
| #define MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT 0 |
| #define MMDC_MPRDDQBY1DL_rd_dq8_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq8_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq8_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq9_del_MASK 0x70u |
| #define MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT 4 |
| #define MMDC_MPRDDQBY1DL_rd_dq9_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq9_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq9_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq10_del_MASK 0x700u |
| #define MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT 8 |
| #define MMDC_MPRDDQBY1DL_rd_dq10_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq10_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq10_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq11_del_MASK 0x7000u |
| #define MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT 12 |
| #define MMDC_MPRDDQBY1DL_rd_dq11_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq11_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq11_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq12_del_MASK 0x70000u |
| #define MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT 16 |
| #define MMDC_MPRDDQBY1DL_rd_dq12_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq12_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq12_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq13_del_MASK 0x700000u |
| #define MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT 20 |
| #define MMDC_MPRDDQBY1DL_rd_dq13_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq13_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq13_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq14_del_MASK 0x7000000u |
| #define MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT 24 |
| #define MMDC_MPRDDQBY1DL_rd_dq14_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq14_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq14_del_MASK) |
| #define MMDC_MPRDDQBY1DL_rd_dq15_del_MASK 0x70000000u |
| #define MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT 28 |
| #define MMDC_MPRDDQBY1DL_rd_dq15_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY1DL_rd_dq15_del_SHIFT))&MMDC_MPRDDQBY1DL_rd_dq15_del_MASK) |
| /* MPRDDQBY2DL Bit Fields */ |
| #define MMDC_MPRDDQBY2DL_rd_dq16_del_MASK 0x7u |
| #define MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT 0 |
| #define MMDC_MPRDDQBY2DL_rd_dq16_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq16_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq16_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq17_del_MASK 0x70u |
| #define MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT 4 |
| #define MMDC_MPRDDQBY2DL_rd_dq17_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq17_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq17_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq18_del_MASK 0x700u |
| #define MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT 8 |
| #define MMDC_MPRDDQBY2DL_rd_dq18_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq18_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq18_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq19_del_MASK 0x7000u |
| #define MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT 12 |
| #define MMDC_MPRDDQBY2DL_rd_dq19_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq19_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq19_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq20_del_MASK 0x70000u |
| #define MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT 16 |
| #define MMDC_MPRDDQBY2DL_rd_dq20_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq20_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq20_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq21_del_MASK 0x700000u |
| #define MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT 20 |
| #define MMDC_MPRDDQBY2DL_rd_dq21_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq21_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq21_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq22_del_MASK 0x7000000u |
| #define MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT 24 |
| #define MMDC_MPRDDQBY2DL_rd_dq22_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq22_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq22_del_MASK) |
| #define MMDC_MPRDDQBY2DL_rd_dq23_del_MASK 0x70000000u |
| #define MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT 28 |
| #define MMDC_MPRDDQBY2DL_rd_dq23_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY2DL_rd_dq23_del_SHIFT))&MMDC_MPRDDQBY2DL_rd_dq23_del_MASK) |
| /* MPRDDQBY3DL Bit Fields */ |
| #define MMDC_MPRDDQBY3DL_rd_dq24_del_MASK 0x7u |
| #define MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT 0 |
| #define MMDC_MPRDDQBY3DL_rd_dq24_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq24_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq24_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq25_del_MASK 0x70u |
| #define MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT 4 |
| #define MMDC_MPRDDQBY3DL_rd_dq25_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq25_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq25_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq26_del_MASK 0x700u |
| #define MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT 8 |
| #define MMDC_MPRDDQBY3DL_rd_dq26_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq26_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq26_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq27_del_MASK 0x7000u |
| #define MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT 12 |
| #define MMDC_MPRDDQBY3DL_rd_dq27_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq27_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq27_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq28_del_MASK 0x70000u |
| #define MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT 16 |
| #define MMDC_MPRDDQBY3DL_rd_dq28_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq28_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq28_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq29_del_MASK 0x700000u |
| #define MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT 20 |
| #define MMDC_MPRDDQBY3DL_rd_dq29_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq29_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq29_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq30_del_MASK 0x7000000u |
| #define MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT 24 |
| #define MMDC_MPRDDQBY3DL_rd_dq30_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq30_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq30_del_MASK) |
| #define MMDC_MPRDDQBY3DL_rd_dq31_del_MASK 0x70000000u |
| #define MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT 28 |
| #define MMDC_MPRDDQBY3DL_rd_dq31_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDQBY3DL_rd_dq31_del_SHIFT))&MMDC_MPRDDQBY3DL_rd_dq31_del_MASK) |
| /* MPWRDQBY0DL Bit Fields */ |
| #define MMDC_MPWRDQBY0DL_wr_dq0_del_MASK 0x3u |
| #define MMDC_MPWRDQBY0DL_wr_dq0_del_SHIFT 0 |
| #define MMDC_MPWRDQBY0DL_wr_dq0_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq0_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq0_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq1_del_MASK 0x30u |
| #define MMDC_MPWRDQBY0DL_wr_dq1_del_SHIFT 4 |
| #define MMDC_MPWRDQBY0DL_wr_dq1_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq1_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq1_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq2_del_MASK 0x300u |
| #define MMDC_MPWRDQBY0DL_wr_dq2_del_SHIFT 8 |
| #define MMDC_MPWRDQBY0DL_wr_dq2_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq2_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq2_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq3_del_MASK 0x3000u |
| #define MMDC_MPWRDQBY0DL_wr_dq3_del_SHIFT 12 |
| #define MMDC_MPWRDQBY0DL_wr_dq3_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq3_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq3_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq4_del_MASK 0x30000u |
| #define MMDC_MPWRDQBY0DL_wr_dq4_del_SHIFT 16 |
| #define MMDC_MPWRDQBY0DL_wr_dq4_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq4_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq4_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq5_del_MASK 0x300000u |
| #define MMDC_MPWRDQBY0DL_wr_dq5_del_SHIFT 20 |
| #define MMDC_MPWRDQBY0DL_wr_dq5_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq5_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq5_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq6_del_MASK 0x3000000u |
| #define MMDC_MPWRDQBY0DL_wr_dq6_del_SHIFT 24 |
| #define MMDC_MPWRDQBY0DL_wr_dq6_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq6_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq6_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dq7_del_MASK 0x30000000u |
| #define MMDC_MPWRDQBY0DL_wr_dq7_del_SHIFT 28 |
| #define MMDC_MPWRDQBY0DL_wr_dq7_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dq7_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dq7_del_MASK) |
| #define MMDC_MPWRDQBY0DL_wr_dm0_del_MASK 0xC0000000u |
| #define MMDC_MPWRDQBY0DL_wr_dm0_del_SHIFT 30 |
| #define MMDC_MPWRDQBY0DL_wr_dm0_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY0DL_wr_dm0_del_SHIFT))&MMDC_MPWRDQBY0DL_wr_dm0_del_MASK) |
| /* MPWRDQBY1DL Bit Fields */ |
| #define MMDC_MPWRDQBY1DL_wr_dq8_del_MASK 0x3u |
| #define MMDC_MPWRDQBY1DL_wr_dq8_del_SHIFT 0 |
| #define MMDC_MPWRDQBY1DL_wr_dq8_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq8_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq8_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq9_del_MASK 0x30u |
| #define MMDC_MPWRDQBY1DL_wr_dq9_del_SHIFT 4 |
| #define MMDC_MPWRDQBY1DL_wr_dq9_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq9_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq9_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq10_del_MASK 0x300u |
| #define MMDC_MPWRDQBY1DL_wr_dq10_del_SHIFT 8 |
| #define MMDC_MPWRDQBY1DL_wr_dq10_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq10_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq10_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq11_del_MASK 0x3000u |
| #define MMDC_MPWRDQBY1DL_wr_dq11_del_SHIFT 12 |
| #define MMDC_MPWRDQBY1DL_wr_dq11_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq11_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq11_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq12_del_MASK 0x30000u |
| #define MMDC_MPWRDQBY1DL_wr_dq12_del_SHIFT 16 |
| #define MMDC_MPWRDQBY1DL_wr_dq12_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq12_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq12_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq13_del_MASK 0x300000u |
| #define MMDC_MPWRDQBY1DL_wr_dq13_del_SHIFT 20 |
| #define MMDC_MPWRDQBY1DL_wr_dq13_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq13_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq13_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq14_del_MASK 0x3000000u |
| #define MMDC_MPWRDQBY1DL_wr_dq14_del_SHIFT 24 |
| #define MMDC_MPWRDQBY1DL_wr_dq14_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq14_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq14_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dq15_del_MASK 0x30000000u |
| #define MMDC_MPWRDQBY1DL_wr_dq15_del_SHIFT 28 |
| #define MMDC_MPWRDQBY1DL_wr_dq15_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dq15_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dq15_del_MASK) |
| #define MMDC_MPWRDQBY1DL_wr_dm1_del_MASK 0xC0000000u |
| #define MMDC_MPWRDQBY1DL_wr_dm1_del_SHIFT 30 |
| #define MMDC_MPWRDQBY1DL_wr_dm1_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY1DL_wr_dm1_del_SHIFT))&MMDC_MPWRDQBY1DL_wr_dm1_del_MASK) |
| /* MPWRDQBY2DL Bit Fields */ |
| #define MMDC_MPWRDQBY2DL_wr_dq16_del_MASK 0x3u |
| #define MMDC_MPWRDQBY2DL_wr_dq16_del_SHIFT 0 |
| #define MMDC_MPWRDQBY2DL_wr_dq16_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq16_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq16_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq17_del_MASK 0x30u |
| #define MMDC_MPWRDQBY2DL_wr_dq17_del_SHIFT 4 |
| #define MMDC_MPWRDQBY2DL_wr_dq17_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq17_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq17_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq18_del_MASK 0x300u |
| #define MMDC_MPWRDQBY2DL_wr_dq18_del_SHIFT 8 |
| #define MMDC_MPWRDQBY2DL_wr_dq18_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq18_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq18_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq19_del_MASK 0x3000u |
| #define MMDC_MPWRDQBY2DL_wr_dq19_del_SHIFT 12 |
| #define MMDC_MPWRDQBY2DL_wr_dq19_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq19_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq19_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq20_del_MASK 0x30000u |
| #define MMDC_MPWRDQBY2DL_wr_dq20_del_SHIFT 16 |
| #define MMDC_MPWRDQBY2DL_wr_dq20_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq20_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq20_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq21_del_MASK 0x300000u |
| #define MMDC_MPWRDQBY2DL_wr_dq21_del_SHIFT 20 |
| #define MMDC_MPWRDQBY2DL_wr_dq21_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq21_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq21_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq22_del_MASK 0x3000000u |
| #define MMDC_MPWRDQBY2DL_wr_dq22_del_SHIFT 24 |
| #define MMDC_MPWRDQBY2DL_wr_dq22_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq22_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq22_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dq23_del_MASK 0x30000000u |
| #define MMDC_MPWRDQBY2DL_wr_dq23_del_SHIFT 28 |
| #define MMDC_MPWRDQBY2DL_wr_dq23_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dq23_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dq23_del_MASK) |
| #define MMDC_MPWRDQBY2DL_wr_dm2_del_MASK 0xC0000000u |
| #define MMDC_MPWRDQBY2DL_wr_dm2_del_SHIFT 30 |
| #define MMDC_MPWRDQBY2DL_wr_dm2_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY2DL_wr_dm2_del_SHIFT))&MMDC_MPWRDQBY2DL_wr_dm2_del_MASK) |
| /* MPWRDQBY3DL Bit Fields */ |
| #define MMDC_MPWRDQBY3DL_wr_dq24_del_MASK 0x3u |
| #define MMDC_MPWRDQBY3DL_wr_dq24_del_SHIFT 0 |
| #define MMDC_MPWRDQBY3DL_wr_dq24_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq24_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq24_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq25_del_MASK 0x30u |
| #define MMDC_MPWRDQBY3DL_wr_dq25_del_SHIFT 4 |
| #define MMDC_MPWRDQBY3DL_wr_dq25_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq25_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq25_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq26_del_MASK 0x300u |
| #define MMDC_MPWRDQBY3DL_wr_dq26_del_SHIFT 8 |
| #define MMDC_MPWRDQBY3DL_wr_dq26_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq26_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq26_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq27_del_MASK 0x3000u |
| #define MMDC_MPWRDQBY3DL_wr_dq27_del_SHIFT 12 |
| #define MMDC_MPWRDQBY3DL_wr_dq27_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq27_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq27_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq28_del_MASK 0x30000u |
| #define MMDC_MPWRDQBY3DL_wr_dq28_del_SHIFT 16 |
| #define MMDC_MPWRDQBY3DL_wr_dq28_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq28_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq28_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq29_del_MASK 0x300000u |
| #define MMDC_MPWRDQBY3DL_wr_dq29_del_SHIFT 20 |
| #define MMDC_MPWRDQBY3DL_wr_dq29_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq29_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq29_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq30_del_MASK 0x3000000u |
| #define MMDC_MPWRDQBY3DL_wr_dq30_del_SHIFT 24 |
| #define MMDC_MPWRDQBY3DL_wr_dq30_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq30_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq30_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dq31_del_MASK 0x30000000u |
| #define MMDC_MPWRDQBY3DL_wr_dq31_del_SHIFT 28 |
| #define MMDC_MPWRDQBY3DL_wr_dq31_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dq31_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dq31_del_MASK) |
| #define MMDC_MPWRDQBY3DL_wr_dm3_del_MASK 0xC0000000u |
| #define MMDC_MPWRDQBY3DL_wr_dm3_del_SHIFT 30 |
| #define MMDC_MPWRDQBY3DL_wr_dm3_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDQBY3DL_wr_dm3_del_SHIFT))&MMDC_MPWRDQBY3DL_wr_dm3_del_MASK) |
| /* MPDGCTRL0 Bit Fields */ |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK 0x7Fu |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT 0 |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT))&MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK) |
| #define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK 0xF00u |
| #define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT 8 |
| #define MMDC_MPDGCTRL0_DG_HC_DEL0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT))&MMDC_MPDGCTRL0_DG_HC_DEL0_MASK) |
| #define MMDC_MPDGCTRL0_HW_DG_ERR_MASK 0x1000u |
| #define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT 12 |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK 0x7F0000u |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT 16 |
| #define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT))&MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK) |
| #define MMDC_MPDGCTRL0_DG_EXT_UP_MASK 0x800000u |
| #define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT 23 |
| #define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK 0xF000000u |
| #define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT 24 |
| #define MMDC_MPDGCTRL0_DG_HC_DEL1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT))&MMDC_MPDGCTRL0_DG_HC_DEL1_MASK) |
| #define MMDC_MPDGCTRL0_HW_DG_EN_MASK 0x10000000u |
| #define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT 28 |
| #define MMDC_MPDGCTRL0_DG_DIS_MASK 0x20000000u |
| #define MMDC_MPDGCTRL0_DG_DIS_SHIFT 29 |
| #define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK 0x40000000u |
| #define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT 30 |
| #define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK 0x80000000u |
| #define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT 31 |
| /* MPDGCTRL1 Bit Fields */ |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_MASK 0x7Fu |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT 0 |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_SHIFT))&MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET2_MASK) |
| #define MMDC_MPDGCTRL1_DG_HC_DEL2_MASK 0xF00u |
| #define MMDC_MPDGCTRL1_DG_HC_DEL2_SHIFT 8 |
| #define MMDC_MPDGCTRL1_DG_HC_DEL2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_HC_DEL2_SHIFT))&MMDC_MPDGCTRL1_DG_HC_DEL2_MASK) |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_MASK 0x7F0000u |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT 16 |
| #define MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_SHIFT))&MMDC_MPDGCTRL1_DG_DL_ABS_OFFSET3_MASK) |
| #define MMDC_MPDGCTRL1_DG_HC_DEL3_MASK 0xF000000u |
| #define MMDC_MPDGCTRL1_DG_HC_DEL3_SHIFT 24 |
| #define MMDC_MPDGCTRL1_DG_HC_DEL3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGCTRL1_DG_HC_DEL3_SHIFT))&MMDC_MPDGCTRL1_DG_HC_DEL3_MASK) |
| /* MPDGDLST0 Bit Fields */ |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK 0x7Fu |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT 0 |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK) |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK 0x7F00u |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT 8 |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK) |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_MASK 0x7F0000u |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_SHIFT 16 |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM2_MASK) |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_MASK 0x7F000000u |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_SHIFT 24 |
| #define MMDC_MPDGDLST0_DG_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_SHIFT))&MMDC_MPDGDLST0_DG_DL_UNIT_NUM3_MASK) |
| /* MPRDDLCTL Bit Fields */ |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK 0x7Fu |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT 0 |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK 0x7F00u |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT 8 |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK 0x7F0000u |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT 16 |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK) |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK 0x7F000000u |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT 24 |
| #define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_SHIFT))&MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK) |
| /* MPRDDLST Bit Fields */ |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK 0x7Fu |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT 0 |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK 0x7F00u |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT 8 |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK 0x7F0000u |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT 16 |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM2_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM2_MASK) |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK 0x7F000000u |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT 24 |
| #define MMDC_MPRDDLST_RD_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLST_RD_DL_UNIT_NUM3_SHIFT))&MMDC_MPRDDLST_RD_DL_UNIT_NUM3_MASK) |
| /* MPWRDLCTL Bit Fields */ |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK 0x7Fu |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT 0 |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK 0x7F00u |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT 8 |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK 0x7F0000u |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT 16 |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK) |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK 0x7F000000u |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT 24 |
| #define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_SHIFT))&MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK) |
| /* MPWRDLST Bit Fields */ |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK 0x7Fu |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT 0 |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK 0x7F00u |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT 8 |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK 0x7F0000u |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT 16 |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM2_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM2_MASK) |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK 0x7F000000u |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT 24 |
| #define MMDC_MPWRDLST_WR_DL_UNIT_NUM3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLST_WR_DL_UNIT_NUM3_SHIFT))&MMDC_MPWRDLST_WR_DL_UNIT_NUM3_MASK) |
| /* MPSDCTRL Bit Fields */ |
| #define MMDC_MPSDCTRL_SDclk0_del_MASK 0x300u |
| #define MMDC_MPSDCTRL_SDclk0_del_SHIFT 8 |
| #define MMDC_MPSDCTRL_SDclk0_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSDCTRL_SDclk0_del_SHIFT))&MMDC_MPSDCTRL_SDclk0_del_MASK) |
| #define MMDC_MPSDCTRL_SDCLK1_del_MASK 0xC00u |
| #define MMDC_MPSDCTRL_SDCLK1_del_SHIFT 10 |
| #define MMDC_MPSDCTRL_SDCLK1_del(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSDCTRL_SDCLK1_del_SHIFT))&MMDC_MPSDCTRL_SDCLK1_del_MASK) |
| /* MPZQLP2CTL Bit Fields */ |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK 0x1FFu |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT 0 |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK 0xFF0000u |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT 16 |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK 0x7F000000u |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT 24 |
| #define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT))&MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) |
| /* MPRDDLHWCTL Bit Fields */ |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK 0x1u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT 0 |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK 0x2u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT 1 |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_MASK 0x4u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR2_SHIFT 2 |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_MASK 0x8u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR3_SHIFT 3 |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK 0x10u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT 4 |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK 0x20u |
| #define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT 5 |
| /* MPWRDLHWCTL Bit Fields */ |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK 0x1u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT 0 |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK 0x2u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT 1 |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_MASK 0x4u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR2_SHIFT 2 |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_MASK 0x8u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR3_SHIFT 3 |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK 0x10u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT 4 |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK 0x20u |
| #define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT 5 |
| /* MPRDDLHWST0 Bit Fields */ |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK 0x7Fu |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT 0 |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK 0x7F00u |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT 8 |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK 0x7F0000u |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT 16 |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK 0x7F000000u |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT 24 |
| #define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT))&MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) |
| /* MPRDDLHWST1 Bit Fields */ |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK 0x7Fu |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT 0 |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_LOW2_MASK) |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK 0x7F00u |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT 8 |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_UP2_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_UP2_MASK) |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK 0x7F0000u |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT 16 |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_LOW3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_LOW3_MASK) |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK 0x7F000000u |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT 24 |
| #define MMDC_MPRDDLHWST1_HW_RD_DL_UP3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPRDDLHWST1_HW_RD_DL_UP3_SHIFT))&MMDC_MPRDDLHWST1_HW_RD_DL_UP3_MASK) |
| /* MPWRDLHWST0 Bit Fields */ |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK 0x7Fu |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT 0 |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK 0x7F00u |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT 8 |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK 0x7F0000u |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT 16 |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK 0x7F000000u |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT 24 |
| #define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT))&MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) |
| /* MPWRDLHWST1 Bit Fields */ |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK 0x7Fu |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT 0 |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_LOW2_MASK) |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK 0x7F00u |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT 8 |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_UP2_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_UP2_MASK) |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK 0x7F0000u |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT 16 |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_LOW3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_LOW3_MASK) |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK 0x7F000000u |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT 24 |
| #define MMDC_MPWRDLHWST1_HW_WR_DL_UP3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRDLHWST1_HW_WR_DL_UP3_SHIFT))&MMDC_MPWRDLHWST1_HW_WR_DL_UP3_MASK) |
| /* MPWLHWERR Bit Fields */ |
| #define MMDC_MPWLHWERR_HW_WL0_DQ_MASK 0xFFu |
| #define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT 0 |
| #define MMDC_MPWLHWERR_HW_WL0_DQ(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL0_DQ_MASK) |
| #define MMDC_MPWLHWERR_HW_WL1_DQ_MASK 0xFF00u |
| #define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT 8 |
| #define MMDC_MPWLHWERR_HW_WL1_DQ(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL1_DQ_MASK) |
| #define MMDC_MPWLHWERR_HW_WL2_DQ_MASK 0xFF0000u |
| #define MMDC_MPWLHWERR_HW_WL2_DQ_SHIFT 16 |
| #define MMDC_MPWLHWERR_HW_WL2_DQ(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL2_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL2_DQ_MASK) |
| #define MMDC_MPWLHWERR_HW_WL3_DQ_MASK 0xFF000000u |
| #define MMDC_MPWLHWERR_HW_WL3_DQ_SHIFT 24 |
| #define MMDC_MPWLHWERR_HW_WL3_DQ(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWLHWERR_HW_WL3_DQ_SHIFT))&MMDC_MPWLHWERR_HW_WL3_DQ_MASK) |
| /* MPDGHWST0 Bit Fields */ |
| #define MMDC_MPDGHWST0_HW_DG_LOW0_MASK 0x7FFu |
| #define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT 0 |
| #define MMDC_MPDGHWST0_HW_DG_LOW0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT))&MMDC_MPDGHWST0_HW_DG_LOW0_MASK) |
| #define MMDC_MPDGHWST0_HW_DG_UP0_MASK 0x7FF0000u |
| #define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT 16 |
| #define MMDC_MPDGHWST0_HW_DG_UP0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST0_HW_DG_UP0_SHIFT))&MMDC_MPDGHWST0_HW_DG_UP0_MASK) |
| /* MPDGHWST1 Bit Fields */ |
| #define MMDC_MPDGHWST1_HW_DG_LOW1_MASK 0x7FFu |
| #define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT 0 |
| #define MMDC_MPDGHWST1_HW_DG_LOW1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT))&MMDC_MPDGHWST1_HW_DG_LOW1_MASK) |
| #define MMDC_MPDGHWST1_HW_DG_UP1_MASK 0x7FF0000u |
| #define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT 16 |
| #define MMDC_MPDGHWST1_HW_DG_UP1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST1_HW_DG_UP1_SHIFT))&MMDC_MPDGHWST1_HW_DG_UP1_MASK) |
| /* MPDGHWST2 Bit Fields */ |
| #define MMDC_MPDGHWST2_HW_DG_LOW2_MASK 0x7FFu |
| #define MMDC_MPDGHWST2_HW_DG_LOW2_SHIFT 0 |
| #define MMDC_MPDGHWST2_HW_DG_LOW2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST2_HW_DG_LOW2_SHIFT))&MMDC_MPDGHWST2_HW_DG_LOW2_MASK) |
| #define MMDC_MPDGHWST2_HW_DG_UP2_MASK 0x7FF0000u |
| #define MMDC_MPDGHWST2_HW_DG_UP2_SHIFT 16 |
| #define MMDC_MPDGHWST2_HW_DG_UP2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST2_HW_DG_UP2_SHIFT))&MMDC_MPDGHWST2_HW_DG_UP2_MASK) |
| /* MPDGHWST3 Bit Fields */ |
| #define MMDC_MPDGHWST3_HW_DG_LOW3_MASK 0x7FFu |
| #define MMDC_MPDGHWST3_HW_DG_LOW3_SHIFT 0 |
| #define MMDC_MPDGHWST3_HW_DG_LOW3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST3_HW_DG_LOW3_SHIFT))&MMDC_MPDGHWST3_HW_DG_LOW3_MASK) |
| #define MMDC_MPDGHWST3_HW_DG_UP3_MASK 0x7FF0000u |
| #define MMDC_MPDGHWST3_HW_DG_UP3_SHIFT 16 |
| #define MMDC_MPDGHWST3_HW_DG_UP3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDGHWST3_HW_DG_UP3_SHIFT))&MMDC_MPDGHWST3_HW_DG_UP3_MASK) |
| /* MPPDCMPR1 Bit Fields */ |
| #define MMDC_MPPDCMPR1_PDV1_MASK 0xFFFFu |
| #define MMDC_MPPDCMPR1_PDV1_SHIFT 0 |
| #define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR1_PDV1_SHIFT))&MMDC_MPPDCMPR1_PDV1_MASK) |
| #define MMDC_MPPDCMPR1_PDV2_MASK 0xFFFF0000u |
| #define MMDC_MPPDCMPR1_PDV2_SHIFT 16 |
| #define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR1_PDV2_SHIFT))&MMDC_MPPDCMPR1_PDV2_MASK) |
| /* MPPDCMPR2 Bit Fields */ |
| #define MMDC_MPPDCMPR2_MPR_CMP_MASK 0x1u |
| #define MMDC_MPPDCMPR2_MPR_CMP_SHIFT 0 |
| #define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK 0x2u |
| #define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT 1 |
| #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK 0x4u |
| #define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT 2 |
| #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK 0x7F0000u |
| #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT 16 |
| #define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT))&MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) |
| #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK 0x7F000000u |
| #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT 24 |
| #define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT))&MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) |
| /* MPSWDAR0 Bit Fields */ |
| #define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK 0x1u |
| #define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT 0 |
| #define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK 0x2u |
| #define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT 1 |
| #define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK 0x4u |
| #define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT 2 |
| #define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK 0x8u |
| #define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT 3 |
| #define MMDC_MPSWDAR0_SW_DUM_CMP2_MASK 0x10u |
| #define MMDC_MPSWDAR0_SW_DUM_CMP2_SHIFT 4 |
| #define MMDC_MPSWDAR0_SW_DUM_CMP3_MASK 0x20u |
| #define MMDC_MPSWDAR0_SW_DUM_CMP3_SHIFT 5 |
| /* MPSWDRDR0 Bit Fields */ |
| #define MMDC_MPSWDRDR0_DUM_RD0_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR0_DUM_RD0_SHIFT 0 |
| #define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR0_DUM_RD0_SHIFT))&MMDC_MPSWDRDR0_DUM_RD0_MASK) |
| /* MPSWDRDR1 Bit Fields */ |
| #define MMDC_MPSWDRDR1_DUM_RD1_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR1_DUM_RD1_SHIFT 0 |
| #define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR1_DUM_RD1_SHIFT))&MMDC_MPSWDRDR1_DUM_RD1_MASK) |
| /* MPSWDRDR2 Bit Fields */ |
| #define MMDC_MPSWDRDR2_DUM_RD2_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR2_DUM_RD2_SHIFT 0 |
| #define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR2_DUM_RD2_SHIFT))&MMDC_MPSWDRDR2_DUM_RD2_MASK) |
| /* MPSWDRDR3 Bit Fields */ |
| #define MMDC_MPSWDRDR3_DUM_RD3_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR3_DUM_RD3_SHIFT 0 |
| #define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR3_DUM_RD3_SHIFT))&MMDC_MPSWDRDR3_DUM_RD3_MASK) |
| /* MPSWDRDR4 Bit Fields */ |
| #define MMDC_MPSWDRDR4_DUM_RD4_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR4_DUM_RD4_SHIFT 0 |
| #define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR4_DUM_RD4_SHIFT))&MMDC_MPSWDRDR4_DUM_RD4_MASK) |
| /* MPSWDRDR5 Bit Fields */ |
| #define MMDC_MPSWDRDR5_DUM_RD5_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR5_DUM_RD5_SHIFT 0 |
| #define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR5_DUM_RD5_SHIFT))&MMDC_MPSWDRDR5_DUM_RD5_MASK) |
| /* MPSWDRDR6 Bit Fields */ |
| #define MMDC_MPSWDRDR6_DUM_RD6_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR6_DUM_RD6_SHIFT 0 |
| #define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR6_DUM_RD6_SHIFT))&MMDC_MPSWDRDR6_DUM_RD6_MASK) |
| /* MPSWDRDR7 Bit Fields */ |
| #define MMDC_MPSWDRDR7_DUM_RD7_MASK 0xFFFFFFFFu |
| #define MMDC_MPSWDRDR7_DUM_RD7_SHIFT 0 |
| #define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPSWDRDR7_DUM_RD7_SHIFT))&MMDC_MPSWDRDR7_DUM_RD7_MASK) |
| /* MPMUR0 Bit Fields */ |
| #define MMDC_MPMUR0_MU_BYP_VAL_MASK 0x3FFu |
| #define MMDC_MPMUR0_MU_BYP_VAL_SHIFT 0 |
| #define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPMUR0_MU_BYP_VAL_SHIFT))&MMDC_MPMUR0_MU_BYP_VAL_MASK) |
| #define MMDC_MPMUR0_MU_BYP_EN_MASK 0x400u |
| #define MMDC_MPMUR0_MU_BYP_EN_SHIFT 10 |
| #define MMDC_MPMUR0_FRC_MSR_MASK 0x800u |
| #define MMDC_MPMUR0_FRC_MSR_SHIFT 11 |
| #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK 0x3FF0000u |
| #define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT 16 |
| #define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT))&MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) |
| /* MPWRCADL Bit Fields */ |
| #define MMDC_MPWRCADL_WR_CA0_DEL_MASK 0x3u |
| #define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT 0 |
| #define MMDC_MPWRCADL_WR_CA0_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA0_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA0_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA1_DEL_MASK 0xCu |
| #define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT 2 |
| #define MMDC_MPWRCADL_WR_CA1_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA1_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA1_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA2_DEL_MASK 0x30u |
| #define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT 4 |
| #define MMDC_MPWRCADL_WR_CA2_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA2_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA2_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA3_DEL_MASK 0xC0u |
| #define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT 6 |
| #define MMDC_MPWRCADL_WR_CA3_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA3_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA3_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA4_DEL_MASK 0x300u |
| #define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT 8 |
| #define MMDC_MPWRCADL_WR_CA4_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA4_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA4_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA5_DEL_MASK 0xC00u |
| #define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT 10 |
| #define MMDC_MPWRCADL_WR_CA5_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA5_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA5_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA6_DEL_MASK 0x3000u |
| #define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT 12 |
| #define MMDC_MPWRCADL_WR_CA6_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA6_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA6_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA7_DEL_MASK 0xC000u |
| #define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT 14 |
| #define MMDC_MPWRCADL_WR_CA7_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA7_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA7_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA8_DEL_MASK 0x30000u |
| #define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT 16 |
| #define MMDC_MPWRCADL_WR_CA8_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA8_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA8_DEL_MASK) |
| #define MMDC_MPWRCADL_WR_CA9_DEL_MASK 0xC0000u |
| #define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT 18 |
| #define MMDC_MPWRCADL_WR_CA9_DEL(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPWRCADL_WR_CA9_DEL_SHIFT))&MMDC_MPWRCADL_WR_CA9_DEL_MASK) |
| /* MPDCCR Bit Fields */ |
| #define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK 0x7u |
| #define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT 0 |
| #define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) |
| #define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK 0x38u |
| #define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT 3 |
| #define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) |
| #define MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK 0x1C0u |
| #define MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT 6 |
| #define MMDC_MPDCCR_WR_DQS2_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS2_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS2_FT_DCC_MASK) |
| #define MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK 0xE00u |
| #define MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT 9 |
| #define MMDC_MPDCCR_WR_DQS3_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_WR_DQS3_FT_DCC_SHIFT))&MMDC_MPDCCR_WR_DQS3_FT_DCC_MASK) |
| #define MMDC_MPDCCR_CK_FT0_DCC_MASK 0x7000u |
| #define MMDC_MPDCCR_CK_FT0_DCC_SHIFT 12 |
| #define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_CK_FT0_DCC_SHIFT))&MMDC_MPDCCR_CK_FT0_DCC_MASK) |
| #define MMDC_MPDCCR_CK_FT1_DCC_MASK 0x70000u |
| #define MMDC_MPDCCR_CK_FT1_DCC_SHIFT 16 |
| #define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_CK_FT1_DCC_SHIFT))&MMDC_MPDCCR_CK_FT1_DCC_MASK) |
| #define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK 0x380000u |
| #define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT 19 |
| #define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) |
| #define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK 0x1C00000u |
| #define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT 22 |
| #define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) |
| #define MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK 0xE000000u |
| #define MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT 25 |
| #define MMDC_MPDCCR_RD_DQS2_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS2_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS2_FT_DCC_MASK) |
| #define MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK 0x70000000u |
| #define MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT 28 |
| #define MMDC_MPDCCR_RD_DQS3_FT_DCC(x) (((uint32_t)(((uint32_t)(x))<<MMDC_MPDCCR_RD_DQS3_FT_DCC_SHIFT))&MMDC_MPDCCR_RD_DQS3_FT_DCC_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group MMDC_Register_Masks */ |
| |
| /* MMDC - Peripheral instance base addresses */ |
| /** Peripheral MMDC base address */ |
| #define MMDC_BASE (0x421B0000u) |
| /** Peripheral MMDC base pointer */ |
| #define MMDC ((MMDC_Type *)MMDC_BASE) |
| #define MMDC_BASE_PTR (MMDC) |
| /** Array initializer of MMDC peripheral base addresses */ |
| #define MMDC_BASE_ADDRS { MMDC_BASE } |
| /** Array initializer of MMDC peripheral base pointers */ |
| #define MMDC_BASE_PTRS { MMDC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- MMDC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MMDC_Register_Accessor_Macros MMDC - Register accessor macros |
| * @{ |
| */ |
| |
| /* MMDC - Register instance definitions */ |
| /* MMDC */ |
| #define MMDC_MDCTL MMDC_MDCTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MDPDC MMDC_MDPDC_REG(MMDC_BASE_PTR) |
| #define MMDC_MDOTC MMDC_MDOTC_REG(MMDC_BASE_PTR) |
| #define MMDC_MDCFG0 MMDC_MDCFG0_REG(MMDC_BASE_PTR) |
| #define MMDC_MDCFG1 MMDC_MDCFG1_REG(MMDC_BASE_PTR) |
| #define MMDC_MDCFG2 MMDC_MDCFG2_REG(MMDC_BASE_PTR) |
| #define MMDC_MDMISC MMDC_MDMISC_REG(MMDC_BASE_PTR) |
| #define MMDC_MDSCR MMDC_MDSCR_REG(MMDC_BASE_PTR) |
| #define MMDC_MDREF MMDC_MDREF_REG(MMDC_BASE_PTR) |
| #define MMDC_MDRWD MMDC_MDRWD_REG(MMDC_BASE_PTR) |
| #define MMDC_MDOR MMDC_MDOR_REG(MMDC_BASE_PTR) |
| #define MMDC_MDMRR MMDC_MDMRR_REG(MMDC_BASE_PTR) |
| #define MMDC_MDCFG3LP MMDC_MDCFG3LP_REG(MMDC_BASE_PTR) |
| #define MMDC_MDMR4 MMDC_MDMR4_REG(MMDC_BASE_PTR) |
| #define MMDC_MDASP MMDC_MDASP_REG(MMDC_BASE_PTR) |
| #define MMDC_MAARCR MMDC_MAARCR_REG(MMDC_BASE_PTR) |
| #define MMDC_MAPSR MMDC_MAPSR_REG(MMDC_BASE_PTR) |
| #define MMDC_MAEXIDR0 MMDC_MAEXIDR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MAEXIDR1 MMDC_MAEXIDR1_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPCR0 MMDC_MADPCR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPCR1 MMDC_MADPCR1_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR0 MMDC_MADPSR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR1 MMDC_MADPSR1_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR2 MMDC_MADPSR2_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR3 MMDC_MADPSR3_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR4 MMDC_MADPSR4_REG(MMDC_BASE_PTR) |
| #define MMDC_MADPSR5 MMDC_MADPSR5_REG(MMDC_BASE_PTR) |
| #define MMDC_MASBS0 MMDC_MASBS0_REG(MMDC_BASE_PTR) |
| #define MMDC_MASBS1 MMDC_MASBS1_REG(MMDC_BASE_PTR) |
| #define MMDC_MAGENP MMDC_MAGENP_REG(MMDC_BASE_PTR) |
| #define MMDC_MPZQHWCTRL MMDC_MPZQHWCTRL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPZQSWCTRL MMDC_MPZQSWCTRL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWLGCR MMDC_MPWLGCR_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWLDECTRL0 MMDC_MPWLDECTRL0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWLDECTRL1 MMDC_MPWLDECTRL1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWLDLST MMDC_MPWLDLST_REG(MMDC_BASE_PTR) |
| #define MMDC_MPODTCTRL MMDC_MPODTCTRL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDQBY0DL MMDC_MPRDDQBY0DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDQBY1DL MMDC_MPRDDQBY1DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDQBY2DL MMDC_MPRDDQBY2DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDQBY3DL MMDC_MPRDDQBY3DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDQBY0DL MMDC_MPWRDQBY0DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDQBY1DL MMDC_MPWRDQBY1DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDQBY2DL MMDC_MPWRDQBY2DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDQBY3DL MMDC_MPWRDQBY3DL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGCTRL0 MMDC_MPDGCTRL0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGCTRL1 MMDC_MPDGCTRL1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGDLST0 MMDC_MPDGDLST0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDLCTL MMDC_MPRDDLCTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDLST MMDC_MPRDDLST_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDLCTL MMDC_MPWRDLCTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDLST MMDC_MPWRDLST_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSDCTRL MMDC_MPSDCTRL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPZQLP2CTL MMDC_MPZQLP2CTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDLHWCTL MMDC_MPRDDLHWCTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDLHWCTL MMDC_MPWRDLHWCTL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDLHWST0 MMDC_MPRDDLHWST0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPRDDLHWST1 MMDC_MPRDDLHWST1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDLHWST0 MMDC_MPWRDLHWST0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRDLHWST1 MMDC_MPWRDLHWST1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWLHWERR MMDC_MPWLHWERR_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGHWST0 MMDC_MPDGHWST0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGHWST1 MMDC_MPDGHWST1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGHWST2 MMDC_MPDGHWST2_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDGHWST3 MMDC_MPDGHWST3_REG(MMDC_BASE_PTR) |
| #define MMDC_MPPDCMPR1 MMDC_MPPDCMPR1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPPDCMPR2 MMDC_MPPDCMPR2_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDAR0 MMDC_MPSWDAR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR0 MMDC_MPSWDRDR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR1 MMDC_MPSWDRDR1_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR2 MMDC_MPSWDRDR2_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR3 MMDC_MPSWDRDR3_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR4 MMDC_MPSWDRDR4_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR5 MMDC_MPSWDRDR5_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR6 MMDC_MPSWDRDR6_REG(MMDC_BASE_PTR) |
| #define MMDC_MPSWDRDR7 MMDC_MPSWDRDR7_REG(MMDC_BASE_PTR) |
| #define MMDC_MPMUR0 MMDC_MPMUR0_REG(MMDC_BASE_PTR) |
| #define MMDC_MPWRCADL MMDC_MPWRCADL_REG(MMDC_BASE_PTR) |
| #define MMDC_MPDCCR MMDC_MPDCCR_REG(MMDC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group MMDC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group MMDC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** MU - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t TR[4]; /**< Processor B Transmit Register 0, array offset: 0x0, array step: 0x4 */ |
| __I uint32_t RR[4]; /**< Processor B Receive Register 0, array offset: 0x10, array step: 0x4 */ |
| __IO uint32_t SR; /**< Processor b Status Register, offset: 0x20 */ |
| __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ |
| } MU_Type, *MU_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros |
| * @{ |
| */ |
| |
| /* MU - Register accessors */ |
| #define MU_TR_REG(base,index) ((base)->TR[index]) |
| #define MU_TR_COUNT 4 |
| #define MU_RR_REG(base,index) ((base)->RR[index]) |
| #define MU_RR_COUNT 4 |
| #define MU_SR_REG(base) ((base)->SR) |
| #define MU_CR_REG(base) ((base)->CR) |
| |
| /*! |
| * @} |
| */ /* end of group MU_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Register_Masks MU Register Masks |
| * @{ |
| */ |
| |
| /* TR Bit Fields */ |
| #define MU_TR_TR0_MASK 0xFFFFFFFFu |
| #define MU_TR_TR0_SHIFT 0 |
| #define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<<MU_TR_TR0_SHIFT))&MU_TR_TR0_MASK) |
| /* RR Bit Fields */ |
| #define MU_RR_RR0_MASK 0xFFFFFFFFu |
| #define MU_RR_RR0_SHIFT 0 |
| #define MU_RR_RR0(x) (((uint32_t)(((uint32_t)(x))<<MU_RR_RR0_SHIFT))&MU_RR_RR0_MASK) |
| /* SR Bit Fields */ |
| #define MU_SR_Fn_MASK 0x7u |
| #define MU_SR_Fn_SHIFT 0 |
| #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_Fn_SHIFT))&MU_SR_Fn_MASK) |
| #define MU_SR_EP_MASK 0x10u |
| #define MU_SR_EP_SHIFT 4 |
| #define MU_SR_PM_MASK 0x60u |
| #define MU_SR_PM_SHIFT 5 |
| #define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_PM_SHIFT))&MU_SR_PM_MASK) |
| #define MU_SR_RS_MASK 0x80u |
| #define MU_SR_RS_SHIFT 7 |
| #define MU_SR_FUP_MASK 0x100u |
| #define MU_SR_FUP_SHIFT 8 |
| #define MU_SR_TEn_MASK 0xF00000u |
| #define MU_SR_TEn_SHIFT 20 |
| #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_TEn_SHIFT))&MU_SR_TEn_MASK) |
| #define MU_SR_RFn_MASK 0xF000000u |
| #define MU_SR_RFn_SHIFT 24 |
| #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_RFn_SHIFT))&MU_SR_RFn_MASK) |
| #define MU_SR_GIPn_MASK 0xF0000000u |
| #define MU_SR_GIPn_SHIFT 28 |
| #define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_GIPn_SHIFT))&MU_SR_GIPn_MASK) |
| /* CR Bit Fields */ |
| #define MU_CR_Fn_MASK 0x7u |
| #define MU_CR_Fn_SHIFT 0 |
| #define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_Fn_SHIFT))&MU_CR_Fn_MASK) |
| #define MU_CR_GIRn_MASK 0xF0000u |
| #define MU_CR_GIRn_SHIFT 16 |
| #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIRn_SHIFT))&MU_CR_GIRn_MASK) |
| #define MU_CR_TIEn_MASK 0xF00000u |
| #define MU_CR_TIEn_SHIFT 20 |
| #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_TIEn_SHIFT))&MU_CR_TIEn_MASK) |
| #define MU_CR_RIEn_MASK 0xF000000u |
| #define MU_CR_RIEn_SHIFT 24 |
| #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_RIEn_SHIFT))&MU_CR_RIEn_MASK) |
| #define MU_CR_GIEn_MASK 0xF0000000u |
| #define MU_CR_GIEn_SHIFT 28 |
| #define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIEn_SHIFT))&MU_CR_GIEn_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group MU_Register_Masks */ |
| |
| /* MU - Peripheral instance base addresses */ |
| /** Peripheral MUB base address */ |
| #define MUB_BASE (0x4229C000u) |
| /** Peripheral MUB base pointer */ |
| #define MUB ((MU_Type *)MUB_BASE) |
| #define MUB_BASE_PTR (MUB) |
| /** Array initializer of MU peripheral base addresses */ |
| #define MU_BASE_ADDRS { MUB_BASE } |
| /** Array initializer of MU peripheral base pointers */ |
| #define MU_BASE_PTRS { MUB } |
| /** Interrupt vectors for the MU peripheral type */ |
| #define MU_IRQS { MU_M4_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- MU - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros |
| * @{ |
| */ |
| |
| /* MU - Register instance definitions */ |
| /* MUB */ |
| #define MUB_TR0 MU_TR_REG(MUB_BASE_PTR,0) |
| #define MUB_TR1 MU_TR_REG(MUB_BASE_PTR,1) |
| #define MUB_TR2 MU_TR_REG(MUB_BASE_PTR,2) |
| #define MUB_TR3 MU_TR_REG(MUB_BASE_PTR,3) |
| #define MUB_RR0 MU_RR_REG(MUB_BASE_PTR,0) |
| #define MUB_RR1 MU_RR_REG(MUB_BASE_PTR,1) |
| #define MUB_RR2 MU_RR_REG(MUB_BASE_PTR,2) |
| #define MUB_RR3 MU_RR_REG(MUB_BASE_PTR,3) |
| #define MUB_SR MU_SR_REG(MUB_BASE_PTR) |
| #define MUB_CR MU_CR_REG(MUB_BASE_PTR) |
| /* MU - Register array accessors */ |
| #define MUB_TR(index) MU_TR_REG(MUB_BASE_PTR,index) |
| #define MUB_RR(index) MU_RR_REG(MUB_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group MU_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group MU_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** OCOTP - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ |
| __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ |
| __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ |
| __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ |
| __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ |
| __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ |
| __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ |
| __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ |
| uint8_t RESERVED_5[32]; |
| __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ |
| uint8_t RESERVED_6[876]; |
| __I uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ |
| uint8_t RESERVED_22[140]; |
| __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ |
| uint8_t RESERVED_23[12]; |
| __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ |
| uint8_t RESERVED_25[12]; |
| __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ |
| uint8_t RESERVED_26[12]; |
| __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ |
| uint8_t RESERVED_28[12]; |
| __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ |
| uint8_t RESERVED_29[12]; |
| __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ |
| uint8_t RESERVED_30[12]; |
| __IO uint32_t RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ |
| uint8_t RESERVED_31[12]; |
| __IO uint32_t HSJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ |
| uint8_t RESERVED_32[12]; |
| __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ |
| uint8_t RESERVED_33[12]; |
| __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ |
| uint8_t RESERVED_34[12]; |
| __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC Address), offset: 0x640 */ |
| uint8_t RESERVED_35[28]; |
| __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (HW Capabilities), offset: 0x660 */ |
| uint8_t RESERVED_36[12]; |
| __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (HW Capabilities), offset: 0x670 */ |
| uint8_t RESERVED_37[92]; |
| __IO uint32_t MISC_CONF; /**< Value of OTP Bank5 Word5 (HW Capabilities), offset: 0x6D0 */ |
| uint8_t RESERVED_38[12]; |
| __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (HW Capabilities), offset: 0x6E0 */ |
| uint8_t RESERVED_39[12]; |
| __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (HW Capabilities), offset: 0x6F0 */ |
| uint8_t RESERVED_40[796]; |
| __IO uint32_t GP30; /**< Value of OTP Bank10 Word1 (General Purpose Customer Defined Info), offset: 0xA10 */ |
| uint8_t RESERVED_41[12]; |
| __IO uint32_t GP31; /**< Value of OTP Bank10 Word2 (General Purpose Customer Defined Info), offset: 0xA20 */ |
| uint8_t RESERVED_42[12]; |
| __IO uint32_t GP32; /**< Value of OTP Bank10 Word3 (General Purpose Customer Defined Info), offset: 0xA30 */ |
| uint8_t RESERVED_43[12]; |
| __IO uint32_t GP33; /**< Value of OTP Bank10 Word4 (General Purpose Customer Defined Info), offset: 0xA40 */ |
| uint8_t RESERVED_44[12]; |
| __IO uint32_t GP34; /**< Value of OTP Bank10 Word5 (General Purpose Customer Defined Info), offset: 0xA50 */ |
| uint8_t RESERVED_45[12]; |
| __IO uint32_t GP35; /**< Value of OTP Bank10 Word6 (General Purpose Customer Defined Info), offset: 0xA60 */ |
| uint8_t RESERVED_46[12]; |
| __IO uint32_t GP36; /**< Value of OTP Bank10 Word7 (General Purpose Customer Defined Info), offset: 0xA70 */ |
| } OCOTP_Type, *OCOTP_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros |
| * @{ |
| */ |
| |
| /* OCOTP - Register accessors */ |
| #define OCOTP_CTRL_REG(base) ((base)->CTRL) |
| #define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) |
| #define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) |
| #define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) |
| #define OCOTP_TIMING_REG(base) ((base)->TIMING) |
| #define OCOTP_DATA_REG(base) ((base)->DATA) |
| #define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) |
| #define OCOTP_READ_FUSE_DATA_REG(base) ((base)->READ_FUSE_DATA) |
| #define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) |
| #define OCOTP_SCS_REG(base) ((base)->SCS) |
| #define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) |
| #define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) |
| #define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) |
| #define OCOTP_VERSION_REG(base) ((base)->VERSION) |
| #define OCOTP_LOCK_REG(base) ((base)->LOCK) |
| #define OCOTP_CFG0_REG(base) ((base)->CFG0) |
| #define OCOTP_CFG1_REG(base) ((base)->CFG1) |
| #define OCOTP_CFG2_REG(base) ((base)->CFG2) |
| #define OCOTP_CFG3_REG(base) ((base)->CFG3) |
| #define OCOTP_CFG4_REG(base) ((base)->CFG4) |
| #define OCOTP_CFG5_REG(base) ((base)->CFG5) |
| #define OCOTP_CFG6_REG(base) ((base)->CFG6) |
| #define OCOTP_MEM0_REG(base) ((base)->MEM0) |
| #define OCOTP_MEM1_REG(base) ((base)->MEM1) |
| #define OCOTP_MEM2_REG(base) ((base)->MEM2) |
| #define OCOTP_MEM3_REG(base) ((base)->MEM3) |
| #define OCOTP_MEM4_REG(base) ((base)->MEM4) |
| #define OCOTP_ANA0_REG(base) ((base)->ANA0) |
| #define OCOTP_ANA1_REG(base) ((base)->ANA1) |
| #define OCOTP_ANA2_REG(base) ((base)->ANA2) |
| #define OCOTP_SRK0_REG(base) ((base)->SRK0) |
| #define OCOTP_SRK1_REG(base) ((base)->SRK1) |
| #define OCOTP_SRK2_REG(base) ((base)->SRK2) |
| #define OCOTP_SRK3_REG(base) ((base)->SRK3) |
| #define OCOTP_SRK4_REG(base) ((base)->SRK4) |
| #define OCOTP_SRK5_REG(base) ((base)->SRK5) |
| #define OCOTP_SRK6_REG(base) ((base)->SRK6) |
| #define OCOTP_SRK7_REG(base) ((base)->SRK7) |
| #define OCOTP_RESP0_REG(base) ((base)->RESP0) |
| #define OCOTP_HSJC_RESP1_REG(base) ((base)->HSJC_RESP1) |
| #define OCOTP_MAC0_REG(base) ((base)->MAC0) |
| #define OCOTP_MAC1_REG(base) ((base)->MAC1) |
| #define OCOTP_MAC2_REG(base) ((base)->MAC2) |
| #define OCOTP_GP1_REG(base) ((base)->GP1) |
| #define OCOTP_GP2_REG(base) ((base)->GP2) |
| #define OCOTP_MISC_CONF_REG(base) ((base)->MISC_CONF) |
| #define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) |
| #define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) |
| #define OCOTP_GP30_REG(base) ((base)->GP30) |
| #define OCOTP_GP31_REG(base) ((base)->GP31) |
| #define OCOTP_GP32_REG(base) ((base)->GP32) |
| #define OCOTP_GP33_REG(base) ((base)->GP33) |
| #define OCOTP_GP34_REG(base) ((base)->GP34) |
| #define OCOTP_GP35_REG(base) ((base)->GP35) |
| #define OCOTP_GP36_REG(base) ((base)->GP36) |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Register_Masks OCOTP Register Masks |
| * @{ |
| */ |
| |
| /* CTRL Bit Fields */ |
| #define OCOTP_CTRL_ADDR_MASK 0x7Fu |
| #define OCOTP_CTRL_ADDR_SHIFT 0 |
| #define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_ADDR_SHIFT))&OCOTP_CTRL_ADDR_MASK) |
| #define OCOTP_CTRL_BUSY_MASK 0x100u |
| #define OCOTP_CTRL_BUSY_SHIFT 8 |
| #define OCOTP_CTRL_ERROR_MASK 0x200u |
| #define OCOTP_CTRL_ERROR_SHIFT 9 |
| #define OCOTP_CTRL_RELOAD_SHADOWS_MASK 0x400u |
| #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT 10 |
| #define OCOTP_CTRL_WR_UNLOCK_MASK 0xFFFF0000u |
| #define OCOTP_CTRL_WR_UNLOCK_SHIFT 16 |
| #define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_WR_UNLOCK_SHIFT))&OCOTP_CTRL_WR_UNLOCK_MASK) |
| /* CTRL_SET Bit Fields */ |
| #define OCOTP_CTRL_SET_ADDR_MASK 0x7Fu |
| #define OCOTP_CTRL_SET_ADDR_SHIFT 0 |
| #define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_ADDR_SHIFT))&OCOTP_CTRL_SET_ADDR_MASK) |
| #define OCOTP_CTRL_SET_BUSY_MASK 0x100u |
| #define OCOTP_CTRL_SET_BUSY_SHIFT 8 |
| #define OCOTP_CTRL_SET_ERROR_MASK 0x200u |
| #define OCOTP_CTRL_SET_ERROR_SHIFT 9 |
| #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK 0x400u |
| #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT 10 |
| #define OCOTP_CTRL_SET_WR_UNLOCK_MASK 0xFFFF0000u |
| #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT 16 |
| #define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_WR_UNLOCK_SHIFT))&OCOTP_CTRL_SET_WR_UNLOCK_MASK) |
| /* CTRL_CLR Bit Fields */ |
| #define OCOTP_CTRL_CLR_ADDR_MASK 0x7Fu |
| #define OCOTP_CTRL_CLR_ADDR_SHIFT 0 |
| #define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_ADDR_SHIFT))&OCOTP_CTRL_CLR_ADDR_MASK) |
| #define OCOTP_CTRL_CLR_BUSY_MASK 0x100u |
| #define OCOTP_CTRL_CLR_BUSY_SHIFT 8 |
| #define OCOTP_CTRL_CLR_ERROR_MASK 0x200u |
| #define OCOTP_CTRL_CLR_ERROR_SHIFT 9 |
| #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK 0x400u |
| #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT 10 |
| #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK 0xFFFF0000u |
| #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT 16 |
| #define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT))&OCOTP_CTRL_CLR_WR_UNLOCK_MASK) |
| /* CTRL_TOG Bit Fields */ |
| #define OCOTP_CTRL_TOG_ADDR_MASK 0x7Fu |
| #define OCOTP_CTRL_TOG_ADDR_SHIFT 0 |
| #define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_ADDR_SHIFT))&OCOTP_CTRL_TOG_ADDR_MASK) |
| #define OCOTP_CTRL_TOG_BUSY_MASK 0x100u |
| #define OCOTP_CTRL_TOG_BUSY_SHIFT 8 |
| #define OCOTP_CTRL_TOG_ERROR_MASK 0x200u |
| #define OCOTP_CTRL_TOG_ERROR_SHIFT 9 |
| #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK 0x400u |
| #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT 10 |
| #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK 0xFFFF0000u |
| #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT 16 |
| #define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT))&OCOTP_CTRL_TOG_WR_UNLOCK_MASK) |
| /* TIMING Bit Fields */ |
| #define OCOTP_TIMING_STROBE_PROG_MASK 0xFFFu |
| #define OCOTP_TIMING_STROBE_PROG_SHIFT 0 |
| #define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_PROG_SHIFT))&OCOTP_TIMING_STROBE_PROG_MASK) |
| #define OCOTP_TIMING_RELAX_MASK 0xF000u |
| #define OCOTP_TIMING_RELAX_SHIFT 12 |
| #define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RELAX_SHIFT))&OCOTP_TIMING_RELAX_MASK) |
| #define OCOTP_TIMING_STROBE_READ_MASK 0x3F0000u |
| #define OCOTP_TIMING_STROBE_READ_SHIFT 16 |
| #define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_STROBE_READ_SHIFT))&OCOTP_TIMING_STROBE_READ_MASK) |
| #define OCOTP_TIMING_WAIT_MASK 0xFC00000u |
| #define OCOTP_TIMING_WAIT_SHIFT 22 |
| #define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_WAIT_SHIFT))&OCOTP_TIMING_WAIT_MASK) |
| /* DATA Bit Fields */ |
| #define OCOTP_DATA_DATA_MASK 0xFFFFFFFFu |
| #define OCOTP_DATA_DATA_SHIFT 0 |
| #define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA_DATA_SHIFT))&OCOTP_DATA_DATA_MASK) |
| /* READ_CTRL Bit Fields */ |
| #define OCOTP_READ_CTRL_READ_FUSE_MASK 0x1u |
| #define OCOTP_READ_CTRL_READ_FUSE_SHIFT 0 |
| /* READ_FUSE_DATA Bit Fields */ |
| #define OCOTP_READ_FUSE_DATA_DATA_MASK 0xFFFFFFFFu |
| #define OCOTP_READ_FUSE_DATA_DATA_SHIFT 0 |
| #define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA_DATA_SHIFT))&OCOTP_READ_FUSE_DATA_DATA_MASK) |
| /* SW_STICKY Bit Fields */ |
| #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK 0x1u |
| #define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT 0 |
| #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK 0x2u |
| #define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT 1 |
| #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK 0x4u |
| #define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT 2 |
| #define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK 0x8u |
| #define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT 3 |
| #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK 0x10u |
| #define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT 4 |
| /* SCS Bit Fields */ |
| #define OCOTP_SCS_HAB_JDE_MASK 0x1u |
| #define OCOTP_SCS_HAB_JDE_SHIFT 0 |
| #define OCOTP_SCS_SPARE_MASK 0x7FFFFFFEu |
| #define OCOTP_SCS_SPARE_SHIFT 1 |
| #define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SPARE_SHIFT))&OCOTP_SCS_SPARE_MASK) |
| #define OCOTP_SCS_LOCK_MASK 0x80000000u |
| #define OCOTP_SCS_LOCK_SHIFT 31 |
| /* SCS_SET Bit Fields */ |
| #define OCOTP_SCS_SET_HAB_JDE_MASK 0x1u |
| #define OCOTP_SCS_SET_HAB_JDE_SHIFT 0 |
| #define OCOTP_SCS_SET_SPARE_MASK 0x7FFFFFFEu |
| #define OCOTP_SCS_SET_SPARE_SHIFT 1 |
| #define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SET_SPARE_SHIFT))&OCOTP_SCS_SET_SPARE_MASK) |
| #define OCOTP_SCS_SET_LOCK_MASK 0x80000000u |
| #define OCOTP_SCS_SET_LOCK_SHIFT 31 |
| /* SCS_CLR Bit Fields */ |
| #define OCOTP_SCS_CLR_HAB_JDE_MASK 0x1u |
| #define OCOTP_SCS_CLR_HAB_JDE_SHIFT 0 |
| #define OCOTP_SCS_CLR_SPARE_MASK 0x7FFFFFFEu |
| #define OCOTP_SCS_CLR_SPARE_SHIFT 1 |
| #define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_CLR_SPARE_SHIFT))&OCOTP_SCS_CLR_SPARE_MASK) |
| #define OCOTP_SCS_CLR_LOCK_MASK 0x80000000u |
| #define OCOTP_SCS_CLR_LOCK_SHIFT 31 |
| /* SCS_TOG Bit Fields */ |
| #define OCOTP_SCS_TOG_HAB_JDE_MASK 0x1u |
| #define OCOTP_SCS_TOG_HAB_JDE_SHIFT 0 |
| #define OCOTP_SCS_TOG_SPARE_MASK 0x7FFFFFFEu |
| #define OCOTP_SCS_TOG_SPARE_SHIFT 1 |
| #define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_TOG_SPARE_SHIFT))&OCOTP_SCS_TOG_SPARE_MASK) |
| #define OCOTP_SCS_TOG_LOCK_MASK 0x80000000u |
| #define OCOTP_SCS_TOG_LOCK_SHIFT 31 |
| /* VERSION Bit Fields */ |
| #define OCOTP_VERSION_STEP_MASK 0xFFFFu |
| #define OCOTP_VERSION_STEP_SHIFT 0 |
| #define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_STEP_SHIFT))&OCOTP_VERSION_STEP_MASK) |
| #define OCOTP_VERSION_MINOR_MASK 0xFF0000u |
| #define OCOTP_VERSION_MINOR_SHIFT 16 |
| #define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MINOR_SHIFT))&OCOTP_VERSION_MINOR_MASK) |
| #define OCOTP_VERSION_MAJOR_MASK 0xFF000000u |
| #define OCOTP_VERSION_MAJOR_SHIFT 24 |
| #define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MAJOR_SHIFT))&OCOTP_VERSION_MAJOR_MASK) |
| /* LOCK Bit Fields */ |
| #define OCOTP_LOCK_TESTER_MASK 0x3u |
| #define OCOTP_LOCK_TESTER_SHIFT 0 |
| #define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_TESTER_SHIFT))&OCOTP_LOCK_TESTER_MASK) |
| #define OCOTP_LOCK_BOOT_CFG_MASK 0xCu |
| #define OCOTP_LOCK_BOOT_CFG_SHIFT 2 |
| #define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_BOOT_CFG_SHIFT))&OCOTP_LOCK_BOOT_CFG_MASK) |
| #define OCOTP_LOCK_MEM_TRIM_MASK 0x30u |
| #define OCOTP_LOCK_MEM_TRIM_SHIFT 4 |
| #define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MEM_TRIM_SHIFT))&OCOTP_LOCK_MEM_TRIM_MASK) |
| #define OCOTP_LOCK_SJC_RESP_MASK 0x40u |
| #define OCOTP_LOCK_SJC_RESP_SHIFT 6 |
| #define OCOTP_LOCK_MAC_ADDR_MASK 0x300u |
| #define OCOTP_LOCK_MAC_ADDR_SHIFT 8 |
| #define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MAC_ADDR_SHIFT))&OCOTP_LOCK_MAC_ADDR_MASK) |
| #define OCOTP_LOCK_GP1_MASK 0xC00u |
| #define OCOTP_LOCK_GP1_SHIFT 10 |
| #define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP1_SHIFT))&OCOTP_LOCK_GP1_MASK) |
| #define OCOTP_LOCK_GP2_MASK 0x3000u |
| #define OCOTP_LOCK_GP2_SHIFT 12 |
| #define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP2_SHIFT))&OCOTP_LOCK_GP2_MASK) |
| #define OCOTP_LOCK_SRK_MASK 0x4000u |
| #define OCOTP_LOCK_SRK_SHIFT 14 |
| #define OCOTP_LOCK_ANALOG_MASK 0xC0000u |
| #define OCOTP_LOCK_ANALOG_SHIFT 18 |
| #define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_ANALOG_SHIFT))&OCOTP_LOCK_ANALOG_MASK) |
| #define OCOTP_LOCK_MISC_CONF_MASK 0x400000u |
| #define OCOTP_LOCK_MISC_CONF_SHIFT 22 |
| #define OCOTP_LOCK_GP3_MASK 0xC0000000u |
| #define OCOTP_LOCK_GP3_SHIFT 30 |
| #define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP3_SHIFT))&OCOTP_LOCK_GP3_MASK) |
| /* CFG0 Bit Fields */ |
| #define OCOTP_CFG0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG0_BITS_SHIFT 0 |
| #define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG0_BITS_SHIFT))&OCOTP_CFG0_BITS_MASK) |
| /* CFG1 Bit Fields */ |
| #define OCOTP_CFG1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG1_BITS_SHIFT 0 |
| #define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG1_BITS_SHIFT))&OCOTP_CFG1_BITS_MASK) |
| /* CFG2 Bit Fields */ |
| #define OCOTP_CFG2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG2_BITS_SHIFT 0 |
| #define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG2_BITS_SHIFT))&OCOTP_CFG2_BITS_MASK) |
| /* CFG3 Bit Fields */ |
| #define OCOTP_CFG3_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG3_BITS_SHIFT 0 |
| #define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG3_BITS_SHIFT))&OCOTP_CFG3_BITS_MASK) |
| /* CFG4 Bit Fields */ |
| #define OCOTP_CFG4_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG4_BITS_SHIFT 0 |
| #define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG4_BITS_SHIFT))&OCOTP_CFG4_BITS_MASK) |
| /* CFG5 Bit Fields */ |
| #define OCOTP_CFG5_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG5_BITS_SHIFT 0 |
| #define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG5_BITS_SHIFT))&OCOTP_CFG5_BITS_MASK) |
| /* CFG6 Bit Fields */ |
| #define OCOTP_CFG6_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_CFG6_BITS_SHIFT 0 |
| #define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CFG6_BITS_SHIFT))&OCOTP_CFG6_BITS_MASK) |
| /* MEM0 Bit Fields */ |
| #define OCOTP_MEM0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MEM0_BITS_SHIFT 0 |
| #define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM0_BITS_SHIFT))&OCOTP_MEM0_BITS_MASK) |
| /* MEM1 Bit Fields */ |
| #define OCOTP_MEM1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MEM1_BITS_SHIFT 0 |
| #define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM1_BITS_SHIFT))&OCOTP_MEM1_BITS_MASK) |
| /* MEM2 Bit Fields */ |
| #define OCOTP_MEM2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MEM2_BITS_SHIFT 0 |
| #define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM2_BITS_SHIFT))&OCOTP_MEM2_BITS_MASK) |
| /* MEM3 Bit Fields */ |
| #define OCOTP_MEM3_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MEM3_BITS_SHIFT 0 |
| #define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM3_BITS_SHIFT))&OCOTP_MEM3_BITS_MASK) |
| /* MEM4 Bit Fields */ |
| #define OCOTP_MEM4_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MEM4_BITS_SHIFT 0 |
| #define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM4_BITS_SHIFT))&OCOTP_MEM4_BITS_MASK) |
| /* ANA0 Bit Fields */ |
| #define OCOTP_ANA0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_ANA0_BITS_SHIFT 0 |
| #define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_BITS_SHIFT))&OCOTP_ANA0_BITS_MASK) |
| /* ANA1 Bit Fields */ |
| #define OCOTP_ANA1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_ANA1_BITS_SHIFT 0 |
| #define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA1_BITS_SHIFT))&OCOTP_ANA1_BITS_MASK) |
| /* ANA2 Bit Fields */ |
| #define OCOTP_ANA2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_ANA2_BITS_SHIFT 0 |
| #define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA2_BITS_SHIFT))&OCOTP_ANA2_BITS_MASK) |
| /* SRK0 Bit Fields */ |
| #define OCOTP_SRK0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK0_BITS_SHIFT 0 |
| #define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK0_BITS_SHIFT))&OCOTP_SRK0_BITS_MASK) |
| /* SRK1 Bit Fields */ |
| #define OCOTP_SRK1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK1_BITS_SHIFT 0 |
| #define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK1_BITS_SHIFT))&OCOTP_SRK1_BITS_MASK) |
| /* SRK2 Bit Fields */ |
| #define OCOTP_SRK2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK2_BITS_SHIFT 0 |
| #define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK2_BITS_SHIFT))&OCOTP_SRK2_BITS_MASK) |
| /* SRK3 Bit Fields */ |
| #define OCOTP_SRK3_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK3_BITS_SHIFT 0 |
| #define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK3_BITS_SHIFT))&OCOTP_SRK3_BITS_MASK) |
| /* SRK4 Bit Fields */ |
| #define OCOTP_SRK4_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK4_BITS_SHIFT 0 |
| #define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK4_BITS_SHIFT))&OCOTP_SRK4_BITS_MASK) |
| /* SRK5 Bit Fields */ |
| #define OCOTP_SRK5_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK5_BITS_SHIFT 0 |
| #define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK5_BITS_SHIFT))&OCOTP_SRK5_BITS_MASK) |
| /* SRK6 Bit Fields */ |
| #define OCOTP_SRK6_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK6_BITS_SHIFT 0 |
| #define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK6_BITS_SHIFT))&OCOTP_SRK6_BITS_MASK) |
| /* SRK7 Bit Fields */ |
| #define OCOTP_SRK7_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK7_BITS_SHIFT 0 |
| #define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK7_BITS_SHIFT))&OCOTP_SRK7_BITS_MASK) |
| /* RESP0 Bit Fields */ |
| #define OCOTP_RESP0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_RESP0_BITS_SHIFT 0 |
| #define OCOTP_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_RESP0_BITS_SHIFT))&OCOTP_RESP0_BITS_MASK) |
| /* HSJC_RESP1 Bit Fields */ |
| #define OCOTP_HSJC_RESP1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_HSJC_RESP1_BITS_SHIFT 0 |
| #define OCOTP_HSJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_HSJC_RESP1_BITS_SHIFT))&OCOTP_HSJC_RESP1_BITS_MASK) |
| /* MAC0 Bit Fields */ |
| #define OCOTP_MAC0_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MAC0_BITS_SHIFT 0 |
| #define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC0_BITS_SHIFT))&OCOTP_MAC0_BITS_MASK) |
| /* MAC1 Bit Fields */ |
| #define OCOTP_MAC1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MAC1_BITS_SHIFT 0 |
| #define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC1_BITS_SHIFT))&OCOTP_MAC1_BITS_MASK) |
| /* MAC2 Bit Fields */ |
| #define OCOTP_MAC2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MAC2_BITS_SHIFT 0 |
| #define OCOTP_MAC2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC2_BITS_SHIFT))&OCOTP_MAC2_BITS_MASK) |
| /* GP1 Bit Fields */ |
| #define OCOTP_GP1_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP1_BITS_SHIFT 0 |
| #define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP1_BITS_SHIFT))&OCOTP_GP1_BITS_MASK) |
| /* GP2 Bit Fields */ |
| #define OCOTP_GP2_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP2_BITS_SHIFT 0 |
| #define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP2_BITS_SHIFT))&OCOTP_GP2_BITS_MASK) |
| /* MISC_CONF Bit Fields */ |
| #define OCOTP_MISC_CONF_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_MISC_CONF_BITS_SHIFT 0 |
| #define OCOTP_MISC_CONF_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MISC_CONF_BITS_SHIFT))&OCOTP_MISC_CONF_BITS_MASK) |
| /* FIELD_RETURN Bit Fields */ |
| #define OCOTP_FIELD_RETURN_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_FIELD_RETURN_BITS_SHIFT 0 |
| #define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_FIELD_RETURN_BITS_SHIFT))&OCOTP_FIELD_RETURN_BITS_MASK) |
| /* SRK_REVOKE Bit Fields */ |
| #define OCOTP_SRK_REVOKE_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_SRK_REVOKE_BITS_SHIFT 0 |
| #define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_BITS_SHIFT))&OCOTP_SRK_REVOKE_BITS_MASK) |
| /* GP30 Bit Fields */ |
| #define OCOTP_GP30_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP30_BITS_SHIFT 0 |
| #define OCOTP_GP30_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP30_BITS_SHIFT))&OCOTP_GP30_BITS_MASK) |
| /* GP31 Bit Fields */ |
| #define OCOTP_GP31_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP31_BITS_SHIFT 0 |
| #define OCOTP_GP31_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP31_BITS_SHIFT))&OCOTP_GP31_BITS_MASK) |
| /* GP32 Bit Fields */ |
| #define OCOTP_GP32_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP32_BITS_SHIFT 0 |
| #define OCOTP_GP32_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP32_BITS_SHIFT))&OCOTP_GP32_BITS_MASK) |
| /* GP33 Bit Fields */ |
| #define OCOTP_GP33_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP33_BITS_SHIFT 0 |
| #define OCOTP_GP33_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP33_BITS_SHIFT))&OCOTP_GP33_BITS_MASK) |
| /* GP34 Bit Fields */ |
| #define OCOTP_GP34_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP34_BITS_SHIFT 0 |
| #define OCOTP_GP34_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP34_BITS_SHIFT))&OCOTP_GP34_BITS_MASK) |
| /* GP35 Bit Fields */ |
| #define OCOTP_GP35_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP35_BITS_SHIFT 0 |
| #define OCOTP_GP35_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP35_BITS_SHIFT))&OCOTP_GP35_BITS_MASK) |
| /* GP36 Bit Fields */ |
| #define OCOTP_GP36_BITS_MASK 0xFFFFFFFFu |
| #define OCOTP_GP36_BITS_SHIFT 0 |
| #define OCOTP_GP36_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP36_BITS_SHIFT))&OCOTP_GP36_BITS_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Register_Masks */ |
| |
| /* OCOTP - Peripheral instance base addresses */ |
| /** Peripheral OCOTP base address */ |
| #define OCOTP_BASE (0x421BC000u) |
| /** Peripheral OCOTP base pointer */ |
| #define OCOTP ((OCOTP_Type *)OCOTP_BASE) |
| #define OCOTP_BASE_PTR (OCOTP) |
| /** Array initializer of OCOTP peripheral base addresses */ |
| #define OCOTP_BASE_ADDRS { OCOTP_BASE } |
| /** Array initializer of OCOTP peripheral base pointers */ |
| #define OCOTP_BASE_PTRS { OCOTP } |
| |
| /* ---------------------------------------------------------------------------- |
| -- OCOTP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros |
| * @{ |
| */ |
| |
| /* OCOTP - Register instance definitions */ |
| /* OCOTP */ |
| #define OCOTP_CTRL OCOTP_CTRL_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CTRL_SET OCOTP_CTRL_SET_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CTRL_CLR OCOTP_CTRL_CLR_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CTRL_TOG OCOTP_CTRL_TOG_REG(OCOTP_BASE_PTR) |
| #define OCOTP_TIMING OCOTP_TIMING_REG(OCOTP_BASE_PTR) |
| #define OCOTP_DATA OCOTP_DATA_REG(OCOTP_BASE_PTR) |
| #define OCOTP_READ_CTRL OCOTP_READ_CTRL_REG(OCOTP_BASE_PTR) |
| #define OCOTP_READ_FUSE_DATA OCOTP_READ_FUSE_DATA_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SW_STICKY OCOTP_SW_STICKY_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SCS OCOTP_SCS_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SCS_SET OCOTP_SCS_SET_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SCS_CLR OCOTP_SCS_CLR_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SCS_TOG OCOTP_SCS_TOG_REG(OCOTP_BASE_PTR) |
| #define OCOTP_VERSION OCOTP_VERSION_REG(OCOTP_BASE_PTR) |
| #define OCOTP_LOCK OCOTP_LOCK_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG0 OCOTP_CFG0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG1 OCOTP_CFG1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG2 OCOTP_CFG2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG3 OCOTP_CFG3_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG4 OCOTP_CFG4_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG5 OCOTP_CFG5_REG(OCOTP_BASE_PTR) |
| #define OCOTP_CFG6 OCOTP_CFG6_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MEM0 OCOTP_MEM0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MEM1 OCOTP_MEM1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MEM2 OCOTP_MEM2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MEM3 OCOTP_MEM3_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MEM4 OCOTP_MEM4_REG(OCOTP_BASE_PTR) |
| #define OCOTP_ANA0 OCOTP_ANA0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_ANA1 OCOTP_ANA1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_ANA2 OCOTP_ANA2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK0 OCOTP_SRK0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK1 OCOTP_SRK1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK2 OCOTP_SRK2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK3 OCOTP_SRK3_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK4 OCOTP_SRK4_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK5 OCOTP_SRK5_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK6 OCOTP_SRK6_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK7 OCOTP_SRK7_REG(OCOTP_BASE_PTR) |
| #define OCOTP_RESP0 OCOTP_RESP0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_HSJC_RESP1 OCOTP_HSJC_RESP1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MAC0 OCOTP_MAC0_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MAC1 OCOTP_MAC1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MAC2 OCOTP_MAC2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP1 OCOTP_GP1_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP2 OCOTP_GP2_REG(OCOTP_BASE_PTR) |
| #define OCOTP_MISC_CONF OCOTP_MISC_CONF_REG(OCOTP_BASE_PTR) |
| #define OCOTP_FIELD_RETURN OCOTP_FIELD_RETURN_REG(OCOTP_BASE_PTR) |
| #define OCOTP_SRK_REVOKE OCOTP_SRK_REVOKE_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP30 OCOTP_GP30_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP31 OCOTP_GP31_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP32 OCOTP_GP32_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP33 OCOTP_GP33_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP34 OCOTP_GP34_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP35 OCOTP_GP35_REG(OCOTP_BASE_PTR) |
| #define OCOTP_GP36 OCOTP_GP36_REG(OCOTP_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group OCOTP_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PGC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** PGC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[512]; |
| __IO uint32_t PCIE_PHY_CTRL; /**< PGC Control Register, offset: 0x200 */ |
| __IO uint32_t PCIE_PHY_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x204 */ |
| __IO uint32_t PCIE_PHY_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x208 */ |
| __IO uint32_t PCIE_PHY_SR; /**< Power Gating Controller Status Register, offset: 0x20C */ |
| uint8_t RESERVED_1[16]; |
| __IO uint32_t MEGA_CTRL; /**< PGC Control Register, offset: 0x220 */ |
| __IO uint32_t MEGA_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x224 */ |
| __IO uint32_t MEGA_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x228 */ |
| __IO uint32_t MEGA_SR; /**< Power Gating Controller Status Register, offset: 0x22C */ |
| uint8_t RESERVED_2[16]; |
| __IO uint32_t DISPLAY_CTRL; /**< PGC Control Register, offset: 0x240 */ |
| __IO uint32_t DISPLAY_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x244 */ |
| __IO uint32_t DISPLAY_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x248 */ |
| __IO uint32_t DISPLAY_SR; /**< Power Gating Controller Status Register, offset: 0x24C */ |
| uint8_t RESERVED_3[16]; |
| __IO uint32_t GPU_CTRL; /**< PGC Control Register, offset: 0x260 */ |
| __IO uint32_t GPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x264 */ |
| __IO uint32_t GPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x268 */ |
| __IO uint32_t GPU_SR; /**< Power Gating Controller Status Register, offset: 0x26C */ |
| uint8_t RESERVED_4[48]; |
| __IO uint32_t CPU_CTRL; /**< PGC Control Register, offset: 0x2A0 */ |
| __IO uint32_t CPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x2A4 */ |
| __IO uint32_t CPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x2A8 */ |
| __IO uint32_t CPU_SR; /**< Power Gating Controller Status Register, offset: 0x2AC */ |
| } PGC_Type, *PGC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- PGC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros |
| * @{ |
| */ |
| |
| /* PGC - Register accessors */ |
| #define PGC_PCIE_PHY_CTRL_REG(base) ((base)->PCIE_PHY_CTRL) |
| #define PGC_PCIE_PHY_PUPSCR_REG(base) ((base)->PCIE_PHY_PUPSCR) |
| #define PGC_PCIE_PHY_PDNSCR_REG(base) ((base)->PCIE_PHY_PDNSCR) |
| #define PGC_PCIE_PHY_SR_REG(base) ((base)->PCIE_PHY_SR) |
| #define PGC_MEGA_CTRL_REG(base) ((base)->MEGA_CTRL) |
| #define PGC_MEGA_PUPSCR_REG(base) ((base)->MEGA_PUPSCR) |
| #define PGC_MEGA_PDNSCR_REG(base) ((base)->MEGA_PDNSCR) |
| #define PGC_MEGA_SR_REG(base) ((base)->MEGA_SR) |
| #define PGC_DISPLAY_CTRL_REG(base) ((base)->DISPLAY_CTRL) |
| #define PGC_DISPLAY_PUPSCR_REG(base) ((base)->DISPLAY_PUPSCR) |
| #define PGC_DISPLAY_PDNSCR_REG(base) ((base)->DISPLAY_PDNSCR) |
| #define PGC_DISPLAY_SR_REG(base) ((base)->DISPLAY_SR) |
| #define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) |
| #define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) |
| #define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) |
| #define PGC_GPU_SR_REG(base) ((base)->GPU_SR) |
| #define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) |
| #define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) |
| #define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) |
| #define PGC_CPU_SR_REG(base) ((base)->CPU_SR) |
| |
| /*! |
| * @} |
| */ /* end of group PGC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PGC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PGC_Register_Masks PGC Register Masks |
| * @{ |
| */ |
| |
| /* PCIE_PHY_CTRL Bit Fields */ |
| #define PGC_PCIE_PHY_CTRL_PCR_MASK 0x1u |
| #define PGC_PCIE_PHY_CTRL_PCR_SHIFT 0 |
| /* PCIE_PHY_PUPSCR Bit Fields */ |
| #define PGC_PCIE_PHY_PUPSCR_SW_MASK 0x3Fu |
| #define PGC_PCIE_PHY_PUPSCR_SW_SHIFT 0 |
| #define PGC_PCIE_PHY_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PUPSCR_SW_SHIFT))&PGC_PCIE_PHY_PUPSCR_SW_MASK) |
| #define PGC_PCIE_PHY_PUPSCR_SW2ISO_MASK 0x3F00u |
| #define PGC_PCIE_PHY_PUPSCR_SW2ISO_SHIFT 8 |
| #define PGC_PCIE_PHY_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PUPSCR_SW2ISO_SHIFT))&PGC_PCIE_PHY_PUPSCR_SW2ISO_MASK) |
| /* PCIE_PHY_PDNSCR Bit Fields */ |
| #define PGC_PCIE_PHY_PDNSCR_ISO_MASK 0x3Fu |
| #define PGC_PCIE_PHY_PDNSCR_ISO_SHIFT 0 |
| #define PGC_PCIE_PHY_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PDNSCR_ISO_SHIFT))&PGC_PCIE_PHY_PDNSCR_ISO_MASK) |
| #define PGC_PCIE_PHY_PDNSCR_ISO2SW_MASK 0x3F00u |
| #define PGC_PCIE_PHY_PDNSCR_ISO2SW_SHIFT 8 |
| #define PGC_PCIE_PHY_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_PCIE_PHY_PDNSCR_ISO2SW_SHIFT))&PGC_PCIE_PHY_PDNSCR_ISO2SW_MASK) |
| /* PCIE_PHY_SR Bit Fields */ |
| #define PGC_PCIE_PHY_SR_PSR_MASK 0x1u |
| #define PGC_PCIE_PHY_SR_PSR_SHIFT 0 |
| /* MEGA_CTRL Bit Fields */ |
| #define PGC_MEGA_CTRL_PCR_MASK 0x1u |
| #define PGC_MEGA_CTRL_PCR_SHIFT 0 |
| /* MEGA_PUPSCR Bit Fields */ |
| #define PGC_MEGA_PUPSCR_SW_MASK 0x3Fu |
| #define PGC_MEGA_PUPSCR_SW_SHIFT 0 |
| #define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PUPSCR_SW_SHIFT))&PGC_MEGA_PUPSCR_SW_MASK) |
| #define PGC_MEGA_PUPSCR_SW2ISO_MASK 0x3F00u |
| #define PGC_MEGA_PUPSCR_SW2ISO_SHIFT 8 |
| #define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PUPSCR_SW2ISO_SHIFT))&PGC_MEGA_PUPSCR_SW2ISO_MASK) |
| /* MEGA_PDNSCR Bit Fields */ |
| #define PGC_MEGA_PDNSCR_ISO_MASK 0x3Fu |
| #define PGC_MEGA_PDNSCR_ISO_SHIFT 0 |
| #define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PDNSCR_ISO_SHIFT))&PGC_MEGA_PDNSCR_ISO_MASK) |
| #define PGC_MEGA_PDNSCR_ISO2SW_MASK 0x3F00u |
| #define PGC_MEGA_PDNSCR_ISO2SW_SHIFT 8 |
| #define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_MEGA_PDNSCR_ISO2SW_SHIFT))&PGC_MEGA_PDNSCR_ISO2SW_MASK) |
| /* MEGA_SR Bit Fields */ |
| #define PGC_MEGA_SR_PSR_MASK 0x1u |
| #define PGC_MEGA_SR_PSR_SHIFT 0 |
| /* DISPLAY_CTRL Bit Fields */ |
| #define PGC_DISPLAY_CTRL_PCR_MASK 0x1u |
| #define PGC_DISPLAY_CTRL_PCR_SHIFT 0 |
| /* DISPLAY_PUPSCR Bit Fields */ |
| #define PGC_DISPLAY_PUPSCR_SW_MASK 0x3Fu |
| #define PGC_DISPLAY_PUPSCR_SW_SHIFT 0 |
| #define PGC_DISPLAY_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PUPSCR_SW_SHIFT))&PGC_DISPLAY_PUPSCR_SW_MASK) |
| #define PGC_DISPLAY_PUPSCR_SW2ISO_MASK 0x3F00u |
| #define PGC_DISPLAY_PUPSCR_SW2ISO_SHIFT 8 |
| #define PGC_DISPLAY_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PUPSCR_SW2ISO_SHIFT))&PGC_DISPLAY_PUPSCR_SW2ISO_MASK) |
| /* DISPLAY_PDNSCR Bit Fields */ |
| #define PGC_DISPLAY_PDNSCR_ISO_MASK 0x3Fu |
| #define PGC_DISPLAY_PDNSCR_ISO_SHIFT 0 |
| #define PGC_DISPLAY_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PDNSCR_ISO_SHIFT))&PGC_DISPLAY_PDNSCR_ISO_MASK) |
| #define PGC_DISPLAY_PDNSCR_ISO2SW_MASK 0x3F00u |
| #define PGC_DISPLAY_PDNSCR_ISO2SW_SHIFT 8 |
| #define PGC_DISPLAY_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_DISPLAY_PDNSCR_ISO2SW_SHIFT))&PGC_DISPLAY_PDNSCR_ISO2SW_MASK) |
| /* DISPLAY_SR Bit Fields */ |
| #define PGC_DISPLAY_SR_PSR_MASK 0x1u |
| #define PGC_DISPLAY_SR_PSR_SHIFT 0 |
| /* GPU_CTRL Bit Fields */ |
| #define PGC_GPU_CTRL_PCR_MASK 0x1u |
| #define PGC_GPU_CTRL_PCR_SHIFT 0 |
| /* GPU_PUPSCR Bit Fields */ |
| #define PGC_GPU_PUPSCR_SW_MASK 0x3Fu |
| #define PGC_GPU_PUPSCR_SW_SHIFT 0 |
| #define PGC_GPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW_SHIFT))&PGC_GPU_PUPSCR_SW_MASK) |
| #define PGC_GPU_PUPSCR_SW2ISO_MASK 0x3F00u |
| #define PGC_GPU_PUPSCR_SW2ISO_SHIFT 8 |
| #define PGC_GPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW2ISO_SHIFT))&PGC_GPU_PUPSCR_SW2ISO_MASK) |
| /* GPU_PDNSCR Bit Fields */ |
| #define PGC_GPU_PDNSCR_ISO_MASK 0x3Fu |
| #define PGC_GPU_PDNSCR_ISO_SHIFT 0 |
| #define PGC_GPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO_SHIFT))&PGC_GPU_PDNSCR_ISO_MASK) |
| #define PGC_GPU_PDNSCR_ISO2SW_MASK 0x3F00u |
| #define PGC_GPU_PDNSCR_ISO2SW_SHIFT 8 |
| #define PGC_GPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO2SW_SHIFT))&PGC_GPU_PDNSCR_ISO2SW_MASK) |
| /* GPU_SR Bit Fields */ |
| #define PGC_GPU_SR_PSR_MASK 0x1u |
| #define PGC_GPU_SR_PSR_SHIFT 0 |
| /* CPU_CTRL Bit Fields */ |
| #define PGC_CPU_CTRL_PCR_MASK 0x1u |
| #define PGC_CPU_CTRL_PCR_SHIFT 0 |
| /* CPU_PUPSCR Bit Fields */ |
| #define PGC_CPU_PUPSCR_SW_MASK 0x3Fu |
| #define PGC_CPU_PUPSCR_SW_SHIFT 0 |
| #define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW_SHIFT))&PGC_CPU_PUPSCR_SW_MASK) |
| #define PGC_CPU_PUPSCR_SW2ISO_MASK 0x3F00u |
| #define PGC_CPU_PUPSCR_SW2ISO_SHIFT 8 |
| #define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW2ISO_SHIFT))&PGC_CPU_PUPSCR_SW2ISO_MASK) |
| /* CPU_PDNSCR Bit Fields */ |
| #define PGC_CPU_PDNSCR_ISO_MASK 0x3Fu |
| #define PGC_CPU_PDNSCR_ISO_SHIFT 0 |
| #define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO_SHIFT))&PGC_CPU_PDNSCR_ISO_MASK) |
| #define PGC_CPU_PDNSCR_ISO2SW_MASK 0x3F00u |
| #define PGC_CPU_PDNSCR_ISO2SW_SHIFT 8 |
| #define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO2SW_SHIFT))&PGC_CPU_PDNSCR_ISO2SW_MASK) |
| /* CPU_SR Bit Fields */ |
| #define PGC_CPU_SR_PSR_MASK 0x1u |
| #define PGC_CPU_SR_PSR_SHIFT 0 |
| |
| /*! |
| * @} |
| */ /* end of group PGC_Register_Masks */ |
| |
| /* PGC - Peripheral instance base addresses */ |
| /** Peripheral PGC_ARM base address */ |
| #define PGC_ARM_BASE (0x420DC040u) |
| /** Peripheral PGC_ARM base pointer */ |
| #define PGC_ARM ((PGC_Type *)PGC_ARM_BASE) |
| #define PGC_ARM_BASE_PTR (PGC_ARM) |
| /** Peripheral PGC_GPU base address */ |
| #define PGC_GPU_BASE (0x420DC000u) |
| /** Peripheral PGC_GPU base pointer */ |
| #define PGC_GPU ((PGC_Type *)PGC_GPU_BASE) |
| #define PGC_GPU_BASE_PTR (PGC_GPU) |
| /** Array initializer of PGC peripheral base addresses */ |
| #define PGC_BASE_ADDRS { PGC_ARM_BASE, PGC_GPU_BASE } |
| /** Array initializer of PGC peripheral base pointers */ |
| #define PGC_BASE_PTRS { PGC_ARM, PGC_GPU } |
| |
| /* ---------------------------------------------------------------------------- |
| -- PGC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros |
| * @{ |
| */ |
| |
| /* PGC - Register instance definitions */ |
| /* PGC_ARM */ |
| #define PGC_ARM_PCIE_PHY_CTRL PGC_PCIE_PHY_CTRL_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_PCIE_PHY_PUPSCR PGC_PCIE_PHY_PUPSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_PCIE_PHY_PDNSCR PGC_PCIE_PHY_PDNSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_PCIE_PHY_SR PGC_PCIE_PHY_SR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_MEGA_CTRL PGC_MEGA_CTRL_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_MEGA_PUPSCR PGC_MEGA_PUPSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_MEGA_PDNSCR PGC_MEGA_PDNSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_MEGA_SR PGC_MEGA_SR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_DISPLAY_CTRL PGC_DISPLAY_CTRL_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_DISPLAY_PUPSCR PGC_DISPLAY_PUPSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_DISPLAY_PDNSCR PGC_DISPLAY_PDNSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_DISPLAY_SR PGC_DISPLAY_SR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_GPU_CTRL PGC_GPU_CTRL_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_GPU_SR PGC_GPU_SR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_CPU_CTRL PGC_CPU_CTRL_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_ARM_BASE_PTR) |
| #define PGC_ARM_CPU_SR PGC_CPU_SR_REG(PGC_ARM_BASE_PTR) |
| /* PGC_GPU */ |
| #define PGC_GPU_PCIE_PHY_CTRL PGC_PCIE_PHY_CTRL_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_PCIE_PHY_PUPSCR PGC_PCIE_PHY_PUPSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_PCIE_PHY_PDNSCR PGC_PCIE_PHY_PDNSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_PCIE_PHY_SR PGC_PCIE_PHY_SR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_MEGA_CTRL PGC_MEGA_CTRL_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_MEGA_PUPSCR PGC_MEGA_PUPSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_MEGA_PDNSCR PGC_MEGA_PDNSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_MEGA_SR PGC_MEGA_SR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_DISPLAY_CTRL PGC_DISPLAY_CTRL_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_DISPLAY_PUPSCR PGC_DISPLAY_PUPSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_DISPLAY_PDNSCR PGC_DISPLAY_PDNSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_DISPLAY_SR PGC_DISPLAY_SR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_GPU_CTRL PGC_GPU_CTRL_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_GPU_SR PGC_GPU_SR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_CPU_CTRL PGC_CPU_CTRL_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_GPU_BASE_PTR) |
| #define PGC_GPU_CPU_SR PGC_CPU_SR_REG(PGC_GPU_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group PGC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group PGC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PMU Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** PMU - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[272]; |
| __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ |
| __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ |
| __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ |
| __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ |
| __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ |
| __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ |
| __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ |
| __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ |
| uint8_t RESERVED_6[240]; |
| __IO uint32_t LOWPWR_CTRL_SET; /**< Low Power Control Register, offset: 0x270 */ |
| __IO uint32_t LOWPWR_CTRL_CLR; /**< Low Power Control Register, offset: 0x274 */ |
| __IO uint32_t LOWPWR_CTRL_TOG; /**< Low Power Control Register, offset: 0x278 */ |
| } PMU_Type, *PMU_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- PMU - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros |
| * @{ |
| */ |
| |
| /* PMU - Register accessors */ |
| #define PMU_REG_1P1_REG(base) ((base)->REG_1P1) |
| #define PMU_REG_3P0_REG(base) ((base)->REG_3P0) |
| #define PMU_REG_2P5_REG(base) ((base)->REG_2P5) |
| #define PMU_REG_CORE_REG(base) ((base)->REG_CORE) |
| #define PMU_MISC0_REG(base) ((base)->MISC0) |
| #define PMU_MISC1_REG(base) ((base)->MISC1) |
| #define PMU_MISC1_SET_REG(base) ((base)->MISC1_SET) |
| #define PMU_MISC1_CLR_REG(base) ((base)->MISC1_CLR) |
| #define PMU_MISC1_TOG_REG(base) ((base)->MISC1_TOG) |
| #define PMU_MISC2_REG(base) ((base)->MISC2) |
| #define PMU_MISC2_SET_REG(base) ((base)->MISC2_SET) |
| #define PMU_MISC2_CLR_REG(base) ((base)->MISC2_CLR) |
| #define PMU_MISC2_TOG_REG(base) ((base)->MISC2_TOG) |
| #define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) |
| #define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) |
| #define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) |
| |
| /*! |
| * @} |
| */ /* end of group PMU_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PMU Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PMU_Register_Masks PMU Register Masks |
| * @{ |
| */ |
| |
| /* REG_1P1 Bit Fields */ |
| #define PMU_REG_1P1_ENABLE_LINREG_MASK 0x1u |
| #define PMU_REG_1P1_ENABLE_LINREG_SHIFT 0 |
| #define PMU_REG_1P1_ENABLE_BO_MASK 0x2u |
| #define PMU_REG_1P1_ENABLE_BO_SHIFT 1 |
| #define PMU_REG_1P1_ENABLE_ILIMIT_MASK 0x4u |
| #define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT 2 |
| #define PMU_REG_1P1_ENABLE_PULLDOWN_MASK 0x8u |
| #define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT 3 |
| #define PMU_REG_1P1_BO_OFFSET_MASK 0x70u |
| #define PMU_REG_1P1_BO_OFFSET_SHIFT 4 |
| #define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P1_BO_OFFSET_SHIFT))&PMU_REG_1P1_BO_OFFSET_MASK) |
| #define PMU_REG_1P1_OUTPUT_TRG_MASK 0x1F00u |
| #define PMU_REG_1P1_OUTPUT_TRG_SHIFT 8 |
| #define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P1_OUTPUT_TRG_SHIFT))&PMU_REG_1P1_OUTPUT_TRG_MASK) |
| #define PMU_REG_1P1_BO_VDD1P1_MASK 0x10000u |
| #define PMU_REG_1P1_BO_VDD1P1_SHIFT 16 |
| #define PMU_REG_1P1_OK_VDD1P1_MASK 0x20000u |
| #define PMU_REG_1P1_OK_VDD1P1_SHIFT 17 |
| #define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK 0x40000u |
| #define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT 18 |
| #define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK 0x80000u |
| #define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT 19 |
| /* REG_3P0 Bit Fields */ |
| #define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u |
| #define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 |
| #define PMU_REG_3P0_ENABLE_BO_MASK 0x2u |
| #define PMU_REG_3P0_ENABLE_BO_SHIFT 1 |
| #define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u |
| #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 |
| #define PMU_REG_3P0_BO_OFFSET_MASK 0x70u |
| #define PMU_REG_3P0_BO_OFFSET_SHIFT 4 |
| #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) |
| #define PMU_REG_3P0_VBUS_SEL_MASK 0x80u |
| #define PMU_REG_3P0_VBUS_SEL_SHIFT 7 |
| #define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u |
| #define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 |
| #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) |
| #define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u |
| #define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 |
| #define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u |
| #define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 |
| /* REG_2P5 Bit Fields */ |
| #define PMU_REG_2P5_ENABLE_LINREG_MASK 0x1u |
| #define PMU_REG_2P5_ENABLE_LINREG_SHIFT 0 |
| #define PMU_REG_2P5_ENABLE_BO_MASK 0x2u |
| #define PMU_REG_2P5_ENABLE_BO_SHIFT 1 |
| #define PMU_REG_2P5_ENABLE_ILIMIT_MASK 0x4u |
| #define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT 2 |
| #define PMU_REG_2P5_ENABLE_PULLDOWN_MASK 0x8u |
| #define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT 3 |
| #define PMU_REG_2P5_BO_OFFSET_MASK 0x70u |
| #define PMU_REG_2P5_BO_OFFSET_SHIFT 4 |
| #define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_2P5_BO_OFFSET_SHIFT))&PMU_REG_2P5_BO_OFFSET_MASK) |
| #define PMU_REG_2P5_OUTPUT_TRG_MASK 0x1F00u |
| #define PMU_REG_2P5_OUTPUT_TRG_SHIFT 8 |
| #define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_2P5_OUTPUT_TRG_SHIFT))&PMU_REG_2P5_OUTPUT_TRG_MASK) |
| #define PMU_REG_2P5_BO_VDD2P5_MASK 0x10000u |
| #define PMU_REG_2P5_BO_VDD2P5_SHIFT 16 |
| #define PMU_REG_2P5_OK_VDD2P5_MASK 0x20000u |
| #define PMU_REG_2P5_OK_VDD2P5_SHIFT 17 |
| #define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK 0x40000u |
| #define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT 18 |
| /* REG_CORE Bit Fields */ |
| #define PMU_REG_CORE_REG0_TARG_MASK 0x1Fu |
| #define PMU_REG_CORE_REG0_TARG_SHIFT 0 |
| #define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG0_TARG_SHIFT))&PMU_REG_CORE_REG0_TARG_MASK) |
| #define PMU_REG_CORE_REG1_TARG_MASK 0x3E00u |
| #define PMU_REG_CORE_REG1_TARG_SHIFT 9 |
| #define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG1_TARG_SHIFT))&PMU_REG_CORE_REG1_TARG_MASK) |
| #define PMU_REG_CORE_REG2_TARG_MASK 0x7C0000u |
| #define PMU_REG_CORE_REG2_TARG_SHIFT 18 |
| #define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_REG2_TARG_SHIFT))&PMU_REG_CORE_REG2_TARG_MASK) |
| #define PMU_REG_CORE_RAMP_RATE_MASK 0x18000000u |
| #define PMU_REG_CORE_RAMP_RATE_SHIFT 27 |
| #define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_CORE_RAMP_RATE_SHIFT))&PMU_REG_CORE_RAMP_RATE_MASK) |
| #define PMU_REG_CORE_FET_ODRIVE_MASK 0x20000000u |
| #define PMU_REG_CORE_FET_ODRIVE_SHIFT 29 |
| /* MISC0 Bit Fields */ |
| #define PMU_MISC0_REFTOP_PWD_MASK 0x1u |
| #define PMU_MISC0_REFTOP_PWD_SHIFT 0 |
| #define PMU_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define PMU_MISC0_REFTOP_VBGADJ_MASK 0x70u |
| #define PMU_MISC0_REFTOP_VBGADJ_SHIFT 4 |
| #define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_REFTOP_VBGADJ_SHIFT))&PMU_MISC0_REFTOP_VBGADJ_MASK) |
| #define PMU_MISC0_REFTOP_VBGUP_MASK 0x80u |
| #define PMU_MISC0_REFTOP_VBGUP_SHIFT 7 |
| #define PMU_MISC0_STOP_MODE_CONFIG_MASK 0xC00u |
| #define PMU_MISC0_STOP_MODE_CONFIG_SHIFT 10 |
| #define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_STOP_MODE_CONFIG_SHIFT))&PMU_MISC0_STOP_MODE_CONFIG_MASK) |
| #define PMU_MISC0_RTC_RINGOSC_EN_MASK 0x1000u |
| #define PMU_MISC0_RTC_RINGOSC_EN_SHIFT 12 |
| #define PMU_MISC0_OSC_I_MASK 0x6000u |
| #define PMU_MISC0_OSC_I_SHIFT 13 |
| #define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_OSC_I_SHIFT))&PMU_MISC0_OSC_I_MASK) |
| #define PMU_MISC0_OSC_XTALOK_MASK 0x8000u |
| #define PMU_MISC0_OSC_XTALOK_SHIFT 15 |
| #define PMU_MISC0_OSC_XTALOK_EN_MASK 0x10000u |
| #define PMU_MISC0_OSC_XTALOK_EN_SHIFT 16 |
| #define PMU_MISC0_CLKGATE_CTRL_MASK 0x2000000u |
| #define PMU_MISC0_CLKGATE_CTRL_SHIFT 25 |
| #define PMU_MISC0_CLKGATE_DELAY_MASK 0x1C000000u |
| #define PMU_MISC0_CLKGATE_DELAY_SHIFT 26 |
| #define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC0_CLKGATE_DELAY_SHIFT))&PMU_MISC0_CLKGATE_DELAY_MASK) |
| #define PMU_MISC0_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT 29 |
| #define PMU_MISC0_XTAL_24M_PWD_MASK 0x40000000u |
| #define PMU_MISC0_XTAL_24M_PWD_SHIFT 30 |
| #define PMU_MISC0_VID_PLL_PREDIV_MASK 0x80000000u |
| #define PMU_MISC0_VID_PLL_PREDIV_SHIFT 31 |
| /* MISC1 Bit Fields */ |
| #define PMU_MISC1_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define PMU_MISC1_LVDS1_CLK_SEL_SHIFT 0 |
| #define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_LVDS1_CLK_SEL_MASK) |
| #define PMU_MISC1_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define PMU_MISC1_LVDS2_CLK_SEL_SHIFT 5 |
| #define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_LVDS2_CLK_SEL_MASK) |
| #define PMU_MISC1_LVDSCLK1_OBEN_MASK 0x400u |
| #define PMU_MISC1_LVDSCLK1_OBEN_SHIFT 10 |
| #define PMU_MISC1_LVDSCLK2_OBEN_MASK 0x800u |
| #define PMU_MISC1_LVDSCLK2_OBEN_SHIFT 11 |
| #define PMU_MISC1_LVDSCLK1_IBEN_MASK 0x1000u |
| #define PMU_MISC1_LVDSCLK1_IBEN_SHIFT 12 |
| #define PMU_MISC1_LVDSCLK2_IBEN_MASK 0x2000u |
| #define PMU_MISC1_LVDSCLK2_IBEN_SHIFT 13 |
| #define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define PMU_MISC1_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define PMU_MISC1_IRQ_TEMPPANIC_SHIFT 27 |
| #define PMU_MISC1_IRQ_TEMPLOW_MASK 0x10000000u |
| #define PMU_MISC1_IRQ_TEMPLOW_SHIFT 28 |
| #define PMU_MISC1_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define PMU_MISC1_IRQ_TEMPHIGH_SHIFT 29 |
| #define PMU_MISC1_IRQ_ANA_BO_MASK 0x40000000u |
| #define PMU_MISC1_IRQ_ANA_BO_SHIFT 30 |
| #define PMU_MISC1_IRQ_DIG_BO_MASK 0x80000000u |
| #define PMU_MISC1_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_SET Bit Fields */ |
| #define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT 0 |
| #define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) |
| #define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT 5 |
| #define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) |
| #define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK 0x400u |
| #define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT 10 |
| #define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK 0x800u |
| #define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT 11 |
| #define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK 0x1000u |
| #define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT 12 |
| #define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK 0x2000u |
| #define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT 13 |
| #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT 27 |
| #define PMU_MISC1_SET_IRQ_TEMPLOW_MASK 0x10000000u |
| #define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT 28 |
| #define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT 29 |
| #define PMU_MISC1_SET_IRQ_ANA_BO_MASK 0x40000000u |
| #define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT 30 |
| #define PMU_MISC1_SET_IRQ_DIG_BO_MASK 0x80000000u |
| #define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_CLR Bit Fields */ |
| #define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT 0 |
| #define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) |
| #define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT 5 |
| #define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) |
| #define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK 0x400u |
| #define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT 10 |
| #define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK 0x800u |
| #define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT 11 |
| #define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK 0x1000u |
| #define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT 12 |
| #define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK 0x2000u |
| #define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT 13 |
| #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT 27 |
| #define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK 0x10000000u |
| #define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT 28 |
| #define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT 29 |
| #define PMU_MISC1_CLR_IRQ_ANA_BO_MASK 0x40000000u |
| #define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT 30 |
| #define PMU_MISC1_CLR_IRQ_DIG_BO_MASK 0x80000000u |
| #define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT 31 |
| /* MISC1_TOG Bit Fields */ |
| #define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK 0x1Fu |
| #define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT 0 |
| #define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT))&PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) |
| #define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK 0x3E0u |
| #define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT 5 |
| #define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT))&PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) |
| #define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK 0x400u |
| #define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT 10 |
| #define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK 0x800u |
| #define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT 11 |
| #define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK 0x1000u |
| #define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT 12 |
| #define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK 0x2000u |
| #define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT 13 |
| #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK 0x10000u |
| #define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT 16 |
| #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK 0x20000u |
| #define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT 17 |
| #define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK 0x8000000u |
| #define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT 27 |
| #define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK 0x10000000u |
| #define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT 28 |
| #define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK 0x20000000u |
| #define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT 29 |
| #define PMU_MISC1_TOG_IRQ_ANA_BO_MASK 0x40000000u |
| #define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT 30 |
| #define PMU_MISC1_TOG_IRQ_DIG_BO_MASK 0x80000000u |
| #define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT 31 |
| /* MISC2 Bit Fields */ |
| #define PMU_MISC2_REG0_BO_OFFSET_MASK 0x7u |
| #define PMU_MISC2_REG0_BO_OFFSET_SHIFT 0 |
| #define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_REG0_BO_OFFSET_MASK) |
| #define PMU_MISC2_REG0_BO_STATUS_MASK 0x8u |
| #define PMU_MISC2_REG0_BO_STATUS_SHIFT 3 |
| #define PMU_MISC2_REG0_ENABLE_BO_MASK 0x20u |
| #define PMU_MISC2_REG0_ENABLE_BO_SHIFT 5 |
| #define PMU_MISC2_PLL3_disable_MASK 0x80u |
| #define PMU_MISC2_PLL3_disable_SHIFT 7 |
| #define PMU_MISC2_REG1_BO_OFFSET_MASK 0x700u |
| #define PMU_MISC2_REG1_BO_OFFSET_SHIFT 8 |
| #define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_REG1_BO_OFFSET_MASK) |
| #define PMU_MISC2_REG1_BO_STATUS_MASK 0x800u |
| #define PMU_MISC2_REG1_BO_STATUS_SHIFT 11 |
| #define PMU_MISC2_REG1_ENABLE_BO_MASK 0x2000u |
| #define PMU_MISC2_REG1_ENABLE_BO_SHIFT 13 |
| #define PMU_MISC2_AUDIO_DIV_LSB_MASK 0x8000u |
| #define PMU_MISC2_AUDIO_DIV_LSB_SHIFT 15 |
| #define PMU_MISC2_REG2_BO_OFFSET_MASK 0x70000u |
| #define PMU_MISC2_REG2_BO_OFFSET_SHIFT 16 |
| #define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_REG2_BO_OFFSET_MASK) |
| #define PMU_MISC2_REG2_BO_STATUS_MASK 0x80000u |
| #define PMU_MISC2_REG2_BO_STATUS_SHIFT 19 |
| #define PMU_MISC2_REG2_ENABLE_BO_MASK 0x200000u |
| #define PMU_MISC2_REG2_ENABLE_BO_SHIFT 21 |
| #define PMU_MISC2_REG2_OK_MASK 0x400000u |
| #define PMU_MISC2_REG2_OK_SHIFT 22 |
| #define PMU_MISC2_AUDIO_DIV_MSB_MASK 0x800000u |
| #define PMU_MISC2_AUDIO_DIV_MSB_SHIFT 23 |
| #define PMU_MISC2_REG0_STEP_TIME_MASK 0x3000000u |
| #define PMU_MISC2_REG0_STEP_TIME_SHIFT 24 |
| #define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG0_STEP_TIME_SHIFT))&PMU_MISC2_REG0_STEP_TIME_MASK) |
| #define PMU_MISC2_REG1_STEP_TIME_MASK 0xC000000u |
| #define PMU_MISC2_REG1_STEP_TIME_SHIFT 26 |
| #define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG1_STEP_TIME_SHIFT))&PMU_MISC2_REG1_STEP_TIME_MASK) |
| #define PMU_MISC2_REG2_STEP_TIME_MASK 0x30000000u |
| #define PMU_MISC2_REG2_STEP_TIME_SHIFT 28 |
| #define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_REG2_STEP_TIME_SHIFT))&PMU_MISC2_REG2_STEP_TIME_MASK) |
| #define PMU_MISC2_VIDEO_DIV_MASK 0xC0000000u |
| #define PMU_MISC2_VIDEO_DIV_SHIFT 30 |
| #define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_VIDEO_DIV_SHIFT))&PMU_MISC2_VIDEO_DIV_MASK) |
| /* MISC2_SET Bit Fields */ |
| #define PMU_MISC2_SET_REG0_BO_OFFSET_MASK 0x7u |
| #define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT 0 |
| #define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG0_BO_OFFSET_MASK) |
| #define PMU_MISC2_SET_REG0_BO_STATUS_MASK 0x8u |
| #define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT 3 |
| #define PMU_MISC2_SET_REG0_ENABLE_BO_MASK 0x20u |
| #define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT 5 |
| #define PMU_MISC2_SET_PLL3_disable_MASK 0x80u |
| #define PMU_MISC2_SET_PLL3_disable_SHIFT 7 |
| #define PMU_MISC2_SET_REG1_BO_OFFSET_MASK 0x700u |
| #define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT 8 |
| #define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG1_BO_OFFSET_MASK) |
| #define PMU_MISC2_SET_REG1_BO_STATUS_MASK 0x800u |
| #define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT 11 |
| #define PMU_MISC2_SET_REG1_ENABLE_BO_MASK 0x2000u |
| #define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT 13 |
| #define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK 0x8000u |
| #define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT 15 |
| #define PMU_MISC2_SET_REG2_BO_OFFSET_MASK 0x70000u |
| #define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT 16 |
| #define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_SET_REG2_BO_OFFSET_MASK) |
| #define PMU_MISC2_SET_REG2_BO_STATUS_MASK 0x80000u |
| #define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT 19 |
| #define PMU_MISC2_SET_REG2_ENABLE_BO_MASK 0x200000u |
| #define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT 21 |
| #define PMU_MISC2_SET_REG2_OK_MASK 0x400000u |
| #define PMU_MISC2_SET_REG2_OK_SHIFT 22 |
| #define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK 0x800000u |
| #define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT 23 |
| #define PMU_MISC2_SET_REG0_STEP_TIME_MASK 0x3000000u |
| #define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT 24 |
| #define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG0_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG0_STEP_TIME_MASK) |
| #define PMU_MISC2_SET_REG1_STEP_TIME_MASK 0xC000000u |
| #define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT 26 |
| #define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG1_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG1_STEP_TIME_MASK) |
| #define PMU_MISC2_SET_REG2_STEP_TIME_MASK 0x30000000u |
| #define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT 28 |
| #define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_REG2_STEP_TIME_SHIFT))&PMU_MISC2_SET_REG2_STEP_TIME_MASK) |
| #define PMU_MISC2_SET_VIDEO_DIV_MASK 0xC0000000u |
| #define PMU_MISC2_SET_VIDEO_DIV_SHIFT 30 |
| #define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_SET_VIDEO_DIV_SHIFT))&PMU_MISC2_SET_VIDEO_DIV_MASK) |
| /* MISC2_CLR Bit Fields */ |
| #define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK 0x7u |
| #define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT 0 |
| #define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) |
| #define PMU_MISC2_CLR_REG0_BO_STATUS_MASK 0x8u |
| #define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT 3 |
| #define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK 0x20u |
| #define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT 5 |
| #define PMU_MISC2_CLR_PLL3_disable_MASK 0x80u |
| #define PMU_MISC2_CLR_PLL3_disable_SHIFT 7 |
| #define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK 0x700u |
| #define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT 8 |
| #define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) |
| #define PMU_MISC2_CLR_REG1_BO_STATUS_MASK 0x800u |
| #define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT 11 |
| #define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK 0x2000u |
| #define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT 13 |
| #define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK 0x8000u |
| #define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT 15 |
| #define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK 0x70000u |
| #define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT 16 |
| #define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) |
| #define PMU_MISC2_CLR_REG2_BO_STATUS_MASK 0x80000u |
| #define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT 19 |
| #define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK 0x200000u |
| #define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT 21 |
| #define PMU_MISC2_CLR_REG2_OK_MASK 0x400000u |
| #define PMU_MISC2_CLR_REG2_OK_SHIFT 22 |
| #define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK 0x800000u |
| #define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT 23 |
| #define PMU_MISC2_CLR_REG0_STEP_TIME_MASK 0x3000000u |
| #define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT 24 |
| #define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG0_STEP_TIME_MASK) |
| #define PMU_MISC2_CLR_REG1_STEP_TIME_MASK 0xC000000u |
| #define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT 26 |
| #define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG1_STEP_TIME_MASK) |
| #define PMU_MISC2_CLR_REG2_STEP_TIME_MASK 0x30000000u |
| #define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT 28 |
| #define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT))&PMU_MISC2_CLR_REG2_STEP_TIME_MASK) |
| #define PMU_MISC2_CLR_VIDEO_DIV_MASK 0xC0000000u |
| #define PMU_MISC2_CLR_VIDEO_DIV_SHIFT 30 |
| #define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_CLR_VIDEO_DIV_SHIFT))&PMU_MISC2_CLR_VIDEO_DIV_MASK) |
| /* MISC2_TOG Bit Fields */ |
| #define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK 0x7u |
| #define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT 0 |
| #define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) |
| #define PMU_MISC2_TOG_REG0_BO_STATUS_MASK 0x8u |
| #define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT 3 |
| #define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK 0x20u |
| #define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT 5 |
| #define PMU_MISC2_TOG_PLL3_disable_MASK 0x80u |
| #define PMU_MISC2_TOG_PLL3_disable_SHIFT 7 |
| #define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK 0x700u |
| #define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT 8 |
| #define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) |
| #define PMU_MISC2_TOG_REG1_BO_STATUS_MASK 0x800u |
| #define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT 11 |
| #define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK 0x2000u |
| #define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT 13 |
| #define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK 0x8000u |
| #define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT 15 |
| #define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK 0x70000u |
| #define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT 16 |
| #define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT))&PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) |
| #define PMU_MISC2_TOG_REG2_BO_STATUS_MASK 0x80000u |
| #define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT 19 |
| #define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK 0x200000u |
| #define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT 21 |
| #define PMU_MISC2_TOG_REG2_OK_MASK 0x400000u |
| #define PMU_MISC2_TOG_REG2_OK_SHIFT 22 |
| #define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK 0x800000u |
| #define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT 23 |
| #define PMU_MISC2_TOG_REG0_STEP_TIME_MASK 0x3000000u |
| #define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT 24 |
| #define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG0_STEP_TIME_MASK) |
| #define PMU_MISC2_TOG_REG1_STEP_TIME_MASK 0xC000000u |
| #define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT 26 |
| #define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG1_STEP_TIME_MASK) |
| #define PMU_MISC2_TOG_REG2_STEP_TIME_MASK 0x30000000u |
| #define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT 28 |
| #define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT))&PMU_MISC2_TOG_REG2_STEP_TIME_MASK) |
| #define PMU_MISC2_TOG_VIDEO_DIV_MASK 0xC0000000u |
| #define PMU_MISC2_TOG_VIDEO_DIV_SHIFT 30 |
| #define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x))<<PMU_MISC2_TOG_VIDEO_DIV_SHIFT))&PMU_MISC2_TOG_VIDEO_DIV_MASK) |
| /* LOWPWR_CTRL_SET Bit Fields */ |
| #define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK 0x1u |
| #define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT 0 |
| #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK 0xEu |
| #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT 1 |
| #define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) |
| #define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK 0x10u |
| #define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT 4 |
| #define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK 0x20u |
| #define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT 5 |
| #define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK 0x40u |
| #define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT 6 |
| #define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u |
| #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 |
| #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u |
| #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 |
| #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u |
| #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 |
| #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u |
| #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 |
| #define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) |
| #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x20000u |
| #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 17 |
| #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x40000u |
| #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 18 |
| /* LOWPWR_CTRL_CLR Bit Fields */ |
| #define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK 0x1u |
| #define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT 0 |
| #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK 0xEu |
| #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT 1 |
| #define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) |
| #define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK 0x10u |
| #define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT 4 |
| #define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK 0x20u |
| #define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT 5 |
| #define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK 0x40u |
| #define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT 6 |
| #define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u |
| #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 |
| #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u |
| #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 |
| #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u |
| #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 |
| #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u |
| #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 |
| #define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) |
| #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x20000u |
| #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 17 |
| #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x40000u |
| #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 18 |
| /* LOWPWR_CTRL_TOG Bit Fields */ |
| #define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK 0x1u |
| #define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT 0 |
| #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK 0xEu |
| #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT 1 |
| #define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT))&PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) |
| #define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK 0x10u |
| #define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT 4 |
| #define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK 0x20u |
| #define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT 5 |
| #define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK 0x40u |
| #define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT 6 |
| #define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u |
| #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 |
| #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u |
| #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 |
| #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u |
| #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 |
| #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u |
| #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 |
| #define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) |
| #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x20000u |
| #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 17 |
| #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x40000u |
| #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 18 |
| |
| /*! |
| * @} |
| */ /* end of group PMU_Register_Masks */ |
| |
| /* PMU - Peripheral instance base addresses */ |
| /** Peripheral PMU base address */ |
| #define PMU_BASE (0x420C8000u) |
| /** Peripheral PMU base pointer */ |
| #define PMU ((PMU_Type *)PMU_BASE) |
| #define PMU_BASE_PTR (PMU) |
| /** Array initializer of PMU peripheral base addresses */ |
| #define PMU_BASE_ADDRS { PMU_BASE } |
| /** Array initializer of PMU peripheral base pointers */ |
| #define PMU_BASE_PTRS { PMU } |
| /** Interrupt vectors for the PMU peripheral type */ |
| #define PMU_IRQS { PMU1_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- PMU - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros |
| * @{ |
| */ |
| |
| /* PMU - Register instance definitions */ |
| /* PMU */ |
| #define PMU_REG_1P1 PMU_REG_1P1_REG(PMU_BASE_PTR) |
| #define PMU_REG_3P0 PMU_REG_3P0_REG(PMU_BASE_PTR) |
| #define PMU_REG_2P5 PMU_REG_2P5_REG(PMU_BASE_PTR) |
| #define PMU_REG_CORE PMU_REG_CORE_REG(PMU_BASE_PTR) |
| #define PMU_MISC0 PMU_MISC0_REG(PMU_BASE_PTR) |
| #define PMU_MISC1 PMU_MISC1_REG(PMU_BASE_PTR) |
| #define PMU_MISC1_SET PMU_MISC1_SET_REG(PMU_BASE_PTR) |
| #define PMU_MISC1_CLR PMU_MISC1_CLR_REG(PMU_BASE_PTR) |
| #define PMU_MISC1_TOG PMU_MISC1_TOG_REG(PMU_BASE_PTR) |
| #define PMU_MISC2 PMU_MISC2_REG(PMU_BASE_PTR) |
| #define PMU_MISC2_SET PMU_MISC2_SET_REG(PMU_BASE_PTR) |
| #define PMU_MISC2_CLR PMU_MISC2_CLR_REG(PMU_BASE_PTR) |
| #define PMU_MISC2_TOG PMU_MISC2_TOG_REG(PMU_BASE_PTR) |
| #define PMU_LOWPWR_CTRL_SET PMU_LOWPWR_CTRL_SET_REG(PMU_BASE_PTR) |
| #define PMU_LOWPWR_CTRL_CLR PMU_LOWPWR_CTRL_CLR_REG(PMU_BASE_PTR) |
| #define PMU_LOWPWR_CTRL_TOG PMU_LOWPWR_CTRL_TOG_REG(PMU_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group PMU_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group PMU_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** PWM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ |
| __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ |
| __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ |
| __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ |
| __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ |
| __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ |
| } PWM_Type, *PWM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros |
| * @{ |
| */ |
| |
| /* PWM - Register accessors */ |
| #define PWM_PWMCR_REG(base) ((base)->PWMCR) |
| #define PWM_PWMSR_REG(base) ((base)->PWMSR) |
| #define PWM_PWMIR_REG(base) ((base)->PWMIR) |
| #define PWM_PWMSAR_REG(base) ((base)->PWMSAR) |
| #define PWM_PWMPR_REG(base) ((base)->PWMPR) |
| #define PWM_PWMCNR_REG(base) ((base)->PWMCNR) |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Register_Masks PWM Register Masks |
| * @{ |
| */ |
| |
| /* PWMCR Bit Fields */ |
| #define PWM_PWMCR_EN_MASK 0x1u |
| #define PWM_PWMCR_EN_SHIFT 0 |
| #define PWM_PWMCR_REPEAT_MASK 0x6u |
| #define PWM_PWMCR_REPEAT_SHIFT 1 |
| #define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_REPEAT_SHIFT))&PWM_PWMCR_REPEAT_MASK) |
| #define PWM_PWMCR_SWR_MASK 0x8u |
| #define PWM_PWMCR_SWR_SHIFT 3 |
| #define PWM_PWMCR_PRESCALER_MASK 0xFFF0u |
| #define PWM_PWMCR_PRESCALER_SHIFT 4 |
| #define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_PRESCALER_SHIFT))&PWM_PWMCR_PRESCALER_MASK) |
| #define PWM_PWMCR_CLKSRC_MASK 0x30000u |
| #define PWM_PWMCR_CLKSRC_SHIFT 16 |
| #define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_CLKSRC_SHIFT))&PWM_PWMCR_CLKSRC_MASK) |
| #define PWM_PWMCR_POUTC_MASK 0xC0000u |
| #define PWM_PWMCR_POUTC_SHIFT 18 |
| #define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_POUTC_SHIFT))&PWM_PWMCR_POUTC_MASK) |
| #define PWM_PWMCR_HCTR_MASK 0x100000u |
| #define PWM_PWMCR_HCTR_SHIFT 20 |
| #define PWM_PWMCR_BCTR_MASK 0x200000u |
| #define PWM_PWMCR_BCTR_SHIFT 21 |
| #define PWM_PWMCR_DBGEN_MASK 0x400000u |
| #define PWM_PWMCR_DBGEN_SHIFT 22 |
| #define PWM_PWMCR_WAITEN_MASK 0x800000u |
| #define PWM_PWMCR_WAITEN_SHIFT 23 |
| #define PWM_PWMCR_DOZEN_MASK 0x1000000u |
| #define PWM_PWMCR_DOZEN_SHIFT 24 |
| #define PWM_PWMCR_STOPEN_MASK 0x2000000u |
| #define PWM_PWMCR_STOPEN_SHIFT 25 |
| #define PWM_PWMCR_FWM_MASK 0xC000000u |
| #define PWM_PWMCR_FWM_SHIFT 26 |
| #define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_FWM_SHIFT))&PWM_PWMCR_FWM_MASK) |
| /* PWMSR Bit Fields */ |
| #define PWM_PWMSR_FIFOAV_MASK 0x7u |
| #define PWM_PWMSR_FIFOAV_SHIFT 0 |
| #define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMSR_FIFOAV_SHIFT))&PWM_PWMSR_FIFOAV_MASK) |
| #define PWM_PWMSR_FE_MASK 0x8u |
| #define PWM_PWMSR_FE_SHIFT 3 |
| #define PWM_PWMSR_ROV_MASK 0x10u |
| #define PWM_PWMSR_ROV_SHIFT 4 |
| #define PWM_PWMSR_CMP_MASK 0x20u |
| #define PWM_PWMSR_CMP_SHIFT 5 |
| #define PWM_PWMSR_FWE_MASK 0x40u |
| #define PWM_PWMSR_FWE_SHIFT 6 |
| /* PWMIR Bit Fields */ |
| #define PWM_PWMIR_FIE_MASK 0x1u |
| #define PWM_PWMIR_FIE_SHIFT 0 |
| #define PWM_PWMIR_RIE_MASK 0x2u |
| #define PWM_PWMIR_RIE_SHIFT 1 |
| #define PWM_PWMIR_CIE_MASK 0x4u |
| #define PWM_PWMIR_CIE_SHIFT 2 |
| /* PWMSAR Bit Fields */ |
| #define PWM_PWMSAR_SAMPLE_MASK 0xFFFFu |
| #define PWM_PWMSAR_SAMPLE_SHIFT 0 |
| #define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMSAR_SAMPLE_SHIFT))&PWM_PWMSAR_SAMPLE_MASK) |
| /* PWMPR Bit Fields */ |
| #define PWM_PWMPR_PERIOD_MASK 0xFFFFu |
| #define PWM_PWMPR_PERIOD_SHIFT 0 |
| #define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMPR_PERIOD_SHIFT))&PWM_PWMPR_PERIOD_MASK) |
| /* PWMCNR Bit Fields */ |
| #define PWM_PWMCNR_COUNT_MASK 0xFFFFu |
| #define PWM_PWMCNR_COUNT_SHIFT 0 |
| #define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCNR_COUNT_SHIFT))&PWM_PWMCNR_COUNT_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Register_Masks */ |
| |
| /* PWM - Peripheral instance base addresses */ |
| /** Peripheral PWM1 base address */ |
| #define PWM1_BASE (0x42080000u) |
| /** Peripheral PWM1 base pointer */ |
| #define PWM1 ((PWM_Type *)PWM1_BASE) |
| #define PWM1_BASE_PTR (PWM1) |
| /** Peripheral PWM2 base address */ |
| #define PWM2_BASE (0x42084000u) |
| /** Peripheral PWM2 base pointer */ |
| #define PWM2 ((PWM_Type *)PWM2_BASE) |
| #define PWM2_BASE_PTR (PWM2) |
| /** Peripheral PWM3 base address */ |
| #define PWM3_BASE (0x42088000u) |
| /** Peripheral PWM3 base pointer */ |
| #define PWM3 ((PWM_Type *)PWM3_BASE) |
| #define PWM3_BASE_PTR (PWM3) |
| /** Peripheral PWM4 base address */ |
| #define PWM4_BASE (0x4208C000u) |
| /** Peripheral PWM4 base pointer */ |
| #define PWM4 ((PWM_Type *)PWM4_BASE) |
| #define PWM4_BASE_PTR (PWM4) |
| /** Peripheral PWM5 base address */ |
| #define PWM5_BASE (0x422A4000u) |
| /** Peripheral PWM5 base pointer */ |
| #define PWM5 ((PWM_Type *)PWM5_BASE) |
| #define PWM5_BASE_PTR (PWM5) |
| /** Peripheral PWM6 base address */ |
| #define PWM6_BASE (0x422A8000u) |
| /** Peripheral PWM6 base pointer */ |
| #define PWM6 ((PWM_Type *)PWM6_BASE) |
| #define PWM6_BASE_PTR (PWM6) |
| /** Peripheral PWM7 base address */ |
| #define PWM7_BASE (0x422AC000u) |
| /** Peripheral PWM7 base pointer */ |
| #define PWM7 ((PWM_Type *)PWM7_BASE) |
| #define PWM7_BASE_PTR (PWM7) |
| /** Peripheral PWM8 base address */ |
| #define PWM8_BASE (0x422B0000u) |
| /** Peripheral PWM8 base pointer */ |
| #define PWM8 ((PWM_Type *)PWM8_BASE) |
| #define PWM8_BASE_PTR (PWM8) |
| /** Array initializer of PWM peripheral base addresses */ |
| #define PWM_BASE_ADDRS { PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE } |
| /** Array initializer of PWM peripheral base pointers */ |
| #define PWM_BASE_PTRS { PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 } |
| |
| /* ---------------------------------------------------------------------------- |
| -- PWM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros |
| * @{ |
| */ |
| |
| /* PWM - Register instance definitions */ |
| /* PWM1 */ |
| #define PWM1_PWMCR PWM_PWMCR_REG(PWM1_BASE_PTR) |
| #define PWM1_PWMSR PWM_PWMSR_REG(PWM1_BASE_PTR) |
| #define PWM1_PWMIR PWM_PWMIR_REG(PWM1_BASE_PTR) |
| #define PWM1_PWMSAR PWM_PWMSAR_REG(PWM1_BASE_PTR) |
| #define PWM1_PWMPR PWM_PWMPR_REG(PWM1_BASE_PTR) |
| #define PWM1_PWMCNR PWM_PWMCNR_REG(PWM1_BASE_PTR) |
| /* PWM2 */ |
| #define PWM2_PWMCR PWM_PWMCR_REG(PWM2_BASE_PTR) |
| #define PWM2_PWMSR PWM_PWMSR_REG(PWM2_BASE_PTR) |
| #define PWM2_PWMIR PWM_PWMIR_REG(PWM2_BASE_PTR) |
| #define PWM2_PWMSAR PWM_PWMSAR_REG(PWM2_BASE_PTR) |
| #define PWM2_PWMPR PWM_PWMPR_REG(PWM2_BASE_PTR) |
| #define PWM2_PWMCNR PWM_PWMCNR_REG(PWM2_BASE_PTR) |
| /* PWM3 */ |
| #define PWM3_PWMCR PWM_PWMCR_REG(PWM3_BASE_PTR) |
| #define PWM3_PWMSR PWM_PWMSR_REG(PWM3_BASE_PTR) |
| #define PWM3_PWMIR PWM_PWMIR_REG(PWM3_BASE_PTR) |
| #define PWM3_PWMSAR PWM_PWMSAR_REG(PWM3_BASE_PTR) |
| #define PWM3_PWMPR PWM_PWMPR_REG(PWM3_BASE_PTR) |
| #define PWM3_PWMCNR PWM_PWMCNR_REG(PWM3_BASE_PTR) |
| /* PWM4 */ |
| #define PWM4_PWMCR PWM_PWMCR_REG(PWM4_BASE_PTR) |
| #define PWM4_PWMSR PWM_PWMSR_REG(PWM4_BASE_PTR) |
| #define PWM4_PWMIR PWM_PWMIR_REG(PWM4_BASE_PTR) |
| #define PWM4_PWMSAR PWM_PWMSAR_REG(PWM4_BASE_PTR) |
| #define PWM4_PWMPR PWM_PWMPR_REG(PWM4_BASE_PTR) |
| #define PWM4_PWMCNR PWM_PWMCNR_REG(PWM4_BASE_PTR) |
| /* PWM5 */ |
| #define PWM5_PWMCR PWM_PWMCR_REG(PWM5_BASE_PTR) |
| #define PWM5_PWMSR PWM_PWMSR_REG(PWM5_BASE_PTR) |
| #define PWM5_PWMIR PWM_PWMIR_REG(PWM5_BASE_PTR) |
| #define PWM5_PWMSAR PWM_PWMSAR_REG(PWM5_BASE_PTR) |
| #define PWM5_PWMPR PWM_PWMPR_REG(PWM5_BASE_PTR) |
| #define PWM5_PWMCNR PWM_PWMCNR_REG(PWM5_BASE_PTR) |
| /* PWM6 */ |
| #define PWM6_PWMCR PWM_PWMCR_REG(PWM6_BASE_PTR) |
| #define PWM6_PWMSR PWM_PWMSR_REG(PWM6_BASE_PTR) |
| #define PWM6_PWMIR PWM_PWMIR_REG(PWM6_BASE_PTR) |
| #define PWM6_PWMSAR PWM_PWMSAR_REG(PWM6_BASE_PTR) |
| #define PWM6_PWMPR PWM_PWMPR_REG(PWM6_BASE_PTR) |
| #define PWM6_PWMCNR PWM_PWMCNR_REG(PWM6_BASE_PTR) |
| /* PWM7 */ |
| #define PWM7_PWMCR PWM_PWMCR_REG(PWM7_BASE_PTR) |
| #define PWM7_PWMSR PWM_PWMSR_REG(PWM7_BASE_PTR) |
| #define PWM7_PWMIR PWM_PWMIR_REG(PWM7_BASE_PTR) |
| #define PWM7_PWMSAR PWM_PWMSAR_REG(PWM7_BASE_PTR) |
| #define PWM7_PWMPR PWM_PWMPR_REG(PWM7_BASE_PTR) |
| #define PWM7_PWMCNR PWM_PWMCNR_REG(PWM7_BASE_PTR) |
| /* PWM8 */ |
| #define PWM8_PWMCR PWM_PWMCR_REG(PWM8_BASE_PTR) |
| #define PWM8_PWMSR PWM_PWMSR_REG(PWM8_BASE_PTR) |
| #define PWM8_PWMIR PWM_PWMIR_REG(PWM8_BASE_PTR) |
| #define PWM8_PWMSAR PWM_PWMSAR_REG(PWM8_BASE_PTR) |
| #define PWM8_PWMPR PWM_PWMPR_REG(PWM8_BASE_PTR) |
| #define PWM8_PWMCNR PWM_PWMCNR_REG(PWM8_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group PWM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PXP Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** PXP - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ |
| uint8_t RESERVED_4[12]; |
| __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ |
| uint8_t RESERVED_5[12]; |
| __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ |
| uint8_t RESERVED_6[12]; |
| __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ |
| uint8_t RESERVED_7[12]; |
| __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ |
| uint8_t RESERVED_8[12]; |
| __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ |
| uint8_t RESERVED_9[12]; |
| __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ |
| uint8_t RESERVED_10[12]; |
| __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ |
| uint8_t RESERVED_11[12]; |
| __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ |
| uint8_t RESERVED_12[12]; |
| __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ |
| uint8_t RESERVED_13[12]; |
| __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ |
| uint8_t RESERVED_14[12]; |
| __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ |
| uint8_t RESERVED_15[12]; |
| __IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */ |
| uint8_t RESERVED_16[12]; |
| __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ |
| uint8_t RESERVED_17[12]; |
| __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ |
| uint8_t RESERVED_18[12]; |
| __IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */ |
| uint8_t RESERVED_19[12]; |
| __IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */ |
| uint8_t RESERVED_20[12]; |
| __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ |
| uint8_t RESERVED_21[12]; |
| __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ |
| uint8_t RESERVED_22[12]; |
| __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ |
| uint8_t RESERVED_23[12]; |
| __IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */ |
| uint8_t RESERVED_24[12]; |
| __IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */ |
| uint8_t RESERVED_25[12]; |
| __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ |
| uint8_t RESERVED_26[12]; |
| __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ |
| uint8_t RESERVED_27[12]; |
| __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ |
| uint8_t RESERVED_28[12]; |
| __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ |
| uint8_t RESERVED_29[12]; |
| __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ |
| uint8_t RESERVED_30[12]; |
| __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ |
| uint8_t RESERVED_31[12]; |
| __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ |
| uint8_t RESERVED_32[12]; |
| __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ |
| uint8_t RESERVED_33[12]; |
| __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ |
| uint8_t RESERVED_34[12]; |
| __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ |
| uint8_t RESERVED_35[12]; |
| __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ |
| uint8_t RESERVED_36[12]; |
| __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ |
| uint8_t RESERVED_37[12]; |
| __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ |
| uint8_t RESERVED_38[12]; |
| __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ |
| uint8_t RESERVED_39[12]; |
| __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ |
| uint8_t RESERVED_40[12]; |
| __IO uint32_t HIST_CTRL; /**< Histogram Control Register., offset: 0x290 */ |
| uint8_t RESERVED_41[12]; |
| __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2A0 */ |
| uint8_t RESERVED_42[12]; |
| __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B0 */ |
| uint8_t RESERVED_43[12]; |
| __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2C0 */ |
| uint8_t RESERVED_44[12]; |
| __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2D0 */ |
| uint8_t RESERVED_45[12]; |
| __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2E0 */ |
| uint8_t RESERVED_46[12]; |
| __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2F0 */ |
| uint8_t RESERVED_47[12]; |
| __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x300 */ |
| uint8_t RESERVED_48[12]; |
| __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x310 */ |
| uint8_t RESERVED_49[12]; |
| __IO uint32_t POWER; /**< PXP Power Control Register., offset: 0x320 */ |
| uint8_t RESERVED_50[220]; |
| __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ |
| } PXP_Type, *PXP_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- PXP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros |
| * @{ |
| */ |
| |
| /* PXP - Register accessors */ |
| #define PXP_CTRL_REG(base) ((base)->CTRL) |
| #define PXP_STAT_REG(base) ((base)->STAT) |
| #define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) |
| #define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) |
| #define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) |
| #define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) |
| #define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) |
| #define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) |
| #define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) |
| #define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) |
| #define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) |
| #define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) |
| #define PXP_PS_BUF_REG(base) ((base)->PS_BUF) |
| #define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) |
| #define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) |
| #define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) |
| #define PXP_PS_BACKGROUND_REG(base) ((base)->PS_BACKGROUND) |
| #define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) |
| #define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) |
| #define PXP_PS_CLRKEYLOW_REG(base) ((base)->PS_CLRKEYLOW) |
| #define PXP_PS_CLRKEYHIGH_REG(base) ((base)->PS_CLRKEYHIGH) |
| #define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) |
| #define PXP_AS_BUF_REG(base) ((base)->AS_BUF) |
| #define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) |
| #define PXP_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) |
| #define PXP_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) |
| #define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) |
| #define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) |
| #define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) |
| #define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) |
| #define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) |
| #define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) |
| #define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) |
| #define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) |
| #define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) |
| #define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) |
| #define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) |
| #define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) |
| #define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) |
| #define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) |
| #define PXP_CFA_REG(base) ((base)->CFA) |
| #define PXP_HIST_CTRL_REG(base) ((base)->HIST_CTRL) |
| #define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) |
| #define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) |
| #define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) |
| #define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) |
| #define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) |
| #define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) |
| #define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) |
| #define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) |
| #define PXP_POWER_REG(base) ((base)->POWER) |
| #define PXP_NEXT_REG(base) ((base)->NEXT) |
| |
| /*! |
| * @} |
| */ /* end of group PXP_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- PXP Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PXP_Register_Masks PXP Register Masks |
| * @{ |
| */ |
| |
| /* CTRL Bit Fields */ |
| #define PXP_CTRL_ENABLE_MASK 0x1u |
| #define PXP_CTRL_ENABLE_SHIFT 0 |
| #define PXP_CTRL_IRQ_ENABLE_MASK 0x2u |
| #define PXP_CTRL_IRQ_ENABLE_SHIFT 1 |
| #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u |
| #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 |
| #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u |
| #define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 |
| #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK 0x10u |
| #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT 4 |
| #define PXP_CTRL_RSVD0_MASK 0xE0u |
| #define PXP_CTRL_RSVD0_SHIFT 5 |
| #define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD0_SHIFT))&PXP_CTRL_RSVD0_MASK) |
| #define PXP_CTRL_ROTATE_MASK 0x300u |
| #define PXP_CTRL_ROTATE_SHIFT 8 |
| #define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE_SHIFT))&PXP_CTRL_ROTATE_MASK) |
| #define PXP_CTRL_HFLIP_MASK 0x400u |
| #define PXP_CTRL_HFLIP_SHIFT 10 |
| #define PXP_CTRL_VFLIP_MASK 0x800u |
| #define PXP_CTRL_VFLIP_SHIFT 11 |
| #define PXP_CTRL_RSVD1_MASK 0x3FF000u |
| #define PXP_CTRL_RSVD1_SHIFT 12 |
| #define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD1_SHIFT))&PXP_CTRL_RSVD1_MASK) |
| #define PXP_CTRL_ROT_POS_MASK 0x400000u |
| #define PXP_CTRL_ROT_POS_SHIFT 22 |
| #define PXP_CTRL_BLOCK_SIZE_MASK 0x800000u |
| #define PXP_CTRL_BLOCK_SIZE_SHIFT 23 |
| #define PXP_CTRL_RSVD3_MASK 0xF000000u |
| #define PXP_CTRL_RSVD3_SHIFT 24 |
| #define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD3_SHIFT))&PXP_CTRL_RSVD3_MASK) |
| #define PXP_CTRL_EN_REPEAT_MASK 0x10000000u |
| #define PXP_CTRL_EN_REPEAT_SHIFT 28 |
| #define PXP_CTRL_RSVD4_MASK 0x20000000u |
| #define PXP_CTRL_RSVD4_SHIFT 29 |
| #define PXP_CTRL_CLKGATE_MASK 0x40000000u |
| #define PXP_CTRL_CLKGATE_SHIFT 30 |
| #define PXP_CTRL_SFTRST_MASK 0x80000000u |
| #define PXP_CTRL_SFTRST_SHIFT 31 |
| /* STAT Bit Fields */ |
| #define PXP_STAT_IRQ_MASK 0x1u |
| #define PXP_STAT_IRQ_SHIFT 0 |
| #define PXP_STAT_AXI_WRITE_ERROR_MASK 0x2u |
| #define PXP_STAT_AXI_WRITE_ERROR_SHIFT 1 |
| #define PXP_STAT_AXI_READ_ERROR_MASK 0x4u |
| #define PXP_STAT_AXI_READ_ERROR_SHIFT 2 |
| #define PXP_STAT_NEXT_IRQ_MASK 0x8u |
| #define PXP_STAT_NEXT_IRQ_SHIFT 3 |
| #define PXP_STAT_AXI_ERROR_ID_MASK 0xF0u |
| #define PXP_STAT_AXI_ERROR_ID_SHIFT 4 |
| #define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_SHIFT))&PXP_STAT_AXI_ERROR_ID_MASK) |
| #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK 0x100u |
| #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT 8 |
| #define PXP_STAT_RSVD2_MASK 0xFE00u |
| #define PXP_STAT_RSVD2_SHIFT 9 |
| #define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_RSVD2_SHIFT))&PXP_STAT_RSVD2_MASK) |
| #define PXP_STAT_BLOCKY_MASK 0xFF0000u |
| #define PXP_STAT_BLOCKY_SHIFT 16 |
| #define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKY_SHIFT))&PXP_STAT_BLOCKY_MASK) |
| #define PXP_STAT_BLOCKX_MASK 0xFF000000u |
| #define PXP_STAT_BLOCKX_SHIFT 24 |
| #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKX_SHIFT))&PXP_STAT_BLOCKX_MASK) |
| /* OUT_CTRL Bit Fields */ |
| #define PXP_OUT_CTRL_FORMAT_MASK 0x1Fu |
| #define PXP_OUT_CTRL_FORMAT_SHIFT 0 |
| #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_OUT_CTRL_FORMAT_MASK) |
| #define PXP_OUT_CTRL_RSVD0_MASK 0xE0u |
| #define PXP_OUT_CTRL_RSVD0_SHIFT 5 |
| #define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_OUT_CTRL_RSVD0_MASK) |
| #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK 0x300u |
| #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT 8 |
| #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) |
| #define PXP_OUT_CTRL_RSVD1_MASK 0x7FFC00u |
| #define PXP_OUT_CTRL_RSVD1_SHIFT 10 |
| #define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_OUT_CTRL_RSVD1_MASK) |
| #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK 0x800000u |
| #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT 23 |
| #define PXP_OUT_CTRL_ALPHA_MASK 0xFF000000u |
| #define PXP_OUT_CTRL_ALPHA_SHIFT 24 |
| #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_OUT_CTRL_ALPHA_MASK) |
| /* OUT_BUF Bit Fields */ |
| #define PXP_OUT_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_OUT_BUF_ADDR_SHIFT 0 |
| #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF_ADDR_SHIFT))&PXP_OUT_BUF_ADDR_MASK) |
| /* OUT_BUF2 Bit Fields */ |
| #define PXP_OUT_BUF2_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_OUT_BUF2_ADDR_SHIFT 0 |
| #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF2_ADDR_SHIFT))&PXP_OUT_BUF2_ADDR_MASK) |
| /* OUT_PITCH Bit Fields */ |
| #define PXP_OUT_PITCH_PITCH_MASK 0xFFFFu |
| #define PXP_OUT_PITCH_PITCH_SHIFT 0 |
| #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_PITCH_SHIFT))&PXP_OUT_PITCH_PITCH_MASK) |
| #define PXP_OUT_PITCH_RSVD_MASK 0xFFFF0000u |
| #define PXP_OUT_PITCH_RSVD_SHIFT 16 |
| #define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_RSVD_SHIFT))&PXP_OUT_PITCH_RSVD_MASK) |
| /* OUT_LRC Bit Fields */ |
| #define PXP_OUT_LRC_Y_MASK 0x3FFFu |
| #define PXP_OUT_LRC_Y_SHIFT 0 |
| #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_Y_SHIFT))&PXP_OUT_LRC_Y_MASK) |
| #define PXP_OUT_LRC_RSVD0_MASK 0xC000u |
| #define PXP_OUT_LRC_RSVD0_SHIFT 14 |
| #define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD0_SHIFT))&PXP_OUT_LRC_RSVD0_MASK) |
| #define PXP_OUT_LRC_X_MASK 0x3FFF0000u |
| #define PXP_OUT_LRC_X_SHIFT 16 |
| #define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_X_SHIFT))&PXP_OUT_LRC_X_MASK) |
| #define PXP_OUT_LRC_RSVD1_MASK 0xC0000000u |
| #define PXP_OUT_LRC_RSVD1_SHIFT 30 |
| #define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD1_SHIFT))&PXP_OUT_LRC_RSVD1_MASK) |
| /* OUT_PS_ULC Bit Fields */ |
| #define PXP_OUT_PS_ULC_Y_MASK 0x3FFFu |
| #define PXP_OUT_PS_ULC_Y_SHIFT 0 |
| #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_Y_SHIFT))&PXP_OUT_PS_ULC_Y_MASK) |
| #define PXP_OUT_PS_ULC_RSVD0_MASK 0xC000u |
| #define PXP_OUT_PS_ULC_RSVD0_SHIFT 14 |
| #define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_OUT_PS_ULC_RSVD0_MASK) |
| #define PXP_OUT_PS_ULC_X_MASK 0x3FFF0000u |
| #define PXP_OUT_PS_ULC_X_SHIFT 16 |
| #define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_X_SHIFT))&PXP_OUT_PS_ULC_X_MASK) |
| #define PXP_OUT_PS_ULC_RSVD1_MASK 0xC0000000u |
| #define PXP_OUT_PS_ULC_RSVD1_SHIFT 30 |
| #define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_OUT_PS_ULC_RSVD1_MASK) |
| /* OUT_PS_LRC Bit Fields */ |
| #define PXP_OUT_PS_LRC_Y_MASK 0x3FFFu |
| #define PXP_OUT_PS_LRC_Y_SHIFT 0 |
| #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_Y_SHIFT))&PXP_OUT_PS_LRC_Y_MASK) |
| #define PXP_OUT_PS_LRC_RSVD0_MASK 0xC000u |
| #define PXP_OUT_PS_LRC_RSVD0_SHIFT 14 |
| #define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_OUT_PS_LRC_RSVD0_MASK) |
| #define PXP_OUT_PS_LRC_X_MASK 0x3FFF0000u |
| #define PXP_OUT_PS_LRC_X_SHIFT 16 |
| #define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_X_SHIFT))&PXP_OUT_PS_LRC_X_MASK) |
| #define PXP_OUT_PS_LRC_RSVD1_MASK 0xC0000000u |
| #define PXP_OUT_PS_LRC_RSVD1_SHIFT 30 |
| #define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_OUT_PS_LRC_RSVD1_MASK) |
| /* OUT_AS_ULC Bit Fields */ |
| #define PXP_OUT_AS_ULC_Y_MASK 0x3FFFu |
| #define PXP_OUT_AS_ULC_Y_SHIFT 0 |
| #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_Y_SHIFT))&PXP_OUT_AS_ULC_Y_MASK) |
| #define PXP_OUT_AS_ULC_RSVD0_MASK 0xC000u |
| #define PXP_OUT_AS_ULC_RSVD0_SHIFT 14 |
| #define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_OUT_AS_ULC_RSVD0_MASK) |
| #define PXP_OUT_AS_ULC_X_MASK 0x3FFF0000u |
| #define PXP_OUT_AS_ULC_X_SHIFT 16 |
| #define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_X_SHIFT))&PXP_OUT_AS_ULC_X_MASK) |
| #define PXP_OUT_AS_ULC_RSVD1_MASK 0xC0000000u |
| #define PXP_OUT_AS_ULC_RSVD1_SHIFT 30 |
| #define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_OUT_AS_ULC_RSVD1_MASK) |
| /* OUT_AS_LRC Bit Fields */ |
| #define PXP_OUT_AS_LRC_Y_MASK 0x3FFFu |
| #define PXP_OUT_AS_LRC_Y_SHIFT 0 |
| #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_Y_SHIFT))&PXP_OUT_AS_LRC_Y_MASK) |
| #define PXP_OUT_AS_LRC_RSVD0_MASK 0xC000u |
| #define PXP_OUT_AS_LRC_RSVD0_SHIFT 14 |
| #define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_OUT_AS_LRC_RSVD0_MASK) |
| #define PXP_OUT_AS_LRC_X_MASK 0x3FFF0000u |
| #define PXP_OUT_AS_LRC_X_SHIFT 16 |
| #define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_X_SHIFT))&PXP_OUT_AS_LRC_X_MASK) |
| #define PXP_OUT_AS_LRC_RSVD1_MASK 0xC0000000u |
| #define PXP_OUT_AS_LRC_RSVD1_SHIFT 30 |
| #define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_OUT_AS_LRC_RSVD1_MASK) |
| /* PS_CTRL Bit Fields */ |
| #define PXP_PS_CTRL_FORMAT_MASK 0x1Fu |
| #define PXP_PS_CTRL_FORMAT_SHIFT 0 |
| #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_FORMAT_SHIFT))&PXP_PS_CTRL_FORMAT_MASK) |
| #define PXP_PS_CTRL_WB_SWAP_MASK 0x20u |
| #define PXP_PS_CTRL_WB_SWAP_SHIFT 5 |
| #define PXP_PS_CTRL_RSVD0_MASK 0xC0u |
| #define PXP_PS_CTRL_RSVD0_SHIFT 6 |
| #define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD0_SHIFT))&PXP_PS_CTRL_RSVD0_MASK) |
| #define PXP_PS_CTRL_DECY_MASK 0x300u |
| #define PXP_PS_CTRL_DECY_SHIFT 8 |
| #define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECY_SHIFT))&PXP_PS_CTRL_DECY_MASK) |
| #define PXP_PS_CTRL_DECX_MASK 0xC00u |
| #define PXP_PS_CTRL_DECX_SHIFT 10 |
| #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECX_SHIFT))&PXP_PS_CTRL_DECX_MASK) |
| #define PXP_PS_CTRL_RSVD1_MASK 0xFFFFF000u |
| #define PXP_PS_CTRL_RSVD1_SHIFT 12 |
| #define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD1_SHIFT))&PXP_PS_CTRL_RSVD1_MASK) |
| /* PS_BUF Bit Fields */ |
| #define PXP_PS_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_PS_BUF_ADDR_SHIFT 0 |
| #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_BUF_ADDR_SHIFT))&PXP_PS_BUF_ADDR_MASK) |
| /* PS_UBUF Bit Fields */ |
| #define PXP_PS_UBUF_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_PS_UBUF_ADDR_SHIFT 0 |
| #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_UBUF_ADDR_SHIFT))&PXP_PS_UBUF_ADDR_MASK) |
| /* PS_VBUF Bit Fields */ |
| #define PXP_PS_VBUF_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_PS_VBUF_ADDR_SHIFT 0 |
| #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_VBUF_ADDR_SHIFT))&PXP_PS_VBUF_ADDR_MASK) |
| /* PS_PITCH Bit Fields */ |
| #define PXP_PS_PITCH_PITCH_MASK 0xFFFFu |
| #define PXP_PS_PITCH_PITCH_SHIFT 0 |
| #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_PITCH_SHIFT))&PXP_PS_PITCH_PITCH_MASK) |
| #define PXP_PS_PITCH_RSVD_MASK 0xFFFF0000u |
| #define PXP_PS_PITCH_RSVD_SHIFT 16 |
| #define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_RSVD_SHIFT))&PXP_PS_PITCH_RSVD_MASK) |
| /* PS_BACKGROUND Bit Fields */ |
| #define PXP_PS_BACKGROUND_COLOR_MASK 0xFFFFFFu |
| #define PXP_PS_BACKGROUND_COLOR_SHIFT 0 |
| #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_BACKGROUND_COLOR_SHIFT))&PXP_PS_BACKGROUND_COLOR_MASK) |
| #define PXP_PS_BACKGROUND_RSVD_MASK 0xFF000000u |
| #define PXP_PS_BACKGROUND_RSVD_SHIFT 24 |
| #define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_BACKGROUND_RSVD_SHIFT))&PXP_PS_BACKGROUND_RSVD_MASK) |
| /* PS_SCALE Bit Fields */ |
| #define PXP_PS_SCALE_XSCALE_MASK 0x7FFFu |
| #define PXP_PS_SCALE_XSCALE_SHIFT 0 |
| #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_XSCALE_SHIFT))&PXP_PS_SCALE_XSCALE_MASK) |
| #define PXP_PS_SCALE_RSVD1_MASK 0x8000u |
| #define PXP_PS_SCALE_RSVD1_SHIFT 15 |
| #define PXP_PS_SCALE_YSCALE_MASK 0x7FFF0000u |
| #define PXP_PS_SCALE_YSCALE_SHIFT 16 |
| #define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_YSCALE_SHIFT))&PXP_PS_SCALE_YSCALE_MASK) |
| #define PXP_PS_SCALE_RSVD2_MASK 0x80000000u |
| #define PXP_PS_SCALE_RSVD2_SHIFT 31 |
| /* PS_OFFSET Bit Fields */ |
| #define PXP_PS_OFFSET_XOFFSET_MASK 0xFFFu |
| #define PXP_PS_OFFSET_XOFFSET_SHIFT 0 |
| #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_PS_OFFSET_XOFFSET_MASK) |
| #define PXP_PS_OFFSET_RSVD1_MASK 0xF000u |
| #define PXP_PS_OFFSET_RSVD1_SHIFT 12 |
| #define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_PS_OFFSET_RSVD1_MASK) |
| #define PXP_PS_OFFSET_YOFFSET_MASK 0xFFF0000u |
| #define PXP_PS_OFFSET_YOFFSET_SHIFT 16 |
| #define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_PS_OFFSET_YOFFSET_MASK) |
| #define PXP_PS_OFFSET_RSVD2_MASK 0xF0000000u |
| #define PXP_PS_OFFSET_RSVD2_SHIFT 28 |
| #define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_PS_OFFSET_RSVD2_MASK) |
| /* PS_CLRKEYLOW Bit Fields */ |
| #define PXP_PS_CLRKEYLOW_PIXEL_MASK 0xFFFFFFu |
| #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT 0 |
| #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYLOW_PIXEL_SHIFT))&PXP_PS_CLRKEYLOW_PIXEL_MASK) |
| #define PXP_PS_CLRKEYLOW_RSVD1_MASK 0xFF000000u |
| #define PXP_PS_CLRKEYLOW_RSVD1_SHIFT 24 |
| #define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYLOW_RSVD1_SHIFT))&PXP_PS_CLRKEYLOW_RSVD1_MASK) |
| /* PS_CLRKEYHIGH Bit Fields */ |
| #define PXP_PS_CLRKEYHIGH_PIXEL_MASK 0xFFFFFFu |
| #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT 0 |
| #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYHIGH_PIXEL_SHIFT))&PXP_PS_CLRKEYHIGH_PIXEL_MASK) |
| #define PXP_PS_CLRKEYHIGH_RSVD1_MASK 0xFF000000u |
| #define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT 24 |
| #define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CLRKEYHIGH_RSVD1_SHIFT))&PXP_PS_CLRKEYHIGH_RSVD1_MASK) |
| /* AS_CTRL Bit Fields */ |
| #define PXP_AS_CTRL_RSVD0_MASK 0x1u |
| #define PXP_AS_CTRL_RSVD0_SHIFT 0 |
| #define PXP_AS_CTRL_ALPHA_CTRL_MASK 0x6u |
| #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT 1 |
| #define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_AS_CTRL_ALPHA_CTRL_MASK) |
| #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u |
| #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 |
| #define PXP_AS_CTRL_FORMAT_MASK 0xF0u |
| #define PXP_AS_CTRL_FORMAT_SHIFT 4 |
| #define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_FORMAT_SHIFT))&PXP_AS_CTRL_FORMAT_MASK) |
| #define PXP_AS_CTRL_ALPHA_MASK 0xFF00u |
| #define PXP_AS_CTRL_ALPHA_SHIFT 8 |
| #define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_SHIFT))&PXP_AS_CTRL_ALPHA_MASK) |
| #define PXP_AS_CTRL_ROP_MASK 0xF0000u |
| #define PXP_AS_CTRL_ROP_SHIFT 16 |
| #define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ROP_SHIFT))&PXP_AS_CTRL_ROP_MASK) |
| #define PXP_AS_CTRL_ALPHA_INVERT_MASK 0x100000u |
| #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT 20 |
| #define PXP_AS_CTRL_RSVD1_MASK 0xFFE00000u |
| #define PXP_AS_CTRL_RSVD1_SHIFT 21 |
| #define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_RSVD1_SHIFT))&PXP_AS_CTRL_RSVD1_MASK) |
| /* AS_BUF Bit Fields */ |
| #define PXP_AS_BUF_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_AS_BUF_ADDR_SHIFT 0 |
| #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_BUF_ADDR_SHIFT))&PXP_AS_BUF_ADDR_MASK) |
| /* AS_PITCH Bit Fields */ |
| #define PXP_AS_PITCH_PITCH_MASK 0xFFFFu |
| #define PXP_AS_PITCH_PITCH_SHIFT 0 |
| #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_PITCH_SHIFT))&PXP_AS_PITCH_PITCH_MASK) |
| #define PXP_AS_PITCH_RSVD_MASK 0xFFFF0000u |
| #define PXP_AS_PITCH_RSVD_SHIFT 16 |
| #define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_RSVD_SHIFT))&PXP_AS_PITCH_RSVD_MASK) |
| /* AS_CLRKEYLOW Bit Fields */ |
| #define PXP_AS_CLRKEYLOW_PIXEL_MASK 0xFFFFFFu |
| #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT 0 |
| #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYLOW_PIXEL_SHIFT))&PXP_AS_CLRKEYLOW_PIXEL_MASK) |
| #define PXP_AS_CLRKEYLOW_RSVD1_MASK 0xFF000000u |
| #define PXP_AS_CLRKEYLOW_RSVD1_SHIFT 24 |
| #define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYLOW_RSVD1_SHIFT))&PXP_AS_CLRKEYLOW_RSVD1_MASK) |
| /* AS_CLRKEYHIGH Bit Fields */ |
| #define PXP_AS_CLRKEYHIGH_PIXEL_MASK 0xFFFFFFu |
| #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT 0 |
| #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYHIGH_PIXEL_SHIFT))&PXP_AS_CLRKEYHIGH_PIXEL_MASK) |
| #define PXP_AS_CLRKEYHIGH_RSVD1_MASK 0xFF000000u |
| #define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT 24 |
| #define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CLRKEYHIGH_RSVD1_SHIFT))&PXP_AS_CLRKEYHIGH_RSVD1_MASK) |
| /* CSC1_COEF0 Bit Fields */ |
| #define PXP_CSC1_COEF0_Y_OFFSET_MASK 0x1FFu |
| #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT 0 |
| #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_CSC1_COEF0_Y_OFFSET_MASK) |
| #define PXP_CSC1_COEF0_UV_OFFSET_MASK 0x3FE00u |
| #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT 9 |
| #define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_CSC1_COEF0_UV_OFFSET_MASK) |
| #define PXP_CSC1_COEF0_C0_MASK 0x1FFC0000u |
| #define PXP_CSC1_COEF0_C0_SHIFT 18 |
| #define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_C0_SHIFT))&PXP_CSC1_COEF0_C0_MASK) |
| #define PXP_CSC1_COEF0_RSVD1_MASK 0x20000000u |
| #define PXP_CSC1_COEF0_RSVD1_SHIFT 29 |
| #define PXP_CSC1_COEF0_BYPASS_MASK 0x40000000u |
| #define PXP_CSC1_COEF0_BYPASS_SHIFT 30 |
| #define PXP_CSC1_COEF0_YCBCR_MODE_MASK 0x80000000u |
| #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT 31 |
| /* CSC1_COEF1 Bit Fields */ |
| #define PXP_CSC1_COEF1_C4_MASK 0x7FFu |
| #define PXP_CSC1_COEF1_C4_SHIFT 0 |
| #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C4_SHIFT))&PXP_CSC1_COEF1_C4_MASK) |
| #define PXP_CSC1_COEF1_RSVD0_MASK 0xF800u |
| #define PXP_CSC1_COEF1_RSVD0_SHIFT 11 |
| #define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_CSC1_COEF1_RSVD0_MASK) |
| #define PXP_CSC1_COEF1_C1_MASK 0x7FF0000u |
| #define PXP_CSC1_COEF1_C1_SHIFT 16 |
| #define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C1_SHIFT))&PXP_CSC1_COEF1_C1_MASK) |
| #define PXP_CSC1_COEF1_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC1_COEF1_RSVD1_SHIFT 27 |
| #define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_CSC1_COEF1_RSVD1_MASK) |
| /* CSC1_COEF2 Bit Fields */ |
| #define PXP_CSC1_COEF2_C3_MASK 0x7FFu |
| #define PXP_CSC1_COEF2_C3_SHIFT 0 |
| #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C3_SHIFT))&PXP_CSC1_COEF2_C3_MASK) |
| #define PXP_CSC1_COEF2_RSVD0_MASK 0xF800u |
| #define PXP_CSC1_COEF2_RSVD0_SHIFT 11 |
| #define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_CSC1_COEF2_RSVD0_MASK) |
| #define PXP_CSC1_COEF2_C2_MASK 0x7FF0000u |
| #define PXP_CSC1_COEF2_C2_SHIFT 16 |
| #define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C2_SHIFT))&PXP_CSC1_COEF2_C2_MASK) |
| #define PXP_CSC1_COEF2_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC1_COEF2_RSVD1_SHIFT 27 |
| #define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_CSC1_COEF2_RSVD1_MASK) |
| /* CSC2_CTRL Bit Fields */ |
| #define PXP_CSC2_CTRL_BYPASS_MASK 0x1u |
| #define PXP_CSC2_CTRL_BYPASS_SHIFT 0 |
| #define PXP_CSC2_CTRL_CSC_MODE_MASK 0x6u |
| #define PXP_CSC2_CTRL_CSC_MODE_SHIFT 1 |
| #define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_CSC2_CTRL_CSC_MODE_MASK) |
| #define PXP_CSC2_CTRL_RSVD_MASK 0xFFFFFFF8u |
| #define PXP_CSC2_CTRL_RSVD_SHIFT 3 |
| #define PXP_CSC2_CTRL_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_CSC2_CTRL_RSVD_MASK) |
| /* CSC2_COEF0 Bit Fields */ |
| #define PXP_CSC2_COEF0_A1_MASK 0x7FFu |
| #define PXP_CSC2_COEF0_A1_SHIFT 0 |
| #define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A1_SHIFT))&PXP_CSC2_COEF0_A1_MASK) |
| #define PXP_CSC2_COEF0_RSVD0_MASK 0xF800u |
| #define PXP_CSC2_COEF0_RSVD0_SHIFT 11 |
| #define PXP_CSC2_COEF0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_CSC2_COEF0_RSVD0_MASK) |
| #define PXP_CSC2_COEF0_A2_MASK 0x7FF0000u |
| #define PXP_CSC2_COEF0_A2_SHIFT 16 |
| #define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A2_SHIFT))&PXP_CSC2_COEF0_A2_MASK) |
| #define PXP_CSC2_COEF0_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC2_COEF0_RSVD1_SHIFT 27 |
| #define PXP_CSC2_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_CSC2_COEF0_RSVD1_MASK) |
| /* CSC2_COEF1 Bit Fields */ |
| #define PXP_CSC2_COEF1_A3_MASK 0x7FFu |
| #define PXP_CSC2_COEF1_A3_SHIFT 0 |
| #define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_A3_SHIFT))&PXP_CSC2_COEF1_A3_MASK) |
| #define PXP_CSC2_COEF1_RSVD0_MASK 0xF800u |
| #define PXP_CSC2_COEF1_RSVD0_SHIFT 11 |
| #define PXP_CSC2_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_CSC2_COEF1_RSVD0_MASK) |
| #define PXP_CSC2_COEF1_B1_MASK 0x7FF0000u |
| #define PXP_CSC2_COEF1_B1_SHIFT 16 |
| #define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_B1_SHIFT))&PXP_CSC2_COEF1_B1_MASK) |
| #define PXP_CSC2_COEF1_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC2_COEF1_RSVD1_SHIFT 27 |
| #define PXP_CSC2_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_CSC2_COEF1_RSVD1_MASK) |
| /* CSC2_COEF2 Bit Fields */ |
| #define PXP_CSC2_COEF2_B2_MASK 0x7FFu |
| #define PXP_CSC2_COEF2_B2_SHIFT 0 |
| #define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B2_SHIFT))&PXP_CSC2_COEF2_B2_MASK) |
| #define PXP_CSC2_COEF2_RSVD0_MASK 0xF800u |
| #define PXP_CSC2_COEF2_RSVD0_SHIFT 11 |
| #define PXP_CSC2_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_CSC2_COEF2_RSVD0_MASK) |
| #define PXP_CSC2_COEF2_B3_MASK 0x7FF0000u |
| #define PXP_CSC2_COEF2_B3_SHIFT 16 |
| #define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B3_SHIFT))&PXP_CSC2_COEF2_B3_MASK) |
| #define PXP_CSC2_COEF2_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC2_COEF2_RSVD1_SHIFT 27 |
| #define PXP_CSC2_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_CSC2_COEF2_RSVD1_MASK) |
| /* CSC2_COEF3 Bit Fields */ |
| #define PXP_CSC2_COEF3_C1_MASK 0x7FFu |
| #define PXP_CSC2_COEF3_C1_SHIFT 0 |
| #define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C1_SHIFT))&PXP_CSC2_COEF3_C1_MASK) |
| #define PXP_CSC2_COEF3_RSVD0_MASK 0xF800u |
| #define PXP_CSC2_COEF3_RSVD0_SHIFT 11 |
| #define PXP_CSC2_COEF3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_CSC2_COEF3_RSVD0_MASK) |
| #define PXP_CSC2_COEF3_C2_MASK 0x7FF0000u |
| #define PXP_CSC2_COEF3_C2_SHIFT 16 |
| #define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C2_SHIFT))&PXP_CSC2_COEF3_C2_MASK) |
| #define PXP_CSC2_COEF3_RSVD1_MASK 0xF8000000u |
| #define PXP_CSC2_COEF3_RSVD1_SHIFT 27 |
| #define PXP_CSC2_COEF3_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_CSC2_COEF3_RSVD1_MASK) |
| /* CSC2_COEF4 Bit Fields */ |
| #define PXP_CSC2_COEF4_C3_MASK 0x7FFu |
| #define PXP_CSC2_COEF4_C3_SHIFT 0 |
| #define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_C3_SHIFT))&PXP_CSC2_COEF4_C3_MASK) |
| #define PXP_CSC2_COEF4_RSVD0_MASK 0xF800u |
| #define PXP_CSC2_COEF4_RSVD0_SHIFT 11 |
| #define PXP_CSC2_COEF4_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_CSC2_COEF4_RSVD0_MASK) |
| #define PXP_CSC2_COEF4_D1_MASK 0x1FF0000u |
| #define PXP_CSC2_COEF4_D1_SHIFT 16 |
| #define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_D1_SHIFT))&PXP_CSC2_COEF4_D1_MASK) |
| #define PXP_CSC2_COEF4_RSVD1_MASK 0xFE000000u |
| #define PXP_CSC2_COEF4_RSVD1_SHIFT 25 |
| #define PXP_CSC2_COEF4_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_CSC2_COEF4_RSVD1_MASK) |
| /* CSC2_COEF5 Bit Fields */ |
| #define PXP_CSC2_COEF5_D2_MASK 0x1FFu |
| #define PXP_CSC2_COEF5_D2_SHIFT 0 |
| #define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D2_SHIFT))&PXP_CSC2_COEF5_D2_MASK) |
| #define PXP_CSC2_COEF5_RSVD0_MASK 0xFE00u |
| #define PXP_CSC2_COEF5_RSVD0_SHIFT 9 |
| #define PXP_CSC2_COEF5_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_CSC2_COEF5_RSVD0_MASK) |
| #define PXP_CSC2_COEF5_D3_MASK 0x1FF0000u |
| #define PXP_CSC2_COEF5_D3_SHIFT 16 |
| #define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D3_SHIFT))&PXP_CSC2_COEF5_D3_MASK) |
| #define PXP_CSC2_COEF5_RSVD1_MASK 0xFE000000u |
| #define PXP_CSC2_COEF5_RSVD1_SHIFT 25 |
| #define PXP_CSC2_COEF5_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_CSC2_COEF5_RSVD1_MASK) |
| /* LUT_CTRL Bit Fields */ |
| #define PXP_LUT_CTRL_DMA_START_MASK 0x1u |
| #define PXP_LUT_CTRL_DMA_START_SHIFT 0 |
| #define PXP_LUT_CTRL_RSVD0_MASK 0xFEu |
| #define PXP_LUT_CTRL_RSVD0_SHIFT 1 |
| #define PXP_LUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_LUT_CTRL_RSVD0_MASK) |
| #define PXP_LUT_CTRL_INVALID_MASK 0x100u |
| #define PXP_LUT_CTRL_INVALID_SHIFT 8 |
| #define PXP_LUT_CTRL_LRU_UPD_MASK 0x200u |
| #define PXP_LUT_CTRL_LRU_UPD_SHIFT 9 |
| #define PXP_LUT_CTRL_SEL_8KB_MASK 0x400u |
| #define PXP_LUT_CTRL_SEL_8KB_SHIFT 10 |
| #define PXP_LUT_CTRL_RSVD1_MASK 0xF800u |
| #define PXP_LUT_CTRL_RSVD1_SHIFT 11 |
| #define PXP_LUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_LUT_CTRL_RSVD1_MASK) |
| #define PXP_LUT_CTRL_OUT_MODE_MASK 0x30000u |
| #define PXP_LUT_CTRL_OUT_MODE_SHIFT 16 |
| #define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_LUT_CTRL_OUT_MODE_MASK) |
| #define PXP_LUT_CTRL_RSVD2_MASK 0xFC0000u |
| #define PXP_LUT_CTRL_RSVD2_SHIFT 18 |
| #define PXP_LUT_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_LUT_CTRL_RSVD2_MASK) |
| #define PXP_LUT_CTRL_LOOKUP_MODE_MASK 0x3000000u |
| #define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT 24 |
| #define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_LUT_CTRL_LOOKUP_MODE_MASK) |
| #define PXP_LUT_CTRL_RSVD3_MASK 0x7C000000u |
| #define PXP_LUT_CTRL_RSVD3_SHIFT 26 |
| #define PXP_LUT_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_LUT_CTRL_RSVD3_MASK) |
| #define PXP_LUT_CTRL_BYPASS_MASK 0x80000000u |
| #define PXP_LUT_CTRL_BYPASS_SHIFT 31 |
| /* LUT_ADDR Bit Fields */ |
| #define PXP_LUT_ADDR_ADDR_MASK 0x3FFFu |
| #define PXP_LUT_ADDR_ADDR_SHIFT 0 |
| #define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_ADDR_SHIFT))&PXP_LUT_ADDR_ADDR_MASK) |
| #define PXP_LUT_ADDR_RSVD1_MASK 0xC000u |
| #define PXP_LUT_ADDR_RSVD1_SHIFT 14 |
| #define PXP_LUT_ADDR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_LUT_ADDR_RSVD1_MASK) |
| #define PXP_LUT_ADDR_NUM_BYTES_MASK 0x7FFF0000u |
| #define PXP_LUT_ADDR_NUM_BYTES_SHIFT 16 |
| #define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_LUT_ADDR_NUM_BYTES_MASK) |
| #define PXP_LUT_ADDR_RSVD2_MASK 0x80000000u |
| #define PXP_LUT_ADDR_RSVD2_SHIFT 31 |
| /* LUT_DATA Bit Fields */ |
| #define PXP_LUT_DATA_DATA_MASK 0xFFFFFFFFu |
| #define PXP_LUT_DATA_DATA_SHIFT 0 |
| #define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_DATA_DATA_SHIFT))&PXP_LUT_DATA_DATA_MASK) |
| /* LUT_EXTMEM Bit Fields */ |
| #define PXP_LUT_EXTMEM_ADDR_MASK 0xFFFFFFFFu |
| #define PXP_LUT_EXTMEM_ADDR_SHIFT 0 |
| #define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_LUT_EXTMEM_ADDR_MASK) |
| /* CFA Bit Fields */ |
| #define PXP_CFA_DATA_MASK 0xFFFFFFFFu |
| #define PXP_CFA_DATA_SHIFT 0 |
| #define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_CFA_DATA_SHIFT))&PXP_CFA_DATA_MASK) |
| /* HIST_CTRL Bit Fields */ |
| #define PXP_HIST_CTRL_STATUS_MASK 0xFu |
| #define PXP_HIST_CTRL_STATUS_SHIFT 0 |
| #define PXP_HIST_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_STATUS_SHIFT))&PXP_HIST_CTRL_STATUS_MASK) |
| #define PXP_HIST_CTRL_PANEL_MODE_MASK 0x30u |
| #define PXP_HIST_CTRL_PANEL_MODE_SHIFT 4 |
| #define PXP_HIST_CTRL_PANEL_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_PANEL_MODE_SHIFT))&PXP_HIST_CTRL_PANEL_MODE_MASK) |
| #define PXP_HIST_CTRL_RSVD_MASK 0xFFFFFFC0u |
| #define PXP_HIST_CTRL_RSVD_SHIFT 6 |
| #define PXP_HIST_CTRL_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST_CTRL_RSVD_SHIFT))&PXP_HIST_CTRL_RSVD_MASK) |
| /* HIST2_PARAM Bit Fields */ |
| #define PXP_HIST2_PARAM_VALUE0_MASK 0x1Fu |
| #define PXP_HIST2_PARAM_VALUE0_SHIFT 0 |
| #define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HIST2_PARAM_VALUE0_MASK) |
| #define PXP_HIST2_PARAM_RSVD0_MASK 0xE0u |
| #define PXP_HIST2_PARAM_RSVD0_SHIFT 5 |
| #define PXP_HIST2_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HIST2_PARAM_RSVD0_MASK) |
| #define PXP_HIST2_PARAM_VALUE1_MASK 0x1F00u |
| #define PXP_HIST2_PARAM_VALUE1_SHIFT 8 |
| #define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HIST2_PARAM_VALUE1_MASK) |
| #define PXP_HIST2_PARAM_RSVD1_MASK 0xE000u |
| #define PXP_HIST2_PARAM_RSVD1_SHIFT 13 |
| #define PXP_HIST2_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HIST2_PARAM_RSVD1_MASK) |
| #define PXP_HIST2_PARAM_RSVD_MASK 0xFFFF0000u |
| #define PXP_HIST2_PARAM_RSVD_SHIFT 16 |
| #define PXP_HIST2_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HIST2_PARAM_RSVD_MASK) |
| /* HIST4_PARAM Bit Fields */ |
| #define PXP_HIST4_PARAM_VALUE0_MASK 0x1Fu |
| #define PXP_HIST4_PARAM_VALUE0_SHIFT 0 |
| #define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HIST4_PARAM_VALUE0_MASK) |
| #define PXP_HIST4_PARAM_RSVD0_MASK 0xE0u |
| #define PXP_HIST4_PARAM_RSVD0_SHIFT 5 |
| #define PXP_HIST4_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HIST4_PARAM_RSVD0_MASK) |
| #define PXP_HIST4_PARAM_VALUE1_MASK 0x1F00u |
| #define PXP_HIST4_PARAM_VALUE1_SHIFT 8 |
| #define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HIST4_PARAM_VALUE1_MASK) |
| #define PXP_HIST4_PARAM_RSVD1_MASK 0xE000u |
| #define PXP_HIST4_PARAM_RSVD1_SHIFT 13 |
| #define PXP_HIST4_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HIST4_PARAM_RSVD1_MASK) |
| #define PXP_HIST4_PARAM_VALUE2_MASK 0x1F0000u |
| #define PXP_HIST4_PARAM_VALUE2_SHIFT 16 |
| #define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HIST4_PARAM_VALUE2_MASK) |
| #define PXP_HIST4_PARAM_RSVD2_MASK 0xE00000u |
| #define PXP_HIST4_PARAM_RSVD2_SHIFT 21 |
| #define PXP_HIST4_PARAM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HIST4_PARAM_RSVD2_MASK) |
| #define PXP_HIST4_PARAM_VALUE3_MASK 0x1F000000u |
| #define PXP_HIST4_PARAM_VALUE3_SHIFT 24 |
| #define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HIST4_PARAM_VALUE3_MASK) |
| #define PXP_HIST4_PARAM_RSVD3_MASK 0xE0000000u |
| #define PXP_HIST4_PARAM_RSVD3_SHIFT 29 |
| #define PXP_HIST4_PARAM_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HIST4_PARAM_RSVD3_MASK) |
| /* HIST8_PARAM0 Bit Fields */ |
| #define PXP_HIST8_PARAM0_VALUE0_MASK 0x1Fu |
| #define PXP_HIST8_PARAM0_VALUE0_SHIFT 0 |
| #define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HIST8_PARAM0_VALUE0_MASK) |
| #define PXP_HIST8_PARAM0_RSVD0_MASK 0xE0u |
| #define PXP_HIST8_PARAM0_RSVD0_SHIFT 5 |
| #define PXP_HIST8_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HIST8_PARAM0_RSVD0_MASK) |
| #define PXP_HIST8_PARAM0_VALUE1_MASK 0x1F00u |
| #define PXP_HIST8_PARAM0_VALUE1_SHIFT 8 |
| #define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HIST8_PARAM0_VALUE1_MASK) |
| #define PXP_HIST8_PARAM0_RSVD1_MASK 0xE000u |
| #define PXP_HIST8_PARAM0_RSVD1_SHIFT 13 |
| #define PXP_HIST8_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HIST8_PARAM0_RSVD1_MASK) |
| #define PXP_HIST8_PARAM0_VALUE2_MASK 0x1F0000u |
| #define PXP_HIST8_PARAM0_VALUE2_SHIFT 16 |
| #define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HIST8_PARAM0_VALUE2_MASK) |
| #define PXP_HIST8_PARAM0_RSVD2_MASK 0xE00000u |
| #define PXP_HIST8_PARAM0_RSVD2_SHIFT 21 |
| #define PXP_HIST8_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HIST8_PARAM0_RSVD2_MASK) |
| #define PXP_HIST8_PARAM0_VALUE3_MASK 0x1F000000u |
| #define PXP_HIST8_PARAM0_VALUE3_SHIFT 24 |
| #define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HIST8_PARAM0_VALUE3_MASK) |
| #define PXP_HIST8_PARAM0_RSVD3_MASK 0xE0000000u |
| #define PXP_HIST8_PARAM0_RSVD3_SHIFT 29 |
| #define PXP_HIST8_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HIST8_PARAM0_RSVD3_MASK) |
| /* HIST8_PARAM1 Bit Fields */ |
| #define PXP_HIST8_PARAM1_VALUE4_MASK 0x1Fu |
| #define PXP_HIST8_PARAM1_VALUE4_SHIFT 0 |
| #define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HIST8_PARAM1_VALUE4_MASK) |
| #define PXP_HIST8_PARAM1_RSVD4_MASK 0xE0u |
| #define PXP_HIST8_PARAM1_RSVD4_SHIFT 5 |
| #define PXP_HIST8_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HIST8_PARAM1_RSVD4_MASK) |
| #define PXP_HIST8_PARAM1_VALUE5_MASK 0x1F00u |
| #define PXP_HIST8_PARAM1_VALUE5_SHIFT 8 |
| #define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HIST8_PARAM1_VALUE5_MASK) |
| #define PXP_HIST8_PARAM1_RSVD5_MASK 0xE000u |
| #define PXP_HIST8_PARAM1_RSVD5_SHIFT 13 |
| #define PXP_HIST8_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HIST8_PARAM1_RSVD5_MASK) |
| #define PXP_HIST8_PARAM1_VALUE6_MASK 0x1F0000u |
| #define PXP_HIST8_PARAM1_VALUE6_SHIFT 16 |
| #define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HIST8_PARAM1_VALUE6_MASK) |
| #define PXP_HIST8_PARAM1_RSVD6_MASK 0xE00000u |
| #define PXP_HIST8_PARAM1_RSVD6_SHIFT 21 |
| #define PXP_HIST8_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HIST8_PARAM1_RSVD6_MASK) |
| #define PXP_HIST8_PARAM1_VALUE7_MASK 0x1F000000u |
| #define PXP_HIST8_PARAM1_VALUE7_SHIFT 24 |
| #define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HIST8_PARAM1_VALUE7_MASK) |
| #define PXP_HIST8_PARAM1_RSVD7_MASK 0xE0000000u |
| #define PXP_HIST8_PARAM1_RSVD7_SHIFT 29 |
| #define PXP_HIST8_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HIST8_PARAM1_RSVD7_MASK) |
| /* HIST16_PARAM0 Bit Fields */ |
| #define PXP_HIST16_PARAM0_VALUE0_MASK 0x1Fu |
| #define PXP_HIST16_PARAM0_VALUE0_SHIFT 0 |
| #define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HIST16_PARAM0_VALUE0_MASK) |
| #define PXP_HIST16_PARAM0_RSVD0_MASK 0xE0u |
| #define PXP_HIST16_PARAM0_RSVD0_SHIFT 5 |
| #define PXP_HIST16_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HIST16_PARAM0_RSVD0_MASK) |
| #define PXP_HIST16_PARAM0_VALUE1_MASK 0x1F00u |
| #define PXP_HIST16_PARAM0_VALUE1_SHIFT 8 |
| #define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HIST16_PARAM0_VALUE1_MASK) |
| #define PXP_HIST16_PARAM0_RSVD1_MASK 0xE000u |
| #define PXP_HIST16_PARAM0_RSVD1_SHIFT 13 |
| #define PXP_HIST16_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HIST16_PARAM0_RSVD1_MASK) |
| #define PXP_HIST16_PARAM0_VALUE2_MASK 0x1F0000u |
| #define PXP_HIST16_PARAM0_VALUE2_SHIFT 16 |
| #define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HIST16_PARAM0_VALUE2_MASK) |
| #define PXP_HIST16_PARAM0_RSVD2_MASK 0xE00000u |
| #define PXP_HIST16_PARAM0_RSVD2_SHIFT 21 |
| #define PXP_HIST16_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HIST16_PARAM0_RSVD2_MASK) |
| #define PXP_HIST16_PARAM0_VALUE3_MASK 0x1F000000u |
| #define PXP_HIST16_PARAM0_VALUE3_SHIFT 24 |
| #define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HIST16_PARAM0_VALUE3_MASK) |
| #define PXP_HIST16_PARAM0_RSVD3_MASK 0xE0000000u |
| #define PXP_HIST16_PARAM0_RSVD3_SHIFT 29 |
| #define PXP_HIST16_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HIST16_PARAM0_RSVD3_MASK) |
| /* HIST16_PARAM1 Bit Fields */ |
| #define PXP_HIST16_PARAM1_VALUE4_MASK 0x1Fu |
| #define PXP_HIST16_PARAM1_VALUE4_SHIFT 0 |
| #define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HIST16_PARAM1_VALUE4_MASK) |
| #define PXP_HIST16_PARAM1_RSVD4_MASK 0xE0u |
| #define PXP_HIST16_PARAM1_RSVD4_SHIFT 5 |
| #define PXP_HIST16_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HIST16_PARAM1_RSVD4_MASK) |
| #define PXP_HIST16_PARAM1_VALUE5_MASK 0x1F00u |
| #define PXP_HIST16_PARAM1_VALUE5_SHIFT 8 |
| #define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HIST16_PARAM1_VALUE5_MASK) |
| #define PXP_HIST16_PARAM1_RSVD5_MASK 0xE000u |
| #define PXP_HIST16_PARAM1_RSVD5_SHIFT 13 |
| #define PXP_HIST16_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HIST16_PARAM1_RSVD5_MASK) |
| #define PXP_HIST16_PARAM1_VALUE6_MASK 0x1F0000u |
| #define PXP_HIST16_PARAM1_VALUE6_SHIFT 16 |
| #define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HIST16_PARAM1_VALUE6_MASK) |
| #define PXP_HIST16_PARAM1_RSVD6_MASK 0xE00000u |
| #define PXP_HIST16_PARAM1_RSVD6_SHIFT 21 |
| #define PXP_HIST16_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HIST16_PARAM1_RSVD6_MASK) |
| #define PXP_HIST16_PARAM1_VALUE7_MASK 0x1F000000u |
| #define PXP_HIST16_PARAM1_VALUE7_SHIFT 24 |
| #define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HIST16_PARAM1_VALUE7_MASK) |
| #define PXP_HIST16_PARAM1_RSVD7_MASK 0xE0000000u |
| #define PXP_HIST16_PARAM1_RSVD7_SHIFT 29 |
| #define PXP_HIST16_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HIST16_PARAM1_RSVD7_MASK) |
| /* HIST16_PARAM2 Bit Fields */ |
| #define PXP_HIST16_PARAM2_VALUE8_MASK 0x1Fu |
| #define PXP_HIST16_PARAM2_VALUE8_SHIFT 0 |
| #define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HIST16_PARAM2_VALUE8_MASK) |
| #define PXP_HIST16_PARAM2_RSVD8_MASK 0xE0u |
| #define PXP_HIST16_PARAM2_RSVD8_SHIFT 5 |
| #define PXP_HIST16_PARAM2_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HIST16_PARAM2_RSVD8_MASK) |
| #define PXP_HIST16_PARAM2_VALUE9_MASK 0x1F00u |
| #define PXP_HIST16_PARAM2_VALUE9_SHIFT 8 |
| #define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HIST16_PARAM2_VALUE9_MASK) |
| #define PXP_HIST16_PARAM2_RSVD9_MASK 0xE000u |
| #define PXP_HIST16_PARAM2_RSVD9_SHIFT 13 |
| #define PXP_HIST16_PARAM2_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HIST16_PARAM2_RSVD9_MASK) |
| #define PXP_HIST16_PARAM2_VALUE10_MASK 0x1F0000u |
| #define PXP_HIST16_PARAM2_VALUE10_SHIFT 16 |
| #define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HIST16_PARAM2_VALUE10_MASK) |
| #define PXP_HIST16_PARAM2_RSVD10_MASK 0xE00000u |
| #define PXP_HIST16_PARAM2_RSVD10_SHIFT 21 |
| #define PXP_HIST16_PARAM2_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HIST16_PARAM2_RSVD10_MASK) |
| #define PXP_HIST16_PARAM2_VALUE11_MASK 0x1F000000u |
| #define PXP_HIST16_PARAM2_VALUE11_SHIFT 24 |
| #define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HIST16_PARAM2_VALUE11_MASK) |
| #define PXP_HIST16_PARAM2_RSVD11_MASK 0xE0000000u |
| #define PXP_HIST16_PARAM2_RSVD11_SHIFT 29 |
| #define PXP_HIST16_PARAM2_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HIST16_PARAM2_RSVD11_MASK) |
| /* HIST16_PARAM3 Bit Fields */ |
| #define PXP_HIST16_PARAM3_VALUE12_MASK 0x1Fu |
| #define PXP_HIST16_PARAM3_VALUE12_SHIFT 0 |
| #define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HIST16_PARAM3_VALUE12_MASK) |
| #define PXP_HIST16_PARAM3_RSVD12_MASK 0xE0u |
| #define PXP_HIST16_PARAM3_RSVD12_SHIFT 5 |
| #define PXP_HIST16_PARAM3_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HIST16_PARAM3_RSVD12_MASK) |
| #define PXP_HIST16_PARAM3_VALUE13_MASK 0x1F00u |
| #define PXP_HIST16_PARAM3_VALUE13_SHIFT 8 |
| #define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HIST16_PARAM3_VALUE13_MASK) |
| #define PXP_HIST16_PARAM3_RSVD13_MASK 0xE000u |
| #define PXP_HIST16_PARAM3_RSVD13_SHIFT 13 |
| #define PXP_HIST16_PARAM3_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HIST16_PARAM3_RSVD13_MASK) |
| #define PXP_HIST16_PARAM3_VALUE14_MASK 0x1F0000u |
| #define PXP_HIST16_PARAM3_VALUE14_SHIFT 16 |
| #define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HIST16_PARAM3_VALUE14_MASK) |
| #define PXP_HIST16_PARAM3_RSVD14_MASK 0xE00000u |
| #define PXP_HIST16_PARAM3_RSVD14_SHIFT 21 |
| #define PXP_HIST16_PARAM3_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HIST16_PARAM3_RSVD14_MASK) |
| #define PXP_HIST16_PARAM3_VALUE15_MASK 0x1F000000u |
| #define PXP_HIST16_PARAM3_VALUE15_SHIFT 24 |
| #define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HIST16_PARAM3_VALUE15_MASK) |
| #define PXP_HIST16_PARAM3_RSVD15_MASK 0xE0000000u |
| #define PXP_HIST16_PARAM3_RSVD15_SHIFT 29 |
| #define PXP_HIST16_PARAM3_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HIST16_PARAM3_RSVD15_MASK) |
| /* POWER Bit Fields */ |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0_MASK 0x7u |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0_SHIFT 0 |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY0_BANK0_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY0_BANK0_MASK) |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN_MASK 0x38u |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN_SHIFT 3 |
| #define PXP_POWER_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY0_BANKN_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY0_BANKN_MASK) |
| #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN_MASK 0x1C0u |
| #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN_SHIFT 6 |
| #define PXP_POWER_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_POWER_LUT_LP_STATE_WAY1_BANKN_SHIFT))&PXP_POWER_LUT_LP_STATE_WAY1_BANKN_MASK) |
| #define PXP_POWER_ROT_MEM_LP_STATE_MASK 0xE00u |
| #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT 9 |
| #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_POWER_ROT_MEM_LP_STATE_SHIFT))&PXP_POWER_ROT_MEM_LP_STATE_MASK) |
| #define PXP_POWER_CTRL_MASK 0xFFFFF000u |
| #define PXP_POWER_CTRL_SHIFT 12 |
| #define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_POWER_CTRL_SHIFT))&PXP_POWER_CTRL_MASK) |
| /* NEXT Bit Fields */ |
| #define PXP_NEXT_ENABLED_MASK 0x1u |
| #define PXP_NEXT_ENABLED_SHIFT 0 |
| #define PXP_NEXT_RSVD_MASK 0x2u |
| #define PXP_NEXT_RSVD_SHIFT 1 |
| #define PXP_NEXT_POINTER_MASK 0xFFFFFFFCu |
| #define PXP_NEXT_POINTER_SHIFT 2 |
| #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x))<<PXP_NEXT_POINTER_SHIFT))&PXP_NEXT_POINTER_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group PXP_Register_Masks */ |
| |
| /* PXP - Peripheral instance base addresses */ |
| /** Peripheral PXP base address */ |
| #define PXP_BASE (0x42218000u) |
| /** Peripheral PXP base pointer */ |
| #define PXP ((PXP_Type *)PXP_BASE) |
| #define PXP_BASE_PTR (PXP) |
| /** Array initializer of PXP peripheral base addresses */ |
| #define PXP_BASE_ADDRS { PXP_BASE } |
| /** Array initializer of PXP peripheral base pointers */ |
| #define PXP_BASE_PTRS { PXP } |
| /** Interrupt vectors for the PXP peripheral type */ |
| #define PXP_IRQS { PXP_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- PXP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros |
| * @{ |
| */ |
| |
| /* PXP - Register instance definitions */ |
| /* PXP */ |
| #define PXP_CTRL PXP_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_STAT PXP_STAT_REG(PXP_BASE_PTR) |
| #define PXP_OUT_CTRL PXP_OUT_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_OUT_BUF PXP_OUT_BUF_REG(PXP_BASE_PTR) |
| #define PXP_OUT_BUF2 PXP_OUT_BUF2_REG(PXP_BASE_PTR) |
| #define PXP_OUT_PITCH PXP_OUT_PITCH_REG(PXP_BASE_PTR) |
| #define PXP_OUT_LRC PXP_OUT_LRC_REG(PXP_BASE_PTR) |
| #define PXP_OUT_PS_ULC PXP_OUT_PS_ULC_REG(PXP_BASE_PTR) |
| #define PXP_OUT_PS_LRC PXP_OUT_PS_LRC_REG(PXP_BASE_PTR) |
| #define PXP_OUT_AS_ULC PXP_OUT_AS_ULC_REG(PXP_BASE_PTR) |
| #define PXP_OUT_AS_LRC PXP_OUT_AS_LRC_REG(PXP_BASE_PTR) |
| #define PXP_PS_CTRL PXP_PS_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_PS_BUF PXP_PS_BUF_REG(PXP_BASE_PTR) |
| #define PXP_PS_UBUF PXP_PS_UBUF_REG(PXP_BASE_PTR) |
| #define PXP_PS_VBUF PXP_PS_VBUF_REG(PXP_BASE_PTR) |
| #define PXP_PS_PITCH PXP_PS_PITCH_REG(PXP_BASE_PTR) |
| #define PXP_PS_BACKGROUND PXP_PS_BACKGROUND_REG(PXP_BASE_PTR) |
| #define PXP_PS_SCALE PXP_PS_SCALE_REG(PXP_BASE_PTR) |
| #define PXP_PS_OFFSET PXP_PS_OFFSET_REG(PXP_BASE_PTR) |
| #define PXP_PS_CLRKEYLOW PXP_PS_CLRKEYLOW_REG(PXP_BASE_PTR) |
| #define PXP_PS_CLRKEYHIGH PXP_PS_CLRKEYHIGH_REG(PXP_BASE_PTR) |
| #define PXP_AS_CTRL PXP_AS_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_AS_BUF PXP_AS_BUF_REG(PXP_BASE_PTR) |
| #define PXP_AS_PITCH PXP_AS_PITCH_REG(PXP_BASE_PTR) |
| #define PXP_AS_CLRKEYLOW PXP_AS_CLRKEYLOW_REG(PXP_BASE_PTR) |
| #define PXP_AS_CLRKEYHIGH PXP_AS_CLRKEYHIGH_REG(PXP_BASE_PTR) |
| #define PXP_CSC1_COEF0 PXP_CSC1_COEF0_REG(PXP_BASE_PTR) |
| #define PXP_CSC1_COEF1 PXP_CSC1_COEF1_REG(PXP_BASE_PTR) |
| #define PXP_CSC1_COEF2 PXP_CSC1_COEF2_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_CTRL PXP_CSC2_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF0 PXP_CSC2_COEF0_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF1 PXP_CSC2_COEF1_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF2 PXP_CSC2_COEF2_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF3 PXP_CSC2_COEF3_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF4 PXP_CSC2_COEF4_REG(PXP_BASE_PTR) |
| #define PXP_CSC2_COEF5 PXP_CSC2_COEF5_REG(PXP_BASE_PTR) |
| #define PXP_LUT_CTRL PXP_LUT_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_LUT_ADDR PXP_LUT_ADDR_REG(PXP_BASE_PTR) |
| #define PXP_LUT_DATA PXP_LUT_DATA_REG(PXP_BASE_PTR) |
| #define PXP_LUT_EXTMEM PXP_LUT_EXTMEM_REG(PXP_BASE_PTR) |
| #define PXP_CFA PXP_CFA_REG(PXP_BASE_PTR) |
| #define PXP_HIST_CTRL PXP_HIST_CTRL_REG(PXP_BASE_PTR) |
| #define PXP_HIST2_PARAM PXP_HIST2_PARAM_REG(PXP_BASE_PTR) |
| #define PXP_HIST4_PARAM PXP_HIST4_PARAM_REG(PXP_BASE_PTR) |
| #define PXP_HIST8_PARAM0 PXP_HIST8_PARAM0_REG(PXP_BASE_PTR) |
| #define PXP_HIST8_PARAM1 PXP_HIST8_PARAM1_REG(PXP_BASE_PTR) |
| #define PXP_HIST16_PARAM0 PXP_HIST16_PARAM0_REG(PXP_BASE_PTR) |
| #define PXP_HIST16_PARAM1 PXP_HIST16_PARAM1_REG(PXP_BASE_PTR) |
| #define PXP_HIST16_PARAM2 PXP_HIST16_PARAM2_REG(PXP_BASE_PTR) |
| #define PXP_HIST16_PARAM3 PXP_HIST16_PARAM3_REG(PXP_BASE_PTR) |
| #define PXP_POWER PXP_POWER_REG(PXP_BASE_PTR) |
| #define PXP_NEXT PXP_NEXT_REG(PXP_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group PXP_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group PXP_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** QuadSPI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ |
| __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ |
| __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ |
| __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ |
| __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ |
| __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ |
| __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ |
| __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ |
| __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ |
| uint8_t RESERVED_2[196]; |
| __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ |
| __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ |
| __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ |
| uint8_t RESERVED_4[60]; |
| __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ |
| __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ |
| uint8_t RESERVED_5[4]; |
| __I uint32_t SR; /**< Status Register, offset: 0x15C */ |
| __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ |
| __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ |
| __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ |
| __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ |
| uint8_t RESERVED_6[16]; |
| __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ |
| __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ |
| __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ |
| __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ |
| uint8_t RESERVED_7[112]; |
| __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ |
| uint8_t RESERVED_8[128]; |
| __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ |
| __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ |
| uint8_t RESERVED_9[8]; |
| __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ |
| } QuadSPI_Type, *QuadSPI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros |
| * @{ |
| */ |
| |
| /* QuadSPI - Register accessors */ |
| #define QuadSPI_MCR_REG(base) ((base)->MCR) |
| #define QuadSPI_IPCR_REG(base) ((base)->IPCR) |
| #define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) |
| #define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) |
| #define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) |
| #define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) |
| #define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) |
| #define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) |
| #define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) |
| #define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) |
| #define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) |
| #define QuadSPI_SFAR_REG(base) ((base)->SFAR) |
| #define QuadSPI_SMPR_REG(base) ((base)->SMPR) |
| #define QuadSPI_RBSR_REG(base) ((base)->RBSR) |
| #define QuadSPI_RBCT_REG(base) ((base)->RBCT) |
| #define QuadSPI_TBSR_REG(base) ((base)->TBSR) |
| #define QuadSPI_TBDR_REG(base) ((base)->TBDR) |
| #define QuadSPI_SR_REG(base) ((base)->SR) |
| #define QuadSPI_FR_REG(base) ((base)->FR) |
| #define QuadSPI_RSER_REG(base) ((base)->RSER) |
| #define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) |
| #define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) |
| #define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) |
| #define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) |
| #define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) |
| #define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) |
| #define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) |
| #define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) |
| #define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) |
| #define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks |
| * @{ |
| */ |
| |
| /* MCR Bit Fields */ |
| #define QuadSPI_MCR_SWRSTSD_MASK 0x1u |
| #define QuadSPI_MCR_SWRSTSD_SHIFT 0 |
| #define QuadSPI_MCR_SWRSTHD_MASK 0x2u |
| #define QuadSPI_MCR_SWRSTHD_SHIFT 1 |
| #define QuadSPI_MCR_DQS_EN_MASK 0x40u |
| #define QuadSPI_MCR_DQS_EN_SHIFT 6 |
| #define QuadSPI_MCR_DDR_EN_MASK 0x80u |
| #define QuadSPI_MCR_DDR_EN_SHIFT 7 |
| #define QuadSPI_MCR_CLR_RXF_MASK 0x400u |
| #define QuadSPI_MCR_CLR_RXF_SHIFT 10 |
| #define QuadSPI_MCR_CLR_TXF_MASK 0x800u |
| #define QuadSPI_MCR_CLR_TXF_SHIFT 11 |
| #define QuadSPI_MCR_MDIS_MASK 0x4000u |
| #define QuadSPI_MCR_MDIS_SHIFT 14 |
| #define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u |
| #define QuadSPI_MCR_SCLKCFG_SHIFT 24 |
| #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SCLKCFG_SHIFT))&QuadSPI_MCR_SCLKCFG_MASK) |
| /* IPCR Bit Fields */ |
| #define QuadSPI_IPCR_IDATSZ_MASK 0xFFFFu |
| #define QuadSPI_IPCR_IDATSZ_SHIFT 0 |
| #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK) |
| #define QuadSPI_IPCR_PAR_EN_MASK 0x10000u |
| #define QuadSPI_IPCR_PAR_EN_SHIFT 16 |
| #define QuadSPI_IPCR_SEQID_MASK 0xF000000u |
| #define QuadSPI_IPCR_SEQID_SHIFT 24 |
| #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK) |
| /* FLSHCR Bit Fields */ |
| #define QuadSPI_FLSHCR_TCSS_MASK 0xFu |
| #define QuadSPI_FLSHCR_TCSS_SHIFT 0 |
| #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK) |
| #define QuadSPI_FLSHCR_TCSH_MASK 0xF00u |
| #define QuadSPI_FLSHCR_TCSH_SHIFT 8 |
| #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK) |
| /* BUF0CR Bit Fields */ |
| #define QuadSPI_BUF0CR_MSTRID_MASK 0xFu |
| #define QuadSPI_BUF0CR_MSTRID_SHIFT 0 |
| #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK) |
| #define QuadSPI_BUF0CR_ADATSZ_MASK 0xFF00u |
| #define QuadSPI_BUF0CR_ADATSZ_SHIFT 8 |
| #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK) |
| #define QuadSPI_BUF0CR_HP_EN_MASK 0x80000000u |
| #define QuadSPI_BUF0CR_HP_EN_SHIFT 31 |
| /* BUF1CR Bit Fields */ |
| #define QuadSPI_BUF1CR_MSTRID_MASK 0xFu |
| #define QuadSPI_BUF1CR_MSTRID_SHIFT 0 |
| #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK) |
| #define QuadSPI_BUF1CR_ADATSZ_MASK 0xFF00u |
| #define QuadSPI_BUF1CR_ADATSZ_SHIFT 8 |
| #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK) |
| /* BUF2CR Bit Fields */ |
| #define QuadSPI_BUF2CR_MSTRID_MASK 0xFu |
| #define QuadSPI_BUF2CR_MSTRID_SHIFT 0 |
| #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK) |
| #define QuadSPI_BUF2CR_ADATSZ_MASK 0xFF00u |
| #define QuadSPI_BUF2CR_ADATSZ_SHIFT 8 |
| #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK) |
| /* BUF3CR Bit Fields */ |
| #define QuadSPI_BUF3CR_MSTRID_MASK 0xFu |
| #define QuadSPI_BUF3CR_MSTRID_SHIFT 0 |
| #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK) |
| #define QuadSPI_BUF3CR_ADATSZ_MASK 0xFF00u |
| #define QuadSPI_BUF3CR_ADATSZ_SHIFT 8 |
| #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK) |
| #define QuadSPI_BUF3CR_ALLMST_MASK 0x80000000u |
| #define QuadSPI_BUF3CR_ALLMST_SHIFT 31 |
| /* BFGENCR Bit Fields */ |
| #define QuadSPI_BFGENCR_SEQID_MASK 0xF000u |
| #define QuadSPI_BFGENCR_SEQID_SHIFT 12 |
| #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK) |
| #define QuadSPI_BFGENCR_PAR_EN_MASK 0x10000u |
| #define QuadSPI_BFGENCR_PAR_EN_SHIFT 16 |
| /* BUF0IND Bit Fields */ |
| #define QuadSPI_BUF0IND_TPINDX0_MASK 0xFFFFFFF8u |
| #define QuadSPI_BUF0IND_TPINDX0_SHIFT 3 |
| #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK) |
| /* BUF1IND Bit Fields */ |
| #define QuadSPI_BUF1IND_TPINDX1_MASK 0xFFFFFFF8u |
| #define QuadSPI_BUF1IND_TPINDX1_SHIFT 3 |
| #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK) |
| /* BUF2IND Bit Fields */ |
| #define QuadSPI_BUF2IND_TPINDX2_MASK 0xFFFFFFF8u |
| #define QuadSPI_BUF2IND_TPINDX2_SHIFT 3 |
| #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK) |
| /* SFAR Bit Fields */ |
| #define QuadSPI_SFAR_SFADR_MASK 0xFFFFFFFFu |
| #define QuadSPI_SFAR_SFADR_SHIFT 0 |
| #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK) |
| /* SMPR Bit Fields */ |
| #define QuadSPI_SMPR_HSENA_MASK 0x1u |
| #define QuadSPI_SMPR_HSENA_SHIFT 0 |
| #define QuadSPI_SMPR_HSPHS_MASK 0x2u |
| #define QuadSPI_SMPR_HSPHS_SHIFT 1 |
| #define QuadSPI_SMPR_HSDLY_MASK 0x4u |
| #define QuadSPI_SMPR_HSDLY_SHIFT 2 |
| #define QuadSPI_SMPR_FSPHS_MASK 0x20u |
| #define QuadSPI_SMPR_FSPHS_SHIFT 5 |
| #define QuadSPI_SMPR_FSDLY_MASK 0x40u |
| #define QuadSPI_SMPR_FSDLY_SHIFT 6 |
| #define QuadSPI_SMPR_DDRSMP_MASK 0x70000u |
| #define QuadSPI_SMPR_DDRSMP_SHIFT 16 |
| #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK) |
| /* RBSR Bit Fields */ |
| #define QuadSPI_RBSR_RDBFL_MASK 0x3F00u |
| #define QuadSPI_RBSR_RDBFL_SHIFT 8 |
| #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK) |
| #define QuadSPI_RBSR_RDCTR_MASK 0xFFFF0000u |
| #define QuadSPI_RBSR_RDCTR_SHIFT 16 |
| #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK) |
| /* RBCT Bit Fields */ |
| #define QuadSPI_RBCT_WMRK_MASK 0x1Fu |
| #define QuadSPI_RBCT_WMRK_SHIFT 0 |
| #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK) |
| #define QuadSPI_RBCT_RXBRD_MASK 0x100u |
| #define QuadSPI_RBCT_RXBRD_SHIFT 8 |
| /* TBSR Bit Fields */ |
| #define QuadSPI_TBSR_TRBFL_MASK 0x3F00u |
| #define QuadSPI_TBSR_TRBFL_SHIFT 8 |
| #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK) |
| #define QuadSPI_TBSR_TRCTR_MASK 0xFFFF0000u |
| #define QuadSPI_TBSR_TRCTR_SHIFT 16 |
| #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK) |
| /* TBDR Bit Fields */ |
| #define QuadSPI_TBDR_TXDATA_MASK 0xFFFFFFFFu |
| #define QuadSPI_TBDR_TXDATA_SHIFT 0 |
| #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK) |
| /* SR Bit Fields */ |
| #define QuadSPI_SR_BUSY_MASK 0x1u |
| #define QuadSPI_SR_BUSY_SHIFT 0 |
| #define QuadSPI_SR_IP_ACC_MASK 0x2u |
| #define QuadSPI_SR_IP_ACC_SHIFT 1 |
| #define QuadSPI_SR_AHB_ACC_MASK 0x4u |
| #define QuadSPI_SR_AHB_ACC_SHIFT 2 |
| #define QuadSPI_SR_RESERVED_MASK 0x8u |
| #define QuadSPI_SR_RESERVED_SHIFT 3 |
| #define QuadSPI_SR_AHBGNT_MASK 0x20u |
| #define QuadSPI_SR_AHBGNT_SHIFT 5 |
| #define QuadSPI_SR_AHBTRN_MASK 0x40u |
| #define QuadSPI_SR_AHBTRN_SHIFT 6 |
| #define QuadSPI_SR_AHB0NE_MASK 0x80u |
| #define QuadSPI_SR_AHB0NE_SHIFT 7 |
| #define QuadSPI_SR_AHB1NE_MASK 0x100u |
| #define QuadSPI_SR_AHB1NE_SHIFT 8 |
| #define QuadSPI_SR_AHB2NE_MASK 0x200u |
| #define QuadSPI_SR_AHB2NE_SHIFT 9 |
| #define QuadSPI_SR_AHB3NE_MASK 0x400u |
| #define QuadSPI_SR_AHB3NE_SHIFT 10 |
| #define QuadSPI_SR_AHB0FUL_MASK 0x800u |
| #define QuadSPI_SR_AHB0FUL_SHIFT 11 |
| #define QuadSPI_SR_AHB1FUL_MASK 0x1000u |
| #define QuadSPI_SR_AHB1FUL_SHIFT 12 |
| #define QuadSPI_SR_AHB2FUL_MASK 0x2000u |
| #define QuadSPI_SR_AHB2FUL_SHIFT 13 |
| #define QuadSPI_SR_AHB3FUL_MASK 0x4000u |
| #define QuadSPI_SR_AHB3FUL_SHIFT 14 |
| #define QuadSPI_SR_RXWE_MASK 0x10000u |
| #define QuadSPI_SR_RXWE_SHIFT 16 |
| #define QuadSPI_SR_RXFULL_MASK 0x80000u |
| #define QuadSPI_SR_RXFULL_SHIFT 19 |
| #define QuadSPI_SR_RXDMA_MASK 0x800000u |
| #define QuadSPI_SR_RXDMA_SHIFT 23 |
| #define QuadSPI_SR_TXEDA_MASK 0x1000000u |
| #define QuadSPI_SR_TXEDA_SHIFT 24 |
| #define QuadSPI_SR_TXFULL_MASK 0x8000000u |
| #define QuadSPI_SR_TXFULL_SHIFT 27 |
| #define QuadSPI_SR_DLPSMP_MASK 0xE0000000u |
| #define QuadSPI_SR_DLPSMP_SHIFT 29 |
| #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK) |
| /* FR Bit Fields */ |
| #define QuadSPI_FR_TFF_MASK 0x1u |
| #define QuadSPI_FR_TFF_SHIFT 0 |
| #define QuadSPI_FR_IPGEF_MASK 0x10u |
| #define QuadSPI_FR_IPGEF_SHIFT 4 |
| #define QuadSPI_FR_IPIEF_MASK 0x40u |
| #define QuadSPI_FR_IPIEF_SHIFT 6 |
| #define QuadSPI_FR_IPAEF_MASK 0x80u |
| #define QuadSPI_FR_IPAEF_SHIFT 7 |
| #define QuadSPI_FR_IUEF_MASK 0x800u |
| #define QuadSPI_FR_IUEF_SHIFT 11 |
| #define QuadSPI_FR_ABOF_MASK 0x1000u |
| #define QuadSPI_FR_ABOF_SHIFT 12 |
| #define QuadSPI_FR_ABSEF_MASK 0x8000u |
| #define QuadSPI_FR_ABSEF_SHIFT 15 |
| #define QuadSPI_FR_RBDF_MASK 0x10000u |
| #define QuadSPI_FR_RBDF_SHIFT 16 |
| #define QuadSPI_FR_RBOF_MASK 0x20000u |
| #define QuadSPI_FR_RBOF_SHIFT 17 |
| #define QuadSPI_FR_ILLINE_MASK 0x800000u |
| #define QuadSPI_FR_ILLINE_SHIFT 23 |
| #define QuadSPI_FR_TBUF_MASK 0x4000000u |
| #define QuadSPI_FR_TBUF_SHIFT 26 |
| #define QuadSPI_FR_TBFF_MASK 0x8000000u |
| #define QuadSPI_FR_TBFF_SHIFT 27 |
| #define QuadSPI_FR_RESERVED_MASK 0x60000000u |
| #define QuadSPI_FR_RESERVED_SHIFT 29 |
| #define QuadSPI_FR_RESERVED(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_RESERVED_SHIFT))&QuadSPI_FR_RESERVED_MASK) |
| #define QuadSPI_FR_DLPFF_MASK 0x80000000u |
| #define QuadSPI_FR_DLPFF_SHIFT 31 |
| /* RSER Bit Fields */ |
| #define QuadSPI_RSER_TFIE_MASK 0x1u |
| #define QuadSPI_RSER_TFIE_SHIFT 0 |
| #define QuadSPI_RSER_IPGEIE_MASK 0x10u |
| #define QuadSPI_RSER_IPGEIE_SHIFT 4 |
| #define QuadSPI_RSER_IPIEIE_MASK 0x40u |
| #define QuadSPI_RSER_IPIEIE_SHIFT 6 |
| #define QuadSPI_RSER_IPAEIE_MASK 0x80u |
| #define QuadSPI_RSER_IPAEIE_SHIFT 7 |
| #define QuadSPI_RSER_IUEIE_MASK 0x800u |
| #define QuadSPI_RSER_IUEIE_SHIFT 11 |
| #define QuadSPI_RSER_ABOIE_MASK 0x1000u |
| #define QuadSPI_RSER_ABOIE_SHIFT 12 |
| #define QuadSPI_RSER_ABSEIE_MASK 0x8000u |
| #define QuadSPI_RSER_ABSEIE_SHIFT 15 |
| #define QuadSPI_RSER_RBDIE_MASK 0x10000u |
| #define QuadSPI_RSER_RBDIE_SHIFT 16 |
| #define QuadSPI_RSER_RBOIE_MASK 0x20000u |
| #define QuadSPI_RSER_RBOIE_SHIFT 17 |
| #define QuadSPI_RSER_RBDDE_MASK 0x200000u |
| #define QuadSPI_RSER_RBDDE_SHIFT 21 |
| #define QuadSPI_RSER_ILLINIE_MASK 0x800000u |
| #define QuadSPI_RSER_ILLINIE_SHIFT 23 |
| #define QuadSPI_RSER_TBUIE_MASK 0x4000000u |
| #define QuadSPI_RSER_TBUIE_SHIFT 26 |
| #define QuadSPI_RSER_TBFIE_MASK 0x8000000u |
| #define QuadSPI_RSER_TBFIE_SHIFT 27 |
| #define QuadSPI_RSER_RESERVED_MASK 0x10000000u |
| #define QuadSPI_RSER_RESERVED_SHIFT 28 |
| #define QuadSPI_RSER_DLPFIE_MASK 0x80000000u |
| #define QuadSPI_RSER_DLPFIE_SHIFT 31 |
| /* SPNDST Bit Fields */ |
| #define QuadSPI_SPNDST_SUSPND_MASK 0x1u |
| #define QuadSPI_SPNDST_SUSPND_SHIFT 0 |
| #define QuadSPI_SPNDST_SPDBUF_MASK 0xC0u |
| #define QuadSPI_SPNDST_SPDBUF_SHIFT 6 |
| #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK) |
| #define QuadSPI_SPNDST_DATLFT_MASK 0xFE00u |
| #define QuadSPI_SPNDST_DATLFT_SHIFT 9 |
| #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK) |
| /* SPTRCLR Bit Fields */ |
| #define QuadSPI_SPTRCLR_BFPTRC_MASK 0x1u |
| #define QuadSPI_SPTRCLR_BFPTRC_SHIFT 0 |
| #define QuadSPI_SPTRCLR_IPPTRC_MASK 0x100u |
| #define QuadSPI_SPTRCLR_IPPTRC_SHIFT 8 |
| /* SFA1AD Bit Fields */ |
| #define QuadSPI_SFA1AD_TPADA1_MASK 0xFFFFFC00u |
| #define QuadSPI_SFA1AD_TPADA1_SHIFT 10 |
| #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK) |
| /* SFA2AD Bit Fields */ |
| #define QuadSPI_SFA2AD_TPADA2_MASK 0xFFFFFC00u |
| #define QuadSPI_SFA2AD_TPADA2_SHIFT 10 |
| #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK) |
| /* SFB1AD Bit Fields */ |
| #define QuadSPI_SFB1AD_TPADB1_MASK 0xFFFFFC00u |
| #define QuadSPI_SFB1AD_TPADB1_SHIFT 10 |
| #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK) |
| /* SFB2AD Bit Fields */ |
| #define QuadSPI_SFB2AD_TPADB2_MASK 0xFFFFFC00u |
| #define QuadSPI_SFB2AD_TPADB2_SHIFT 10 |
| #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK) |
| /* RBDR Bit Fields */ |
| #define QuadSPI_RBDR_RXDATA_MASK 0xFFFFFFFFu |
| #define QuadSPI_RBDR_RXDATA_SHIFT 0 |
| #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK) |
| /* LUTKEY Bit Fields */ |
| #define QuadSPI_LUTKEY_KEY_MASK 0xFFFFFFFFu |
| #define QuadSPI_LUTKEY_KEY_SHIFT 0 |
| #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK) |
| /* LCKCR Bit Fields */ |
| #define QuadSPI_LCKCR_LOCK_MASK 0x1u |
| #define QuadSPI_LCKCR_LOCK_SHIFT 0 |
| #define QuadSPI_LCKCR_UNLOCK_MASK 0x2u |
| #define QuadSPI_LCKCR_UNLOCK_SHIFT 1 |
| /* LUT Bit Fields */ |
| #define QuadSPI_LUT_OPRND0_MASK 0xFFu |
| #define QuadSPI_LUT_OPRND0_SHIFT 0 |
| #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK) |
| #define QuadSPI_LUT_PAD0_MASK 0x300u |
| #define QuadSPI_LUT_PAD0_SHIFT 8 |
| #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK) |
| #define QuadSPI_LUT_INSTR0_MASK 0xFC00u |
| #define QuadSPI_LUT_INSTR0_SHIFT 10 |
| #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK) |
| #define QuadSPI_LUT_OPRND1_MASK 0xFF0000u |
| #define QuadSPI_LUT_OPRND1_SHIFT 16 |
| #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK) |
| #define QuadSPI_LUT_PAD1_MASK 0x3000000u |
| #define QuadSPI_LUT_PAD1_SHIFT 24 |
| #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK) |
| #define QuadSPI_LUT_INSTR1_MASK 0xFC000000u |
| #define QuadSPI_LUT_INSTR1_SHIFT 26 |
| #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Register_Masks */ |
| |
| /* QuadSPI - Peripheral instance base addresses */ |
| /** Peripheral QuadSPI1 base address */ |
| #define QuadSPI1_BASE (0x421E0000u) |
| /** Peripheral QuadSPI1 base pointer */ |
| #define QuadSPI1 ((QuadSPI_Type *)QuadSPI1_BASE) |
| #define QuadSPI1_BASE_PTR (QuadSPI1) |
| /** Peripheral QuadSPI2 base address */ |
| #define QuadSPI2_BASE (0x421E4000u) |
| /** Peripheral QuadSPI2 base pointer */ |
| #define QuadSPI2 ((QuadSPI_Type *)QuadSPI2_BASE) |
| #define QuadSPI2_BASE_PTR (QuadSPI2) |
| /** Array initializer of QuadSPI peripheral base addresses */ |
| #define QuadSPI_BASE_ADDRS { QuadSPI1_BASE, QuadSPI2_BASE } |
| /** Array initializer of QuadSPI peripheral base pointers */ |
| #define QuadSPI_BASE_PTRS { QuadSPI1, QuadSPI2 } |
| /** Interrupt vectors for the QuadSPI peripheral type */ |
| #define QSPI_IRQS { QSPI1_IRQn, QSPI2_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- QuadSPI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros |
| * @{ |
| */ |
| |
| /* QuadSPI - Register instance definitions */ |
| /* QuadSPI1 */ |
| #define QuadSPI1_MCR QuadSPI_MCR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_IPCR QuadSPI_IPCR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_FLSHCR QuadSPI_FLSHCR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF0CR QuadSPI_BUF0CR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF1CR QuadSPI_BUF1CR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF2CR QuadSPI_BUF2CR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF3CR QuadSPI_BUF3CR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BFGENCR QuadSPI_BFGENCR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF0IND QuadSPI_BUF0IND_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF1IND QuadSPI_BUF1IND_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_BUF2IND QuadSPI_BUF2IND_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SFAR QuadSPI_SFAR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SMPR QuadSPI_SMPR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_RBSR QuadSPI_RBSR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_RBCT QuadSPI_RBCT_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_TBSR QuadSPI_TBSR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_TBDR QuadSPI_TBDR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SR QuadSPI_SR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_FR QuadSPI_FR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_RSER QuadSPI_RSER_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SPNDST QuadSPI_SPNDST_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SPTRCLR QuadSPI_SPTRCLR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SFA1AD QuadSPI_SFA1AD_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SFA2AD QuadSPI_SFA2AD_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SFB1AD QuadSPI_SFB1AD_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_SFB2AD QuadSPI_SFB2AD_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_RBDR0 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,0) |
| #define QuadSPI1_RBDR1 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,1) |
| #define QuadSPI1_RBDR2 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,2) |
| #define QuadSPI1_RBDR3 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,3) |
| #define QuadSPI1_RBDR4 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,4) |
| #define QuadSPI1_RBDR5 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,5) |
| #define QuadSPI1_RBDR6 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,6) |
| #define QuadSPI1_RBDR7 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,7) |
| #define QuadSPI1_RBDR8 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,8) |
| #define QuadSPI1_RBDR9 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,9) |
| #define QuadSPI1_RBDR10 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,10) |
| #define QuadSPI1_RBDR11 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,11) |
| #define QuadSPI1_RBDR12 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,12) |
| #define QuadSPI1_RBDR13 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,13) |
| #define QuadSPI1_RBDR14 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,14) |
| #define QuadSPI1_RBDR15 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,15) |
| #define QuadSPI1_RBDR16 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,16) |
| #define QuadSPI1_RBDR17 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,17) |
| #define QuadSPI1_RBDR18 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,18) |
| #define QuadSPI1_RBDR19 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,19) |
| #define QuadSPI1_RBDR20 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,20) |
| #define QuadSPI1_RBDR21 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,21) |
| #define QuadSPI1_RBDR22 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,22) |
| #define QuadSPI1_RBDR23 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,23) |
| #define QuadSPI1_RBDR24 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,24) |
| #define QuadSPI1_RBDR25 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,25) |
| #define QuadSPI1_RBDR26 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,26) |
| #define QuadSPI1_RBDR27 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,27) |
| #define QuadSPI1_RBDR28 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,28) |
| #define QuadSPI1_RBDR29 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,29) |
| #define QuadSPI1_RBDR30 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,30) |
| #define QuadSPI1_RBDR31 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,31) |
| #define QuadSPI1_LUTKEY QuadSPI_LUTKEY_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_LCKCR QuadSPI_LCKCR_REG(QuadSPI1_BASE_PTR) |
| #define QuadSPI1_LUT0 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,0) |
| #define QuadSPI1_LUT1 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,1) |
| #define QuadSPI1_LUT2 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,2) |
| #define QuadSPI1_LUT3 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,3) |
| #define QuadSPI1_LUT4 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,4) |
| #define QuadSPI1_LUT5 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,5) |
| #define QuadSPI1_LUT6 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,6) |
| #define QuadSPI1_LUT7 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,7) |
| #define QuadSPI1_LUT8 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,8) |
| #define QuadSPI1_LUT9 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,9) |
| #define QuadSPI1_LUT10 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,10) |
| #define QuadSPI1_LUT11 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,11) |
| #define QuadSPI1_LUT12 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,12) |
| #define QuadSPI1_LUT13 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,13) |
| #define QuadSPI1_LUT14 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,14) |
| #define QuadSPI1_LUT15 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,15) |
| #define QuadSPI1_LUT16 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,16) |
| #define QuadSPI1_LUT17 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,17) |
| #define QuadSPI1_LUT18 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,18) |
| #define QuadSPI1_LUT19 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,19) |
| #define QuadSPI1_LUT20 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,20) |
| #define QuadSPI1_LUT21 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,21) |
| #define QuadSPI1_LUT22 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,22) |
| #define QuadSPI1_LUT23 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,23) |
| #define QuadSPI1_LUT24 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,24) |
| #define QuadSPI1_LUT25 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,25) |
| #define QuadSPI1_LUT26 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,26) |
| #define QuadSPI1_LUT27 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,27) |
| #define QuadSPI1_LUT28 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,28) |
| #define QuadSPI1_LUT29 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,29) |
| #define QuadSPI1_LUT30 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,30) |
| #define QuadSPI1_LUT31 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,31) |
| #define QuadSPI1_LUT32 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,32) |
| #define QuadSPI1_LUT33 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,33) |
| #define QuadSPI1_LUT34 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,34) |
| #define QuadSPI1_LUT35 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,35) |
| #define QuadSPI1_LUT36 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,36) |
| #define QuadSPI1_LUT37 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,37) |
| #define QuadSPI1_LUT38 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,38) |
| #define QuadSPI1_LUT39 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,39) |
| #define QuadSPI1_LUT40 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,40) |
| #define QuadSPI1_LUT41 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,41) |
| #define QuadSPI1_LUT42 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,42) |
| #define QuadSPI1_LUT43 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,43) |
| #define QuadSPI1_LUT44 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,44) |
| #define QuadSPI1_LUT45 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,45) |
| #define QuadSPI1_LUT46 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,46) |
| #define QuadSPI1_LUT47 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,47) |
| #define QuadSPI1_LUT48 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,48) |
| #define QuadSPI1_LUT49 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,49) |
| #define QuadSPI1_LUT50 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,50) |
| #define QuadSPI1_LUT51 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,51) |
| #define QuadSPI1_LUT52 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,52) |
| #define QuadSPI1_LUT53 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,53) |
| #define QuadSPI1_LUT54 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,54) |
| #define QuadSPI1_LUT55 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,55) |
| #define QuadSPI1_LUT56 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,56) |
| #define QuadSPI1_LUT57 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,57) |
| #define QuadSPI1_LUT58 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,58) |
| #define QuadSPI1_LUT59 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,59) |
| #define QuadSPI1_LUT60 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,60) |
| #define QuadSPI1_LUT61 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,61) |
| #define QuadSPI1_LUT62 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,62) |
| #define QuadSPI1_LUT63 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,63) |
| /* QuadSPI2 */ |
| #define QuadSPI2_MCR QuadSPI_MCR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_IPCR QuadSPI_IPCR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_FLSHCR QuadSPI_FLSHCR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF0CR QuadSPI_BUF0CR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF1CR QuadSPI_BUF1CR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF2CR QuadSPI_BUF2CR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF3CR QuadSPI_BUF3CR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BFGENCR QuadSPI_BFGENCR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF0IND QuadSPI_BUF0IND_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF1IND QuadSPI_BUF1IND_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_BUF2IND QuadSPI_BUF2IND_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SFAR QuadSPI_SFAR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SMPR QuadSPI_SMPR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_RBSR QuadSPI_RBSR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_RBCT QuadSPI_RBCT_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_TBSR QuadSPI_TBSR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_TBDR QuadSPI_TBDR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SR QuadSPI_SR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_FR QuadSPI_FR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_RSER QuadSPI_RSER_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SPNDST QuadSPI_SPNDST_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SPTRCLR QuadSPI_SPTRCLR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SFA1AD QuadSPI_SFA1AD_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SFA2AD QuadSPI_SFA2AD_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SFB1AD QuadSPI_SFB1AD_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_SFB2AD QuadSPI_SFB2AD_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_RBDR0 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,0) |
| #define QuadSPI2_RBDR1 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,1) |
| #define QuadSPI2_RBDR2 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,2) |
| #define QuadSPI2_RBDR3 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,3) |
| #define QuadSPI2_RBDR4 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,4) |
| #define QuadSPI2_RBDR5 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,5) |
| #define QuadSPI2_RBDR6 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,6) |
| #define QuadSPI2_RBDR7 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,7) |
| #define QuadSPI2_RBDR8 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,8) |
| #define QuadSPI2_RBDR9 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,9) |
| #define QuadSPI2_RBDR10 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,10) |
| #define QuadSPI2_RBDR11 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,11) |
| #define QuadSPI2_RBDR12 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,12) |
| #define QuadSPI2_RBDR13 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,13) |
| #define QuadSPI2_RBDR14 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,14) |
| #define QuadSPI2_RBDR15 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,15) |
| #define QuadSPI2_RBDR16 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,16) |
| #define QuadSPI2_RBDR17 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,17) |
| #define QuadSPI2_RBDR18 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,18) |
| #define QuadSPI2_RBDR19 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,19) |
| #define QuadSPI2_RBDR20 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,20) |
| #define QuadSPI2_RBDR21 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,21) |
| #define QuadSPI2_RBDR22 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,22) |
| #define QuadSPI2_RBDR23 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,23) |
| #define QuadSPI2_RBDR24 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,24) |
| #define QuadSPI2_RBDR25 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,25) |
| #define QuadSPI2_RBDR26 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,26) |
| #define QuadSPI2_RBDR27 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,27) |
| #define QuadSPI2_RBDR28 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,28) |
| #define QuadSPI2_RBDR29 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,29) |
| #define QuadSPI2_RBDR30 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,30) |
| #define QuadSPI2_RBDR31 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,31) |
| #define QuadSPI2_LUTKEY QuadSPI_LUTKEY_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_LCKCR QuadSPI_LCKCR_REG(QuadSPI2_BASE_PTR) |
| #define QuadSPI2_LUT0 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,0) |
| #define QuadSPI2_LUT1 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,1) |
| #define QuadSPI2_LUT2 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,2) |
| #define QuadSPI2_LUT3 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,3) |
| #define QuadSPI2_LUT4 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,4) |
| #define QuadSPI2_LUT5 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,5) |
| #define QuadSPI2_LUT6 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,6) |
| #define QuadSPI2_LUT7 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,7) |
| #define QuadSPI2_LUT8 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,8) |
| #define QuadSPI2_LUT9 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,9) |
| #define QuadSPI2_LUT10 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,10) |
| #define QuadSPI2_LUT11 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,11) |
| #define QuadSPI2_LUT12 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,12) |
| #define QuadSPI2_LUT13 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,13) |
| #define QuadSPI2_LUT14 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,14) |
| #define QuadSPI2_LUT15 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,15) |
| #define QuadSPI2_LUT16 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,16) |
| #define QuadSPI2_LUT17 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,17) |
| #define QuadSPI2_LUT18 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,18) |
| #define QuadSPI2_LUT19 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,19) |
| #define QuadSPI2_LUT20 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,20) |
| #define QuadSPI2_LUT21 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,21) |
| #define QuadSPI2_LUT22 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,22) |
| #define QuadSPI2_LUT23 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,23) |
| #define QuadSPI2_LUT24 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,24) |
| #define QuadSPI2_LUT25 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,25) |
| #define QuadSPI2_LUT26 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,26) |
| #define QuadSPI2_LUT27 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,27) |
| #define QuadSPI2_LUT28 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,28) |
| #define QuadSPI2_LUT29 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,29) |
| #define QuadSPI2_LUT30 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,30) |
| #define QuadSPI2_LUT31 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,31) |
| #define QuadSPI2_LUT32 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,32) |
| #define QuadSPI2_LUT33 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,33) |
| #define QuadSPI2_LUT34 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,34) |
| #define QuadSPI2_LUT35 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,35) |
| #define QuadSPI2_LUT36 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,36) |
| #define QuadSPI2_LUT37 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,37) |
| #define QuadSPI2_LUT38 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,38) |
| #define QuadSPI2_LUT39 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,39) |
| #define QuadSPI2_LUT40 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,40) |
| #define QuadSPI2_LUT41 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,41) |
| #define QuadSPI2_LUT42 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,42) |
| #define QuadSPI2_LUT43 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,43) |
| #define QuadSPI2_LUT44 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,44) |
| #define QuadSPI2_LUT45 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,45) |
| #define QuadSPI2_LUT46 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,46) |
| #define QuadSPI2_LUT47 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,47) |
| #define QuadSPI2_LUT48 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,48) |
| #define QuadSPI2_LUT49 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,49) |
| #define QuadSPI2_LUT50 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,50) |
| #define QuadSPI2_LUT51 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,51) |
| #define QuadSPI2_LUT52 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,52) |
| #define QuadSPI2_LUT53 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,53) |
| #define QuadSPI2_LUT54 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,54) |
| #define QuadSPI2_LUT55 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,55) |
| #define QuadSPI2_LUT56 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,56) |
| #define QuadSPI2_LUT57 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,57) |
| #define QuadSPI2_LUT58 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,58) |
| #define QuadSPI2_LUT59 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,59) |
| #define QuadSPI2_LUT60 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,60) |
| #define QuadSPI2_LUT61 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,61) |
| #define QuadSPI2_LUT62 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,62) |
| #define QuadSPI2_LUT63 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,63) |
| /* QuadSPI - Register array accessors */ |
| #define QuadSPI1_RBDR(index) QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,index) |
| #define QuadSPI2_RBDR(index) QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,index) |
| #define QuadSPI1_LUT(index) QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,index) |
| #define QuadSPI2_LUT(index) QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group QuadSPI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** RDC - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t VIR; /**< Version Information, offset: 0x0 */ |
| uint8_t RESERVED_0[32]; |
| __IO uint32_t STAT; /**< Status, offset: 0x24 */ |
| __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */ |
| __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */ |
| uint8_t RESERVED_1[464]; |
| __IO uint32_t MDA[32]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */ |
| uint8_t RESERVED_2[384]; |
| __IO uint32_t PDAP[110]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */ |
| uint8_t RESERVED_3[584]; |
| struct { /* offset: 0x800, array step: 0x10 */ |
| __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */ |
| __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ |
| __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ |
| __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ |
| } MR[55]; |
| } RDC_Type, *RDC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros |
| * @{ |
| */ |
| |
| /* RDC - Register accessors */ |
| #define RDC_VIR_REG(base) ((base)->VIR) |
| #define RDC_STAT_REG(base) ((base)->STAT) |
| #define RDC_INTCTRL_REG(base) ((base)->INTCTRL) |
| #define RDC_INTSTAT_REG(base) ((base)->INTSTAT) |
| #define RDC_MDA_REG(base,index) ((base)->MDA[index]) |
| #define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) |
| #define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) |
| #define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) |
| #define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) |
| #define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Register_Accessor_Macros */ |
| /* ---------------------------------------------------------------------------- |
| -- RDC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Register_Masks RDC Register Masks |
| * @{ |
| */ |
| |
| /* VIR Bit Fields */ |
| #define RDC_VIR_NDID_MASK 0xFu |
| #define RDC_VIR_NDID_SHIFT 0 |
| #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NDID_SHIFT))&RDC_VIR_NDID_MASK) |
| #define RDC_VIR_NMSTR_MASK 0xFF0u |
| #define RDC_VIR_NMSTR_SHIFT 4 |
| #define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NMSTR_SHIFT))&RDC_VIR_NMSTR_MASK) |
| #define RDC_VIR_NPER_MASK 0xFF000u |
| #define RDC_VIR_NPER_SHIFT 12 |
| #define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NPER_SHIFT))&RDC_VIR_NPER_MASK) |
| #define RDC_VIR_NRGN_MASK 0xFF00000u |
| #define RDC_VIR_NRGN_SHIFT 20 |
| #define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NRGN_SHIFT))&RDC_VIR_NRGN_MASK) |
| /* STAT Bit Fields */ |
| #define RDC_STAT_DID_MASK 0xFu |
| #define RDC_STAT_DID_SHIFT 0 |
| #define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x))<<RDC_STAT_DID_SHIFT))&RDC_STAT_DID_MASK) |
| #define RDC_STAT_PDS_MASK 0x100u |
| #define RDC_STAT_PDS_SHIFT 8 |
| /* INTCTRL Bit Fields */ |
| #define RDC_INTCTRL_RCI_EN_MASK 0x1u |
| #define RDC_INTCTRL_RCI_EN_SHIFT 0 |
| /* INTSTAT Bit Fields */ |
| #define RDC_INTSTAT_INT_MASK 0x1u |
| #define RDC_INTSTAT_INT_SHIFT 0 |
| /* MDA Bit Fields */ |
| #define RDC_MDA_DID_MASK 0x3u |
| #define RDC_MDA_DID_SHIFT 0 |
| #define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x))<<RDC_MDA_DID_SHIFT))&RDC_MDA_DID_MASK) |
| #define RDC_MDA_LCK_MASK 0x80000000u |
| #define RDC_MDA_LCK_SHIFT 31 |
| /* PDAP Bit Fields */ |
| #define RDC_PDAP_D0W_MASK 0x1u |
| #define RDC_PDAP_D0W_SHIFT 0 |
| #define RDC_PDAP_D0R_MASK 0x2u |
| #define RDC_PDAP_D0R_SHIFT 1 |
| #define RDC_PDAP_D1W_MASK 0x4u |
| #define RDC_PDAP_D1W_SHIFT 2 |
| #define RDC_PDAP_D1R_MASK 0x8u |
| #define RDC_PDAP_D1R_SHIFT 3 |
| #define RDC_PDAP_D2W_MASK 0x10u |
| #define RDC_PDAP_D2W_SHIFT 4 |
| #define RDC_PDAP_D2R_MASK 0x20u |
| #define RDC_PDAP_D2R_SHIFT 5 |
| #define RDC_PDAP_D3W_MASK 0x40u |
| #define RDC_PDAP_D3W_SHIFT 6 |
| #define RDC_PDAP_D3R_MASK 0x80u |
| #define RDC_PDAP_D3R_SHIFT 7 |
| #define RDC_PDAP_SREQ_MASK 0x40000000u |
| #define RDC_PDAP_SREQ_SHIFT 30 |
| #define RDC_PDAP_LCK_MASK 0x80000000u |
| #define RDC_PDAP_LCK_SHIFT 31 |
| /* MRSA Bit Fields */ |
| #define RDC_MRSA_SADR_MASK 0xFFFFFF80u |
| #define RDC_MRSA_SADR_SHIFT 7 |
| #define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRSA_SADR_SHIFT))&RDC_MRSA_SADR_MASK) |
| /* MREA Bit Fields */ |
| #define RDC_MREA_EADR_MASK 0xFFFFFF80u |
| #define RDC_MREA_EADR_SHIFT 7 |
| #define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MREA_EADR_SHIFT))&RDC_MREA_EADR_MASK) |
| /* MRC Bit Fields */ |
| #define RDC_MRC_D0W_MASK 0x1u |
| #define RDC_MRC_D0W_SHIFT 0 |
| #define RDC_MRC_D0R_MASK 0x2u |
| #define RDC_MRC_D0R_SHIFT 1 |
| #define RDC_MRC_D1W_MASK 0x4u |
| #define RDC_MRC_D1W_SHIFT 2 |
| #define RDC_MRC_D1R_MASK 0x8u |
| #define RDC_MRC_D1R_SHIFT 3 |
| #define RDC_MRC_D2W_MASK 0x10u |
| #define RDC_MRC_D2W_SHIFT 4 |
| #define RDC_MRC_D2R_MASK 0x20u |
| #define RDC_MRC_D2R_SHIFT 5 |
| #define RDC_MRC_D3W_MASK 0x40u |
| #define RDC_MRC_D3W_SHIFT 6 |
| #define RDC_MRC_D3R_MASK 0x80u |
| #define RDC_MRC_D3R_SHIFT 7 |
| #define RDC_MRC_ENA_MASK 0x40000000u |
| #define RDC_MRC_ENA_SHIFT 30 |
| #define RDC_MRC_LCK_MASK 0x80000000u |
| #define RDC_MRC_LCK_SHIFT 31 |
| /* MRVS Bit Fields */ |
| #define RDC_MRVS_VDID_MASK 0x3u |
| #define RDC_MRVS_VDID_SHIFT 0 |
| #define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VDID_SHIFT))&RDC_MRVS_VDID_MASK) |
| #define RDC_MRVS_AD_MASK 0x10u |
| #define RDC_MRVS_AD_SHIFT 4 |
| #define RDC_MRVS_VADR_MASK 0xFFFFFFE0u |
| #define RDC_MRVS_VADR_SHIFT 5 |
| #define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VADR_SHIFT))&RDC_MRVS_VADR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Register_Masks */ |
| |
| /* RDC - Peripheral instance base addresses */ |
| /** Peripheral RDC base address */ |
| #define RDC_BASE (0x420FC000u) |
| /** Peripheral RDC base pointer */ |
| #define RDC ((RDC_Type *)RDC_BASE) |
| #define RDC_BASE_PTR (RDC) |
| /** Array initializer of RDC peripheral base addresses */ |
| #define RDC_BASE_ADDRS { RDC_BASE } |
| /** Array initializer of RDC peripheral base pointers */ |
| #define RDC_BASE_PTRS { RDC } |
| /** Interrupt vectors for the RDC peripheral type */ |
| #define RDC_IRQS { RDC_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros |
| * @{ |
| */ |
| |
| /* RDC - Register instance definitions */ |
| /* RDC */ |
| #define RDC_VIR RDC_VIR_REG(RDC_BASE_PTR) |
| #define RDC_STAT RDC_STAT_REG(RDC_BASE_PTR) |
| #define RDC_INTCTRL RDC_INTCTRL_REG(RDC_BASE_PTR) |
| #define RDC_INTSTAT RDC_INTSTAT_REG(RDC_BASE_PTR) |
| #define RDC_MDA0 RDC_MDA_REG(RDC_BASE_PTR,0) |
| #define RDC_MDA1 RDC_MDA_REG(RDC_BASE_PTR,1) |
| #define RDC_MDA2 RDC_MDA_REG(RDC_BASE_PTR,2) |
| #define RDC_MDA3 RDC_MDA_REG(RDC_BASE_PTR,3) |
| #define RDC_MDA4 RDC_MDA_REG(RDC_BASE_PTR,4) |
| #define RDC_MDA5 RDC_MDA_REG(RDC_BASE_PTR,5) |
| #define RDC_MDA6 RDC_MDA_REG(RDC_BASE_PTR,6) |
| #define RDC_MDA7 RDC_MDA_REG(RDC_BASE_PTR,7) |
| #define RDC_MDA8 RDC_MDA_REG(RDC_BASE_PTR,8) |
| #define RDC_MDA9 RDC_MDA_REG(RDC_BASE_PTR,9) |
| #define RDC_MDA10 RDC_MDA_REG(RDC_BASE_PTR,10) |
| #define RDC_MDA11 RDC_MDA_REG(RDC_BASE_PTR,11) |
| #define RDC_MDA12 RDC_MDA_REG(RDC_BASE_PTR,12) |
| #define RDC_MDA13 RDC_MDA_REG(RDC_BASE_PTR,13) |
| #define RDC_MDA14 RDC_MDA_REG(RDC_BASE_PTR,14) |
| #define RDC_MDA15 RDC_MDA_REG(RDC_BASE_PTR,15) |
| #define RDC_MDA16 RDC_MDA_REG(RDC_BASE_PTR,16) |
| #define RDC_MDA17 RDC_MDA_REG(RDC_BASE_PTR,17) |
| #define RDC_MDA18 RDC_MDA_REG(RDC_BASE_PTR,18) |
| #define RDC_MDA19 RDC_MDA_REG(RDC_BASE_PTR,19) |
| #define RDC_MDA20 RDC_MDA_REG(RDC_BASE_PTR,20) |
| #define RDC_MDA21 RDC_MDA_REG(RDC_BASE_PTR,21) |
| #define RDC_MDA22 RDC_MDA_REG(RDC_BASE_PTR,22) |
| #define RDC_MDA23 RDC_MDA_REG(RDC_BASE_PTR,23) |
| #define RDC_MDA24 RDC_MDA_REG(RDC_BASE_PTR,24) |
| #define RDC_MDA25 RDC_MDA_REG(RDC_BASE_PTR,25) |
| #define RDC_MDA26 RDC_MDA_REG(RDC_BASE_PTR,26) |
| #define RDC_MDA27 RDC_MDA_REG(RDC_BASE_PTR,27) |
| #define RDC_MDA28 RDC_MDA_REG(RDC_BASE_PTR,28) |
| #define RDC_MDA29 RDC_MDA_REG(RDC_BASE_PTR,29) |
| #define RDC_MDA30 RDC_MDA_REG(RDC_BASE_PTR,30) |
| #define RDC_MDA31 RDC_MDA_REG(RDC_BASE_PTR,31) |
| #define RDC_PDAP0 RDC_PDAP_REG(RDC_BASE_PTR,0) |
| #define RDC_PDAP1 RDC_PDAP_REG(RDC_BASE_PTR,1) |
| #define RDC_PDAP2 RDC_PDAP_REG(RDC_BASE_PTR,2) |
| #define RDC_PDAP3 RDC_PDAP_REG(RDC_BASE_PTR,3) |
| #define RDC_PDAP4 RDC_PDAP_REG(RDC_BASE_PTR,4) |
| #define RDC_PDAP5 RDC_PDAP_REG(RDC_BASE_PTR,5) |
| #define RDC_PDAP6 RDC_PDAP_REG(RDC_BASE_PTR,6) |
| #define RDC_PDAP7 RDC_PDAP_REG(RDC_BASE_PTR,7) |
| #define RDC_PDAP8 RDC_PDAP_REG(RDC_BASE_PTR,8) |
| #define RDC_PDAP9 RDC_PDAP_REG(RDC_BASE_PTR,9) |
| #define RDC_PDAP10 RDC_PDAP_REG(RDC_BASE_PTR,10) |
| #define RDC_PDAP11 RDC_PDAP_REG(RDC_BASE_PTR,11) |
| #define RDC_PDAP12 RDC_PDAP_REG(RDC_BASE_PTR,12) |
| #define RDC_PDAP13 RDC_PDAP_REG(RDC_BASE_PTR,13) |
| #define RDC_PDAP14 RDC_PDAP_REG(RDC_BASE_PTR,14) |
| #define RDC_PDAP15 RDC_PDAP_REG(RDC_BASE_PTR,15) |
| #define RDC_PDAP16 RDC_PDAP_REG(RDC_BASE_PTR,16) |
| #define RDC_PDAP17 RDC_PDAP_REG(RDC_BASE_PTR,17) |
| #define RDC_PDAP18 RDC_PDAP_REG(RDC_BASE_PTR,18) |
| #define RDC_PDAP19 RDC_PDAP_REG(RDC_BASE_PTR,19) |
| #define RDC_PDAP20 RDC_PDAP_REG(RDC_BASE_PTR,20) |
| #define RDC_PDAP21 RDC_PDAP_REG(RDC_BASE_PTR,21) |
| #define RDC_PDAP22 RDC_PDAP_REG(RDC_BASE_PTR,22) |
| #define RDC_PDAP23 RDC_PDAP_REG(RDC_BASE_PTR,23) |
| #define RDC_PDAP24 RDC_PDAP_REG(RDC_BASE_PTR,24) |
| #define RDC_PDAP25 RDC_PDAP_REG(RDC_BASE_PTR,25) |
| #define RDC_PDAP26 RDC_PDAP_REG(RDC_BASE_PTR,26) |
| #define RDC_PDAP27 RDC_PDAP_REG(RDC_BASE_PTR,27) |
| #define RDC_PDAP28 RDC_PDAP_REG(RDC_BASE_PTR,28) |
| #define RDC_PDAP29 RDC_PDAP_REG(RDC_BASE_PTR,29) |
| #define RDC_PDAP30 RDC_PDAP_REG(RDC_BASE_PTR,30) |
| #define RDC_PDAP31 RDC_PDAP_REG(RDC_BASE_PTR,31) |
| #define RDC_PDAP32 RDC_PDAP_REG(RDC_BASE_PTR,32) |
| #define RDC_PDAP33 RDC_PDAP_REG(RDC_BASE_PTR,33) |
| #define RDC_PDAP34 RDC_PDAP_REG(RDC_BASE_PTR,34) |
| #define RDC_PDAP35 RDC_PDAP_REG(RDC_BASE_PTR,35) |
| #define RDC_PDAP36 RDC_PDAP_REG(RDC_BASE_PTR,36) |
| #define RDC_PDAP37 RDC_PDAP_REG(RDC_BASE_PTR,37) |
| #define RDC_PDAP38 RDC_PDAP_REG(RDC_BASE_PTR,38) |
| #define RDC_PDAP39 RDC_PDAP_REG(RDC_BASE_PTR,39) |
| #define RDC_PDAP40 RDC_PDAP_REG(RDC_BASE_PTR,40) |
| #define RDC_PDAP41 RDC_PDAP_REG(RDC_BASE_PTR,41) |
| #define RDC_PDAP42 RDC_PDAP_REG(RDC_BASE_PTR,42) |
| #define RDC_PDAP43 RDC_PDAP_REG(RDC_BASE_PTR,43) |
| #define RDC_PDAP44 RDC_PDAP_REG(RDC_BASE_PTR,44) |
| #define RDC_PDAP45 RDC_PDAP_REG(RDC_BASE_PTR,45) |
| #define RDC_PDAP46 RDC_PDAP_REG(RDC_BASE_PTR,46) |
| #define RDC_PDAP47 RDC_PDAP_REG(RDC_BASE_PTR,47) |
| #define RDC_PDAP48 RDC_PDAP_REG(RDC_BASE_PTR,48) |
| #define RDC_PDAP49 RDC_PDAP_REG(RDC_BASE_PTR,49) |
| #define RDC_PDAP50 RDC_PDAP_REG(RDC_BASE_PTR,50) |
| #define RDC_PDAP51 RDC_PDAP_REG(RDC_BASE_PTR,51) |
| #define RDC_PDAP52 RDC_PDAP_REG(RDC_BASE_PTR,52) |
| #define RDC_PDAP53 RDC_PDAP_REG(RDC_BASE_PTR,53) |
| #define RDC_PDAP54 RDC_PDAP_REG(RDC_BASE_PTR,54) |
| #define RDC_PDAP55 RDC_PDAP_REG(RDC_BASE_PTR,55) |
| #define RDC_PDAP56 RDC_PDAP_REG(RDC_BASE_PTR,56) |
| #define RDC_PDAP57 RDC_PDAP_REG(RDC_BASE_PTR,57) |
| #define RDC_PDAP58 RDC_PDAP_REG(RDC_BASE_PTR,58) |
| #define RDC_PDAP59 RDC_PDAP_REG(RDC_BASE_PTR,59) |
| #define RDC_PDAP60 RDC_PDAP_REG(RDC_BASE_PTR,60) |
| #define RDC_PDAP61 RDC_PDAP_REG(RDC_BASE_PTR,61) |
| #define RDC_PDAP62 RDC_PDAP_REG(RDC_BASE_PTR,62) |
| #define RDC_PDAP63 RDC_PDAP_REG(RDC_BASE_PTR,63) |
| #define RDC_PDAP64 RDC_PDAP_REG(RDC_BASE_PTR,64) |
| #define RDC_PDAP65 RDC_PDAP_REG(RDC_BASE_PTR,65) |
| #define RDC_PDAP66 RDC_PDAP_REG(RDC_BASE_PTR,66) |
| #define RDC_PDAP67 RDC_PDAP_REG(RDC_BASE_PTR,67) |
| #define RDC_PDAP68 RDC_PDAP_REG(RDC_BASE_PTR,68) |
| #define RDC_PDAP69 RDC_PDAP_REG(RDC_BASE_PTR,69) |
| #define RDC_PDAP70 RDC_PDAP_REG(RDC_BASE_PTR,70) |
| #define RDC_PDAP71 RDC_PDAP_REG(RDC_BASE_PTR,71) |
| #define RDC_PDAP72 RDC_PDAP_REG(RDC_BASE_PTR,72) |
| #define RDC_PDAP73 RDC_PDAP_REG(RDC_BASE_PTR,73) |
| #define RDC_PDAP74 RDC_PDAP_REG(RDC_BASE_PTR,74) |
| #define RDC_PDAP75 RDC_PDAP_REG(RDC_BASE_PTR,75) |
| #define RDC_PDAP76 RDC_PDAP_REG(RDC_BASE_PTR,76) |
| #define RDC_PDAP77 RDC_PDAP_REG(RDC_BASE_PTR,77) |
| #define RDC_PDAP78 RDC_PDAP_REG(RDC_BASE_PTR,78) |
| #define RDC_PDAP79 RDC_PDAP_REG(RDC_BASE_PTR,79) |
| #define RDC_PDAP80 RDC_PDAP_REG(RDC_BASE_PTR,80) |
| #define RDC_PDAP81 RDC_PDAP_REG(RDC_BASE_PTR,81) |
| #define RDC_PDAP82 RDC_PDAP_REG(RDC_BASE_PTR,82) |
| #define RDC_PDAP83 RDC_PDAP_REG(RDC_BASE_PTR,83) |
| #define RDC_PDAP84 RDC_PDAP_REG(RDC_BASE_PTR,84) |
| #define RDC_PDAP85 RDC_PDAP_REG(RDC_BASE_PTR,85) |
| #define RDC_PDAP86 RDC_PDAP_REG(RDC_BASE_PTR,86) |
| #define RDC_PDAP87 RDC_PDAP_REG(RDC_BASE_PTR,87) |
| #define RDC_PDAP88 RDC_PDAP_REG(RDC_BASE_PTR,88) |
| #define RDC_PDAP89 RDC_PDAP_REG(RDC_BASE_PTR,89) |
| #define RDC_PDAP90 RDC_PDAP_REG(RDC_BASE_PTR,90) |
| #define RDC_PDAP91 RDC_PDAP_REG(RDC_BASE_PTR,91) |
| #define RDC_PDAP92 RDC_PDAP_REG(RDC_BASE_PTR,92) |
| #define RDC_PDAP93 RDC_PDAP_REG(RDC_BASE_PTR,93) |
| #define RDC_PDAP94 RDC_PDAP_REG(RDC_BASE_PTR,94) |
| #define RDC_PDAP95 RDC_PDAP_REG(RDC_BASE_PTR,95) |
| #define RDC_PDAP96 RDC_PDAP_REG(RDC_BASE_PTR,96) |
| #define RDC_PDAP97 RDC_PDAP_REG(RDC_BASE_PTR,97) |
| #define RDC_PDAP98 RDC_PDAP_REG(RDC_BASE_PTR,98) |
| #define RDC_PDAP99 RDC_PDAP_REG(RDC_BASE_PTR,99) |
| #define RDC_PDAP100 RDC_PDAP_REG(RDC_BASE_PTR,100) |
| #define RDC_PDAP101 RDC_PDAP_REG(RDC_BASE_PTR,101) |
| #define RDC_PDAP102 RDC_PDAP_REG(RDC_BASE_PTR,102) |
| #define RDC_PDAP103 RDC_PDAP_REG(RDC_BASE_PTR,103) |
| #define RDC_PDAP104 RDC_PDAP_REG(RDC_BASE_PTR,104) |
| #define RDC_PDAP105 RDC_PDAP_REG(RDC_BASE_PTR,105) |
| #define RDC_PDAP106 RDC_PDAP_REG(RDC_BASE_PTR,106) |
| #define RDC_PDAP107 RDC_PDAP_REG(RDC_BASE_PTR,107) |
| #define RDC_PDAP108 RDC_PDAP_REG(RDC_BASE_PTR,108) |
| #define RDC_PDAP109 RDC_PDAP_REG(RDC_BASE_PTR,109) |
| #define RDC_MRSA0 RDC_MRSA_REG(RDC_BASE_PTR,0) |
| #define RDC_MREA0 RDC_MREA_REG(RDC_BASE_PTR,0) |
| #define RDC_MRC0 RDC_MRC_REG(RDC_BASE_PTR,0) |
| #define RDC_MRVS0 RDC_MRVS_REG(RDC_BASE_PTR,0) |
| #define RDC_MRSA1 RDC_MRSA_REG(RDC_BASE_PTR,1) |
| #define RDC_MREA1 RDC_MREA_REG(RDC_BASE_PTR,1) |
| #define RDC_MRC1 RDC_MRC_REG(RDC_BASE_PTR,1) |
| #define RDC_MRVS1 RDC_MRVS_REG(RDC_BASE_PTR,1) |
| #define RDC_MRSA2 RDC_MRSA_REG(RDC_BASE_PTR,2) |
| #define RDC_MREA2 RDC_MREA_REG(RDC_BASE_PTR,2) |
| #define RDC_MRC2 RDC_MRC_REG(RDC_BASE_PTR,2) |
| #define RDC_MRVS2 RDC_MRVS_REG(RDC_BASE_PTR,2) |
| #define RDC_MRSA3 RDC_MRSA_REG(RDC_BASE_PTR,3) |
| #define RDC_MREA3 RDC_MREA_REG(RDC_BASE_PTR,3) |
| #define RDC_MRC3 RDC_MRC_REG(RDC_BASE_PTR,3) |
| #define RDC_MRVS3 RDC_MRVS_REG(RDC_BASE_PTR,3) |
| #define RDC_MRSA4 RDC_MRSA_REG(RDC_BASE_PTR,4) |
| #define RDC_MREA4 RDC_MREA_REG(RDC_BASE_PTR,4) |
| #define RDC_MRC4 RDC_MRC_REG(RDC_BASE_PTR,4) |
| #define RDC_MRVS4 RDC_MRVS_REG(RDC_BASE_PTR,4) |
| #define RDC_MRSA5 RDC_MRSA_REG(RDC_BASE_PTR,5) |
| #define RDC_MREA5 RDC_MREA_REG(RDC_BASE_PTR,5) |
| #define RDC_MRC5 RDC_MRC_REG(RDC_BASE_PTR,5) |
| #define RDC_MRVS5 RDC_MRVS_REG(RDC_BASE_PTR,5) |
| #define RDC_MRSA6 RDC_MRSA_REG(RDC_BASE_PTR,6) |
| #define RDC_MREA6 RDC_MREA_REG(RDC_BASE_PTR,6) |
| #define RDC_MRC6 RDC_MRC_REG(RDC_BASE_PTR,6) |
| #define RDC_MRVS6 RDC_MRVS_REG(RDC_BASE_PTR,6) |
| #define RDC_MRSA7 RDC_MRSA_REG(RDC_BASE_PTR,7) |
| #define RDC_MREA7 RDC_MREA_REG(RDC_BASE_PTR,7) |
| #define RDC_MRC7 RDC_MRC_REG(RDC_BASE_PTR,7) |
| #define RDC_MRVS7 RDC_MRVS_REG(RDC_BASE_PTR,7) |
| #define RDC_MRSA8 RDC_MRSA_REG(RDC_BASE_PTR,8) |
| #define RDC_MREA8 RDC_MREA_REG(RDC_BASE_PTR,8) |
| #define RDC_MRC8 RDC_MRC_REG(RDC_BASE_PTR,8) |
| #define RDC_MRVS8 RDC_MRVS_REG(RDC_BASE_PTR,8) |
| #define RDC_MRSA9 RDC_MRSA_REG(RDC_BASE_PTR,9) |
| #define RDC_MREA9 RDC_MREA_REG(RDC_BASE_PTR,9) |
| #define RDC_MRC9 RDC_MRC_REG(RDC_BASE_PTR,9) |
| #define RDC_MRVS9 RDC_MRVS_REG(RDC_BASE_PTR,9) |
| #define RDC_MRSA10 RDC_MRSA_REG(RDC_BASE_PTR,10) |
| #define RDC_MREA10 RDC_MREA_REG(RDC_BASE_PTR,10) |
| #define RDC_MRC10 RDC_MRC_REG(RDC_BASE_PTR,10) |
| #define RDC_MRVS10 RDC_MRVS_REG(RDC_BASE_PTR,10) |
| #define RDC_MRSA11 RDC_MRSA_REG(RDC_BASE_PTR,11) |
| #define RDC_MREA11 RDC_MREA_REG(RDC_BASE_PTR,11) |
| #define RDC_MRC11 RDC_MRC_REG(RDC_BASE_PTR,11) |
| #define RDC_MRVS11 RDC_MRVS_REG(RDC_BASE_PTR,11) |
| #define RDC_MRSA12 RDC_MRSA_REG(RDC_BASE_PTR,12) |
| #define RDC_MREA12 RDC_MREA_REG(RDC_BASE_PTR,12) |
| #define RDC_MRC12 RDC_MRC_REG(RDC_BASE_PTR,12) |
| #define RDC_MRVS12 RDC_MRVS_REG(RDC_BASE_PTR,12) |
| #define RDC_MRSA13 RDC_MRSA_REG(RDC_BASE_PTR,13) |
| #define RDC_MREA13 RDC_MREA_REG(RDC_BASE_PTR,13) |
| #define RDC_MRC13 RDC_MRC_REG(RDC_BASE_PTR,13) |
| #define RDC_MRVS13 RDC_MRVS_REG(RDC_BASE_PTR,13) |
| #define RDC_MRSA14 RDC_MRSA_REG(RDC_BASE_PTR,14) |
| #define RDC_MREA14 RDC_MREA_REG(RDC_BASE_PTR,14) |
| #define RDC_MRC14 RDC_MRC_REG(RDC_BASE_PTR,14) |
| #define RDC_MRVS14 RDC_MRVS_REG(RDC_BASE_PTR,14) |
| #define RDC_MRSA15 RDC_MRSA_REG(RDC_BASE_PTR,15) |
| #define RDC_MREA15 RDC_MREA_REG(RDC_BASE_PTR,15) |
| #define RDC_MRC15 RDC_MRC_REG(RDC_BASE_PTR,15) |
| #define RDC_MRVS15 RDC_MRVS_REG(RDC_BASE_PTR,15) |
| #define RDC_MRSA16 RDC_MRSA_REG(RDC_BASE_PTR,16) |
| #define RDC_MREA16 RDC_MREA_REG(RDC_BASE_PTR,16) |
| #define RDC_MRC16 RDC_MRC_REG(RDC_BASE_PTR,16) |
| #define RDC_MRVS16 RDC_MRVS_REG(RDC_BASE_PTR,16) |
| #define RDC_MRSA17 RDC_MRSA_REG(RDC_BASE_PTR,17) |
| #define RDC_MREA17 RDC_MREA_REG(RDC_BASE_PTR,17) |
| #define RDC_MRC17 RDC_MRC_REG(RDC_BASE_PTR,17) |
| #define RDC_MRVS17 RDC_MRVS_REG(RDC_BASE_PTR,17) |
| #define RDC_MRSA18 RDC_MRSA_REG(RDC_BASE_PTR,18) |
| #define RDC_MREA18 RDC_MREA_REG(RDC_BASE_PTR,18) |
| #define RDC_MRC18 RDC_MRC_REG(RDC_BASE_PTR,18) |
| #define RDC_MRVS18 RDC_MRVS_REG(RDC_BASE_PTR,18) |
| #define RDC_MRSA19 RDC_MRSA_REG(RDC_BASE_PTR,19) |
| #define RDC_MREA19 RDC_MREA_REG(RDC_BASE_PTR,19) |
| #define RDC_MRC19 RDC_MRC_REG(RDC_BASE_PTR,19) |
| #define RDC_MRVS19 RDC_MRVS_REG(RDC_BASE_PTR,19) |
| #define RDC_MRSA20 RDC_MRSA_REG(RDC_BASE_PTR,20) |
| #define RDC_MREA20 RDC_MREA_REG(RDC_BASE_PTR,20) |
| #define RDC_MRC20 RDC_MRC_REG(RDC_BASE_PTR,20) |
| #define RDC_MRVS20 RDC_MRVS_REG(RDC_BASE_PTR,20) |
| #define RDC_MRSA21 RDC_MRSA_REG(RDC_BASE_PTR,21) |
| #define RDC_MREA21 RDC_MREA_REG(RDC_BASE_PTR,21) |
| #define RDC_MRC21 RDC_MRC_REG(RDC_BASE_PTR,21) |
| #define RDC_MRVS21 RDC_MRVS_REG(RDC_BASE_PTR,21) |
| #define RDC_MRSA22 RDC_MRSA_REG(RDC_BASE_PTR,22) |
| #define RDC_MREA22 RDC_MREA_REG(RDC_BASE_PTR,22) |
| #define RDC_MRC22 RDC_MRC_REG(RDC_BASE_PTR,22) |
| #define RDC_MRVS22 RDC_MRVS_REG(RDC_BASE_PTR,22) |
| #define RDC_MRSA23 RDC_MRSA_REG(RDC_BASE_PTR,23) |
| #define RDC_MREA23 RDC_MREA_REG(RDC_BASE_PTR,23) |
| #define RDC_MRC23 RDC_MRC_REG(RDC_BASE_PTR,23) |
| #define RDC_MRVS23 RDC_MRVS_REG(RDC_BASE_PTR,23) |
| #define RDC_MRSA24 RDC_MRSA_REG(RDC_BASE_PTR,24) |
| #define RDC_MREA24 RDC_MREA_REG(RDC_BASE_PTR,24) |
| #define RDC_MRC24 RDC_MRC_REG(RDC_BASE_PTR,24) |
| #define RDC_MRVS24 RDC_MRVS_REG(RDC_BASE_PTR,24) |
| #define RDC_MRSA25 RDC_MRSA_REG(RDC_BASE_PTR,25) |
| #define RDC_MREA25 RDC_MREA_REG(RDC_BASE_PTR,25) |
| #define RDC_MRC25 RDC_MRC_REG(RDC_BASE_PTR,25) |
| #define RDC_MRVS25 RDC_MRVS_REG(RDC_BASE_PTR,25) |
| #define RDC_MRSA26 RDC_MRSA_REG(RDC_BASE_PTR,26) |
| #define RDC_MREA26 RDC_MREA_REG(RDC_BASE_PTR,26) |
| #define RDC_MRC26 RDC_MRC_REG(RDC_BASE_PTR,26) |
| #define RDC_MRVS26 RDC_MRVS_REG(RDC_BASE_PTR,26) |
| #define RDC_MRSA27 RDC_MRSA_REG(RDC_BASE_PTR,27) |
| #define RDC_MREA27 RDC_MREA_REG(RDC_BASE_PTR,27) |
| #define RDC_MRC27 RDC_MRC_REG(RDC_BASE_PTR,27) |
| #define RDC_MRVS27 RDC_MRVS_REG(RDC_BASE_PTR,27) |
| #define RDC_MRSA28 RDC_MRSA_REG(RDC_BASE_PTR,28) |
| #define RDC_MREA28 RDC_MREA_REG(RDC_BASE_PTR,28) |
| #define RDC_MRC28 RDC_MRC_REG(RDC_BASE_PTR,28) |
| #define RDC_MRVS28 RDC_MRVS_REG(RDC_BASE_PTR,28) |
| #define RDC_MRSA29 RDC_MRSA_REG(RDC_BASE_PTR,29) |
| #define RDC_MREA29 RDC_MREA_REG(RDC_BASE_PTR,29) |
| #define RDC_MRC29 RDC_MRC_REG(RDC_BASE_PTR,29) |
| #define RDC_MRVS29 RDC_MRVS_REG(RDC_BASE_PTR,29) |
| #define RDC_MRSA30 RDC_MRSA_REG(RDC_BASE_PTR,30) |
| #define RDC_MREA30 RDC_MREA_REG(RDC_BASE_PTR,30) |
| #define RDC_MRC30 RDC_MRC_REG(RDC_BASE_PTR,30) |
| #define RDC_MRVS30 RDC_MRVS_REG(RDC_BASE_PTR,30) |
| #define RDC_MRSA31 RDC_MRSA_REG(RDC_BASE_PTR,31) |
| #define RDC_MREA31 RDC_MREA_REG(RDC_BASE_PTR,31) |
| #define RDC_MRC31 RDC_MRC_REG(RDC_BASE_PTR,31) |
| #define RDC_MRVS31 RDC_MRVS_REG(RDC_BASE_PTR,31) |
| #define RDC_MRSA32 RDC_MRSA_REG(RDC_BASE_PTR,32) |
| #define RDC_MREA32 RDC_MREA_REG(RDC_BASE_PTR,32) |
| #define RDC_MRC32 RDC_MRC_REG(RDC_BASE_PTR,32) |
| #define RDC_MRVS32 RDC_MRVS_REG(RDC_BASE_PTR,32) |
| #define RDC_MRSA33 RDC_MRSA_REG(RDC_BASE_PTR,33) |
| #define RDC_MREA33 RDC_MREA_REG(RDC_BASE_PTR,33) |
| #define RDC_MRC33 RDC_MRC_REG(RDC_BASE_PTR,33) |
| #define RDC_MRVS33 RDC_MRVS_REG(RDC_BASE_PTR,33) |
| #define RDC_MRSA34 RDC_MRSA_REG(RDC_BASE_PTR,34) |
| #define RDC_MREA34 RDC_MREA_REG(RDC_BASE_PTR,34) |
| #define RDC_MRC34 RDC_MRC_REG(RDC_BASE_PTR,34) |
| #define RDC_MRVS34 RDC_MRVS_REG(RDC_BASE_PTR,34) |
| #define RDC_MRSA35 RDC_MRSA_REG(RDC_BASE_PTR,35) |
| #define RDC_MREA35 RDC_MREA_REG(RDC_BASE_PTR,35) |
| #define RDC_MRC35 RDC_MRC_REG(RDC_BASE_PTR,35) |
| #define RDC_MRVS35 RDC_MRVS_REG(RDC_BASE_PTR,35) |
| #define RDC_MRSA36 RDC_MRSA_REG(RDC_BASE_PTR,36) |
| #define RDC_MREA36 RDC_MREA_REG(RDC_BASE_PTR,36) |
| #define RDC_MRC36 RDC_MRC_REG(RDC_BASE_PTR,36) |
| #define RDC_MRVS36 RDC_MRVS_REG(RDC_BASE_PTR,36) |
| #define RDC_MRSA37 RDC_MRSA_REG(RDC_BASE_PTR,37) |
| #define RDC_MREA37 RDC_MREA_REG(RDC_BASE_PTR,37) |
| #define RDC_MRC37 RDC_MRC_REG(RDC_BASE_PTR,37) |
| #define RDC_MRVS37 RDC_MRVS_REG(RDC_BASE_PTR,37) |
| #define RDC_MRSA38 RDC_MRSA_REG(RDC_BASE_PTR,38) |
| #define RDC_MREA38 RDC_MREA_REG(RDC_BASE_PTR,38) |
| #define RDC_MRC38 RDC_MRC_REG(RDC_BASE_PTR,38) |
| #define RDC_MRVS38 RDC_MRVS_REG(RDC_BASE_PTR,38) |
| #define RDC_MRSA39 RDC_MRSA_REG(RDC_BASE_PTR,39) |
| #define RDC_MREA39 RDC_MREA_REG(RDC_BASE_PTR,39) |
| #define RDC_MRC39 RDC_MRC_REG(RDC_BASE_PTR,39) |
| #define RDC_MRVS39 RDC_MRVS_REG(RDC_BASE_PTR,39) |
| #define RDC_MRSA40 RDC_MRSA_REG(RDC_BASE_PTR,40) |
| #define RDC_MREA40 RDC_MREA_REG(RDC_BASE_PTR,40) |
| #define RDC_MRC40 RDC_MRC_REG(RDC_BASE_PTR,40) |
| #define RDC_MRVS40 RDC_MRVS_REG(RDC_BASE_PTR,40) |
| #define RDC_MRSA41 RDC_MRSA_REG(RDC_BASE_PTR,41) |
| #define RDC_MREA41 RDC_MREA_REG(RDC_BASE_PTR,41) |
| #define RDC_MRC41 RDC_MRC_REG(RDC_BASE_PTR,41) |
| #define RDC_MRVS41 RDC_MRVS_REG(RDC_BASE_PTR,41) |
| #define RDC_MRSA42 RDC_MRSA_REG(RDC_BASE_PTR,42) |
| #define RDC_MREA42 RDC_MREA_REG(RDC_BASE_PTR,42) |
| #define RDC_MRC42 RDC_MRC_REG(RDC_BASE_PTR,42) |
| #define RDC_MRVS42 RDC_MRVS_REG(RDC_BASE_PTR,42) |
| #define RDC_MRSA43 RDC_MRSA_REG(RDC_BASE_PTR,43) |
| #define RDC_MREA43 RDC_MREA_REG(RDC_BASE_PTR,43) |
| #define RDC_MRC43 RDC_MRC_REG(RDC_BASE_PTR,43) |
| #define RDC_MRVS43 RDC_MRVS_REG(RDC_BASE_PTR,43) |
| #define RDC_MRSA44 RDC_MRSA_REG(RDC_BASE_PTR,44) |
| #define RDC_MREA44 RDC_MREA_REG(RDC_BASE_PTR,44) |
| #define RDC_MRC44 RDC_MRC_REG(RDC_BASE_PTR,44) |
| #define RDC_MRVS44 RDC_MRVS_REG(RDC_BASE_PTR,44) |
| #define RDC_MRSA45 RDC_MRSA_REG(RDC_BASE_PTR,45) |
| #define RDC_MREA45 RDC_MREA_REG(RDC_BASE_PTR,45) |
| #define RDC_MRC45 RDC_MRC_REG(RDC_BASE_PTR,45) |
| #define RDC_MRVS45 RDC_MRVS_REG(RDC_BASE_PTR,45) |
| #define RDC_MRSA46 RDC_MRSA_REG(RDC_BASE_PTR,46) |
| #define RDC_MREA46 RDC_MREA_REG(RDC_BASE_PTR,46) |
| #define RDC_MRC46 RDC_MRC_REG(RDC_BASE_PTR,46) |
| #define RDC_MRVS46 RDC_MRVS_REG(RDC_BASE_PTR,46) |
| #define RDC_MRSA47 RDC_MRSA_REG(RDC_BASE_PTR,47) |
| #define RDC_MREA47 RDC_MREA_REG(RDC_BASE_PTR,47) |
| #define RDC_MRC47 RDC_MRC_REG(RDC_BASE_PTR,47) |
| #define RDC_MRVS47 RDC_MRVS_REG(RDC_BASE_PTR,47) |
| #define RDC_MRSA48 RDC_MRSA_REG(RDC_BASE_PTR,48) |
| #define RDC_MREA48 RDC_MREA_REG(RDC_BASE_PTR,48) |
| #define RDC_MRC48 RDC_MRC_REG(RDC_BASE_PTR,48) |
| #define RDC_MRVS48 RDC_MRVS_REG(RDC_BASE_PTR,48) |
| #define RDC_MRSA49 RDC_MRSA_REG(RDC_BASE_PTR,49) |
| #define RDC_MREA49 RDC_MREA_REG(RDC_BASE_PTR,49) |
| #define RDC_MRC49 RDC_MRC_REG(RDC_BASE_PTR,49) |
| #define RDC_MRVS49 RDC_MRVS_REG(RDC_BASE_PTR,49) |
| #define RDC_MRSA50 RDC_MRSA_REG(RDC_BASE_PTR,50) |
| #define RDC_MREA50 RDC_MREA_REG(RDC_BASE_PTR,50) |
| #define RDC_MRC50 RDC_MRC_REG(RDC_BASE_PTR,50) |
| #define RDC_MRVS50 RDC_MRVS_REG(RDC_BASE_PTR,50) |
| #define RDC_MRSA51 RDC_MRSA_REG(RDC_BASE_PTR,51) |
| #define RDC_MREA51 RDC_MREA_REG(RDC_BASE_PTR,51) |
| #define RDC_MRC51 RDC_MRC_REG(RDC_BASE_PTR,51) |
| #define RDC_MRVS51 RDC_MRVS_REG(RDC_BASE_PTR,51) |
| #define RDC_MRSA52 RDC_MRSA_REG(RDC_BASE_PTR,52) |
| #define RDC_MREA52 RDC_MREA_REG(RDC_BASE_PTR,52) |
| #define RDC_MRC52 RDC_MRC_REG(RDC_BASE_PTR,52) |
| #define RDC_MRVS52 RDC_MRVS_REG(RDC_BASE_PTR,52) |
| #define RDC_MRSA53 RDC_MRSA_REG(RDC_BASE_PTR,53) |
| #define RDC_MREA53 RDC_MREA_REG(RDC_BASE_PTR,53) |
| #define RDC_MRC53 RDC_MRC_REG(RDC_BASE_PTR,53) |
| #define RDC_MRVS53 RDC_MRVS_REG(RDC_BASE_PTR,53) |
| #define RDC_MRSA54 RDC_MRSA_REG(RDC_BASE_PTR,54) |
| #define RDC_MREA54 RDC_MREA_REG(RDC_BASE_PTR,54) |
| #define RDC_MRC54 RDC_MRC_REG(RDC_BASE_PTR,54) |
| #define RDC_MRVS54 RDC_MRVS_REG(RDC_BASE_PTR,54) |
| /* RDC - Register array accessors */ |
| #define RDC_MDA(index) RDC_MDA_REG(RDC_BASE_PTR,index) |
| #define RDC_PDAP(index) RDC_PDAP_REG(RDC_BASE_PTR,index) |
| #define RDC_MRSA(index) RDC_MRSA_REG(RDC_BASE_PTR,index) |
| #define RDC_MREA(index) RDC_MREA_REG(RDC_BASE_PTR,index) |
| #define RDC_MRC(index) RDC_MRC_REG(RDC_BASE_PTR,index) |
| #define RDC_MRVS(index) RDC_MRVS_REG(RDC_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group RDC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** RDC_SEMAPHORE - Register Layout Typedef */ |
| typedef struct { |
| __IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */ |
| union { /* offset: 0x40 */ |
| __IO uint16_t RSTGT_W; /**< Reset Gate Write,offset: 0x40 */ |
| __IO uint16_t RSTGT_R; /**< Reset Gate Read,offset: 0x40 */ |
| }; |
| } RDC_SEMAPHORE_Type, *RDC_SEMAPHORE_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros |
| * @{ |
| */ |
| |
| /* RDC_SEMAPHORE - Register accessors */ |
| #define RDC_SEMAPHORE_GATE_REG(base,index) ((base)->GATE[index]) |
| #define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) |
| #define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks |
| * @{ |
| */ |
| |
| /* GATE Bit Fields */ |
| #define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu |
| #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 |
| #define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_GTFSM_SHIFT))&RDC_SEMAPHORE_GATE_GTFSM_MASK) |
| #define RDC_SEMAPHORE_GATE_LDOM_MASK 0x60u |
| #define RDC_SEMAPHORE_GATE_LDOM_SHIFT 5 |
| #define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_LDOM_SHIFT))&RDC_SEMAPHORE_GATE_LDOM_MASK) |
| /* RSTGT_W Bit Fields */ |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK 0xFFu |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT 0 |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK 0xFF00u |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT 8 |
| #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) |
| /* RSTGT_R Bit Fields */ |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK 0xFu |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT 0 |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK 0x30u |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT 4 |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK 0xFF00u |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT 8 |
| #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Register_Masks */ |
| |
| /* RDC_SEMAPHORE - Peripheral instance base addresses */ |
| /** Peripheral RDC_SEMAPHORE1 base address */ |
| #define RDC_SEMAPHORE1_BASE (0x420F4000u) |
| /** Peripheral RDC_SEMAPHORE1 base pointer */ |
| #define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) |
| #define RDC_SEMAPHORE1_BASE_PTR (RDC_SEMAPHORE1) |
| /** Peripheral RDC_SEMAPHORE2 base address */ |
| #define RDC_SEMAPHORE2_BASE (0x420F8000u) |
| /** Peripheral RDC_SEMAPHORE2 base pointer */ |
| #define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) |
| #define RDC_SEMAPHORE2_BASE_PTR (RDC_SEMAPHORE2) |
| /** Array initializer of RDC_SEMAPHORE peripheral base addresses */ |
| #define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } |
| /** Array initializer of RDC_SEMAPHORE peripheral base pointers */ |
| #define RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 } |
| |
| /* ---------------------------------------------------------------------------- |
| -- RDC_SEMAPHORE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros |
| * @{ |
| */ |
| |
| /* RDC_SEMAPHORE - Register instance definitions */ |
| /* RDC_SEMAPHORE1 */ |
| #define RDC_SEMAPHORE1_GATE0 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,0) |
| #define RDC_SEMAPHORE1_GATE1 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,1) |
| #define RDC_SEMAPHORE1_GATE2 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,2) |
| #define RDC_SEMAPHORE1_GATE3 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,3) |
| #define RDC_SEMAPHORE1_GATE4 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,4) |
| #define RDC_SEMAPHORE1_GATE5 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,5) |
| #define RDC_SEMAPHORE1_GATE6 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,6) |
| #define RDC_SEMAPHORE1_GATE7 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,7) |
| #define RDC_SEMAPHORE1_GATE8 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,8) |
| #define RDC_SEMAPHORE1_GATE9 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,9) |
| #define RDC_SEMAPHORE1_GATE10 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,10) |
| #define RDC_SEMAPHORE1_GATE11 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,11) |
| #define RDC_SEMAPHORE1_GATE12 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,12) |
| #define RDC_SEMAPHORE1_GATE13 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,13) |
| #define RDC_SEMAPHORE1_GATE14 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,14) |
| #define RDC_SEMAPHORE1_GATE15 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,15) |
| #define RDC_SEMAPHORE1_GATE16 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,16) |
| #define RDC_SEMAPHORE1_GATE17 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,17) |
| #define RDC_SEMAPHORE1_GATE18 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,18) |
| #define RDC_SEMAPHORE1_GATE19 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,19) |
| #define RDC_SEMAPHORE1_GATE20 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,20) |
| #define RDC_SEMAPHORE1_GATE21 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,21) |
| #define RDC_SEMAPHORE1_GATE22 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,22) |
| #define RDC_SEMAPHORE1_GATE23 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,23) |
| #define RDC_SEMAPHORE1_GATE24 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,24) |
| #define RDC_SEMAPHORE1_GATE25 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,25) |
| #define RDC_SEMAPHORE1_GATE26 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,26) |
| #define RDC_SEMAPHORE1_GATE27 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,27) |
| #define RDC_SEMAPHORE1_GATE28 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,28) |
| #define RDC_SEMAPHORE1_GATE29 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,29) |
| #define RDC_SEMAPHORE1_GATE30 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,30) |
| #define RDC_SEMAPHORE1_GATE31 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,31) |
| #define RDC_SEMAPHORE1_GATE32 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,32) |
| #define RDC_SEMAPHORE1_GATE33 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,33) |
| #define RDC_SEMAPHORE1_GATE34 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,34) |
| #define RDC_SEMAPHORE1_GATE35 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,35) |
| #define RDC_SEMAPHORE1_GATE36 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,36) |
| #define RDC_SEMAPHORE1_GATE37 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,37) |
| #define RDC_SEMAPHORE1_GATE38 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,38) |
| #define RDC_SEMAPHORE1_GATE39 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,39) |
| #define RDC_SEMAPHORE1_GATE40 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,40) |
| #define RDC_SEMAPHORE1_GATE41 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,41) |
| #define RDC_SEMAPHORE1_GATE42 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,42) |
| #define RDC_SEMAPHORE1_GATE43 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,43) |
| #define RDC_SEMAPHORE1_GATE44 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,44) |
| #define RDC_SEMAPHORE1_GATE45 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,45) |
| #define RDC_SEMAPHORE1_GATE46 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,46) |
| #define RDC_SEMAPHORE1_GATE47 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,47) |
| #define RDC_SEMAPHORE1_GATE48 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,48) |
| #define RDC_SEMAPHORE1_GATE49 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,49) |
| #define RDC_SEMAPHORE1_GATE50 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,50) |
| #define RDC_SEMAPHORE1_GATE51 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,51) |
| #define RDC_SEMAPHORE1_GATE52 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,52) |
| #define RDC_SEMAPHORE1_GATE53 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,53) |
| #define RDC_SEMAPHORE1_GATE54 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,54) |
| #define RDC_SEMAPHORE1_GATE55 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,55) |
| #define RDC_SEMAPHORE1_GATE56 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,56) |
| #define RDC_SEMAPHORE1_GATE57 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,57) |
| #define RDC_SEMAPHORE1_GATE58 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,58) |
| #define RDC_SEMAPHORE1_GATE59 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,59) |
| #define RDC_SEMAPHORE1_GATE60 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,60) |
| #define RDC_SEMAPHORE1_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,61) |
| #define RDC_SEMAPHORE1_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,62) |
| #define RDC_SEMAPHORE1_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,63) |
| #define RDC_SEMAPHORE1_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE1_BASE_PTR) |
| #define RDC_SEMAPHORE1_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR) |
| /* RDC_SEMAPHORE2 */ |
| #define RDC_SEMAPHORE2_GATE0 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,0) |
| #define RDC_SEMAPHORE2_GATE1 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,1) |
| #define RDC_SEMAPHORE2_GATE2 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,2) |
| #define RDC_SEMAPHORE2_GATE3 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,3) |
| #define RDC_SEMAPHORE2_GATE4 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,4) |
| #define RDC_SEMAPHORE2_GATE5 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,5) |
| #define RDC_SEMAPHORE2_GATE6 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,6) |
| #define RDC_SEMAPHORE2_GATE7 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,7) |
| #define RDC_SEMAPHORE2_GATE8 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,8) |
| #define RDC_SEMAPHORE2_GATE9 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,9) |
| #define RDC_SEMAPHORE2_GATE10 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,10) |
| #define RDC_SEMAPHORE2_GATE11 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,11) |
| #define RDC_SEMAPHORE2_GATE12 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,12) |
| #define RDC_SEMAPHORE2_GATE13 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,13) |
| #define RDC_SEMAPHORE2_GATE14 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,14) |
| #define RDC_SEMAPHORE2_GATE15 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,15) |
| #define RDC_SEMAPHORE2_GATE16 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,16) |
| #define RDC_SEMAPHORE2_GATE17 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,17) |
| #define RDC_SEMAPHORE2_GATE18 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,18) |
| #define RDC_SEMAPHORE2_GATE19 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,19) |
| #define RDC_SEMAPHORE2_GATE20 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,20) |
| #define RDC_SEMAPHORE2_GATE21 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,21) |
| #define RDC_SEMAPHORE2_GATE22 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,22) |
| #define RDC_SEMAPHORE2_GATE23 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,23) |
| #define RDC_SEMAPHORE2_GATE24 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,24) |
| #define RDC_SEMAPHORE2_GATE25 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,25) |
| #define RDC_SEMAPHORE2_GATE26 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,26) |
| #define RDC_SEMAPHORE2_GATE27 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,27) |
| #define RDC_SEMAPHORE2_GATE28 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,28) |
| #define RDC_SEMAPHORE2_GATE29 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,29) |
| #define RDC_SEMAPHORE2_GATE30 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,30) |
| #define RDC_SEMAPHORE2_GATE31 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,31) |
| #define RDC_SEMAPHORE2_GATE32 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,32) |
| #define RDC_SEMAPHORE2_GATE33 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,33) |
| #define RDC_SEMAPHORE2_GATE34 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,34) |
| #define RDC_SEMAPHORE2_GATE35 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,35) |
| #define RDC_SEMAPHORE2_GATE36 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,36) |
| #define RDC_SEMAPHORE2_GATE37 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,37) |
| #define RDC_SEMAPHORE2_GATE38 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,38) |
| #define RDC_SEMAPHORE2_GATE39 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,39) |
| #define RDC_SEMAPHORE2_GATE40 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,40) |
| #define RDC_SEMAPHORE2_GATE41 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,41) |
| #define RDC_SEMAPHORE2_GATE42 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,42) |
| #define RDC_SEMAPHORE2_GATE43 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,43) |
| #define RDC_SEMAPHORE2_GATE44 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,44) |
| #define RDC_SEMAPHORE2_GATE45 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,45) |
| #define RDC_SEMAPHORE2_GATE46 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,46) |
| #define RDC_SEMAPHORE2_GATE47 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,47) |
| #define RDC_SEMAPHORE2_GATE48 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,48) |
| #define RDC_SEMAPHORE2_GATE49 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,49) |
| #define RDC_SEMAPHORE2_GATE50 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,50) |
| #define RDC_SEMAPHORE2_GATE51 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,51) |
| #define RDC_SEMAPHORE2_GATE52 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,52) |
| #define RDC_SEMAPHORE2_GATE53 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,53) |
| #define RDC_SEMAPHORE2_GATE54 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,54) |
| #define RDC_SEMAPHORE2_GATE55 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,55) |
| #define RDC_SEMAPHORE2_GATE56 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,56) |
| #define RDC_SEMAPHORE2_GATE57 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,57) |
| #define RDC_SEMAPHORE2_GATE58 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,58) |
| #define RDC_SEMAPHORE2_GATE59 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,59) |
| #define RDC_SEMAPHORE2_GATE60 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,60) |
| #define RDC_SEMAPHORE2_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,61) |
| #define RDC_SEMAPHORE2_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,62) |
| #define RDC_SEMAPHORE2_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,63) |
| #define RDC_SEMAPHORE2_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE2_BASE_PTR) |
| #define RDC_SEMAPHORE2_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR) |
| /* RDC_SEMAPHORE - Register array accessors */ |
| #define RDC_SEMAPHORE1_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,index) |
| #define RDC_SEMAPHORE2_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group RDC_SEMAPHORE_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** ROMC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[212]; |
| __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ |
| __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ |
| __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ |
| __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ |
| __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_1[200]; |
| __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ |
| } ROMC_Type, *ROMC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ROMC - Register accessors */ |
| #define ROMC_ROMPATCHD_REG(base,index) ((base)->ROMPATCHD[index]) |
| #define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) |
| #define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) |
| #define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) |
| #define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) |
| #define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Register_Masks ROMC Register Masks |
| * @{ |
| */ |
| |
| /* ROMPATCHD Bit Fields */ |
| #define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu |
| #define ROMC_ROMPATCHD_DATAX_SHIFT 0 |
| #define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHD_DATAX_SHIFT))&ROMC_ROMPATCHD_DATAX_MASK) |
| /* ROMPATCHCNTL Bit Fields */ |
| #define ROMC_ROMPATCHCNTL_DATAFIX_MASK 0xFFu |
| #define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT 0 |
| #define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHCNTL_DATAFIX_SHIFT))&ROMC_ROMPATCHCNTL_DATAFIX_MASK) |
| #define ROMC_ROMPATCHCNTL_DIS_MASK 0x20000000u |
| #define ROMC_ROMPATCHCNTL_DIS_SHIFT 29 |
| /* ROMPATCHENH Bit Fields */ |
| /* ROMPATCHENL Bit Fields */ |
| #define ROMC_ROMPATCHENL_ENABLE_MASK 0xFFFFu |
| #define ROMC_ROMPATCHENL_ENABLE_SHIFT 0 |
| #define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHENL_ENABLE_SHIFT))&ROMC_ROMPATCHENL_ENABLE_MASK) |
| /* ROMPATCHA Bit Fields */ |
| #define ROMC_ROMPATCHA_THUMBX_MASK 0x1u |
| #define ROMC_ROMPATCHA_THUMBX_SHIFT 0 |
| #define ROMC_ROMPATCHA_ADDRX_MASK 0x7FFFFEu |
| #define ROMC_ROMPATCHA_ADDRX_SHIFT 1 |
| #define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHA_ADDRX_SHIFT))&ROMC_ROMPATCHA_ADDRX_MASK) |
| /* ROMPATCHSR Bit Fields */ |
| #define ROMC_ROMPATCHSR_SOURCE_MASK 0x3Fu |
| #define ROMC_ROMPATCHSR_SOURCE_SHIFT 0 |
| #define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHSR_SOURCE_SHIFT))&ROMC_ROMPATCHSR_SOURCE_MASK) |
| #define ROMC_ROMPATCHSR_SW_MASK 0x20000u |
| #define ROMC_ROMPATCHSR_SW_SHIFT 17 |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Register_Masks */ |
| |
| /* ROMC - Peripheral instance base addresses */ |
| /** Peripheral ROMC base address */ |
| #define ROMC_BASE (0x421AC000u) |
| /** Peripheral ROMC base pointer */ |
| #define ROMC ((ROMC_Type *)ROMC_BASE) |
| #define ROMC_BASE_PTR (ROMC) |
| /** Array initializer of ROMC peripheral base addresses */ |
| #define ROMC_BASE_ADDRS { ROMC_BASE } |
| /** Array initializer of ROMC peripheral base pointers */ |
| #define ROMC_BASE_PTRS { ROMC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- ROMC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros |
| * @{ |
| */ |
| |
| /* ROMC - Register instance definitions */ |
| /* ROMC */ |
| #define ROMC_ROMPATCH0D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,0) |
| #define ROMC_ROMPATCH1D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,1) |
| #define ROMC_ROMPATCH2D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,2) |
| #define ROMC_ROMPATCH3D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,3) |
| #define ROMC_ROMPATCH4D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,4) |
| #define ROMC_ROMPATCH5D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,5) |
| #define ROMC_ROMPATCH6D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,6) |
| #define ROMC_ROMPATCH7D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,7) |
| #define ROMC_ROMPATCHCNTL ROMC_ROMPATCHCNTL_REG(ROMC_BASE_PTR) |
| #define ROMC_ROMPATCHENH ROMC_ROMPATCHENH_REG(ROMC_BASE_PTR) |
| #define ROMC_ROMPATCHENL ROMC_ROMPATCHENL_REG(ROMC_BASE_PTR) |
| #define ROMC_ROMPATCH0A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,0) |
| #define ROMC_ROMPATCH1A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,1) |
| #define ROMC_ROMPATCH2A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,2) |
| #define ROMC_ROMPATCH3A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,3) |
| #define ROMC_ROMPATCH4A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,4) |
| #define ROMC_ROMPATCH5A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,5) |
| #define ROMC_ROMPATCH6A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,6) |
| #define ROMC_ROMPATCH7A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,7) |
| #define ROMC_ROMPATCH8A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,8) |
| #define ROMC_ROMPATCH9A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,9) |
| #define ROMC_ROMPATCH10A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,10) |
| #define ROMC_ROMPATCH11A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,11) |
| #define ROMC_ROMPATCH12A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,12) |
| #define ROMC_ROMPATCH13A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,13) |
| #define ROMC_ROMPATCH14A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,14) |
| #define ROMC_ROMPATCH15A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,15) |
| #define ROMC_ROMPATCHSR ROMC_ROMPATCHSR_REG(ROMC_BASE_PTR) |
| /* ROMC - Register array accessors */ |
| #define ROMC_ROMPATCHD(index) ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,index) |
| #define ROMC_ROMPATCHA(index) ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group ROMC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SDMAARM - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ |
| __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ |
| __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ |
| __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ |
| __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ |
| __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ |
| __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ |
| __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ |
| uint8_t RESERVED_0[4]; |
| __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ |
| __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ |
| __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ |
| __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ |
| __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ |
| __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ |
| __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ |
| __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ |
| __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ |
| __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ |
| __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ |
| __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ |
| __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ |
| __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ |
| __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ |
| uint8_t RESERVED_2[8]; |
| __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ |
| __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ |
| uint8_t RESERVED_3[136]; |
| __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ |
| uint8_t RESERVED_4[128]; |
| __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ |
| } SDMAARM_Type, *SDMAARM_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMAARM - Register accessors */ |
| #define SDMAARM_MC0PTR_REG(base) ((base)->MC0PTR) |
| #define SDMAARM_INTR_REG(base) ((base)->INTR) |
| #define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) |
| #define SDMAARM_HSTART_REG(base) ((base)->HSTART) |
| #define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) |
| #define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) |
| #define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) |
| #define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) |
| #define SDMAARM_RESET_REG(base) ((base)->RESET) |
| #define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) |
| #define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) |
| #define SDMAARM_PSW_REG(base) ((base)->PSW) |
| #define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) |
| #define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) |
| #define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) |
| #define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) |
| #define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) |
| #define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) |
| #define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) |
| #define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) |
| #define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) |
| #define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) |
| #define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) |
| #define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) |
| #define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) |
| #define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) |
| #define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) |
| #define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks |
| * @{ |
| */ |
| |
| /* MC0PTR Bit Fields */ |
| #define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu |
| #define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 |
| #define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_MC0PTR_MC0PTR_SHIFT))&SDMAARM_MC0PTR_MC0PTR_MASK) |
| /* INTR Bit Fields */ |
| #define SDMAARM_INTR_HI_MASK 0xFFFFFFFFu |
| #define SDMAARM_INTR_HI_SHIFT 0 |
| #define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTR_HI_SHIFT))&SDMAARM_INTR_HI_MASK) |
| /* STOP_STAT Bit Fields */ |
| #define SDMAARM_STOP_STAT_HE_MASK 0xFFFFFFFFu |
| #define SDMAARM_STOP_STAT_HE_SHIFT 0 |
| #define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_STOP_STAT_HE_SHIFT))&SDMAARM_STOP_STAT_HE_MASK) |
| /* HSTART Bit Fields */ |
| #define SDMAARM_HSTART_HSTART_HE_MASK 0xFFFFFFFFu |
| #define SDMAARM_HSTART_HSTART_HE_SHIFT 0 |
| #define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_HSTART_HSTART_HE_SHIFT))&SDMAARM_HSTART_HSTART_HE_MASK) |
| /* EVTOVR Bit Fields */ |
| #define SDMAARM_EVTOVR_EO_MASK 0xFFFFFFFFu |
| #define SDMAARM_EVTOVR_EO_SHIFT 0 |
| #define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTOVR_EO_SHIFT))&SDMAARM_EVTOVR_EO_MASK) |
| /* DSPOVR Bit Fields */ |
| #define SDMAARM_DSPOVR_DO_MASK 0xFFFFFFFFu |
| #define SDMAARM_DSPOVR_DO_SHIFT 0 |
| #define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_DSPOVR_DO_SHIFT))&SDMAARM_DSPOVR_DO_MASK) |
| /* HOSTOVR Bit Fields */ |
| #define SDMAARM_HOSTOVR_HO_MASK 0xFFFFFFFFu |
| #define SDMAARM_HOSTOVR_HO_SHIFT 0 |
| #define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_HOSTOVR_HO_SHIFT))&SDMAARM_HOSTOVR_HO_MASK) |
| /* EVTPEND Bit Fields */ |
| #define SDMAARM_EVTPEND_EP_MASK 0xFFFFFFFFu |
| #define SDMAARM_EVTPEND_EP_SHIFT 0 |
| #define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTPEND_EP_SHIFT))&SDMAARM_EVTPEND_EP_MASK) |
| /* RESET Bit Fields */ |
| #define SDMAARM_RESET_RESET_MASK 0x1u |
| #define SDMAARM_RESET_RESET_SHIFT 0 |
| #define SDMAARM_RESET_RESCHED_MASK 0x2u |
| #define SDMAARM_RESET_RESCHED_SHIFT 1 |
| /* EVTERR Bit Fields */ |
| #define SDMAARM_EVTERR_CHNERR_MASK 0xFFFFFFFFu |
| #define SDMAARM_EVTERR_CHNERR_SHIFT 0 |
| #define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERR_CHNERR_SHIFT))&SDMAARM_EVTERR_CHNERR_MASK) |
| /* INTRMASK Bit Fields */ |
| #define SDMAARM_INTRMASK_HIMASK_MASK 0xFFFFFFFFu |
| #define SDMAARM_INTRMASK_HIMASK_SHIFT 0 |
| #define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTRMASK_HIMASK_SHIFT))&SDMAARM_INTRMASK_HIMASK_MASK) |
| /* PSW Bit Fields */ |
| #define SDMAARM_PSW_CCR_MASK 0xFu |
| #define SDMAARM_PSW_CCR_SHIFT 0 |
| #define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCR_SHIFT))&SDMAARM_PSW_CCR_MASK) |
| #define SDMAARM_PSW_CCP_MASK 0xF0u |
| #define SDMAARM_PSW_CCP_SHIFT 4 |
| #define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCP_SHIFT))&SDMAARM_PSW_CCP_MASK) |
| #define SDMAARM_PSW_NCR_MASK 0x1F00u |
| #define SDMAARM_PSW_NCR_SHIFT 8 |
| #define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCR_SHIFT))&SDMAARM_PSW_NCR_MASK) |
| #define SDMAARM_PSW_NCP_MASK 0xE000u |
| #define SDMAARM_PSW_NCP_SHIFT 13 |
| #define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCP_SHIFT))&SDMAARM_PSW_NCP_MASK) |
| /* EVTERRDBG Bit Fields */ |
| #define SDMAARM_EVTERRDBG_CHNERR_MASK 0xFFFFFFFFu |
| #define SDMAARM_EVTERRDBG_CHNERR_SHIFT 0 |
| #define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERRDBG_CHNERR_SHIFT))&SDMAARM_EVTERRDBG_CHNERR_MASK) |
| /* CONFIG Bit Fields */ |
| #define SDMAARM_CONFIG_CSM_MASK 0x3u |
| #define SDMAARM_CONFIG_CSM_SHIFT 0 |
| #define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CONFIG_CSM_SHIFT))&SDMAARM_CONFIG_CSM_MASK) |
| #define SDMAARM_CONFIG_ACR_MASK 0x10u |
| #define SDMAARM_CONFIG_ACR_SHIFT 4 |
| #define SDMAARM_CONFIG_RTDOBS_MASK 0x800u |
| #define SDMAARM_CONFIG_RTDOBS_SHIFT 11 |
| #define SDMAARM_CONFIG_DSPDMA_MASK 0x1000u |
| #define SDMAARM_CONFIG_DSPDMA_SHIFT 12 |
| /* SDMA_LOCK Bit Fields */ |
| #define SDMAARM_SDMA_LOCK_LOCK_MASK 0x1u |
| #define SDMAARM_SDMA_LOCK_LOCK_SHIFT 0 |
| #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK 0x2u |
| #define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT 1 |
| /* ONCE_ENB Bit Fields */ |
| #define SDMAARM_ONCE_ENB_ENB_MASK 0x1u |
| #define SDMAARM_ONCE_ENB_ENB_SHIFT 0 |
| /* ONCE_DATA Bit Fields */ |
| #define SDMAARM_ONCE_DATA_DATA_MASK 0xFFFFFFFFu |
| #define SDMAARM_ONCE_DATA_DATA_SHIFT 0 |
| #define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_DATA_DATA_SHIFT))&SDMAARM_ONCE_DATA_DATA_MASK) |
| /* ONCE_INSTR Bit Fields */ |
| #define SDMAARM_ONCE_INSTR_INSTR_MASK 0xFFFFu |
| #define SDMAARM_ONCE_INSTR_INSTR_SHIFT 0 |
| #define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_INSTR_INSTR_SHIFT))&SDMAARM_ONCE_INSTR_INSTR_MASK) |
| /* ONCE_STAT Bit Fields */ |
| #define SDMAARM_ONCE_STAT_ECDR_MASK 0x7u |
| #define SDMAARM_ONCE_STAT_ECDR_SHIFT 0 |
| #define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_ECDR_SHIFT))&SDMAARM_ONCE_STAT_ECDR_MASK) |
| #define SDMAARM_ONCE_STAT_MST_MASK 0x80u |
| #define SDMAARM_ONCE_STAT_MST_SHIFT 7 |
| #define SDMAARM_ONCE_STAT_SWB_MASK 0x100u |
| #define SDMAARM_ONCE_STAT_SWB_SHIFT 8 |
| #define SDMAARM_ONCE_STAT_ODR_MASK 0x200u |
| #define SDMAARM_ONCE_STAT_ODR_SHIFT 9 |
| #define SDMAARM_ONCE_STAT_EDR_MASK 0x400u |
| #define SDMAARM_ONCE_STAT_EDR_SHIFT 10 |
| #define SDMAARM_ONCE_STAT_RCV_MASK 0x800u |
| #define SDMAARM_ONCE_STAT_RCV_SHIFT 11 |
| #define SDMAARM_ONCE_STAT_PST_MASK 0xF000u |
| #define SDMAARM_ONCE_STAT_PST_SHIFT 12 |
| #define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_PST_SHIFT))&SDMAARM_ONCE_STAT_PST_MASK) |
| /* ONCE_CMD Bit Fields */ |
| #define SDMAARM_ONCE_CMD_CMD_MASK 0xFu |
| #define SDMAARM_ONCE_CMD_CMD_SHIFT 0 |
| #define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_CMD_CMD_SHIFT))&SDMAARM_ONCE_CMD_CMD_MASK) |
| /* ILLINSTADDR Bit Fields */ |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK 0x3FFFu |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT 0 |
| #define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT))&SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) |
| /* CHN0ADDR Bit Fields */ |
| #define SDMAARM_CHN0ADDR_CHN0ADDR_MASK 0x3FFFu |
| #define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT 0 |
| #define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT))&SDMAARM_CHN0ADDR_CHN0ADDR_MASK) |
| #define SDMAARM_CHN0ADDR_SMSZ_MASK 0x4000u |
| #define SDMAARM_CHN0ADDR_SMSZ_SHIFT 14 |
| /* EVT_MIRROR Bit Fields */ |
| #define SDMAARM_EVT_MIRROR_EVENTS_MASK 0xFFFFFFFFu |
| #define SDMAARM_EVT_MIRROR_EVENTS_SHIFT 0 |
| #define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR_EVENTS_MASK) |
| /* EVT_MIRROR2 Bit Fields */ |
| #define SDMAARM_EVT_MIRROR2_EVENTS_MASK 0xFFFFu |
| #define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT 0 |
| #define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR2_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR2_EVENTS_MASK) |
| /* XTRIG_CONF1 Bit Fields */ |
| #define SDMAARM_XTRIG_CONF1_NUM0_MASK 0x3Fu |
| #define SDMAARM_XTRIG_CONF1_NUM0_SHIFT 0 |
| #define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM0_SHIFT))&SDMAARM_XTRIG_CONF1_NUM0_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF0_MASK 0x40u |
| #define SDMAARM_XTRIG_CONF1_CNF0_SHIFT 6 |
| #define SDMAARM_XTRIG_CONF1_NUM1_MASK 0x3F00u |
| #define SDMAARM_XTRIG_CONF1_NUM1_SHIFT 8 |
| #define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM1_SHIFT))&SDMAARM_XTRIG_CONF1_NUM1_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF1_MASK 0x4000u |
| #define SDMAARM_XTRIG_CONF1_CNF1_SHIFT 14 |
| #define SDMAARM_XTRIG_CONF1_NUM2_MASK 0x3F0000u |
| #define SDMAARM_XTRIG_CONF1_NUM2_SHIFT 16 |
| #define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM2_SHIFT))&SDMAARM_XTRIG_CONF1_NUM2_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF2_MASK 0x400000u |
| #define SDMAARM_XTRIG_CONF1_CNF2_SHIFT 22 |
| #define SDMAARM_XTRIG_CONF1_NUM3_MASK 0x3F000000u |
| #define SDMAARM_XTRIG_CONF1_NUM3_SHIFT 24 |
| #define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM3_SHIFT))&SDMAARM_XTRIG_CONF1_NUM3_MASK) |
| #define SDMAARM_XTRIG_CONF1_CNF3_MASK 0x40000000u |
| #define SDMAARM_XTRIG_CONF1_CNF3_SHIFT 30 |
| /* XTRIG_CONF2 Bit Fields */ |
| #define SDMAARM_XTRIG_CONF2_NUM4_MASK 0x3Fu |
| #define SDMAARM_XTRIG_CONF2_NUM4_SHIFT 0 |
| #define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM4_SHIFT))&SDMAARM_XTRIG_CONF2_NUM4_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF4_MASK 0x40u |
| #define SDMAARM_XTRIG_CONF2_CNF4_SHIFT 6 |
| #define SDMAARM_XTRIG_CONF2_NUM5_MASK 0x3F00u |
| #define SDMAARM_XTRIG_CONF2_NUM5_SHIFT 8 |
| #define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM5_SHIFT))&SDMAARM_XTRIG_CONF2_NUM5_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF5_MASK 0x4000u |
| #define SDMAARM_XTRIG_CONF2_CNF5_SHIFT 14 |
| #define SDMAARM_XTRIG_CONF2_NUM6_MASK 0x3F0000u |
| #define SDMAARM_XTRIG_CONF2_NUM6_SHIFT 16 |
| #define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM6_SHIFT))&SDMAARM_XTRIG_CONF2_NUM6_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF6_MASK 0x400000u |
| #define SDMAARM_XTRIG_CONF2_CNF6_SHIFT 22 |
| #define SDMAARM_XTRIG_CONF2_NUM7_MASK 0x3F000000u |
| #define SDMAARM_XTRIG_CONF2_NUM7_SHIFT 24 |
| #define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM7_SHIFT))&SDMAARM_XTRIG_CONF2_NUM7_MASK) |
| #define SDMAARM_XTRIG_CONF2_CNF7_MASK 0x40000000u |
| #define SDMAARM_XTRIG_CONF2_CNF7_SHIFT 30 |
| /* SDMA_CHNPRI Bit Fields */ |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK 0x7u |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT 0 |
| #define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT))&SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) |
| /* CHNENBL Bit Fields */ |
| #define SDMAARM_CHNENBL_ENBLn_MASK 0xFFFFFFFFu |
| #define SDMAARM_CHNENBL_ENBLn_SHIFT 0 |
| #define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHNENBL_ENBLn_SHIFT))&SDMAARM_CHNENBL_ENBLn_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Register_Masks */ |
| |
| /* SDMAARM - Peripheral instance base addresses */ |
| /** Peripheral SDMAARM base address */ |
| #define SDMAARM_BASE (0x420EC000u) |
| /** Peripheral SDMAARM base pointer */ |
| #define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) |
| #define SDMAARM_BASE_PTR (SDMAARM) |
| /** Array initializer of SDMAARM peripheral base addresses */ |
| #define SDMAARM_BASE_ADDRS { SDMAARM_BASE } |
| /** Array initializer of SDMAARM peripheral base pointers */ |
| #define SDMAARM_BASE_PTRS { SDMAARM } |
| /** Interrupt vectors for the SDMAARM peripheral type */ |
| #define SDMAARM_IRQS { SDMA_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMAARM - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMAARM - Register instance definitions */ |
| /* SDMAARM */ |
| #define SDMAARM_MC0PTR SDMAARM_MC0PTR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_INTR SDMAARM_INTR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_STOP_STAT SDMAARM_STOP_STAT_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_HSTART SDMAARM_HSTART_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVTOVR SDMAARM_EVTOVR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_DSPOVR SDMAARM_DSPOVR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_HOSTOVR SDMAARM_HOSTOVR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVTPEND SDMAARM_EVTPEND_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_RESET SDMAARM_RESET_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVTERR SDMAARM_EVTERR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_INTRMASK SDMAARM_INTRMASK_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_PSW SDMAARM_PSW_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVTERRDBG SDMAARM_EVTERRDBG_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_CONFIG SDMAARM_CONFIG_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_SDMA_LOCK SDMAARM_SDMA_LOCK_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ONCE_ENB SDMAARM_ONCE_ENB_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ONCE_DATA SDMAARM_ONCE_DATA_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ONCE_INSTR SDMAARM_ONCE_INSTR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ONCE_STAT SDMAARM_ONCE_STAT_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ONCE_CMD SDMAARM_ONCE_CMD_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_ILLINSTADDR SDMAARM_ILLINSTADDR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_CHN0ADDR SDMAARM_CHN0ADDR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVT_MIRROR SDMAARM_EVT_MIRROR_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_EVT_MIRROR2 SDMAARM_EVT_MIRROR2_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_XTRIG_CONF1 SDMAARM_XTRIG_CONF1_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_XTRIG_CONF2 SDMAARM_XTRIG_CONF2_REG(SDMAARM_BASE_PTR) |
| #define SDMAARM_SDMA_CHNPRI0 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,0) |
| #define SDMAARM_SDMA_CHNPRI1 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,1) |
| #define SDMAARM_SDMA_CHNPRI2 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,2) |
| #define SDMAARM_SDMA_CHNPRI3 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,3) |
| #define SDMAARM_SDMA_CHNPRI4 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,4) |
| #define SDMAARM_SDMA_CHNPRI5 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,5) |
| #define SDMAARM_SDMA_CHNPRI6 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,6) |
| #define SDMAARM_SDMA_CHNPRI7 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,7) |
| #define SDMAARM_SDMA_CHNPRI8 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,8) |
| #define SDMAARM_SDMA_CHNPRI9 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,9) |
| #define SDMAARM_SDMA_CHNPRI10 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,10) |
| #define SDMAARM_SDMA_CHNPRI11 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,11) |
| #define SDMAARM_SDMA_CHNPRI12 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,12) |
| #define SDMAARM_SDMA_CHNPRI13 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,13) |
| #define SDMAARM_SDMA_CHNPRI14 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,14) |
| #define SDMAARM_SDMA_CHNPRI15 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,15) |
| #define SDMAARM_SDMA_CHNPRI16 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,16) |
| #define SDMAARM_SDMA_CHNPRI17 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,17) |
| #define SDMAARM_SDMA_CHNPRI18 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,18) |
| #define SDMAARM_SDMA_CHNPRI19 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,19) |
| #define SDMAARM_SDMA_CHNPRI20 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,20) |
| #define SDMAARM_SDMA_CHNPRI21 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,21) |
| #define SDMAARM_SDMA_CHNPRI22 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,22) |
| #define SDMAARM_SDMA_CHNPRI23 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,23) |
| #define SDMAARM_SDMA_CHNPRI24 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,24) |
| #define SDMAARM_SDMA_CHNPRI25 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,25) |
| #define SDMAARM_SDMA_CHNPRI26 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,26) |
| #define SDMAARM_SDMA_CHNPRI27 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,27) |
| #define SDMAARM_SDMA_CHNPRI28 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,28) |
| #define SDMAARM_SDMA_CHNPRI29 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,29) |
| #define SDMAARM_SDMA_CHNPRI30 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,30) |
| #define SDMAARM_SDMA_CHNPRI31 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,31) |
| #define SDMAARM_CHNENBL0 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,0) |
| #define SDMAARM_CHNENBL1 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,1) |
| #define SDMAARM_CHNENBL2 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,2) |
| #define SDMAARM_CHNENBL3 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,3) |
| #define SDMAARM_CHNENBL4 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,4) |
| #define SDMAARM_CHNENBL5 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,5) |
| #define SDMAARM_CHNENBL6 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,6) |
| #define SDMAARM_CHNENBL7 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,7) |
| #define SDMAARM_CHNENBL8 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,8) |
| #define SDMAARM_CHNENBL9 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,9) |
| #define SDMAARM_CHNENBL10 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,10) |
| #define SDMAARM_CHNENBL11 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,11) |
| #define SDMAARM_CHNENBL12 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,12) |
| #define SDMAARM_CHNENBL13 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,13) |
| #define SDMAARM_CHNENBL14 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,14) |
| #define SDMAARM_CHNENBL15 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,15) |
| #define SDMAARM_CHNENBL16 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,16) |
| #define SDMAARM_CHNENBL17 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,17) |
| #define SDMAARM_CHNENBL18 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,18) |
| #define SDMAARM_CHNENBL19 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,19) |
| #define SDMAARM_CHNENBL20 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,20) |
| #define SDMAARM_CHNENBL21 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,21) |
| #define SDMAARM_CHNENBL22 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,22) |
| #define SDMAARM_CHNENBL23 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,23) |
| #define SDMAARM_CHNENBL24 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,24) |
| #define SDMAARM_CHNENBL25 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,25) |
| #define SDMAARM_CHNENBL26 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,26) |
| #define SDMAARM_CHNENBL27 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,27) |
| #define SDMAARM_CHNENBL28 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,28) |
| #define SDMAARM_CHNENBL29 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,29) |
| #define SDMAARM_CHNENBL30 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,30) |
| #define SDMAARM_CHNENBL31 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,31) |
| #define SDMAARM_CHNENBL32 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,32) |
| #define SDMAARM_CHNENBL33 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,33) |
| #define SDMAARM_CHNENBL34 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,34) |
| #define SDMAARM_CHNENBL35 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,35) |
| #define SDMAARM_CHNENBL36 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,36) |
| #define SDMAARM_CHNENBL37 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,37) |
| #define SDMAARM_CHNENBL38 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,38) |
| #define SDMAARM_CHNENBL39 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,39) |
| #define SDMAARM_CHNENBL40 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,40) |
| #define SDMAARM_CHNENBL41 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,41) |
| #define SDMAARM_CHNENBL42 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,42) |
| #define SDMAARM_CHNENBL43 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,43) |
| #define SDMAARM_CHNENBL44 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,44) |
| #define SDMAARM_CHNENBL45 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,45) |
| #define SDMAARM_CHNENBL46 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,46) |
| #define SDMAARM_CHNENBL47 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,47) |
| /* SDMAARM - Register array accessors */ |
| #define SDMAARM_SDMA_CHNPRI(index) SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,index) |
| #define SDMAARM_CHNENBL(index) SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SDMAARM_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMABP Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMABP_Peripheral_Access_Layer SDMABP Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SDMABP - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DC0PTR; /**< Channel 0 Pointer, offset: 0x0 */ |
| __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ |
| __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ |
| __I uint32_t DSTART; /**< Channel Start, offset: 0xC */ |
| uint8_t RESERVED_0[24]; |
| __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ |
| __IO uint32_t INTRMASK; /**< Channel DSP Interrupt Mask, offset: 0x2C */ |
| uint8_t RESERVED_1[4]; |
| __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ |
| } SDMABP_Type, *SDMABP_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMABP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMABP - Register accessors */ |
| #define SDMABP_DC0PTR_REG(base) ((base)->DC0PTR) |
| #define SDMABP_INTR_REG(base) ((base)->INTR) |
| #define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) |
| #define SDMABP_DSTART_REG(base) ((base)->DSTART) |
| #define SDMABP_EVTERR_REG(base) ((base)->EVTERR) |
| #define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) |
| #define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) |
| |
| /*! |
| * @} |
| */ /* end of group SDMABP_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMABP Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMABP_Register_Masks SDMABP Register Masks |
| * @{ |
| */ |
| |
| /* DC0PTR Bit Fields */ |
| #define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu |
| #define SDMABP_DC0PTR_DC0PTR_SHIFT 0 |
| #define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DC0PTR_DC0PTR_SHIFT))&SDMABP_DC0PTR_DC0PTR_MASK) |
| /* INTR Bit Fields */ |
| #define SDMABP_INTR_DI_MASK 0xFFFFFFFFu |
| #define SDMABP_INTR_DI_SHIFT 0 |
| #define SDMABP_INTR_DI(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTR_DI_SHIFT))&SDMABP_INTR_DI_MASK) |
| /* STOP_STAT Bit Fields */ |
| #define SDMABP_STOP_STAT_DE_MASK 0xFFFFFFFFu |
| #define SDMABP_STOP_STAT_DE_SHIFT 0 |
| #define SDMABP_STOP_STAT_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_STOP_STAT_DE_SHIFT))&SDMABP_STOP_STAT_DE_MASK) |
| /* DSTART Bit Fields */ |
| #define SDMABP_DSTART_DSTART_DE_MASK 0xFFFFFFFFu |
| #define SDMABP_DSTART_DSTART_DE_SHIFT 0 |
| #define SDMABP_DSTART_DSTART_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DSTART_DSTART_DE_SHIFT))&SDMABP_DSTART_DSTART_DE_MASK) |
| /* EVTERR Bit Fields */ |
| #define SDMABP_EVTERR_CHNERR_MASK 0xFFFFFFFFu |
| #define SDMABP_EVTERR_CHNERR_SHIFT 0 |
| #define SDMABP_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERR_CHNERR_SHIFT))&SDMABP_EVTERR_CHNERR_MASK) |
| /* INTRMASK Bit Fields */ |
| #define SDMABP_INTRMASK_DIMASK_MASK 0xFFFFFFFFu |
| #define SDMABP_INTRMASK_DIMASK_SHIFT 0 |
| #define SDMABP_INTRMASK_DIMASK(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTRMASK_DIMASK_SHIFT))&SDMABP_INTRMASK_DIMASK_MASK) |
| /* EVTERRDBG Bit Fields */ |
| #define SDMABP_EVTERRDBG_CHNERR_MASK 0xFFFFFFFFu |
| #define SDMABP_EVTERRDBG_CHNERR_SHIFT 0 |
| #define SDMABP_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERRDBG_CHNERR_SHIFT))&SDMABP_EVTERRDBG_CHNERR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SDMABP_Register_Masks */ |
| |
| /* SDMABP - Peripheral instance base addresses */ |
| /** Peripheral SDMABP base address */ |
| #define SDMABP_BASE (0x420EC000u) |
| /** Peripheral SDMABP base pointer */ |
| #define SDMABP ((SDMABP_Type *)SDMABP_BASE) |
| #define SDMABP_BASE_PTR (SDMABP) |
| /** Array initializer of SDMABP peripheral base addresses */ |
| #define SDMABP_BASE_ADDRS { SDMABP_BASE } |
| /** Array initializer of SDMABP peripheral base pointers */ |
| #define SDMABP_BASE_PTRS { SDMABP } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMABP - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMABP - Register instance definitions */ |
| /* SDMABP */ |
| #define SDMABP_DC0PTR SDMABP_DC0PTR_REG(SDMABP_BASE_PTR) |
| #define SDMABP_INTR SDMABP_INTR_REG(SDMABP_BASE_PTR) |
| #define SDMABP_STOP_STAT SDMABP_STOP_STAT_REG(SDMABP_BASE_PTR) |
| #define SDMABP_DSTART SDMABP_DSTART_REG(SDMABP_BASE_PTR) |
| #define SDMABP_EVTERR SDMABP_EVTERR_REG(SDMABP_BASE_PTR) |
| #define SDMABP_INTRMASK SDMABP_INTRMASK_REG(SDMABP_BASE_PTR) |
| #define SDMABP_EVTERRDBG SDMABP_EVTERRDBG_REG(SDMABP_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SDMABP_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SDMABP_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMACORE Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMACORE_Peripheral_Access_Layer SDMACORE Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SDMACORE - Register Layout Typedef */ |
| typedef struct { |
| union { /* offset: 0x0 */ |
| __I uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer,offset: 0x0 */ |
| struct { /* offset: 0x2 */ |
| uint8_t RESERVED_0[2]; |
| __I uint32_t CCPTR; /**< Current Channel Pointer,offset: 0x2 */ |
| } CCPTR; |
| struct { /* offset: 0x3 */ |
| uint8_t RESERVED_0[3]; |
| __I uint32_t CCR; /**< Current Channel Register,offset: 0x3 */ |
| } CCR; |
| struct { /* offset: 0x4 */ |
| uint8_t RESERVED_0[4]; |
| __I uint32_t NCR; /**< Highest Pending Channel Register,offset: 0x4 */ |
| } NCR; |
| struct { /* offset: 0x5 */ |
| uint8_t RESERVED_0[5]; |
| __I uint32_t EVENTS; /**< External DMA Requests Mirror,offset: 0x5 */ |
| } EVENTS; |
| struct { /* offset: 0x6 */ |
| uint8_t RESERVED_0[6]; |
| __I uint32_t CCPRI; /**< Current Channel Priority,offset: 0x6 */ |
| } CCPRI; |
| struct { /* offset: 0x7 */ |
| uint8_t RESERVED_0[7]; |
| __I uint32_t NCPRI; /**< Next Channel Priority,offset: 0x7 */ |
| } NCPRI; |
| struct { /* offset: 0x9 */ |
| uint8_t RESERVED_0[9]; |
| __IO uint32_t ECOUNT; /**< OnCE Event Cell Counter,offset: 0x9 */ |
| } ECOUNT; |
| struct { /* offset: 0xA */ |
| uint8_t RESERVED_0[10]; |
| __IO uint32_t ECTL; /**< OnCE Event Cell Control Register,offset: 0xA */ |
| } ECTL; |
| struct { /* offset: 0xB */ |
| uint8_t RESERVED_0[11]; |
| __IO uint32_t EAA; /**< OnCE Event Address Register A,offset: 0xB */ |
| } EAA; |
| struct { /* offset: 0xC */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t EAB; /**< OnCE Event Cell Address Register B,offset: 0xC */ |
| } EAB; |
| struct { /* offset: 0xD */ |
| uint8_t RESERVED_0[13]; |
| __IO uint32_t EAM; /**< OnCE Event Cell Address Mask,offset: 0xD */ |
| } EAM; |
| struct { /* offset: 0xE */ |
| uint8_t RESERVED_0[14]; |
| __IO uint32_t ED; /**< OnCE Event Cell Data Register,offset: 0xE */ |
| } ED; |
| struct { /* offset: 0xF */ |
| uint8_t RESERVED_0[15]; |
| __IO uint32_t EDM; /**< OnCE Event Cell Data Mask,offset: 0xF */ |
| } EDM; |
| }; |
| uint8_t RESERVED_0[5]; |
| union { /* offset: 0x18 */ |
| __IO uint32_t RTB; /**< OnCE Real-Time Buffer,offset: 0x18 */ |
| struct { /* offset: 0x19 */ |
| uint8_t RESERVED_0[1]; |
| __I uint32_t TB; /**< OnCE Trace Buffer,offset: 0x19 */ |
| } TB; |
| struct { /* offset: 0x1A */ |
| uint8_t RESERVED_0[2]; |
| __I uint32_t OSTAT; /**< OnCE Status,offset: 0x1A */ |
| } OSTAT; |
| struct { /* offset: 0x1C */ |
| uint8_t RESERVED_0[4]; |
| __I uint32_t MCHN0ADDR; /**< Channel 0 Boot Address,offset: 0x1C */ |
| } MCHN0ADDR; |
| struct { /* offset: 0x1D */ |
| uint8_t RESERVED_0[5]; |
| __I uint32_t ENDIANNESS; /**< ENDIAN Status Register,offset: 0x1D */ |
| } ENDIANNESS; |
| struct { /* offset: 0x1E */ |
| uint8_t RESERVED_0[6]; |
| __I uint32_t SDMA_LOCK; /**< Lock Status Register,offset: 0x1E */ |
| } SDMA_LOCK; |
| struct { /* offset: 0x1F */ |
| uint8_t RESERVED_0[7]; |
| __I uint32_t EVENTS2; /**< External DMA Requests Mirror #2,offset: 0x1F */ |
| } EVENTS2; |
| }; |
| } SDMACORE_Type, *SDMACORE_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMACORE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMACORE - Register accessors */ |
| #define SDMACORE_MC0PTR_REG(base) ((base)->MC0PTR) |
| #define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) |
| #define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) |
| #define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) |
| #define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) |
| #define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) |
| #define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) |
| #define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) |
| #define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) |
| #define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) |
| #define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) |
| #define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) |
| #define SDMACORE_ED_REG(base) ((base)->ED.ED) |
| #define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) |
| #define SDMACORE_RTB_REG(base) ((base)->RTB) |
| #define SDMACORE_TB_REG(base) ((base)->TB.TB) |
| #define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) |
| #define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) |
| #define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) |
| #define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) |
| #define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) |
| |
| /*! |
| * @} |
| */ /* end of group SDMACORE_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMACORE Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks |
| * @{ |
| */ |
| |
| /* MC0PTR Bit Fields */ |
| #define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu |
| #define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 |
| #define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MC0PTR_MC0PTR_SHIFT))&SDMACORE_MC0PTR_MC0PTR_MASK) |
| /* CCPTR Bit Fields */ |
| #define SDMACORE_CCPTR_CCPTR_MASK 0xFFFFu |
| #define SDMACORE_CCPTR_CCPTR_SHIFT 0 |
| #define SDMACORE_CCPTR_CCPTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPTR_CCPTR_SHIFT))&SDMACORE_CCPTR_CCPTR_MASK) |
| /* CCR Bit Fields */ |
| #define SDMACORE_CCR_CCR_MASK 0x1Fu |
| #define SDMACORE_CCR_CCR_SHIFT 0 |
| #define SDMACORE_CCR_CCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCR_CCR_SHIFT))&SDMACORE_CCR_CCR_MASK) |
| /* NCR Bit Fields */ |
| #define SDMACORE_NCR_NCR_MASK 0x1Fu |
| #define SDMACORE_NCR_NCR_SHIFT 0 |
| #define SDMACORE_NCR_NCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCR_NCR_SHIFT))&SDMACORE_NCR_NCR_MASK) |
| /* EVENTS Bit Fields */ |
| #define SDMACORE_EVENTS_EVENTS_MASK 0xFFFFFFFFu |
| #define SDMACORE_EVENTS_EVENTS_SHIFT 0 |
| #define SDMACORE_EVENTS_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS_EVENTS_SHIFT))&SDMACORE_EVENTS_EVENTS_MASK) |
| /* CCPRI Bit Fields */ |
| #define SDMACORE_CCPRI_CCPRI_MASK 0x7u |
| #define SDMACORE_CCPRI_CCPRI_SHIFT 0 |
| #define SDMACORE_CCPRI_CCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPRI_CCPRI_SHIFT))&SDMACORE_CCPRI_CCPRI_MASK) |
| /* NCPRI Bit Fields */ |
| #define SDMACORE_NCPRI_NCPRI_MASK 0x7u |
| #define SDMACORE_NCPRI_NCPRI_SHIFT 0 |
| #define SDMACORE_NCPRI_NCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCPRI_NCPRI_SHIFT))&SDMACORE_NCPRI_NCPRI_MASK) |
| /* ECOUNT Bit Fields */ |
| #define SDMACORE_ECOUNT_ECOUNT_MASK 0xFFFFu |
| #define SDMACORE_ECOUNT_ECOUNT_SHIFT 0 |
| #define SDMACORE_ECOUNT_ECOUNT(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECOUNT_ECOUNT_SHIFT))&SDMACORE_ECOUNT_ECOUNT_MASK) |
| /* ECTL Bit Fields */ |
| #define SDMACORE_ECTL_ATS_MASK 0x3u |
| #define SDMACORE_ECTL_ATS_SHIFT 0 |
| #define SDMACORE_ECTL_ATS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATS_SHIFT))&SDMACORE_ECTL_ATS_MASK) |
| #define SDMACORE_ECTL_AATC_MASK 0xCu |
| #define SDMACORE_ECTL_AATC_SHIFT 2 |
| #define SDMACORE_ECTL_AATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_AATC_SHIFT))&SDMACORE_ECTL_AATC_MASK) |
| #define SDMACORE_ECTL_ABTC_MASK 0x30u |
| #define SDMACORE_ECTL_ABTC_SHIFT 4 |
| #define SDMACORE_ECTL_ABTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ABTC_SHIFT))&SDMACORE_ECTL_ABTC_MASK) |
| #define SDMACORE_ECTL_ATC_MASK 0xC0u |
| #define SDMACORE_ECTL_ATC_SHIFT 6 |
| #define SDMACORE_ECTL_ATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATC_SHIFT))&SDMACORE_ECTL_ATC_MASK) |
| #define SDMACORE_ECTL_DTC_MASK 0x300u |
| #define SDMACORE_ECTL_DTC_SHIFT 8 |
| #define SDMACORE_ECTL_DTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_DTC_SHIFT))&SDMACORE_ECTL_DTC_MASK) |
| #define SDMACORE_ECTL_ECTC_MASK 0xC00u |
| #define SDMACORE_ECTL_ECTC_SHIFT 10 |
| #define SDMACORE_ECTL_ECTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ECTC_SHIFT))&SDMACORE_ECTL_ECTC_MASK) |
| #define SDMACORE_ECTL_CNT_MASK 0x1000u |
| #define SDMACORE_ECTL_CNT_SHIFT 12 |
| #define SDMACORE_ECTL_EN_MASK 0x2000u |
| #define SDMACORE_ECTL_EN_SHIFT 13 |
| /* EAA Bit Fields */ |
| #define SDMACORE_EAA_EAA_MASK 0xFFFFu |
| #define SDMACORE_EAA_EAA_SHIFT 0 |
| #define SDMACORE_EAA_EAA(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAA_EAA_SHIFT))&SDMACORE_EAA_EAA_MASK) |
| /* EAB Bit Fields */ |
| #define SDMACORE_EAB_EAB_MASK 0xFFFFu |
| #define SDMACORE_EAB_EAB_SHIFT 0 |
| #define SDMACORE_EAB_EAB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAB_EAB_SHIFT))&SDMACORE_EAB_EAB_MASK) |
| /* EAM Bit Fields */ |
| #define SDMACORE_EAM_EAM_MASK 0xFFFFu |
| #define SDMACORE_EAM_EAM_SHIFT 0 |
| #define SDMACORE_EAM_EAM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAM_EAM_SHIFT))&SDMACORE_EAM_EAM_MASK) |
| /* ED Bit Fields */ |
| #define SDMACORE_ED_ED_MASK 0xFFFFFFFFu |
| #define SDMACORE_ED_ED_SHIFT 0 |
| #define SDMACORE_ED_ED(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ED_ED_SHIFT))&SDMACORE_ED_ED_MASK) |
| /* EDM Bit Fields */ |
| #define SDMACORE_EDM_EDM_MASK 0xFFFFFFFFu |
| #define SDMACORE_EDM_EDM_SHIFT 0 |
| #define SDMACORE_EDM_EDM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EDM_EDM_SHIFT))&SDMACORE_EDM_EDM_MASK) |
| /* RTB Bit Fields */ |
| #define SDMACORE_RTB_RTB_MASK 0xFFFFFFFFu |
| #define SDMACORE_RTB_RTB_SHIFT 0 |
| #define SDMACORE_RTB_RTB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_RTB_RTB_SHIFT))&SDMACORE_RTB_RTB_MASK) |
| /* TB Bit Fields */ |
| #define SDMACORE_TB_CHFADDR_MASK 0x3FFFu |
| #define SDMACORE_TB_CHFADDR_SHIFT 0 |
| #define SDMACORE_TB_CHFADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_CHFADDR_SHIFT))&SDMACORE_TB_CHFADDR_MASK) |
| #define SDMACORE_TB_TADDR_MASK 0xFFFC000u |
| #define SDMACORE_TB_TADDR_SHIFT 14 |
| #define SDMACORE_TB_TADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_TADDR_SHIFT))&SDMACORE_TB_TADDR_MASK) |
| #define SDMACORE_TB_TBF_MASK 0x10000000u |
| #define SDMACORE_TB_TBF_SHIFT 28 |
| /* OSTAT Bit Fields */ |
| #define SDMACORE_OSTAT_ECDR_MASK 0x7u |
| #define SDMACORE_OSTAT_ECDR_SHIFT 0 |
| #define SDMACORE_OSTAT_ECDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_ECDR_SHIFT))&SDMACORE_OSTAT_ECDR_MASK) |
| #define SDMACORE_OSTAT_MST_MASK 0x80u |
| #define SDMACORE_OSTAT_MST_SHIFT 7 |
| #define SDMACORE_OSTAT_SWB_MASK 0x100u |
| #define SDMACORE_OSTAT_SWB_SHIFT 8 |
| #define SDMACORE_OSTAT_ODR_MASK 0x200u |
| #define SDMACORE_OSTAT_ODR_SHIFT 9 |
| #define SDMACORE_OSTAT_EDR_MASK 0x400u |
| #define SDMACORE_OSTAT_EDR_SHIFT 10 |
| #define SDMACORE_OSTAT_RCV_MASK 0x800u |
| #define SDMACORE_OSTAT_RCV_SHIFT 11 |
| #define SDMACORE_OSTAT_PST_MASK 0xF000u |
| #define SDMACORE_OSTAT_PST_SHIFT 12 |
| #define SDMACORE_OSTAT_PST(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_PST_SHIFT))&SDMACORE_OSTAT_PST_MASK) |
| /* MCHN0ADDR Bit Fields */ |
| #define SDMACORE_MCHN0ADDR_CHN0ADDR_MASK 0x3FFFu |
| #define SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT 0 |
| #define SDMACORE_MCHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT))&SDMACORE_MCHN0ADDR_CHN0ADDR_MASK) |
| #define SDMACORE_MCHN0ADDR_SMSZ_MASK 0x4000u |
| #define SDMACORE_MCHN0ADDR_SMSZ_SHIFT 14 |
| /* ENDIANNESS Bit Fields */ |
| #define SDMACORE_ENDIANNESS_APEND_MASK 0x1u |
| #define SDMACORE_ENDIANNESS_APEND_SHIFT 0 |
| /* SDMA_LOCK Bit Fields */ |
| #define SDMACORE_SDMA_LOCK_LOCK_MASK 0x1u |
| #define SDMACORE_SDMA_LOCK_LOCK_SHIFT 0 |
| /* EVENTS2 Bit Fields */ |
| #define SDMACORE_EVENTS2_EVENTS_MASK 0xFFFFu |
| #define SDMACORE_EVENTS2_EVENTS_SHIFT 0 |
| #define SDMACORE_EVENTS2_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS2_EVENTS_SHIFT))&SDMACORE_EVENTS2_EVENTS_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SDMACORE_Register_Masks */ |
| |
| /* SDMACORE - Peripheral instance base addresses */ |
| /** Peripheral SDMACORE base address */ |
| #define SDMACORE_BASE (0x420EC000u) |
| /** Peripheral SDMACORE base pointer */ |
| #define SDMACORE ((SDMACORE_Type *)SDMACORE_BASE) |
| #define SDMACORE_BASE_PTR (SDMACORE) |
| /** Array initializer of SDMACORE peripheral base addresses */ |
| #define SDMACORE_BASE_ADDRS { SDMACORE_BASE } |
| /** Array initializer of SDMACORE peripheral base pointers */ |
| #define SDMACORE_BASE_PTRS { SDMACORE } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SDMACORE - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros |
| * @{ |
| */ |
| |
| /* SDMACORE - Register instance definitions */ |
| /* SDMACORE */ |
| #define SDMACORE_MC0PTR SDMACORE_MC0PTR_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_CCPTR SDMACORE_CCPTR_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_CCR SDMACORE_CCR_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_NCR SDMACORE_NCR_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EVENTS SDMACORE_EVENTS_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_CCPRI SDMACORE_CCPRI_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_NCPRI SDMACORE_NCPRI_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_ECOUNT SDMACORE_ECOUNT_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_ECTL SDMACORE_ECTL_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EAA SDMACORE_EAA_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EAB SDMACORE_EAB_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EAM SDMACORE_EAM_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_ED SDMACORE_ED_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EDM SDMACORE_EDM_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_RTB SDMACORE_RTB_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_TB SDMACORE_TB_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_OSTAT SDMACORE_OSTAT_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_MCHN0ADDR SDMACORE_MCHN0ADDR_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_ENDIANNESS SDMACORE_ENDIANNESS_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_SDMA_LOCK SDMACORE_SDMA_LOCK_REG(SDMACORE_BASE_PTR) |
| #define SDMACORE_EVENTS2 SDMACORE_EVENTS2_REG(SDMACORE_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SDMACORE_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SDMACORE_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SEMA4 - Register Layout Typedef */ |
| typedef struct { |
| __IO uint8_t GATE00; /**< Semaphores GATE 0 Register, offset: 0x0 */ |
| __IO uint8_t GATE01; /**< Semaphores GATE 1 Register, offset: 0x1 */ |
| __IO uint8_t GATE02; /**< Semaphores GATE 2 Register, offset: 0x2 */ |
| __IO uint8_t GATE03; /**< Semaphores GATE 3 Register, offset: 0x3 */ |
| __IO uint8_t GATE04; /**< Semaphores GATE 4 Register, offset: 0x4 */ |
| __IO uint8_t GATE05; /**< Semaphores GATE 5 Register, offset: 0x5 */ |
| __IO uint8_t GATE06; /**< Semaphores GATE 6 Register, offset: 0x6 */ |
| __IO uint8_t GATE07; /**< Semaphores GATE 7 Register, offset: 0x7 */ |
| __IO uint8_t GATE08; /**< Semaphores GATE 8 Register, offset: 0x8 */ |
| __IO uint8_t GATE09; /**< Semaphores GATE 9 Register, offset: 0x9 */ |
| __IO uint8_t GATE10; /**< Semaphores GATE 10 Register, offset: 0xA */ |
| __IO uint8_t GATE11; /**< Semaphores GATE 11 Register, offset: 0xB */ |
| __IO uint8_t GATE12; /**< Semaphores GATE 12 Register, offset: 0xC */ |
| __IO uint8_t GATE13; /**< Semaphores GATE 13 Register, offset: 0xD */ |
| __IO uint8_t GATE14; /**< Semaphores GATE 14 Register, offset: 0xE */ |
| __IO uint8_t GATE15; /**< Semaphores GATE 15 Register, offset: 0xF */ |
| uint8_t RESERVED_0[48]; |
| struct { /* offset: 0x40, array step: 0x8 */ |
| __IO uint16_t INE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ |
| uint8_t RESERVED_0[6]; |
| } CPnINE[2]; |
| uint8_t RESERVED_1[48]; |
| struct { /* offset: 0x80, array step: 0x8 */ |
| __I uint16_t NTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ |
| uint8_t RESERVED_0[6]; |
| } CPnNTF[2]; |
| uint8_t RESERVED_2[112]; |
| __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset GATE n, offset: 0x100 */ |
| uint8_t RESERVED_3[2]; |
| __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ |
| } SEMA4_Type, *SEMA4_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros |
| * @{ |
| */ |
| |
| /* SEMA4 - Register accessors */ |
| #define SEMA4_GATE00_REG(base) ((base)->GATE00) |
| #define SEMA4_GATE01_REG(base) ((base)->GATE01) |
| #define SEMA4_GATE02_REG(base) ((base)->GATE02) |
| #define SEMA4_GATE03_REG(base) ((base)->GATE03) |
| #define SEMA4_GATE04_REG(base) ((base)->GATE04) |
| #define SEMA4_GATE05_REG(base) ((base)->GATE05) |
| #define SEMA4_GATE06_REG(base) ((base)->GATE06) |
| #define SEMA4_GATE07_REG(base) ((base)->GATE07) |
| #define SEMA4_GATE08_REG(base) ((base)->GATE08) |
| #define SEMA4_GATE09_REG(base) ((base)->GATE09) |
| #define SEMA4_GATE10_REG(base) ((base)->GATE10) |
| #define SEMA4_GATE11_REG(base) ((base)->GATE11) |
| #define SEMA4_GATE12_REG(base) ((base)->GATE12) |
| #define SEMA4_GATE13_REG(base) ((base)->GATE13) |
| #define SEMA4_GATE14_REG(base) ((base)->GATE14) |
| #define SEMA4_GATE15_REG(base) ((base)->GATE15) |
| #define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) |
| #define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) |
| #define SEMA4_RSTGT_REG(base) ((base)->RSTGT) |
| #define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks |
| * @{ |
| */ |
| |
| /* GATE00 Bit Fields */ |
| #define SEMA4_GATE00_GTFSM_MASK 0x3u |
| #define SEMA4_GATE00_GTFSM_SHIFT 0 |
| #define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE00_GTFSM_SHIFT))&SEMA4_GATE00_GTFSM_MASK) |
| /* GATE01 Bit Fields */ |
| #define SEMA4_GATE01_GTFSM_MASK 0x3u |
| #define SEMA4_GATE01_GTFSM_SHIFT 0 |
| #define SEMA4_GATE01_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK) |
| /* GATE02 Bit Fields */ |
| #define SEMA4_GATE02_GTFSM_MASK 0x3u |
| #define SEMA4_GATE02_GTFSM_SHIFT 0 |
| #define SEMA4_GATE02_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK) |
| /* GATE03 Bit Fields */ |
| #define SEMA4_GATE03_GTFSM_MASK 0x3u |
| #define SEMA4_GATE03_GTFSM_SHIFT 0 |
| #define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK) |
| /* GATE04 Bit Fields */ |
| #define SEMA4_GATE04_GTFSM_MASK 0x3u |
| #define SEMA4_GATE04_GTFSM_SHIFT 0 |
| #define SEMA4_GATE04_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE04_GTFSM_SHIFT))&SEMA4_GATE04_GTFSM_MASK) |
| /* GATE05 Bit Fields */ |
| #define SEMA4_GATE05_GTFSM_MASK 0x3u |
| #define SEMA4_GATE05_GTFSM_SHIFT 0 |
| #define SEMA4_GATE05_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK) |
| /* GATE06 Bit Fields */ |
| #define SEMA4_GATE06_GTFSM_MASK 0x3u |
| #define SEMA4_GATE06_GTFSM_SHIFT 0 |
| #define SEMA4_GATE06_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK) |
| /* GATE07 Bit Fields */ |
| #define SEMA4_GATE07_GTFSM_MASK 0x3u |
| #define SEMA4_GATE07_GTFSM_SHIFT 0 |
| #define SEMA4_GATE07_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK) |
| /* GATE08 Bit Fields */ |
| #define SEMA4_GATE08_GTFSM_MASK 0x3u |
| #define SEMA4_GATE08_GTFSM_SHIFT 0 |
| #define SEMA4_GATE08_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE08_GTFSM_SHIFT))&SEMA4_GATE08_GTFSM_MASK) |
| /* GATE09 Bit Fields */ |
| #define SEMA4_GATE09_GTFSM_MASK 0x3u |
| #define SEMA4_GATE09_GTFSM_SHIFT 0 |
| #define SEMA4_GATE09_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK) |
| /* GATE10 Bit Fields */ |
| #define SEMA4_GATE10_GTFSM_MASK 0x3u |
| #define SEMA4_GATE10_GTFSM_SHIFT 0 |
| #define SEMA4_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK) |
| /* GATE11 Bit Fields */ |
| #define SEMA4_GATE11_GTFSM_MASK 0x3u |
| #define SEMA4_GATE11_GTFSM_SHIFT 0 |
| #define SEMA4_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK) |
| /* GATE12 Bit Fields */ |
| #define SEMA4_GATE12_GTFSM_MASK 0x3u |
| #define SEMA4_GATE12_GTFSM_SHIFT 0 |
| #define SEMA4_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE12_GTFSM_SHIFT))&SEMA4_GATE12_GTFSM_MASK) |
| /* GATE13 Bit Fields */ |
| #define SEMA4_GATE13_GTFSM_MASK 0x3u |
| #define SEMA4_GATE13_GTFSM_SHIFT 0 |
| #define SEMA4_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK) |
| /* GATE14 Bit Fields */ |
| #define SEMA4_GATE14_GTFSM_MASK 0x3u |
| #define SEMA4_GATE14_GTFSM_SHIFT 0 |
| #define SEMA4_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK) |
| /* GATE15 Bit Fields */ |
| #define SEMA4_GATE15_GTFSM_MASK 0x3u |
| #define SEMA4_GATE15_GTFSM_SHIFT 0 |
| #define SEMA4_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK) |
| /* CPINE Bit Fields */ |
| #define SEMA4_CPINE_INE7_MASK 0x1u |
| #define SEMA4_CPINE_INE7_SHIFT 0 |
| #define SEMA4_CPINE_INE6_MASK 0x2u |
| #define SEMA4_CPINE_INE6_SHIFT 1 |
| #define SEMA4_CPINE_INE5_MASK 0x4u |
| #define SEMA4_CPINE_INE5_SHIFT 2 |
| #define SEMA4_CPINE_INE4_MASK 0x8u |
| #define SEMA4_CPINE_INE4_SHIFT 3 |
| #define SEMA4_CPINE_INE3_MASK 0x10u |
| #define SEMA4_CPINE_INE3_SHIFT 4 |
| #define SEMA4_CPINE_INE2_MASK 0x20u |
| #define SEMA4_CPINE_INE2_SHIFT 5 |
| #define SEMA4_CPINE_INE1_MASK 0x40u |
| #define SEMA4_CPINE_INE1_SHIFT 6 |
| #define SEMA4_CPINE_INE0_MASK 0x80u |
| #define SEMA4_CPINE_INE0_SHIFT 7 |
| #define SEMA4_CPINE_INE15_MASK 0x100u |
| #define SEMA4_CPINE_INE15_SHIFT 8 |
| #define SEMA4_CPINE_INE14_MASK 0x200u |
| #define SEMA4_CPINE_INE14_SHIFT 9 |
| #define SEMA4_CPINE_INE13_MASK 0x400u |
| #define SEMA4_CPINE_INE13_SHIFT 10 |
| #define SEMA4_CPINE_INE12_MASK 0x800u |
| #define SEMA4_CPINE_INE12_SHIFT 11 |
| #define SEMA4_CPINE_INE11_MASK 0x1000u |
| #define SEMA4_CPINE_INE11_SHIFT 12 |
| #define SEMA4_CPINE_INE10_MASK 0x2000u |
| #define SEMA4_CPINE_INE10_SHIFT 13 |
| #define SEMA4_CPINE_INE9_MASK 0x4000u |
| #define SEMA4_CPINE_INE9_SHIFT 14 |
| #define SEMA4_CPINE_INE8_MASK 0x8000u |
| #define SEMA4_CPINE_INE8_SHIFT 15 |
| /* CPNTF Bit Fields */ |
| #define SEMA4_CPNTF_GN7_MASK 0x1u |
| #define SEMA4_CPNTF_GN7_SHIFT 0 |
| #define SEMA4_CPNTF_GN6_MASK 0x2u |
| #define SEMA4_CPNTF_GN6_SHIFT 1 |
| #define SEMA4_CPNTF_GN5_MASK 0x4u |
| #define SEMA4_CPNTF_GN5_SHIFT 2 |
| #define SEMA4_CPNTF_GN4_MASK 0x8u |
| #define SEMA4_CPNTF_GN4_SHIFT 3 |
| #define SEMA4_CPNTF_GN3_MASK 0x10u |
| #define SEMA4_CPNTF_GN3_SHIFT 4 |
| #define SEMA4_CPNTF_GN2_MASK 0x20u |
| #define SEMA4_CPNTF_GN2_SHIFT 5 |
| #define SEMA4_CPNTF_GN1_MASK 0x40u |
| #define SEMA4_CPNTF_GN1_SHIFT 6 |
| #define SEMA4_CPNTF_GN0_MASK 0x80u |
| #define SEMA4_CPNTF_GN0_SHIFT 7 |
| #define SEMA4_CPNTF_GN15_MASK 0x100u |
| #define SEMA4_CPNTF_GN15_SHIFT 8 |
| #define SEMA4_CPNTF_GN14_MASK 0x200u |
| #define SEMA4_CPNTF_GN14_SHIFT 9 |
| #define SEMA4_CPNTF_GN13_MASK 0x400u |
| #define SEMA4_CPNTF_GN13_SHIFT 10 |
| #define SEMA4_CPNTF_GN12_MASK 0x800u |
| #define SEMA4_CPNTF_GN12_SHIFT 11 |
| #define SEMA4_CPNTF_GN11_MASK 0x1000u |
| #define SEMA4_CPNTF_GN11_SHIFT 12 |
| #define SEMA4_CPNTF_GN10_MASK 0x2000u |
| #define SEMA4_CPNTF_GN10_SHIFT 13 |
| #define SEMA4_CPNTF_GN9_MASK 0x4000u |
| #define SEMA4_CPNTF_GN9_SHIFT 14 |
| #define SEMA4_CPNTF_GN8_MASK 0x8000u |
| #define SEMA4_CPNTF_GN8_SHIFT 15 |
| /* RSTGT Bit Fields */ |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK 0xFFu |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT 0 |
| #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT))&SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) |
| #define SEMA4_RSTGT_RSTGTN_MASK 0xFF00u |
| #define SEMA4_RSTGT_RSTGTN_SHIFT 8 |
| #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGTN_SHIFT))&SEMA4_RSTGT_RSTGTN_MASK) |
| /* RSTNTF Bit Fields */ |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK 0xFFu |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT 0 |
| #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT))&SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) |
| #define SEMA4_RSTNTF_RSTNTN_MASK 0xFF00u |
| #define SEMA4_RSTNTF_RSTNTN_SHIFT 8 |
| #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNTN_SHIFT))&SEMA4_RSTNTF_RSTNTN_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Register_Masks */ |
| |
| /* SEMA4 - Peripheral instance base addresses */ |
| /** Peripheral SEMA4 base address */ |
| #define SEMA4_BASE (0x42290000u) |
| /** Peripheral SEMA4 base pointer */ |
| #define SEMA4 ((SEMA4_Type *)SEMA4_BASE) |
| #define SEMA4_BASE_PTR (SEMA4) |
| /** Array initializer of SEMA4 peripheral base addresses */ |
| #define SEMA4_BASE_ADDRS { SEMA4_BASE } |
| /** Array initializer of SEMA4 peripheral base pointers */ |
| #define SEMA4_BASE_PTRS { SEMA4 } |
| /** Interrupt vectors for the SEMA4 peripheral type */ |
| #define SEMA4_IRQS { SEMA4_CP1_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SEMA4 - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros |
| * @{ |
| */ |
| |
| /* SEMA4 - Register instance definitions */ |
| /* SEMA4 */ |
| #define SEMA4_GATE00 SEMA4_GATE00_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE01 SEMA4_GATE01_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE02 SEMA4_GATE02_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE03 SEMA4_GATE03_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE04 SEMA4_GATE04_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE05 SEMA4_GATE05_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE06 SEMA4_GATE06_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE07 SEMA4_GATE07_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE08 SEMA4_GATE08_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE09 SEMA4_GATE09_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE10 SEMA4_GATE10_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE11 SEMA4_GATE11_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE12 SEMA4_GATE12_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE13 SEMA4_GATE13_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE14 SEMA4_GATE14_REG(SEMA4_BASE_PTR) |
| #define SEMA4_GATE15 SEMA4_GATE15_REG(SEMA4_BASE_PTR) |
| #define SEMA4_CP0INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,0) |
| #define SEMA4_CP1INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,1) |
| #define SEMA4_CP0NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,0) |
| #define SEMA4_CP1NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,1) |
| #define SEMA4_RSTGT SEMA4_RSTGT_REG(SEMA4_BASE_PTR) |
| #define SEMA4_RSTNTF SEMA4_RSTNTF_REG(SEMA4_BASE_PTR) |
| /* SEMA4 - Register array accessors */ |
| #define SEMA4_CPINE(index) SEMA4_CPINE_REG(SEMA4_BASE_PTR,index) |
| #define SEMA4_CPNTF(index) SEMA4_CPNTF_REG(SEMA4_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SEMA4_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SJC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SJC_Peripheral_Access_Layer SJC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SJC - Register Layout Typedef */ |
| typedef struct { |
| union { /* offset: 0x0 */ |
| __I uint32_t GPUSR1; /**< General Purpose Unsecured Status Register 1,offset: 0x0 */ |
| struct { /* offset: 0x1 */ |
| uint8_t RESERVED_0[1]; |
| __I uint32_t GPUSR2; /**< General Purpose Unsecured Status Register 2,offset: 0x1 */ |
| } GPUSR2; |
| struct { /* offset: 0x2 */ |
| uint8_t RESERVED_0[2]; |
| __I uint32_t GPUSR3; /**< General Purpose Unsecured Status Register 3,offset: 0x2 */ |
| } GPUSR3; |
| struct { /* offset: 0x3 */ |
| uint8_t RESERVED_0[3]; |
| __I uint32_t GPSSR; /**< General Purpose Secured Status Register,offset: 0x3 */ |
| } GPSSR; |
| struct { /* offset: 0x4 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t DCR; /**< Debug Control Register,offset: 0x4 */ |
| } DCR; |
| struct { /* offset: 0x5 */ |
| uint8_t RESERVED_0[5]; |
| __I uint32_t SSR; /**< Security Status Register,offset: 0x5 */ |
| } SSR; |
| struct { /* offset: 0x7 */ |
| uint8_t RESERVED_0[7]; |
| __IO uint32_t GPCCR; /**< General Purpose Clocks Control Register,offset: 0x7 */ |
| } GPCCR; |
| }; |
| } SJC_Type, *SJC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SJC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros |
| * @{ |
| */ |
| |
| /* SJC - Register accessors */ |
| #define SJC_GPUSR1_REG(base) ((base)->GPUSR1) |
| #define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) |
| #define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) |
| #define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) |
| #define SJC_DCR_REG(base) ((base)->DCR.DCR) |
| #define SJC_SSR_REG(base) ((base)->SSR.SSR) |
| #define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) |
| |
| /*! |
| * @} |
| */ /* end of group SJC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SJC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SJC_Register_Masks SJC Register Masks |
| * @{ |
| */ |
| |
| /* GPUSR1 Bit Fields */ |
| #define SJC_GPUSR1_A_DBG_MASK 0x1u |
| #define SJC_GPUSR1_A_DBG_SHIFT 0 |
| #define SJC_GPUSR1_A_WFI_MASK 0x2u |
| #define SJC_GPUSR1_A_WFI_SHIFT 1 |
| #define SJC_GPUSR1_S_STAT_MASK 0x1Cu |
| #define SJC_GPUSR1_S_STAT_SHIFT 2 |
| #define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR1_S_STAT_SHIFT))&SJC_GPUSR1_S_STAT_MASK) |
| #define SJC_GPUSR1_PLL_LOCK_MASK 0x100u |
| #define SJC_GPUSR1_PLL_LOCK_SHIFT 8 |
| /* GPUSR2 Bit Fields */ |
| #define SJC_GPUSR2_STBYWFI_MASK 0xFu |
| #define SJC_GPUSR2_STBYWFI_SHIFT 0 |
| #define SJC_GPUSR2_STBYWFI(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFI_SHIFT))&SJC_GPUSR2_STBYWFI_MASK) |
| #define SJC_GPUSR2_S_STAT_MASK 0xF0u |
| #define SJC_GPUSR2_S_STAT_SHIFT 4 |
| #define SJC_GPUSR2_S_STAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_S_STAT_SHIFT))&SJC_GPUSR2_S_STAT_MASK) |
| #define SJC_GPUSR2_STBYWFE_MASK 0xF00u |
| #define SJC_GPUSR2_STBYWFE_SHIFT 8 |
| #define SJC_GPUSR2_STBYWFE(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFE_SHIFT))&SJC_GPUSR2_STBYWFE_MASK) |
| /* GPUSR3 Bit Fields */ |
| #define SJC_GPUSR3_IPG_WAIT_MASK 0x1u |
| #define SJC_GPUSR3_IPG_WAIT_SHIFT 0 |
| #define SJC_GPUSR3_IPG_STOP_MASK 0x2u |
| #define SJC_GPUSR3_IPG_STOP_SHIFT 1 |
| #define SJC_GPUSR3_SYS_WAIT_MASK 0x4u |
| #define SJC_GPUSR3_SYS_WAIT_SHIFT 2 |
| /* GPSSR Bit Fields */ |
| #define SJC_GPSSR_GPSSR_MASK 0xFFFFFFFFu |
| #define SJC_GPSSR_GPSSR_SHIFT 0 |
| #define SJC_GPSSR_GPSSR(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK) |
| /* DCR Bit Fields */ |
| #define SJC_DCR_DE_TO_ARM_MASK 0x1u |
| #define SJC_DCR_DE_TO_ARM_SHIFT 0 |
| #define SJC_DCR_DE_TO_SDMA_MASK 0x2u |
| #define SJC_DCR_DE_TO_SDMA_SHIFT 1 |
| #define SJC_DCR_DEBUG_OBS_MASK 0x8u |
| #define SJC_DCR_DEBUG_OBS_SHIFT 3 |
| #define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK 0x20u |
| #define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT 5 |
| #define SJC_DCR_DIRECT_ARM_REQ_EN_MASK 0x40u |
| #define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT 6 |
| /* SSR Bit Fields */ |
| #define SJC_SSR_KTF_MASK 0x1u |
| #define SJC_SSR_KTF_SHIFT 0 |
| #define SJC_SSR_KTA_MASK 0x2u |
| #define SJC_SSR_KTA_SHIFT 1 |
| #define SJC_SSR_SWF_MASK 0x4u |
| #define SJC_SSR_SWF_SHIFT 2 |
| #define SJC_SSR_SWE_MASK 0x8u |
| #define SJC_SSR_SWE_SHIFT 3 |
| #define SJC_SSR_EBF_MASK 0x10u |
| #define SJC_SSR_EBF_SHIFT 4 |
| #define SJC_SSR_EBG_MASK 0x20u |
| #define SJC_SSR_EBG_SHIFT 5 |
| #define SJC_SSR_FT_MASK 0x100u |
| #define SJC_SSR_FT_SHIFT 8 |
| #define SJC_SSR_SJM_MASK 0x600u |
| #define SJC_SSR_SJM_SHIFT 9 |
| #define SJC_SSR_SJM(x) (((uint32_t)(((uint32_t)(x))<<SJC_SSR_SJM_SHIFT))&SJC_SSR_SJM_MASK) |
| #define SJC_SSR_RSSTAT_MASK 0x1800u |
| #define SJC_SSR_RSSTAT_SHIFT 11 |
| #define SJC_SSR_RSSTAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_SSR_RSSTAT_SHIFT))&SJC_SSR_RSSTAT_MASK) |
| #define SJC_SSR_BOOTIND_MASK 0x4000u |
| #define SJC_SSR_BOOTIND_SHIFT 14 |
| /* GPCCR Bit Fields */ |
| #define SJC_GPCCR_SCLKR_MASK 0x1u |
| #define SJC_GPCCR_SCLKR_SHIFT 0 |
| #define SJC_GPCCR_ACLKOFFDIS_MASK 0x2u |
| #define SJC_GPCCR_ACLKOFFDIS_SHIFT 1 |
| |
| /*! |
| * @} |
| */ /* end of group SJC_Register_Masks */ |
| |
| /* SJC - Peripheral instance base addresses */ |
| /** Peripheral SJC base address */ |
| #define SJC_BASE (0x40u) |
| /** Peripheral SJC base pointer */ |
| #define SJC ((SJC_Type *)SJC_BASE) |
| #define SJC_BASE_PTR (SJC) |
| /** Array initializer of SJC peripheral base addresses */ |
| #define SJC_BASE_ADDRS { SJC_BASE } |
| /** Array initializer of SJC peripheral base pointers */ |
| #define SJC_BASE_PTRS { SJC } |
| /** Interrupt vectors for the SJC peripheral type */ |
| #define SJC_IRQS { SJC_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SJC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros |
| * @{ |
| */ |
| |
| /* SJC - Register instance definitions */ |
| /* SJC */ |
| #define SJC_GPUSR1 SJC_GPUSR1_REG(SJC_BASE_PTR) |
| #define SJC_GPUSR2 SJC_GPUSR2_REG(SJC_BASE_PTR) |
| #define SJC_GPUSR3 SJC_GPUSR3_REG(SJC_BASE_PTR) |
| #define SJC_GPSSR SJC_GPSSR_REG(SJC_BASE_PTR) |
| #define SJC_DCR SJC_DCR_REG(SJC_BASE_PTR) |
| #define SJC_SSR SJC_SSR_REG(SJC_BASE_PTR) |
| #define SJC_GPCCR SJC_GPCCR_REG(SJC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SJC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SJC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SNVS - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t HPLR; /**< , offset: 0x0 */ |
| __IO uint32_t HPCOMR; /**< , offset: 0x4 */ |
| __IO uint32_t HPCR; /**< , offset: 0x8 */ |
| uint8_t RESERVED_0[8]; |
| __IO uint32_t HPSR; /**< , offset: 0x14 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t HPRTCMR; /**< , offset: 0x24 */ |
| __IO uint32_t HPRTCLR; /**< , offset: 0x28 */ |
| __IO uint32_t HPTAMR; /**< , offset: 0x2C */ |
| __IO uint32_t HPTALR; /**< , offset: 0x30 */ |
| __IO uint32_t LPLR; /**< , offset: 0x34 */ |
| __IO uint32_t LPCR; /**< , offset: 0x38 */ |
| uint8_t RESERVED_2[16]; |
| __IO uint32_t LPSR; /**< , offset: 0x4C */ |
| uint8_t RESERVED_3[12]; |
| __IO uint32_t LPSMCMR; /**< , offset: 0x5C */ |
| __IO uint32_t LPSMCLR; /**< , offset: 0x60 */ |
| uint8_t RESERVED_4[4]; |
| __IO uint32_t LPGPR; /**< , offset: 0x68 */ |
| uint8_t RESERVED_5[2956]; |
| __I uint32_t HPVIDR1; /**< , offset: 0xBF8 */ |
| __I uint32_t HPVIDR2; /**< , offset: 0xBFC */ |
| } SNVS_Type, *SNVS_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros |
| * @{ |
| */ |
| |
| /* SNVS - Register accessors */ |
| #define SNVS_HPLR_REG(base) ((base)->HPLR) |
| #define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) |
| #define SNVS_HPCR_REG(base) ((base)->HPCR) |
| #define SNVS_HPSR_REG(base) ((base)->HPSR) |
| #define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) |
| #define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) |
| #define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) |
| #define SNVS_HPTALR_REG(base) ((base)->HPTALR) |
| #define SNVS_LPLR_REG(base) ((base)->LPLR) |
| #define SNVS_LPCR_REG(base) ((base)->LPCR) |
| #define SNVS_LPSR_REG(base) ((base)->LPSR) |
| #define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) |
| #define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) |
| #define SNVS_LPGPR_REG(base) ((base)->LPGPR) |
| #define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) |
| #define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Register_Masks SNVS Register Masks |
| * @{ |
| */ |
| |
| /* HPLR Bit Fields */ |
| #define SNVS_HPLR_MC_SL_MASK 0x10u |
| #define SNVS_HPLR_MC_SL_SHIFT 4 |
| #define SNVS_HPLR_GPR_SL_MASK 0x20u |
| #define SNVS_HPLR_GPR_SL_SHIFT 5 |
| /* HPCOMR Bit Fields */ |
| #define SNVS_HPCOMR_LP_SWR_MASK 0x10u |
| #define SNVS_HPCOMR_LP_SWR_SHIFT 4 |
| #define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u |
| #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 |
| #define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u |
| #define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 |
| /* HPCR Bit Fields */ |
| #define SNVS_HPCR_RTC_EN_MASK 0x1u |
| #define SNVS_HPCR_RTC_EN_SHIFT 0 |
| #define SNVS_HPCR_HPTA_EN_MASK 0x2u |
| #define SNVS_HPCR_HPTA_EN_SHIFT 1 |
| #define SNVS_HPCR_PI_EN_MASK 0x8u |
| #define SNVS_HPCR_PI_EN_SHIFT 3 |
| #define SNVS_HPCR_PI_FREQ_MASK 0xF0u |
| #define SNVS_HPCR_PI_FREQ_SHIFT 4 |
| #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_PI_FREQ_SHIFT))&SNVS_HPCR_PI_FREQ_MASK) |
| #define SNVS_HPCR_HPCALB_EN_MASK 0x100u |
| #define SNVS_HPCR_HPCALB_EN_SHIFT 8 |
| #define SNVS_HPCR_HPCALB_VAL_MASK 0x7C00u |
| #define SNVS_HPCR_HPCALB_VAL_SHIFT 10 |
| #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_HPCALB_VAL_SHIFT))&SNVS_HPCR_HPCALB_VAL_MASK) |
| #define SNVS_HPCR_BTN_CONFIG_MASK 0x7000000u |
| #define SNVS_HPCR_BTN_CONFIG_SHIFT 24 |
| #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_BTN_CONFIG_SHIFT))&SNVS_HPCR_BTN_CONFIG_MASK) |
| #define SNVS_HPCR_BTN_MASK_MASK 0x8000000u |
| #define SNVS_HPCR_BTN_MASK_SHIFT 27 |
| /* HPSR Bit Fields */ |
| #define SNVS_HPSR_BTN_MASK 0x40u |
| #define SNVS_HPSR_BTN_SHIFT 6 |
| #define SNVS_HPSR_BI_MASK 0x80u |
| #define SNVS_HPSR_BI_SHIFT 7 |
| /* HPRTCMR Bit Fields */ |
| #define SNVS_HPRTCMR_RTC_MASK 0xFFFFFFFFu |
| #define SNVS_HPRTCMR_RTC_SHIFT 0 |
| #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCMR_RTC_SHIFT))&SNVS_HPRTCMR_RTC_MASK) |
| /* HPRTCLR Bit Fields */ |
| #define SNVS_HPRTCLR_RTC_MASK 0xFFFFFFFFu |
| #define SNVS_HPRTCLR_RTC_SHIFT 0 |
| #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCLR_RTC_SHIFT))&SNVS_HPRTCLR_RTC_MASK) |
| /* HPTAMR Bit Fields */ |
| #define SNVS_HPTAMR_HPTA_MASK 0x7FFFu |
| #define SNVS_HPTAMR_HPTA_SHIFT 0 |
| #define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPTAMR_HPTA_SHIFT))&SNVS_HPTAMR_HPTA_MASK) |
| /* HPTALR Bit Fields */ |
| #define SNVS_HPTALR_HPTA_MASK 0xFFFFFFFFu |
| #define SNVS_HPTALR_HPTA_SHIFT 0 |
| #define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPTALR_HPTA_SHIFT))&SNVS_HPTALR_HPTA_MASK) |
| /* LPLR Bit Fields */ |
| #define SNVS_LPLR_MC_HL_MASK 0x10u |
| #define SNVS_LPLR_MC_HL_SHIFT 4 |
| #define SNVS_LPLR_GPR_HL_MASK 0x20u |
| #define SNVS_LPLR_GPR_HL_SHIFT 5 |
| /* LPCR Bit Fields */ |
| #define SNVS_LPCR_MC_ENV_MASK 0x4u |
| #define SNVS_LPCR_MC_ENV_SHIFT 2 |
| #define SNVS_LPCR_DP_EN_MASK 0x20u |
| #define SNVS_LPCR_DP_EN_SHIFT 5 |
| #define SNVS_LPCR_TOP_MASK 0x40u |
| #define SNVS_LPCR_TOP_SHIFT 6 |
| #define SNVS_LPCR_PWR_GLITCH_EN_MASK 0x80u |
| #define SNVS_LPCR_PWR_GLITCH_EN_SHIFT 7 |
| #define SNVS_LPCR_BTN_PRESS_TIME_MASK 0x30000u |
| #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT 16 |
| #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_BTN_PRESS_TIME_SHIFT))&SNVS_LPCR_BTN_PRESS_TIME_MASK) |
| #define SNVS_LPCR_DEBOUNCE_MASK 0xC0000u |
| #define SNVS_LPCR_DEBOUNCE_SHIFT 18 |
| #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_DEBOUNCE_SHIFT))&SNVS_LPCR_DEBOUNCE_MASK) |
| #define SNVS_LPCR_ON_TIME_MASK 0x300000u |
| #define SNVS_LPCR_ON_TIME_SHIFT 20 |
| #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_ON_TIME_SHIFT))&SNVS_LPCR_ON_TIME_MASK) |
| #define SNVS_LPCR_PK_EN_MASK 0x400000u |
| #define SNVS_LPCR_PK_EN_SHIFT 22 |
| #define SNVS_LPCR_PK_OVERRIDE_MASK 0x800000u |
| #define SNVS_LPCR_PK_OVERRIDE_SHIFT 23 |
| /* LPSR Bit Fields */ |
| #define SNVS_LPSR_MCR_MASK 0x4u |
| #define SNVS_LPSR_MCR_SHIFT 2 |
| #define SNVS_LPSR_EO_MASK 0x20000u |
| #define SNVS_LPSR_EO_SHIFT 17 |
| #define SNVS_LPSR_SPO_MASK 0x40000u |
| #define SNVS_LPSR_SPO_SHIFT 18 |
| /* LPSMCMR Bit Fields */ |
| #define SNVS_LPSMCMR_MON_COUNTER_MASK 0xFFFFu |
| #define SNVS_LPSMCMR_MON_COUNTER_SHIFT 0 |
| #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MON_COUNTER_SHIFT))&SNVS_LPSMCMR_MON_COUNTER_MASK) |
| #define SNVS_LPSMCMR_MC_ERA_BITS_MASK 0xFFFF0000u |
| #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT 16 |
| #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MC_ERA_BITS_SHIFT))&SNVS_LPSMCMR_MC_ERA_BITS_MASK) |
| /* LPSMCLR Bit Fields */ |
| #define SNVS_LPSMCLR_MON_COUNTER_MASK 0xFFFFFFFFu |
| #define SNVS_LPSMCLR_MON_COUNTER_SHIFT 0 |
| #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCLR_MON_COUNTER_SHIFT))&SNVS_LPSMCLR_MON_COUNTER_MASK) |
| /* LPGPR Bit Fields */ |
| #define SNVS_LPGPR_GPR_MASK 0xFFFFFFFFu |
| #define SNVS_LPGPR_GPR_SHIFT 0 |
| #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPGPR_GPR_SHIFT))&SNVS_LPGPR_GPR_MASK) |
| /* HPVIDR1 Bit Fields */ |
| #define SNVS_HPVIDR1_MINOR_REV_MASK 0xFFu |
| #define SNVS_HPVIDR1_MINOR_REV_SHIFT 0 |
| #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MINOR_REV_SHIFT))&SNVS_HPVIDR1_MINOR_REV_MASK) |
| #define SNVS_HPVIDR1_MAJOR_REV_MASK 0xFF00u |
| #define SNVS_HPVIDR1_MAJOR_REV_SHIFT 8 |
| #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MAJOR_REV_SHIFT))&SNVS_HPVIDR1_MAJOR_REV_MASK) |
| #define SNVS_HPVIDR1_IP_ID_MASK 0xFFFF0000u |
| #define SNVS_HPVIDR1_IP_ID_SHIFT 16 |
| #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_IP_ID_SHIFT))&SNVS_HPVIDR1_IP_ID_MASK) |
| /* HPVIDR2 Bit Fields */ |
| #define SNVS_HPVIDR2_CONFIG_OPT_MASK 0xFFu |
| #define SNVS_HPVIDR2_CONFIG_OPT_SHIFT 0 |
| #define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_CONFIG_OPT_SHIFT))&SNVS_HPVIDR2_CONFIG_OPT_MASK) |
| #define SNVS_HPVIDR2_ECO_REV_MASK 0xFF00u |
| #define SNVS_HPVIDR2_ECO_REV_SHIFT 8 |
| #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_ECO_REV_SHIFT))&SNVS_HPVIDR2_ECO_REV_MASK) |
| #define SNVS_HPVIDR2_INTG_OPT_MASK 0xFF0000u |
| #define SNVS_HPVIDR2_INTG_OPT_SHIFT 16 |
| #define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_INTG_OPT_SHIFT))&SNVS_HPVIDR2_INTG_OPT_MASK) |
| #define SNVS_HPVIDR2_IP_ERA_MASK 0xFF000000u |
| #define SNVS_HPVIDR2_IP_ERA_SHIFT 24 |
| #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_IP_ERA_SHIFT))&SNVS_HPVIDR2_IP_ERA_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Register_Masks */ |
| |
| /* SNVS - Peripheral instance base addresses */ |
| /** Peripheral SNVS base address */ |
| #define SNVS_BASE (0x420CC000u) |
| /** Peripheral SNVS base pointer */ |
| #define SNVS ((SNVS_Type *)SNVS_BASE) |
| #define SNVS_BASE_PTR (SNVS) |
| /** Array initializer of SNVS peripheral base addresses */ |
| #define SNVS_BASE_ADDRS { SNVS_BASE } |
| /** Array initializer of SNVS peripheral base pointers */ |
| #define SNVS_BASE_PTRS { SNVS } |
| /** Interrupt vectors for the SNVS peripheral type */ |
| #define SNVS_IRQS { SNVS_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SNVS - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros |
| * @{ |
| */ |
| |
| /* SNVS - Register instance definitions */ |
| /* SNVS */ |
| #define SNVS_HPLR SNVS_HPLR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPCOMR SNVS_HPCOMR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPCR SNVS_HPCR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPSR SNVS_HPSR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPRTCMR SNVS_HPRTCMR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPRTCLR SNVS_HPRTCLR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPTAMR SNVS_HPTAMR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPTALR SNVS_HPTALR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPLR SNVS_LPLR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPCR SNVS_LPCR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPSR SNVS_LPSR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPSMCMR SNVS_LPSMCMR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPSMCLR SNVS_LPSMCLR_REG(SNVS_BASE_PTR) |
| #define SNVS_LPGPR SNVS_LPGPR_REG(SNVS_BASE_PTR) |
| #define SNVS_HPVIDR1 SNVS_HPVIDR1_REG(SNVS_BASE_PTR) |
| #define SNVS_HPVIDR2 SNVS_HPVIDR2_REG(SNVS_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SNVS_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SPBA - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ |
| } SPBA_Type, *SPBA_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros |
| * @{ |
| */ |
| |
| /* SPBA - Register accessors */ |
| #define SPBA_PRR_REG(base,index) ((base)->PRR[index]) |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Register_Masks SPBA Register Masks |
| * @{ |
| */ |
| |
| /* PRR Bit Fields */ |
| #define SPBA_PRR_RARA_MASK 0x1u |
| #define SPBA_PRR_RARA_SHIFT 0 |
| #define SPBA_PRR_RARB_MASK 0x2u |
| #define SPBA_PRR_RARB_SHIFT 1 |
| #define SPBA_PRR_RARC_MASK 0x4u |
| #define SPBA_PRR_RARC_SHIFT 2 |
| #define SPBA_PRR_ROI_MASK 0x30000u |
| #define SPBA_PRR_ROI_SHIFT 16 |
| #define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_ROI_SHIFT))&SPBA_PRR_ROI_MASK) |
| #define SPBA_PRR_RMO_MASK 0xC0000000u |
| #define SPBA_PRR_RMO_SHIFT 30 |
| #define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_RMO_SHIFT))&SPBA_PRR_RMO_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Register_Masks */ |
| |
| /* SPBA - Peripheral instance base addresses */ |
| /** Peripheral SPBA base address */ |
| #define SPBA_BASE (0x40u) |
| /** Peripheral SPBA base pointer */ |
| #define SPBA ((SPBA_Type *)SPBA_BASE) |
| #define SPBA_BASE_PTR (SPBA) |
| /** Array initializer of SPBA peripheral base addresses */ |
| #define SPBA_BASE_ADDRS { SPBA_BASE } |
| /** Array initializer of SPBA peripheral base pointers */ |
| #define SPBA_BASE_PTRS { SPBA } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPBA - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros |
| * @{ |
| */ |
| |
| /* SPBA - Register instance definitions */ |
| /* SPBA */ |
| #define SPBA_PRR0 SPBA_PRR_REG(SPBA_BASE_PTR,0) |
| #define SPBA_PRR1 SPBA_PRR_REG(SPBA_BASE_PTR,1) |
| #define SPBA_PRR2 SPBA_PRR_REG(SPBA_BASE_PTR,2) |
| #define SPBA_PRR3 SPBA_PRR_REG(SPBA_BASE_PTR,3) |
| #define SPBA_PRR4 SPBA_PRR_REG(SPBA_BASE_PTR,4) |
| #define SPBA_PRR5 SPBA_PRR_REG(SPBA_BASE_PTR,5) |
| #define SPBA_PRR6 SPBA_PRR_REG(SPBA_BASE_PTR,6) |
| #define SPBA_PRR7 SPBA_PRR_REG(SPBA_BASE_PTR,7) |
| #define SPBA_PRR8 SPBA_PRR_REG(SPBA_BASE_PTR,8) |
| #define SPBA_PRR9 SPBA_PRR_REG(SPBA_BASE_PTR,9) |
| #define SPBA_PRR10 SPBA_PRR_REG(SPBA_BASE_PTR,10) |
| #define SPBA_PRR11 SPBA_PRR_REG(SPBA_BASE_PTR,11) |
| #define SPBA_PRR12 SPBA_PRR_REG(SPBA_BASE_PTR,12) |
| #define SPBA_PRR13 SPBA_PRR_REG(SPBA_BASE_PTR,13) |
| #define SPBA_PRR14 SPBA_PRR_REG(SPBA_BASE_PTR,14) |
| #define SPBA_PRR15 SPBA_PRR_REG(SPBA_BASE_PTR,15) |
| #define SPBA_PRR16 SPBA_PRR_REG(SPBA_BASE_PTR,16) |
| #define SPBA_PRR17 SPBA_PRR_REG(SPBA_BASE_PTR,17) |
| #define SPBA_PRR18 SPBA_PRR_REG(SPBA_BASE_PTR,18) |
| #define SPBA_PRR19 SPBA_PRR_REG(SPBA_BASE_PTR,19) |
| #define SPBA_PRR20 SPBA_PRR_REG(SPBA_BASE_PTR,20) |
| #define SPBA_PRR21 SPBA_PRR_REG(SPBA_BASE_PTR,21) |
| #define SPBA_PRR22 SPBA_PRR_REG(SPBA_BASE_PTR,22) |
| #define SPBA_PRR23 SPBA_PRR_REG(SPBA_BASE_PTR,23) |
| #define SPBA_PRR24 SPBA_PRR_REG(SPBA_BASE_PTR,24) |
| #define SPBA_PRR25 SPBA_PRR_REG(SPBA_BASE_PTR,25) |
| #define SPBA_PRR26 SPBA_PRR_REG(SPBA_BASE_PTR,26) |
| #define SPBA_PRR27 SPBA_PRR_REG(SPBA_BASE_PTR,27) |
| #define SPBA_PRR28 SPBA_PRR_REG(SPBA_BASE_PTR,28) |
| #define SPBA_PRR29 SPBA_PRR_REG(SPBA_BASE_PTR,29) |
| #define SPBA_PRR30 SPBA_PRR_REG(SPBA_BASE_PTR,30) |
| #define SPBA_PRR31 SPBA_PRR_REG(SPBA_BASE_PTR,31) |
| /* SPBA - Register array accessors */ |
| #define SPBA_PRR(index) SPBA_PRR_REG(SPBA_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SPBA_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SPDIF - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ |
| __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ |
| __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ |
| __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ |
| union { /* offset: 0x10 */ |
| __I uint32_t SIS; /**< InterruptStat Register,offset: 0x10 */ |
| __O uint32_t SIC; /**< InterruptClear Register,offset: 0x10 */ |
| struct { /* offset: 0x14 */ |
| uint8_t RESERVED_0[4]; |
| __I uint32_t SRL; /**< SPDIFRxLeft Register,offset: 0x14 */ |
| } SRL; |
| struct { /* offset: 0x18 */ |
| uint8_t RESERVED_0[8]; |
| __I uint32_t SRR; /**< SPDIFRxRight Register,offset: 0x18 */ |
| } SRR; |
| struct { /* offset: 0x1C */ |
| uint8_t RESERVED_0[12]; |
| __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register,offset: 0x1C */ |
| } SRCSH; |
| struct { /* offset: 0x20 */ |
| uint8_t RESERVED_0[16]; |
| __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register,offset: 0x20 */ |
| } SRCSL; |
| struct { /* offset: 0x24 */ |
| uint8_t RESERVED_0[20]; |
| __I uint32_t SRU; /**< UchannelRx Register,offset: 0x24 */ |
| } SRU; |
| struct { /* offset: 0x28 */ |
| uint8_t RESERVED_0[24]; |
| __I uint32_t SRQ; /**< QchannelRx Register,offset: 0x28 */ |
| } SRQ; |
| struct { /* offset: 0x2C */ |
| uint8_t RESERVED_0[28]; |
| __O uint32_t STL; /**< SPDIFTxLeft Register,offset: 0x2C */ |
| } STL; |
| struct { /* offset: 0x30 */ |
| uint8_t RESERVED_0[32]; |
| __O uint32_t STR; /**< SPDIFTxRight Register,offset: 0x30 */ |
| } STR; |
| struct { /* offset: 0x34 */ |
| uint8_t RESERVED_0[36]; |
| __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register,offset: 0x34 */ |
| } STCSCH; |
| struct { /* offset: 0x38 */ |
| uint8_t RESERVED_0[40]; |
| __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register,offset: 0x38 */ |
| } STCSCL; |
| }; |
| uint8_t RESERVED_0[8]; |
| __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ |
| uint8_t RESERVED_1[8]; |
| __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ |
| } SPDIF_Type, *SPDIF_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Register_Accessor_Macros SPDIF - Register accessor macros |
| * @{ |
| */ |
| |
| /* SPDIF - Register accessors */ |
| #define SPDIF_SCR_REG(base) ((base)->SCR) |
| #define SPDIF_SRCD_REG(base) ((base)->SRCD) |
| #define SPDIF_SRPC_REG(base) ((base)->SRPC) |
| #define SPDIF_SIE_REG(base) ((base)->SIE) |
| #define SPDIF_SIS_REG(base) ((base)->SIS) |
| #define SPDIF_SIC_REG(base) ((base)->SIC) |
| #define SPDIF_SRL_REG(base) ((base)->SRL.SRL) |
| #define SPDIF_SRR_REG(base) ((base)->SRR.SRR) |
| #define SPDIF_SRCSH_REG(base) ((base)->SRCSH.SRCSH) |
| #define SPDIF_SRCSL_REG(base) ((base)->SRCSL.SRCSL) |
| #define SPDIF_SRU_REG(base) ((base)->SRU.SRU) |
| #define SPDIF_SRQ_REG(base) ((base)->SRQ.SRQ) |
| #define SPDIF_STL_REG(base) ((base)->STL.STL) |
| #define SPDIF_STR_REG(base) ((base)->STR.STR) |
| #define SPDIF_STCSCH_REG(base) ((base)->STCSCH.STCSCH) |
| #define SPDIF_STCSCL_REG(base) ((base)->STCSCL.STCSCL) |
| #define SPDIF_SRFM_REG(base) ((base)->SRFM) |
| #define SPDIF_STC_REG(base) ((base)->STC) |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Register_Masks SPDIF Register Masks |
| * @{ |
| */ |
| |
| /* SCR Bit Fields */ |
| #define SPDIF_SCR_USrc_Sel_MASK 0x3u |
| #define SPDIF_SCR_USrc_Sel_SHIFT 0 |
| #define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_USrc_Sel_SHIFT))&SPDIF_SCR_USrc_Sel_MASK) |
| #define SPDIF_SCR_TxSel_MASK 0x1Cu |
| #define SPDIF_SCR_TxSel_SHIFT 2 |
| #define SPDIF_SCR_TxSel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxSel_SHIFT))&SPDIF_SCR_TxSel_MASK) |
| #define SPDIF_SCR_ValCtrl_MASK 0x20u |
| #define SPDIF_SCR_ValCtrl_SHIFT 5 |
| #define SPDIF_SCR_DMA_TX_En_MASK 0x100u |
| #define SPDIF_SCR_DMA_TX_En_SHIFT 8 |
| #define SPDIF_SCR_DMA_Rx_En_MASK 0x200u |
| #define SPDIF_SCR_DMA_Rx_En_SHIFT 9 |
| #define SPDIF_SCR_TxFIFO_Ctrl_MASK 0xC00u |
| #define SPDIF_SCR_TxFIFO_Ctrl_SHIFT 10 |
| #define SPDIF_SCR_TxFIFO_Ctrl(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFO_Ctrl_SHIFT))&SPDIF_SCR_TxFIFO_Ctrl_MASK) |
| #define SPDIF_SCR_soft_reset_MASK 0x1000u |
| #define SPDIF_SCR_soft_reset_SHIFT 12 |
| #define SPDIF_SCR_LOW_POWER_MASK 0x2000u |
| #define SPDIF_SCR_LOW_POWER_SHIFT 13 |
| #define SPDIF_SCR_TxFIFOEmpty_Sel_MASK 0x18000u |
| #define SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT 15 |
| #define SPDIF_SCR_TxFIFOEmpty_Sel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT))&SPDIF_SCR_TxFIFOEmpty_Sel_MASK) |
| #define SPDIF_SCR_TxAutoSync_MASK 0x20000u |
| #define SPDIF_SCR_TxAutoSync_SHIFT 17 |
| #define SPDIF_SCR_RxAutoSync_MASK 0x40000u |
| #define SPDIF_SCR_RxAutoSync_SHIFT 18 |
| #define SPDIF_SCR_RxFIFOFull_Sel_MASK 0x180000u |
| #define SPDIF_SCR_RxFIFOFull_Sel_SHIFT 19 |
| #define SPDIF_SCR_RxFIFOFull_Sel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SCR_RxFIFOFull_Sel_SHIFT))&SPDIF_SCR_RxFIFOFull_Sel_MASK) |
| #define SPDIF_SCR_RxFIFO_Rst_MASK 0x200000u |
| #define SPDIF_SCR_RxFIFO_Rst_SHIFT 21 |
| #define SPDIF_SCR_RxFIFO_Off_On_MASK 0x400000u |
| #define SPDIF_SCR_RxFIFO_Off_On_SHIFT 22 |
| #define SPDIF_SCR_RxFIFO_Ctrl_MASK 0x800000u |
| #define SPDIF_SCR_RxFIFO_Ctrl_SHIFT 23 |
| /* SRCD Bit Fields */ |
| #define SPDIF_SRCD_USyncMode_MASK 0x2u |
| #define SPDIF_SRCD_USyncMode_SHIFT 1 |
| /* SRPC Bit Fields */ |
| #define SPDIF_SRPC_GainSel_MASK 0x38u |
| #define SPDIF_SRPC_GainSel_SHIFT 3 |
| #define SPDIF_SRPC_GainSel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_GainSel_SHIFT))&SPDIF_SRPC_GainSel_MASK) |
| #define SPDIF_SRPC_LOCK_MASK 0x40u |
| #define SPDIF_SRPC_LOCK_SHIFT 6 |
| #define SPDIF_SRPC_ClkSrc_Sel_MASK 0x780u |
| #define SPDIF_SRPC_ClkSrc_Sel_SHIFT 7 |
| #define SPDIF_SRPC_ClkSrc_Sel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRPC_ClkSrc_Sel_SHIFT))&SPDIF_SRPC_ClkSrc_Sel_MASK) |
| /* SIE Bit Fields */ |
| #define SPDIF_SIE_RxFIFOFul_MASK 0x1u |
| #define SPDIF_SIE_RxFIFOFul_SHIFT 0 |
| #define SPDIF_SIE_TxEm_MASK 0x2u |
| #define SPDIF_SIE_TxEm_SHIFT 1 |
| #define SPDIF_SIE_LockLoss_MASK 0x4u |
| #define SPDIF_SIE_LockLoss_SHIFT 2 |
| #define SPDIF_SIE_RxFIFOResyn_MASK 0x8u |
| #define SPDIF_SIE_RxFIFOResyn_SHIFT 3 |
| #define SPDIF_SIE_RxFIFOUnOv_MASK 0x10u |
| #define SPDIF_SIE_RxFIFOUnOv_SHIFT 4 |
| #define SPDIF_SIE_UQErr_MASK 0x20u |
| #define SPDIF_SIE_UQErr_SHIFT 5 |
| #define SPDIF_SIE_UQSync_MASK 0x40u |
| #define SPDIF_SIE_UQSync_SHIFT 6 |
| #define SPDIF_SIE_QRxOv_MASK 0x80u |
| #define SPDIF_SIE_QRxOv_SHIFT 7 |
| #define SPDIF_SIE_QRxFul_MASK 0x100u |
| #define SPDIF_SIE_QRxFul_SHIFT 8 |
| #define SPDIF_SIE_URxOv_MASK 0x200u |
| #define SPDIF_SIE_URxOv_SHIFT 9 |
| #define SPDIF_SIE_URxFul_MASK 0x400u |
| #define SPDIF_SIE_URxFul_SHIFT 10 |
| #define SPDIF_SIE_BitErr_MASK 0x4000u |
| #define SPDIF_SIE_BitErr_SHIFT 14 |
| #define SPDIF_SIE_SymErr_MASK 0x8000u |
| #define SPDIF_SIE_SymErr_SHIFT 15 |
| #define SPDIF_SIE_ValNoGood_MASK 0x10000u |
| #define SPDIF_SIE_ValNoGood_SHIFT 16 |
| #define SPDIF_SIE_CNew_MASK 0x20000u |
| #define SPDIF_SIE_CNew_SHIFT 17 |
| #define SPDIF_SIE_TxResyn_MASK 0x40000u |
| #define SPDIF_SIE_TxResyn_SHIFT 18 |
| #define SPDIF_SIE_TxUnOv_MASK 0x80000u |
| #define SPDIF_SIE_TxUnOv_SHIFT 19 |
| #define SPDIF_SIE_Lock_MASK 0x100000u |
| #define SPDIF_SIE_Lock_SHIFT 20 |
| /* SIS Bit Fields */ |
| #define SPDIF_SIS_RxFIFOFul_MASK 0x1u |
| #define SPDIF_SIS_RxFIFOFul_SHIFT 0 |
| #define SPDIF_SIS_TxEm_MASK 0x2u |
| #define SPDIF_SIS_TxEm_SHIFT 1 |
| #define SPDIF_SIS_LockLoss_MASK 0x4u |
| #define SPDIF_SIS_LockLoss_SHIFT 2 |
| #define SPDIF_SIS_RxFIFOResyn_MASK 0x8u |
| #define SPDIF_SIS_RxFIFOResyn_SHIFT 3 |
| #define SPDIF_SIS_RxFIFOUnOv_MASK 0x10u |
| #define SPDIF_SIS_RxFIFOUnOv_SHIFT 4 |
| #define SPDIF_SIS_UQErr_MASK 0x20u |
| #define SPDIF_SIS_UQErr_SHIFT 5 |
| #define SPDIF_SIS_UQSync_MASK 0x40u |
| #define SPDIF_SIS_UQSync_SHIFT 6 |
| #define SPDIF_SIS_QRxOv_MASK 0x80u |
| #define SPDIF_SIS_QRxOv_SHIFT 7 |
| #define SPDIF_SIS_QRxFul_MASK 0x100u |
| #define SPDIF_SIS_QRxFul_SHIFT 8 |
| #define SPDIF_SIS_URxOv_MASK 0x200u |
| #define SPDIF_SIS_URxOv_SHIFT 9 |
| #define SPDIF_SIS_URxFul_MASK 0x400u |
| #define SPDIF_SIS_URxFul_SHIFT 10 |
| #define SPDIF_SIS_BitErr_MASK 0x4000u |
| #define SPDIF_SIS_BitErr_SHIFT 14 |
| #define SPDIF_SIS_SymErr_MASK 0x8000u |
| #define SPDIF_SIS_SymErr_SHIFT 15 |
| #define SPDIF_SIS_ValNoGood_MASK 0x10000u |
| #define SPDIF_SIS_ValNoGood_SHIFT 16 |
| #define SPDIF_SIS_CNew_MASK 0x20000u |
| #define SPDIF_SIS_CNew_SHIFT 17 |
| #define SPDIF_SIS_TxResyn_MASK 0x40000u |
| #define SPDIF_SIS_TxResyn_SHIFT 18 |
| #define SPDIF_SIS_TxUnOv_MASK 0x80000u |
| #define SPDIF_SIS_TxUnOv_SHIFT 19 |
| #define SPDIF_SIS_Lock_MASK 0x100000u |
| #define SPDIF_SIS_Lock_SHIFT 20 |
| /* SIC Bit Fields */ |
| #define SPDIF_SIC_LockLoss_MASK 0x4u |
| #define SPDIF_SIC_LockLoss_SHIFT 2 |
| #define SPDIF_SIC_RxFIFOResyn_MASK 0x8u |
| #define SPDIF_SIC_RxFIFOResyn_SHIFT 3 |
| #define SPDIF_SIC_RxFIFOUnOv_MASK 0x10u |
| #define SPDIF_SIC_RxFIFOUnOv_SHIFT 4 |
| #define SPDIF_SIC_UQErr_MASK 0x20u |
| #define SPDIF_SIC_UQErr_SHIFT 5 |
| #define SPDIF_SIC_UQSync_MASK 0x40u |
| #define SPDIF_SIC_UQSync_SHIFT 6 |
| #define SPDIF_SIC_QRxOv_MASK 0x80u |
| #define SPDIF_SIC_QRxOv_SHIFT 7 |
| #define SPDIF_SIC_URxOv_MASK 0x200u |
| #define SPDIF_SIC_URxOv_SHIFT 9 |
| #define SPDIF_SIC_BitErr_MASK 0x4000u |
| #define SPDIF_SIC_BitErr_SHIFT 14 |
| #define SPDIF_SIC_SymErr_MASK 0x8000u |
| #define SPDIF_SIC_SymErr_SHIFT 15 |
| #define SPDIF_SIC_ValNoGood_MASK 0x10000u |
| #define SPDIF_SIC_ValNoGood_SHIFT 16 |
| #define SPDIF_SIC_CNew_MASK 0x20000u |
| #define SPDIF_SIC_CNew_SHIFT 17 |
| #define SPDIF_SIC_TxResyn_MASK 0x40000u |
| #define SPDIF_SIC_TxResyn_SHIFT 18 |
| #define SPDIF_SIC_TxUnOv_MASK 0x80000u |
| #define SPDIF_SIC_TxUnOv_SHIFT 19 |
| #define SPDIF_SIC_Lock_MASK 0x100000u |
| #define SPDIF_SIC_Lock_SHIFT 20 |
| /* SRL Bit Fields */ |
| #define SPDIF_SRL_RxDataLeft_MASK 0xFFFFFFu |
| #define SPDIF_SRL_RxDataLeft_SHIFT 0 |
| #define SPDIF_SRL_RxDataLeft(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRL_RxDataLeft_SHIFT))&SPDIF_SRL_RxDataLeft_MASK) |
| /* SRR Bit Fields */ |
| #define SPDIF_SRR_RxDataRight_MASK 0xFFFFFFu |
| #define SPDIF_SRR_RxDataRight_SHIFT 0 |
| #define SPDIF_SRR_RxDataRight(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRR_RxDataRight_SHIFT))&SPDIF_SRR_RxDataRight_MASK) |
| /* SRCSH Bit Fields */ |
| #define SPDIF_SRCSH_RxCChannel_h_MASK 0xFFFFFFu |
| #define SPDIF_SRCSH_RxCChannel_h_SHIFT 0 |
| #define SPDIF_SRCSH_RxCChannel_h(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSH_RxCChannel_h_SHIFT))&SPDIF_SRCSH_RxCChannel_h_MASK) |
| /* SRCSL Bit Fields */ |
| #define SPDIF_SRCSL_RxCChannel_l_MASK 0xFFFFFFu |
| #define SPDIF_SRCSL_RxCChannel_l_SHIFT 0 |
| #define SPDIF_SRCSL_RxCChannel_l(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRCSL_RxCChannel_l_SHIFT))&SPDIF_SRCSL_RxCChannel_l_MASK) |
| /* SRU Bit Fields */ |
| #define SPDIF_SRU_RxUChannel_MASK 0xFFFFFFu |
| #define SPDIF_SRU_RxUChannel_SHIFT 0 |
| #define SPDIF_SRU_RxUChannel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRU_RxUChannel_SHIFT))&SPDIF_SRU_RxUChannel_MASK) |
| /* SRQ Bit Fields */ |
| #define SPDIF_SRQ_RxQChannel_MASK 0xFFFFFFu |
| #define SPDIF_SRQ_RxQChannel_SHIFT 0 |
| #define SPDIF_SRQ_RxQChannel(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRQ_RxQChannel_SHIFT))&SPDIF_SRQ_RxQChannel_MASK) |
| /* STL Bit Fields */ |
| #define SPDIF_STL_TxDataLeft_MASK 0xFFFFFFu |
| #define SPDIF_STL_TxDataLeft_SHIFT 0 |
| #define SPDIF_STL_TxDataLeft(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STL_TxDataLeft_SHIFT))&SPDIF_STL_TxDataLeft_MASK) |
| /* STR Bit Fields */ |
| #define SPDIF_STR_TxDataRight_MASK 0xFFFFFFu |
| #define SPDIF_STR_TxDataRight_SHIFT 0 |
| #define SPDIF_STR_TxDataRight(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STR_TxDataRight_SHIFT))&SPDIF_STR_TxDataRight_MASK) |
| /* STCSCH Bit Fields */ |
| #define SPDIF_STCSCH_TxCChannelCons_h_MASK 0xFFFFFFu |
| #define SPDIF_STCSCH_TxCChannelCons_h_SHIFT 0 |
| #define SPDIF_STCSCH_TxCChannelCons_h(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCH_TxCChannelCons_h_SHIFT))&SPDIF_STCSCH_TxCChannelCons_h_MASK) |
| /* STCSCL Bit Fields */ |
| #define SPDIF_STCSCL_TxCChannelCons_l_MASK 0xFFFFFFu |
| #define SPDIF_STCSCL_TxCChannelCons_l_SHIFT 0 |
| #define SPDIF_STCSCL_TxCChannelCons_l(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STCSCL_TxCChannelCons_l_SHIFT))&SPDIF_STCSCL_TxCChannelCons_l_MASK) |
| /* SRFM Bit Fields */ |
| #define SPDIF_SRFM_FreqMeas_MASK 0xFFFFFFu |
| #define SPDIF_SRFM_FreqMeas_SHIFT 0 |
| #define SPDIF_SRFM_FreqMeas(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_SRFM_FreqMeas_SHIFT))&SPDIF_SRFM_FreqMeas_MASK) |
| /* STC Bit Fields */ |
| #define SPDIF_STC_TxClk_DF_MASK 0x7Fu |
| #define SPDIF_STC_TxClk_DF_SHIFT 0 |
| #define SPDIF_STC_TxClk_DF(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_DF_SHIFT))&SPDIF_STC_TxClk_DF_MASK) |
| #define SPDIF_STC_tx_all_clk_en_MASK 0x80u |
| #define SPDIF_STC_tx_all_clk_en_SHIFT 7 |
| #define SPDIF_STC_TxClk_Source_MASK 0x700u |
| #define SPDIF_STC_TxClk_Source_SHIFT 8 |
| #define SPDIF_STC_TxClk_Source(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_TxClk_Source_SHIFT))&SPDIF_STC_TxClk_Source_MASK) |
| #define SPDIF_STC_SYSCLK_DF_MASK 0xFF800u |
| #define SPDIF_STC_SYSCLK_DF_SHIFT 11 |
| #define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x))<<SPDIF_STC_SYSCLK_DF_SHIFT))&SPDIF_STC_SYSCLK_DF_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Register_Masks */ |
| |
| /* SPDIF - Peripheral instance base addresses */ |
| /** Peripheral SPDIF base address */ |
| #define SPDIF_BASE (0x42004000u) |
| /** Peripheral SPDIF base pointer */ |
| #define SPDIF ((SPDIF_Type *)SPDIF_BASE) |
| #define SPDIF_BASE_PTR (SPDIF) |
| /** Array initializer of SPDIF peripheral base addresses */ |
| #define SPDIF_BASE_ADDRS { SPDIF_BASE } |
| /** Array initializer of SPDIF peripheral base pointers */ |
| #define SPDIF_BASE_PTRS { SPDIF } |
| /** Interrupt vectors for the SPDIF peripheral type */ |
| #define SPDIF_IRQS { SPDIF_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SPDIF - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SPDIF_Register_Accessor_Macros SPDIF - Register accessor macros |
| * @{ |
| */ |
| |
| /* SPDIF - Register instance definitions */ |
| /* SPDIF */ |
| #define SPDIF_SCR SPDIF_SCR_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRCD SPDIF_SRCD_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRPC SPDIF_SRPC_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SIE SPDIF_SIE_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SIS SPDIF_SIS_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SIC SPDIF_SIC_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRL SPDIF_SRL_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRR SPDIF_SRR_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRCSH SPDIF_SRCSH_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRCSL SPDIF_SRCSL_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRU SPDIF_SRU_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRQ SPDIF_SRQ_REG(SPDIF_BASE_PTR) |
| #define SPDIF_STL SPDIF_STL_REG(SPDIF_BASE_PTR) |
| #define SPDIF_STR SPDIF_STR_REG(SPDIF_BASE_PTR) |
| #define SPDIF_STCSCH SPDIF_STCSCH_REG(SPDIF_BASE_PTR) |
| #define SPDIF_STCSCL SPDIF_STCSCL_REG(SPDIF_BASE_PTR) |
| #define SPDIF_SRFM SPDIF_SRFM_REG(SPDIF_BASE_PTR) |
| #define SPDIF_STC SPDIF_STC_REG(SPDIF_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SPDIF_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SRC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ |
| __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ |
| __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ |
| uint8_t RESERVED_0[8]; |
| __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x14 */ |
| __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x18 */ |
| __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ |
| __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x20 */ |
| __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x24 */ |
| __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x28 */ |
| __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x2C */ |
| __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x30 */ |
| __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x34 */ |
| __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x38 */ |
| __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x3C */ |
| __IO uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x40 */ |
| __IO uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x44 */ |
| } SRC_Type, *SRC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros |
| * @{ |
| */ |
| |
| /* SRC - Register accessors */ |
| #define SRC_SCR_REG(base) ((base)->SCR) |
| #define SRC_SBMR1_REG(base) ((base)->SBMR1) |
| #define SRC_SRSR_REG(base) ((base)->SRSR) |
| #define SRC_SISR_REG(base) ((base)->SISR) |
| #define SRC_SIMR_REG(base) ((base)->SIMR) |
| #define SRC_SBMR2_REG(base) ((base)->SBMR2) |
| #define SRC_GPR1_REG(base) ((base)->GPR1) |
| #define SRC_GPR2_REG(base) ((base)->GPR2) |
| #define SRC_GPR3_REG(base) ((base)->GPR3) |
| #define SRC_GPR4_REG(base) ((base)->GPR4) |
| #define SRC_GPR5_REG(base) ((base)->GPR5) |
| #define SRC_GPR6_REG(base) ((base)->GPR6) |
| #define SRC_GPR7_REG(base) ((base)->GPR7) |
| #define SRC_GPR8_REG(base) ((base)->GPR8) |
| #define SRC_GPR9_REG(base) ((base)->GPR9) |
| #define SRC_GPR10_REG(base) ((base)->GPR10) |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Register_Masks SRC Register Masks |
| * @{ |
| */ |
| |
| /* SCR Bit Fields */ |
| #define SRC_SCR_warm_reset_enable_MASK 0x1u |
| #define SRC_SCR_warm_reset_enable_SHIFT 0 |
| #define SRC_SCR_sw_gpu_rst_MASK 0x2u |
| #define SRC_SCR_sw_gpu_rst_SHIFT 1 |
| #define SRC_SCR_m4c_rst_MASK 0x8u |
| #define SRC_SCR_m4c_rst_SHIFT 3 |
| #define SRC_SCR_m4c_non_sclr_rst_MASK 0x10u |
| #define SRC_SCR_m4c_non_sclr_rst_SHIFT 4 |
| #define SRC_SCR_warm_rst_bypass_count_MASK 0x60u |
| #define SRC_SCR_warm_rst_bypass_count_SHIFT 5 |
| #define SRC_SCR_warm_rst_bypass_count(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_warm_rst_bypass_count_SHIFT))&SRC_SCR_warm_rst_bypass_count_MASK) |
| #define SRC_SCR_mask_wdog_rst_MASK 0x780u |
| #define SRC_SCR_mask_wdog_rst_SHIFT 7 |
| #define SRC_SCR_mask_wdog_rst(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_wdog_rst_SHIFT))&SRC_SCR_mask_wdog_rst_MASK) |
| #define SRC_SCR_eim_rst_MASK 0x800u |
| #define SRC_SCR_eim_rst_SHIFT 11 |
| #define SRC_SCR_m4p_rst_MASK 0x1000u |
| #define SRC_SCR_m4p_rst_SHIFT 12 |
| #define SRC_SCR_core0_rst_MASK 0x2000u |
| #define SRC_SCR_core0_rst_SHIFT 13 |
| #define SRC_SCR_core0_dbg_rst_MASK 0x20000u |
| #define SRC_SCR_core0_dbg_rst_SHIFT 17 |
| #define SRC_SCR_mask_tempsense_reset_MASK 0x1C0000u |
| #define SRC_SCR_mask_tempsense_reset_SHIFT 18 |
| #define SRC_SCR_mask_tempsense_reset(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_tempsense_reset_SHIFT))&SRC_SCR_mask_tempsense_reset_MASK) |
| #define SRC_SCR_cores_dbg_rst_MASK 0x200000u |
| #define SRC_SCR_cores_dbg_rst_SHIFT 21 |
| #define SRC_SCR_m4_enable_MASK 0x400000u |
| #define SRC_SCR_m4_enable_SHIFT 22 |
| #define SRC_SCR_wdog3_rst_optn_m4_MASK 0x800000u |
| #define SRC_SCR_wdog3_rst_optn_m4_SHIFT 23 |
| #define SRC_SCR_wdog3_rst_optn_MASK 0x1000000u |
| #define SRC_SCR_wdog3_rst_optn_SHIFT 24 |
| #define SRC_SCR_dbg_rst_msk_pg_MASK 0x2000000u |
| #define SRC_SCR_dbg_rst_msk_pg_SHIFT 25 |
| #define SRC_SCR_mix_rst_strch_MASK 0xC000000u |
| #define SRC_SCR_mix_rst_strch_SHIFT 26 |
| #define SRC_SCR_mix_rst_strch(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mix_rst_strch_SHIFT))&SRC_SCR_mix_rst_strch_MASK) |
| #define SRC_SCR_mask_wdog3_rst_MASK 0xF0000000u |
| #define SRC_SCR_mask_wdog3_rst_SHIFT 28 |
| #define SRC_SCR_mask_wdog3_rst(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_mask_wdog3_rst_SHIFT))&SRC_SCR_mask_wdog3_rst_MASK) |
| /* SBMR1 Bit Fields */ |
| #define SRC_SBMR1_BOOT_CFG1_MASK 0xFFu |
| #define SRC_SBMR1_BOOT_CFG1_SHIFT 0 |
| #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG1_SHIFT))&SRC_SBMR1_BOOT_CFG1_MASK) |
| #define SRC_SBMR1_BOOT_CFG2_MASK 0xFF00u |
| #define SRC_SBMR1_BOOT_CFG2_SHIFT 8 |
| #define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG2_SHIFT))&SRC_SBMR1_BOOT_CFG2_MASK) |
| #define SRC_SBMR1_BOOT_CFG3_MASK 0xFF0000u |
| #define SRC_SBMR1_BOOT_CFG3_SHIFT 16 |
| #define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG3_SHIFT))&SRC_SBMR1_BOOT_CFG3_MASK) |
| #define SRC_SBMR1_BOOT_CFG4_MASK 0xFF000000u |
| #define SRC_SBMR1_BOOT_CFG4_SHIFT 24 |
| #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG4_SHIFT))&SRC_SBMR1_BOOT_CFG4_MASK) |
| /* SRSR Bit Fields */ |
| #define SRC_SRSR_ipp_reset_b_MASK 0x1u |
| #define SRC_SRSR_ipp_reset_b_SHIFT 0 |
| #define SRC_SRSR_csu_reset_b_MASK 0x4u |
| #define SRC_SRSR_csu_reset_b_SHIFT 2 |
| #define SRC_SRSR_ipp_user_reset_b_MASK 0x8u |
| #define SRC_SRSR_ipp_user_reset_b_SHIFT 3 |
| #define SRC_SRSR_wdog_rst_b_MASK 0x10u |
| #define SRC_SRSR_wdog_rst_b_SHIFT 4 |
| #define SRC_SRSR_jtag_rst_b_MASK 0x20u |
| #define SRC_SRSR_jtag_rst_b_SHIFT 5 |
| #define SRC_SRSR_jtag_sw_rst_MASK 0x40u |
| #define SRC_SRSR_jtag_sw_rst_SHIFT 6 |
| #define SRC_SRSR_wdog3_rst_b_MASK 0x80u |
| #define SRC_SRSR_wdog3_rst_b_SHIFT 7 |
| #define SRC_SRSR_tempsense_rst_b_MASK 0x100u |
| #define SRC_SRSR_tempsense_rst_b_SHIFT 8 |
| #define SRC_SRSR_warm_boot_MASK 0x10000u |
| #define SRC_SRSR_warm_boot_SHIFT 16 |
| /* SISR Bit Fields */ |
| #define SRC_SISR_gpu_passed_reset_MASK 0x1u |
| #define SRC_SISR_gpu_passed_reset_SHIFT 0 |
| #define SRC_SISR_m4c_passed_reset_MASK 0x4u |
| #define SRC_SISR_m4c_passed_reset_SHIFT 2 |
| #define SRC_SISR_open_vg_passed_reset_MASK 0x8u |
| #define SRC_SISR_open_vg_passed_reset_SHIFT 3 |
| #define SRC_SISR_m4p_passed_reset_MASK 0x10u |
| #define SRC_SISR_m4p_passed_reset_SHIFT 4 |
| #define SRC_SISR_core0_wdog_rst_req_MASK 0x20u |
| #define SRC_SISR_core0_wdog_rst_req_SHIFT 5 |
| /* SIMR Bit Fields */ |
| #define SRC_SIMR_mask_gpu_passed_reset_MASK 0x1u |
| #define SRC_SIMR_mask_gpu_passed_reset_SHIFT 0 |
| #define SRC_SIMR_mask_open_vg_passed_reset_MASK 0x8u |
| #define SRC_SIMR_mask_open_vg_passed_reset_SHIFT 3 |
| /* SBMR2 Bit Fields */ |
| #define SRC_SBMR2_SEC_CONFIG_MASK 0x3u |
| #define SRC_SBMR2_SEC_CONFIG_SHIFT 0 |
| #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_SEC_CONFIG_SHIFT))&SRC_SBMR2_SEC_CONFIG_MASK) |
| #define SRC_SBMR2_DIR_BT_DIS_MASK 0x8u |
| #define SRC_SBMR2_DIR_BT_DIS_SHIFT 3 |
| #define SRC_SBMR2_BT_FUSE_SEL_MASK 0x10u |
| #define SRC_SBMR2_BT_FUSE_SEL_SHIFT 4 |
| #define SRC_SBMR2_BMOD_MASK 0x3000000u |
| #define SRC_SBMR2_BMOD_SHIFT 24 |
| #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_BMOD_SHIFT))&SRC_SBMR2_BMOD_MASK) |
| /* GPR1 Bit Fields */ |
| #define SRC_GPR1_PERSISTENT_ENTRY0_MASK 0xFFFFFFFFu |
| #define SRC_GPR1_PERSISTENT_ENTRY0_SHIFT 0 |
| #define SRC_GPR1_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR1_PERSISTENT_ENTRY0_SHIFT))&SRC_GPR1_PERSISTENT_ENTRY0_MASK) |
| /* GPR2 Bit Fields */ |
| #define SRC_GPR2_PERSISTENT_ARG0_MASK 0xFFFFFFFFu |
| #define SRC_GPR2_PERSISTENT_ARG0_SHIFT 0 |
| #define SRC_GPR2_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR2_PERSISTENT_ARG0_SHIFT))&SRC_GPR2_PERSISTENT_ARG0_MASK) |
| /* GPR3 Bit Fields */ |
| #define SRC_GPR3_PERSISTENT_ENTRY1_MASK 0xFFFFFFFFu |
| #define SRC_GPR3_PERSISTENT_ENTRY1_SHIFT 0 |
| #define SRC_GPR3_PERSISTENT_ENTRY1(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR3_PERSISTENT_ENTRY1_SHIFT))&SRC_GPR3_PERSISTENT_ENTRY1_MASK) |
| /* GPR4 Bit Fields */ |
| #define SRC_GPR4_PERSISTENT_ARG1_MASK 0xFFFFFFFFu |
| #define SRC_GPR4_PERSISTENT_ARG1_SHIFT 0 |
| #define SRC_GPR4_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR4_PERSISTENT_ARG1_SHIFT))&SRC_GPR4_PERSISTENT_ARG1_MASK) |
| /* GPR5 Bit Fields */ |
| /* GPR6 Bit Fields */ |
| /* GPR7 Bit Fields */ |
| /* GPR8 Bit Fields */ |
| /* GPR9 Bit Fields */ |
| /* GPR10 Bit Fields */ |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Register_Masks */ |
| |
| /* SRC - Peripheral instance base addresses */ |
| /** Peripheral SRC base address */ |
| #define SRC_BASE (0x420D8000u) |
| /** Peripheral SRC base pointer */ |
| #define SRC ((SRC_Type *)SRC_BASE) |
| #define SRC_BASE_PTR (SRC) |
| /** Array initializer of SRC peripheral base addresses */ |
| #define SRC_BASE_ADDRS { SRC_BASE } |
| /** Array initializer of SRC peripheral base pointers */ |
| #define SRC_BASE_PTRS { SRC } |
| /** Interrupt vectors for the SRC peripheral type */ |
| #define SRC_IRQS { SRC_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SRC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros |
| * @{ |
| */ |
| |
| /* SRC - Register instance definitions */ |
| /* SRC */ |
| #define SRC_SCR SRC_SCR_REG(SRC_BASE_PTR) |
| #define SRC_SBMR1 SRC_SBMR1_REG(SRC_BASE_PTR) |
| #define SRC_SRSR SRC_SRSR_REG(SRC_BASE_PTR) |
| #define SRC_SISR SRC_SISR_REG(SRC_BASE_PTR) |
| #define SRC_SIMR SRC_SIMR_REG(SRC_BASE_PTR) |
| #define SRC_SBMR2 SRC_SBMR2_REG(SRC_BASE_PTR) |
| #define SRC_GPR1 SRC_GPR1_REG(SRC_BASE_PTR) |
| #define SRC_GPR2 SRC_GPR2_REG(SRC_BASE_PTR) |
| #define SRC_GPR3 SRC_GPR3_REG(SRC_BASE_PTR) |
| #define SRC_GPR4 SRC_GPR4_REG(SRC_BASE_PTR) |
| #define SRC_GPR5 SRC_GPR5_REG(SRC_BASE_PTR) |
| #define SRC_GPR6 SRC_GPR6_REG(SRC_BASE_PTR) |
| #define SRC_GPR7 SRC_GPR7_REG(SRC_BASE_PTR) |
| #define SRC_GPR8 SRC_GPR8_REG(SRC_BASE_PTR) |
| #define SRC_GPR9 SRC_GPR9_REG(SRC_BASE_PTR) |
| #define SRC_GPR10 SRC_GPR10_REG(SRC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SRC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SSI Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SSI_Peripheral_Access_Layer SSI Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** SSI - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t STX[2]; /**< SSI Transmit Data Register n, array offset: 0x0, array step: 0x4 */ |
| __I uint32_t SRX[2]; /**< SSI Receive Data Register n, array offset: 0x8, array step: 0x4 */ |
| __IO uint32_t SCR; /**< SSI Control Register, offset: 0x10 */ |
| __IO uint32_t SISR; /**< SSI Interrupt Status Register, offset: 0x14 */ |
| __IO uint32_t SIER; /**< SSI Interrupt Enable Register, offset: 0x18 */ |
| __IO uint32_t STCR; /**< SSI Transmit Configuration Register, offset: 0x1C */ |
| __IO uint32_t SRCR; /**< SSI Receive Configuration Register, offset: 0x20 */ |
| __IO uint32_t STCCR; /**< SSI Transmit Clock Control Register, offset: 0x24 */ |
| __IO uint32_t SRCCR; /**< SSI Receive Clock Control Register, offset: 0x28 */ |
| __IO uint32_t SFCSR; /**< SSI FIFO Control/Status Register, offset: 0x2C */ |
| uint8_t RESERVED_0[8]; |
| __IO uint32_t SACNT; /**< SSI AC97 Control Register, offset: 0x38 */ |
| __IO uint32_t SACADD; /**< SSI AC97 Command Address Register, offset: 0x3C */ |
| __IO uint32_t SACDAT; /**< SSI AC97 Command Data Register, offset: 0x40 */ |
| __IO uint32_t SATAG; /**< SSI AC97 Tag Register, offset: 0x44 */ |
| __IO uint32_t STMSK; /**< SSI Transmit Time Slot Mask Register, offset: 0x48 */ |
| __IO uint32_t SRMSK; /**< SSI Receive Time Slot Mask Register, offset: 0x4C */ |
| __I uint32_t SACCST; /**< SSI AC97 Channel Status Register, offset: 0x50 */ |
| __O uint32_t SACCEN; /**< SSI AC97 Channel Enable Register, offset: 0x54 */ |
| __O uint32_t SACCDIS; /**< SSI AC97 Channel Disable Register, offset: 0x58 */ |
| } SSI_Type, *SSI_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- SSI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SSI_Register_Accessor_Macros SSI - Register accessor macros |
| * @{ |
| */ |
| |
| /* SSI - Register accessors */ |
| #define SSI_STX_REG(base,index) ((base)->STX[index]) |
| #define SSI_SRX_REG(base,index) ((base)->SRX[index]) |
| #define SSI_SCR_REG(base) ((base)->SCR) |
| #define SSI_SISR_REG(base) ((base)->SISR) |
| #define SSI_SIER_REG(base) ((base)->SIER) |
| #define SSI_STCR_REG(base) ((base)->STCR) |
| #define SSI_SRCR_REG(base) ((base)->SRCR) |
| #define SSI_STCCR_REG(base) ((base)->STCCR) |
| #define SSI_SRCCR_REG(base) ((base)->SRCCR) |
| #define SSI_SFCSR_REG(base) ((base)->SFCSR) |
| #define SSI_SACNT_REG(base) ((base)->SACNT) |
| #define SSI_SACADD_REG(base) ((base)->SACADD) |
| #define SSI_SACDAT_REG(base) ((base)->SACDAT) |
| #define SSI_SATAG_REG(base) ((base)->SATAG) |
| #define SSI_STMSK_REG(base) ((base)->STMSK) |
| #define SSI_SRMSK_REG(base) ((base)->SRMSK) |
| #define SSI_SACCST_REG(base) ((base)->SACCST) |
| #define SSI_SACCEN_REG(base) ((base)->SACCEN) |
| #define SSI_SACCDIS_REG(base) ((base)->SACCDIS) |
| |
| /*! |
| * @} |
| */ /* end of group SSI_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- SSI Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SSI_Register_Masks SSI Register Masks |
| * @{ |
| */ |
| |
| /* STX Bit Fields */ |
| #define SSI_STX_STXn_MASK 0xFFFFFFFFu |
| #define SSI_STX_STXn_SHIFT 0 |
| #define SSI_STX_STXn(x) (((uint32_t)(((uint32_t)(x))<<SSI_STX_STXn_SHIFT))&SSI_STX_STXn_MASK) |
| /* SRX Bit Fields */ |
| #define SSI_SRX_SRXn_MASK 0xFFFFFFFFu |
| #define SSI_SRX_SRXn_SHIFT 0 |
| #define SSI_SRX_SRXn(x) (((uint32_t)(((uint32_t)(x))<<SSI_SRX_SRXn_SHIFT))&SSI_SRX_SRXn_MASK) |
| /* SCR Bit Fields */ |
| #define SSI_SCR_SSIEN_MASK 0x1u |
| #define SSI_SCR_SSIEN_SHIFT 0 |
| #define SSI_SCR_TE_MASK 0x2u |
| #define SSI_SCR_TE_SHIFT 1 |
| #define SSI_SCR_RE_MASK 0x4u |
| #define SSI_SCR_RE_SHIFT 2 |
| #define SSI_SCR_NET_MASK 0x8u |
| #define SSI_SCR_NET_SHIFT 3 |
| #define SSI_SCR_SYN_MASK 0x10u |
| #define SSI_SCR_SYN_SHIFT 4 |
| #define SSI_SCR_I2S_MODE_MASK 0x60u |
| #define SSI_SCR_I2S_MODE_SHIFT 5 |
| #define SSI_SCR_I2S_MODE(x) (((uint32_t)(((uint32_t)(x))<<SSI_SCR_I2S_MODE_SHIFT))&SSI_SCR_I2S_MODE_MASK) |
| #define SSI_SCR_SYS_CLK_EN_MASK 0x80u |
| #define SSI_SCR_SYS_CLK_EN_SHIFT 7 |
| #define SSI_SCR_TCH_EN_MASK 0x100u |
| #define SSI_SCR_TCH_EN_SHIFT 8 |
| #define SSI_SCR_CLK_IST_MASK 0x200u |
| #define SSI_SCR_CLK_IST_SHIFT 9 |
| #define SSI_SCR_TFR_CLK_DIS_MASK 0x400u |
| #define SSI_SCR_TFR_CLK_DIS_SHIFT 10 |
| #define SSI_SCR_RFR_CLK_DIS_MASK 0x800u |
| #define SSI_SCR_RFR_CLK_DIS_SHIFT 11 |
| #define SSI_SCR_SYNC_TX_FS_MASK 0x1000u |
| #define SSI_SCR_SYNC_TX_FS_SHIFT 12 |
| /* SISR Bit Fields */ |
| #define SSI_SISR_TFE0_MASK 0x1u |
| #define SSI_SISR_TFE0_SHIFT 0 |
| #define SSI_SISR_TFE1_MASK 0x2u |
| #define SSI_SISR_TFE1_SHIFT 1 |
| #define SSI_SISR_RFF0_MASK 0x4u |
| #define SSI_SISR_RFF0_SHIFT 2 |
| #define SSI_SISR_RFF1_MASK 0x8u |
| #define SSI_SISR_RFF1_SHIFT 3 |
| #define SSI_SISR_RLS_MASK 0x10u |
| #define SSI_SISR_RLS_SHIFT 4 |
| #define SSI_SISR_TLS_MASK 0x20u |
| #define SSI_SISR_TLS_SHIFT 5 |
| #define SSI_SISR_RFS_MASK 0x40u |
| #define SSI_SISR_RFS_SHIFT 6 |
| #define SSI_SISR_TFS_MASK 0x80u |
| #define SSI_SISR_TFS_SHIFT 7 |
| #define SSI_SISR_TUE0_MASK 0x100u |
| #define SSI_SISR_TUE0_SHIFT 8 |
| #define SSI_SISR_TUE1_MASK 0x200u |
| #define SSI_SISR_TUE1_SHIFT 9 |
| #define SSI_SISR_ROE0_MASK 0x400u |
| #define SSI_SISR_ROE0_SHIFT 10 |
| #define SSI_SISR_ROE1_MASK 0x800u |
| #define SSI_SISR_ROE1_SHIFT 11 |
| #define SSI_SISR_TDE0_MASK 0x1000u |
| #define SSI_SISR_TDE0_SHIFT 12 |
| #define SSI_SISR_TDE1_MASK 0x2000u |
| #define SSI_SISR_TDE1_SHIFT 13 |
| #define SSI_SISR_RDR0_MASK 0x4000u |
| #define SSI_SISR_RDR0_SHIFT 14 |
| #define SSI_SISR_RDR1_MASK 0x8000u |
| #define SSI_SISR_RDR1_SHIFT 15 |
| #define SSI_SISR_RXT_MASK 0x10000u |
| #define SSI_SISR_RXT_SHIFT 16 |
| #define SSI_SISR_CMDDU_MASK 0x20000u |
| #define SSI_SISR_CMDDU_SHIFT 17 |
| #define SSI_SISR_CMDAU_MASK 0x40000u |
| #define SSI_SISR_CMDAU_SHIFT 18 |
| #define SSI_SISR_TFRC_MASK 0x800000u |
| #define SSI_SISR_TFRC_SHIFT 23 |
| #define SSI_SISR_RFRC_MASK 0x1000000u |
| #define SSI_SISR_RFRC_SHIFT 24 |
| /* SIER Bit Fields */ |
| #define SSI_SIER_TFE0IE_MASK 0x1u |
| #define SSI_SIER_TFE0IE_SHIFT 0 |
| #define SSI_SIER_TFE1IE_MASK 0x2u |
| #define SSI_SIER_TFE1IE_SHIFT 1 |
| #define SSI_SIER_RFF0IE_MASK 0x4u |
| #define SSI_SIER_RFF0IE_SHIFT 2 |
| #define SSI_SIER_RFF1IE_MASK 0x8u |
| #define SSI_SIER_RFF1IE_SHIFT 3 |
| #define SSI_SIER_RLSIE_MASK 0x10u |
| #define SSI_SIER_RLSIE_SHIFT 4 |
| #define SSI_SIER_TLSIE_MASK 0x20u |
| #define SSI_SIER_TLSIE_SHIFT 5 |
| #define SSI_SIER_RFSIE_MASK 0x40u |
| #define SSI_SIER_RFSIE_SHIFT 6 |
| #define SSI_SIER_TFSIE_MASK 0x80u |
| #define SSI_SIER_TFSIE_SHIFT 7 |
| #define SSI_SIER_TUE0IE_MASK 0x100u |
| #define SSI_SIER_TUE0IE_SHIFT 8 |
| #define SSI_SIER_TUE1IE_MASK 0x200u |
| #define SSI_SIER_TUE1IE_SHIFT 9 |
| #define SSI_SIER_ROE0IE_MASK 0x400u |
| #define SSI_SIER_ROE0IE_SHIFT 10 |
| #define SSI_SIER_ROE1IE_MASK 0x800u |
| #define SSI_SIER_ROE1IE_SHIFT 11 |
| #define SSI_SIER_TDE0IE_MASK 0x1000u |
| #define SSI_SIER_TDE0IE_SHIFT 12 |
| #define SSI_SIER_TDE1IE_MASK 0x2000u |
| #define SSI_SIER_TDE1IE_SHIFT 13 |
| #define SSI_SIER_RDR0IE_MASK 0x4000u |
| #define SSI_SIER_RDR0IE_SHIFT 14 |
| #define SSI_SIER_RDR1IE_MASK 0x8000u |
| #define SSI_SIER_RDR1IE_SHIFT 15 |
| #define SSI_SIER_RXTIE_MASK 0x10000u |
| #define SSI_SIER_RXTIE_SHIFT 16 |
| #define SSI_SIER_CMDDUIE_MASK 0x20000u |
| #define SSI_SIER_CMDDUIE_SHIFT 17 |
| #define SSI_SIER_CMDAUIE_MASK 0x40000u |
| #define SSI_SIER_CMDAUIE_SHIFT 18 |
| #define SSI_SIER_TIE_MASK 0x80000u |
| #define SSI_SIER_TIE_SHIFT 19 |
| #define SSI_SIER_TDMAE_MASK 0x100000u |
| #define SSI_SIER_TDMAE_SHIFT 20 |
| #define SSI_SIER_RIE_MASK 0x200000u |
| #define SSI_SIER_RIE_SHIFT 21 |
| #define SSI_SIER_RDMAE_MASK 0x400000u |
| #define SSI_SIER_RDMAE_SHIFT 22 |
| #define SSI_SIER_TFRCIE_MASK 0x800000u |
| #define SSI_SIER_TFRCIE_SHIFT 23 |
| #define SSI_SIER_RFRCIE_MASK 0x1000000u |
| #define SSI_SIER_RFRCIE_SHIFT 24 |
| /* STCR Bit Fields */ |
| #define SSI_STCR_TEFS_MASK 0x1u |
| #define SSI_STCR_TEFS_SHIFT 0 |
| #define SSI_STCR_TFSL_MASK 0x2u |
| #define SSI_STCR_TFSL_SHIFT 1 |
| #define SSI_STCR_TFSI_MASK 0x4u |
| #define SSI_STCR_TFSI_SHIFT 2 |
| #define SSI_STCR_TSCKP_MASK 0x8u |
| #define SSI_STCR_TSCKP_SHIFT 3 |
| #define SSI_STCR_TSHFD_MASK 0x10u |
| #define SSI_STCR_TSHFD_SHIFT 4 |
| #define SSI_STCR_TXDIR_MASK 0x20u |
| #define SSI_STCR_TXDIR_SHIFT 5 |
| #define SSI_STCR_TFDIR_MASK 0x40u |
| #define SSI_STCR_TFDIR_SHIFT 6 |
| #define SSI_STCR_TFEN0_MASK 0x80u |
| #define SSI_STCR_TFEN0_SHIFT 7 |
| #define SSI_STCR_TFEN1_MASK 0x100u |
| #define SSI_STCR_TFEN1_SHIFT 8 |
| #define SSI_STCR_TXBIT0_MASK 0x200u |
| #define SSI_STCR_TXBIT0_SHIFT 9 |
| /* SRCR Bit Fields */ |
| #define SSI_SRCR_REFS_MASK 0x1u |
| #define SSI_SRCR_REFS_SHIFT 0 |
| #define SSI_SRCR_RFSL_MASK 0x2u |
| #define SSI_SRCR_RFSL_SHIFT 1 |
| #define SSI_SRCR_RFSI_MASK 0x4u |
| #define SSI_SRCR_RFSI_SHIFT 2 |
| #define SSI_SRCR_RSCKP_MASK 0x8u |
| #define SSI_SRCR_RSCKP_SHIFT 3 |
| #define SSI_SRCR_RSHFD_MASK 0x10u |
| #define SSI_SRCR_RSHFD_SHIFT 4 |
| #define SSI_SRCR_RXDIR_MASK 0x20u |
| #define SSI_SRCR_RXDIR_SHIFT 5 |
| #define SSI_SRCR_RFDIR_MASK 0x40u |
| #define SSI_SRCR_RFDIR_SHIFT 6 |
| #define SSI_SRCR_RFEN0_MASK 0x80u |
| #define SSI_SRCR_RFEN0_SHIFT 7 |
| #define SSI_SRCR_RFEN1_MASK 0x100u |
| #define SSI_SRCR_RFEN1_SHIFT 8 |
| #define SSI_SRCR_RXBIT0_MASK 0x200u |
| #define SSI_SRCR_RXBIT0_SHIFT 9 |
| #define SSI_SRCR_RXEXT_MASK 0x400u |
| #define SSI_SRCR_RXEXT_SHIFT 10 |
| /* STCCR Bit Fields */ |
| #define SSI_STCCR_PM7_PM0_MASK 0xFFu |
| #define SSI_STCCR_PM7_PM0_SHIFT 0 |
| #define SSI_STCCR_PM7_PM0(x) (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_PM7_PM0_SHIFT))&SSI_STCCR_PM7_PM0_MASK) |
| #define SSI_STCCR_DC4_DC0_MASK 0x1F00u |
| #define SSI_STCCR_DC4_DC0_SHIFT 8 |
| #define SSI_STCCR_DC4_DC0(x) (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_DC4_DC0_SHIFT))&SSI_STCCR_DC4_DC0_MASK) |
| #define SSI_STCCR_WL3_WL0_MASK 0x1E000u |
| #define SSI_STCCR_WL3_WL0_SHIFT 13 |
| #define SSI_STCCR_WL3_WL0(x) (((uint32_t)(((uint32_t)(x))<<SSI_STCCR_WL3_WL0_SHIFT))&SSI_STCCR_WL3_WL0_MASK) |
| #define SSI_STCCR_PSR_MASK 0x20000u |
| #define SSI_STCCR_PSR_SHIFT 17 |
| #define SSI_STCCR_DIV2_MASK 0x40000u |
| #define SSI_STCCR_DIV2_SHIFT 18 |
| /* SRCCR Bit Fields */ |
| #define SSI_SRCCR_PM7_PM0_MASK 0xFFu |
| #define SSI_SRCCR_PM7_PM0_SHIFT 0 |
| #define SSI_SRCCR_PM7_PM0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_PM7_PM0_SHIFT))&SSI_SRCCR_PM7_PM0_MASK) |
| #define SSI_SRCCR_DC4_DC0_MASK 0x1F00u |
| #define SSI_SRCCR_DC4_DC0_SHIFT 8 |
| #define SSI_SRCCR_DC4_DC0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_DC4_DC0_SHIFT))&SSI_SRCCR_DC4_DC0_MASK) |
| #define SSI_SRCCR_WL3_WL0_MASK 0x1E000u |
| #define SSI_SRCCR_WL3_WL0_SHIFT 13 |
| #define SSI_SRCCR_WL3_WL0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SRCCR_WL3_WL0_SHIFT))&SSI_SRCCR_WL3_WL0_MASK) |
| #define SSI_SRCCR_PSR_MASK 0x20000u |
| #define SSI_SRCCR_PSR_SHIFT 17 |
| #define SSI_SRCCR_DIV2_MASK 0x40000u |
| #define SSI_SRCCR_DIV2_SHIFT 18 |
| /* SFCSR Bit Fields */ |
| #define SSI_SFCSR_TFWM0_MASK 0xFu |
| #define SSI_SFCSR_TFWM0_SHIFT 0 |
| #define SSI_SFCSR_TFWM0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFWM0_SHIFT))&SSI_SFCSR_TFWM0_MASK) |
| #define SSI_SFCSR_RFWM0_MASK 0xF0u |
| #define SSI_SFCSR_RFWM0_SHIFT 4 |
| #define SSI_SFCSR_RFWM0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFWM0_SHIFT))&SSI_SFCSR_RFWM0_MASK) |
| #define SSI_SFCSR_TFCNT0_MASK 0xF00u |
| #define SSI_SFCSR_TFCNT0_SHIFT 8 |
| #define SSI_SFCSR_TFCNT0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFCNT0_SHIFT))&SSI_SFCSR_TFCNT0_MASK) |
| #define SSI_SFCSR_RFCNT0_MASK 0xF000u |
| #define SSI_SFCSR_RFCNT0_SHIFT 12 |
| #define SSI_SFCSR_RFCNT0(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFCNT0_SHIFT))&SSI_SFCSR_RFCNT0_MASK) |
| #define SSI_SFCSR_TFWM1_MASK 0xF0000u |
| #define SSI_SFCSR_TFWM1_SHIFT 16 |
| #define SSI_SFCSR_TFWM1(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFWM1_SHIFT))&SSI_SFCSR_TFWM1_MASK) |
| #define SSI_SFCSR_RFWM1_MASK 0xF00000u |
| #define SSI_SFCSR_RFWM1_SHIFT 20 |
| #define SSI_SFCSR_RFWM1(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFWM1_SHIFT))&SSI_SFCSR_RFWM1_MASK) |
| #define SSI_SFCSR_TFCNT1_MASK 0xF000000u |
| #define SSI_SFCSR_TFCNT1_SHIFT 24 |
| #define SSI_SFCSR_TFCNT1(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_TFCNT1_SHIFT))&SSI_SFCSR_TFCNT1_MASK) |
| #define SSI_SFCSR_RFCNT1_MASK 0xF0000000u |
| #define SSI_SFCSR_RFCNT1_SHIFT 28 |
| #define SSI_SFCSR_RFCNT1(x) (((uint32_t)(((uint32_t)(x))<<SSI_SFCSR_RFCNT1_SHIFT))&SSI_SFCSR_RFCNT1_MASK) |
| /* SACNT Bit Fields */ |
| #define SSI_SACNT_AC97EN_MASK 0x1u |
| #define SSI_SACNT_AC97EN_SHIFT 0 |
| #define SSI_SACNT_FV_MASK 0x2u |
| #define SSI_SACNT_FV_SHIFT 1 |
| #define SSI_SACNT_TIF_MASK 0x4u |
| #define SSI_SACNT_TIF_SHIFT 2 |
| #define SSI_SACNT_RD_MASK 0x8u |
| #define SSI_SACNT_RD_SHIFT 3 |
| #define SSI_SACNT_WR_MASK 0x10u |
| #define SSI_SACNT_WR_SHIFT 4 |
| #define SSI_SACNT_FRDIV_MASK 0x7E0u |
| #define SSI_SACNT_FRDIV_SHIFT 5 |
| #define SSI_SACNT_FRDIV(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACNT_FRDIV_SHIFT))&SSI_SACNT_FRDIV_MASK) |
| /* SACADD Bit Fields */ |
| #define SSI_SACADD_SACADD_MASK 0x7FFFFu |
| #define SSI_SACADD_SACADD_SHIFT 0 |
| #define SSI_SACADD_SACADD(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACADD_SACADD_SHIFT))&SSI_SACADD_SACADD_MASK) |
| /* SACDAT Bit Fields */ |
| #define SSI_SACDAT_SACDAT_MASK 0xFFFFFu |
| #define SSI_SACDAT_SACDAT_SHIFT 0 |
| #define SSI_SACDAT_SACDAT(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACDAT_SACDAT_SHIFT))&SSI_SACDAT_SACDAT_MASK) |
| /* SATAG Bit Fields */ |
| #define SSI_SATAG_SATAG_MASK 0xFFFFu |
| #define SSI_SATAG_SATAG_SHIFT 0 |
| #define SSI_SATAG_SATAG(x) (((uint32_t)(((uint32_t)(x))<<SSI_SATAG_SATAG_SHIFT))&SSI_SATAG_SATAG_MASK) |
| /* STMSK Bit Fields */ |
| #define SSI_STMSK_STMSK_MASK 0xFFFFFFFFu |
| #define SSI_STMSK_STMSK_SHIFT 0 |
| #define SSI_STMSK_STMSK(x) (((uint32_t)(((uint32_t)(x))<<SSI_STMSK_STMSK_SHIFT))&SSI_STMSK_STMSK_MASK) |
| /* SRMSK Bit Fields */ |
| #define SSI_SRMSK_SRMSK_MASK 0xFFFFFFFFu |
| #define SSI_SRMSK_SRMSK_SHIFT 0 |
| #define SSI_SRMSK_SRMSK(x) (((uint32_t)(((uint32_t)(x))<<SSI_SRMSK_SRMSK_SHIFT))&SSI_SRMSK_SRMSK_MASK) |
| /* SACCST Bit Fields */ |
| #define SSI_SACCST_SACCST_MASK 0x3FFu |
| #define SSI_SACCST_SACCST_SHIFT 0 |
| #define SSI_SACCST_SACCST(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACCST_SACCST_SHIFT))&SSI_SACCST_SACCST_MASK) |
| /* SACCEN Bit Fields */ |
| #define SSI_SACCEN_SACCEN_MASK 0x3FFu |
| #define SSI_SACCEN_SACCEN_SHIFT 0 |
| #define SSI_SACCEN_SACCEN(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACCEN_SACCEN_SHIFT))&SSI_SACCEN_SACCEN_MASK) |
| /* SACCDIS Bit Fields */ |
| #define SSI_SACCDIS_SACCDIS_MASK 0x3FFu |
| #define SSI_SACCDIS_SACCDIS_SHIFT 0 |
| #define SSI_SACCDIS_SACCDIS(x) (((uint32_t)(((uint32_t)(x))<<SSI_SACCDIS_SACCDIS_SHIFT))&SSI_SACCDIS_SACCDIS_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group SSI_Register_Masks */ |
| |
| /* SSI - Peripheral instance base addresses */ |
| /** Peripheral SSI1 base address */ |
| #define SSI1_BASE (0x42028000u) |
| /** Peripheral SSI1 base pointer */ |
| #define SSI1 ((SSI_Type *)SSI1_BASE) |
| #define SSI1_BASE_PTR (SSI1) |
| /** Peripheral SSI2 base address */ |
| #define SSI2_BASE (0x4202C000u) |
| /** Peripheral SSI2 base pointer */ |
| #define SSI2 ((SSI_Type *)SSI2_BASE) |
| #define SSI2_BASE_PTR (SSI2) |
| /** Peripheral SSI3 base address */ |
| #define SSI3_BASE (0x42030000u) |
| /** Peripheral SSI3 base pointer */ |
| #define SSI3 ((SSI_Type *)SSI3_BASE) |
| #define SSI3_BASE_PTR (SSI3) |
| /** Array initializer of SSI peripheral base addresses */ |
| #define SSI_BASE_ADDRS { SSI1_BASE, SSI2_BASE, SSI3_BASE } |
| /** Array initializer of SSI peripheral base pointers */ |
| #define SSI_BASE_PTRS { SSI1, SSI2, SSI3 } |
| /** Interrupt vectors for the SSI peripheral type */ |
| #define SSI_IRQS { SSI1_IRQn, SSI2_IRQn, SSI3_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- SSI - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup SSI_Register_Accessor_Macros SSI - Register accessor macros |
| * @{ |
| */ |
| |
| /* SSI - Register instance definitions */ |
| /* SSI1 */ |
| #define SSI1_STX0 SSI_STX_REG(SSI1_BASE_PTR,0) |
| #define SSI1_STX1 SSI_STX_REG(SSI1_BASE_PTR,1) |
| #define SSI1_SRX0 SSI_SRX_REG(SSI1_BASE_PTR,0) |
| #define SSI1_SRX1 SSI_SRX_REG(SSI1_BASE_PTR,1) |
| #define SSI1_SCR SSI_SCR_REG(SSI1_BASE_PTR) |
| #define SSI1_SISR SSI_SISR_REG(SSI1_BASE_PTR) |
| #define SSI1_SIER SSI_SIER_REG(SSI1_BASE_PTR) |
| #define SSI1_STCR SSI_STCR_REG(SSI1_BASE_PTR) |
| #define SSI1_SRCR SSI_SRCR_REG(SSI1_BASE_PTR) |
| #define SSI1_STCCR SSI_STCCR_REG(SSI1_BASE_PTR) |
| #define SSI1_SRCCR SSI_SRCCR_REG(SSI1_BASE_PTR) |
| #define SSI1_SFCSR SSI_SFCSR_REG(SSI1_BASE_PTR) |
| #define SSI1_SACNT SSI_SACNT_REG(SSI1_BASE_PTR) |
| #define SSI1_SACADD SSI_SACADD_REG(SSI1_BASE_PTR) |
| #define SSI1_SACDAT SSI_SACDAT_REG(SSI1_BASE_PTR) |
| #define SSI1_SATAG SSI_SATAG_REG(SSI1_BASE_PTR) |
| #define SSI1_STMSK SSI_STMSK_REG(SSI1_BASE_PTR) |
| #define SSI1_SRMSK SSI_SRMSK_REG(SSI1_BASE_PTR) |
| #define SSI1_SACCST SSI_SACCST_REG(SSI1_BASE_PTR) |
| #define SSI1_SACCEN SSI_SACCEN_REG(SSI1_BASE_PTR) |
| #define SSI1_SACCDIS SSI_SACCDIS_REG(SSI1_BASE_PTR) |
| /* SSI2 */ |
| #define SSI2_STX0 SSI_STX_REG(SSI2_BASE_PTR,0) |
| #define SSI2_STX1 SSI_STX_REG(SSI2_BASE_PTR,1) |
| #define SSI2_SRX0 SSI_SRX_REG(SSI2_BASE_PTR,0) |
| #define SSI2_SRX1 SSI_SRX_REG(SSI2_BASE_PTR,1) |
| #define SSI2_SCR SSI_SCR_REG(SSI2_BASE_PTR) |
| #define SSI2_SISR SSI_SISR_REG(SSI2_BASE_PTR) |
| #define SSI2_SIER SSI_SIER_REG(SSI2_BASE_PTR) |
| #define SSI2_STCR SSI_STCR_REG(SSI2_BASE_PTR) |
| #define SSI2_SRCR SSI_SRCR_REG(SSI2_BASE_PTR) |
| #define SSI2_STCCR SSI_STCCR_REG(SSI2_BASE_PTR) |
| #define SSI2_SRCCR SSI_SRCCR_REG(SSI2_BASE_PTR) |
| #define SSI2_SFCSR SSI_SFCSR_REG(SSI2_BASE_PTR) |
| #define SSI2_SACNT SSI_SACNT_REG(SSI2_BASE_PTR) |
| #define SSI2_SACADD SSI_SACADD_REG(SSI2_BASE_PTR) |
| #define SSI2_SACDAT SSI_SACDAT_REG(SSI2_BASE_PTR) |
| #define SSI2_SATAG SSI_SATAG_REG(SSI2_BASE_PTR) |
| #define SSI2_STMSK SSI_STMSK_REG(SSI2_BASE_PTR) |
| #define SSI2_SRMSK SSI_SRMSK_REG(SSI2_BASE_PTR) |
| #define SSI2_SACCST SSI_SACCST_REG(SSI2_BASE_PTR) |
| #define SSI2_SACCEN SSI_SACCEN_REG(SSI2_BASE_PTR) |
| #define SSI2_SACCDIS SSI_SACCDIS_REG(SSI2_BASE_PTR) |
| /* SSI3 */ |
| #define SSI3_STX0 SSI_STX_REG(SSI3_BASE_PTR,0) |
| #define SSI3_STX1 SSI_STX_REG(SSI3_BASE_PTR,1) |
| #define SSI3_SRX0 SSI_SRX_REG(SSI3_BASE_PTR,0) |
| #define SSI3_SRX1 SSI_SRX_REG(SSI3_BASE_PTR,1) |
| #define SSI3_SCR SSI_SCR_REG(SSI3_BASE_PTR) |
| #define SSI3_SISR SSI_SISR_REG(SSI3_BASE_PTR) |
| #define SSI3_SIER SSI_SIER_REG(SSI3_BASE_PTR) |
| #define SSI3_STCR SSI_STCR_REG(SSI3_BASE_PTR) |
| #define SSI3_SRCR SSI_SRCR_REG(SSI3_BASE_PTR) |
| #define SSI3_STCCR SSI_STCCR_REG(SSI3_BASE_PTR) |
| #define SSI3_SRCCR SSI_SRCCR_REG(SSI3_BASE_PTR) |
| #define SSI3_SFCSR SSI_SFCSR_REG(SSI3_BASE_PTR) |
| #define SSI3_SACNT SSI_SACNT_REG(SSI3_BASE_PTR) |
| #define SSI3_SACADD SSI_SACADD_REG(SSI3_BASE_PTR) |
| #define SSI3_SACDAT SSI_SACDAT_REG(SSI3_BASE_PTR) |
| #define SSI3_SATAG SSI_SATAG_REG(SSI3_BASE_PTR) |
| #define SSI3_STMSK SSI_STMSK_REG(SSI3_BASE_PTR) |
| #define SSI3_SRMSK SSI_SRMSK_REG(SSI3_BASE_PTR) |
| #define SSI3_SACCST SSI_SACCST_REG(SSI3_BASE_PTR) |
| #define SSI3_SACCEN SSI_SACCEN_REG(SSI3_BASE_PTR) |
| #define SSI3_SACCDIS SSI_SACCDIS_REG(SSI3_BASE_PTR) |
| /* SSI - Register array accessors */ |
| #define SSI1_STX(index) SSI_STX_REG(SSI1_BASE_PTR,index) |
| #define SSI2_STX(index) SSI_STX_REG(SSI2_BASE_PTR,index) |
| #define SSI3_STX(index) SSI_STX_REG(SSI3_BASE_PTR,index) |
| #define SSI1_SRX(index) SSI_SRX_REG(SSI1_BASE_PTR,index) |
| #define SSI2_SRX(index) SSI_SRX_REG(SSI2_BASE_PTR,index) |
| #define SSI3_SRX(index) SSI_SRX_REG(SSI3_BASE_PTR,index) |
| |
| /*! |
| * @} |
| */ /* end of group SSI_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group SSI_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- TEMPMON Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** TEMPMON - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[384]; |
| __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ |
| __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ |
| __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ |
| __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ |
| __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ |
| __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ |
| __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ |
| __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ |
| uint8_t RESERVED_1[240]; |
| __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ |
| __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ |
| __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ |
| __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ |
| } TEMPMON_Type, *TEMPMON_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- TEMPMON - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros |
| * @{ |
| */ |
| |
| /* TEMPMON - Register accessors */ |
| #define TEMPMON_TEMPSENSE0_REG(base) ((base)->TEMPSENSE0) |
| #define TEMPMON_TEMPSENSE0_SET_REG(base) ((base)->TEMPSENSE0_SET) |
| #define TEMPMON_TEMPSENSE0_CLR_REG(base) ((base)->TEMPSENSE0_CLR) |
| #define TEMPMON_TEMPSENSE0_TOG_REG(base) ((base)->TEMPSENSE0_TOG) |
| #define TEMPMON_TEMPSENSE1_REG(base) ((base)->TEMPSENSE1) |
| #define TEMPMON_TEMPSENSE1_SET_REG(base) ((base)->TEMPSENSE1_SET) |
| #define TEMPMON_TEMPSENSE1_CLR_REG(base) ((base)->TEMPSENSE1_CLR) |
| #define TEMPMON_TEMPSENSE1_TOG_REG(base) ((base)->TEMPSENSE1_TOG) |
| #define TEMPMON_TEMPSENSE2_REG(base) ((base)->TEMPSENSE2) |
| #define TEMPMON_TEMPSENSE2_SET_REG(base) ((base)->TEMPSENSE2_SET) |
| #define TEMPMON_TEMPSENSE2_CLR_REG(base) ((base)->TEMPSENSE2_CLR) |
| #define TEMPMON_TEMPSENSE2_TOG_REG(base) ((base)->TEMPSENSE2_TOG) |
| |
| /*! |
| * @} |
| */ /* end of group TEMPMON_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- TEMPMON Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks |
| * @{ |
| */ |
| |
| /* TEMPSENSE0 Bit Fields */ |
| #define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK 0x1u |
| #define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT 0 |
| #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK 0x2u |
| #define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT 1 |
| #define TEMPMON_TEMPSENSE0_FINISHED_MASK 0x4u |
| #define TEMPMON_TEMPSENSE0_FINISHED_SHIFT 2 |
| #define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK 0xFFF00u |
| #define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8 |
| #define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) |
| #define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK 0xFFF00000u |
| #define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT 20 |
| #define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) |
| /* TEMPSENSE0_SET Bit Fields */ |
| #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK 0x1u |
| #define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT 0 |
| #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK 0x2u |
| #define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT 1 |
| #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK 0x4u |
| #define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT 2 |
| #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK 0xFFF00u |
| #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT 8 |
| #define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) |
| #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK 0xFFF00000u |
| #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT 20 |
| #define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) |
| /* TEMPSENSE0_CLR Bit Fields */ |
| #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK 0x1u |
| #define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT 0 |
| #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK 0x2u |
| #define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT 1 |
| #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK 0x4u |
| #define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT 2 |
| #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK 0xFFF00u |
| #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT 8 |
| #define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) |
| #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK 0xFFF00000u |
| #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT 20 |
| #define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) |
| /* TEMPSENSE0_TOG Bit Fields */ |
| #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK 0x1u |
| #define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT 0 |
| #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK 0x2u |
| #define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT 1 |
| #define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK 0x4u |
| #define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT 2 |
| #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK 0xFFF00u |
| #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT 8 |
| #define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT))&TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) |
| #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK 0xFFF00000u |
| #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT 20 |
| #define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) |
| /* TEMPSENSE1 Bit Fields */ |
| #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFFu |
| #define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT 0 |
| #define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) |
| /* TEMPSENSE1_SET Bit Fields */ |
| #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFFu |
| #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 0 |
| #define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) |
| /* TEMPSENSE1_CLR Bit Fields */ |
| #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFFu |
| #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 0 |
| #define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) |
| /* TEMPSENSE1_TOG Bit Fields */ |
| #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFFu |
| #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 0 |
| #define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) |
| /* TEMPSENSE2 Bit Fields */ |
| #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK 0xFFFu |
| #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT 0 |
| #define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) |
| #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK 0xFFF0000u |
| #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT 16 |
| #define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) |
| /* TEMPSENSE2_SET Bit Fields */ |
| #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK 0xFFFu |
| #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT 0 |
| #define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) |
| #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK 0xFFF0000u |
| #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT 16 |
| #define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) |
| /* TEMPSENSE2_CLR Bit Fields */ |
| #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK 0xFFFu |
| #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT 0 |
| #define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) |
| #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK 0xFFF0000u |
| #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT 16 |
| #define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) |
| /* TEMPSENSE2_TOG Bit Fields */ |
| #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK 0xFFFu |
| #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT 0 |
| #define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) |
| #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK 0xFFF0000u |
| #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT 16 |
| #define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group TEMPMON_Register_Masks */ |
| |
| /* TEMPMON - Peripheral instance base addresses */ |
| /** Peripheral TEMPMON base address */ |
| #define TEMPMON_BASE (0x420C8000u) |
| /** Peripheral TEMPMON base pointer */ |
| #define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) |
| #define TEMPMON_BASE_PTR (TEMPMON) |
| /** Array initializer of TEMPMON peripheral base addresses */ |
| #define TEMPMON_BASE_ADDRS { TEMPMON_BASE } |
| /** Array initializer of TEMPMON peripheral base pointers */ |
| #define TEMPMON_BASE_PTRS { TEMPMON } |
| |
| /* ---------------------------------------------------------------------------- |
| -- TEMPMON - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros |
| * @{ |
| */ |
| |
| /* TEMPMON - Register instance definitions */ |
| /* TEMPMON */ |
| #define TEMPMON_TEMPSENSE0 TEMPMON_TEMPSENSE0_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE0_SET TEMPMON_TEMPSENSE0_SET_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE0_CLR TEMPMON_TEMPSENSE0_CLR_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE0_TOG TEMPMON_TEMPSENSE0_TOG_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE1 TEMPMON_TEMPSENSE1_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE1_SET TEMPMON_TEMPSENSE1_SET_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE1_CLR TEMPMON_TEMPSENSE1_CLR_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE1_TOG TEMPMON_TEMPSENSE1_TOG_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE2 TEMPMON_TEMPSENSE2_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE2_SET TEMPMON_TEMPSENSE2_SET_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE2_CLR TEMPMON_TEMPSENSE2_CLR_REG(TEMPMON_BASE_PTR) |
| #define TEMPMON_TEMPSENSE2_TOG TEMPMON_TEMPSENSE2_TOG_REG(TEMPMON_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group TEMPMON_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group TEMPMON_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** UART - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ |
| uint8_t RESERVED_0[60]; |
| __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ |
| uint8_t RESERVED_1[60]; |
| __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ |
| __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ |
| __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ |
| __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ |
| __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ |
| __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ |
| __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ |
| __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ |
| __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ |
| __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ |
| __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ |
| __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ |
| __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ |
| __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ |
| __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ |
| } UART_Type, *UART_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros |
| * @{ |
| */ |
| |
| /* UART - Register accessors */ |
| #define UART_URXD_REG(base) ((base)->URXD) |
| #define UART_UTXD_REG(base) ((base)->UTXD) |
| #define UART_UCR1_REG(base) ((base)->UCR1) |
| #define UART_UCR2_REG(base) ((base)->UCR2) |
| #define UART_UCR3_REG(base) ((base)->UCR3) |
| #define UART_UCR4_REG(base) ((base)->UCR4) |
| #define UART_UFCR_REG(base) ((base)->UFCR) |
| #define UART_USR1_REG(base) ((base)->USR1) |
| #define UART_USR2_REG(base) ((base)->USR2) |
| #define UART_UESC_REG(base) ((base)->UESC) |
| #define UART_UTIM_REG(base) ((base)->UTIM) |
| #define UART_UBIR_REG(base) ((base)->UBIR) |
| #define UART_UBMR_REG(base) ((base)->UBMR) |
| #define UART_UBRC_REG(base) ((base)->UBRC) |
| #define UART_ONEMS_REG(base) ((base)->ONEMS) |
| #define UART_UTS_REG(base) ((base)->UTS) |
| #define UART_UMCR_REG(base) ((base)->UMCR) |
| |
| /*! |
| * @} |
| */ /* end of group UART_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Register_Masks UART Register Masks |
| * @{ |
| */ |
| |
| /* URXD Bit Fields */ |
| #define UART_URXD_RX_DATA_MASK 0xFFu |
| #define UART_URXD_RX_DATA_SHIFT 0 |
| #define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<<UART_URXD_RX_DATA_SHIFT))&UART_URXD_RX_DATA_MASK) |
| #define UART_URXD_PRERR_MASK 0x400u |
| #define UART_URXD_PRERR_SHIFT 10 |
| #define UART_URXD_BRK_MASK 0x800u |
| #define UART_URXD_BRK_SHIFT 11 |
| #define UART_URXD_FRMERR_MASK 0x1000u |
| #define UART_URXD_FRMERR_SHIFT 12 |
| #define UART_URXD_OVRRUN_MASK 0x2000u |
| #define UART_URXD_OVRRUN_SHIFT 13 |
| #define UART_URXD_ERR_MASK 0x4000u |
| #define UART_URXD_ERR_SHIFT 14 |
| #define UART_URXD_CHARRDY_MASK 0x8000u |
| #define UART_URXD_CHARRDY_SHIFT 15 |
| /* UTXD Bit Fields */ |
| #define UART_UTXD_TX_DATA_MASK 0xFFu |
| #define UART_UTXD_TX_DATA_SHIFT 0 |
| #define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x))<<UART_UTXD_TX_DATA_SHIFT))&UART_UTXD_TX_DATA_MASK) |
| /* UCR1 Bit Fields */ |
| #define UART_UCR1_UARTEN_MASK 0x1u |
| #define UART_UCR1_UARTEN_SHIFT 0 |
| #define UART_UCR1_DOZE_MASK 0x2u |
| #define UART_UCR1_DOZE_SHIFT 1 |
| #define UART_UCR1_ATDMAEN_MASK 0x4u |
| #define UART_UCR1_ATDMAEN_SHIFT 2 |
| #define UART_UCR1_TXDMAEN_MASK 0x8u |
| #define UART_UCR1_TXDMAEN_SHIFT 3 |
| #define UART_UCR1_SNDBRK_MASK 0x10u |
| #define UART_UCR1_SNDBRK_SHIFT 4 |
| #define UART_UCR1_RTSDEN_MASK 0x20u |
| #define UART_UCR1_RTSDEN_SHIFT 5 |
| #define UART_UCR1_TXMPTYEN_MASK 0x40u |
| #define UART_UCR1_TXMPTYEN_SHIFT 6 |
| #define UART_UCR1_IREN_MASK 0x80u |
| #define UART_UCR1_IREN_SHIFT 7 |
| #define UART_UCR1_RXDMAEN_MASK 0x100u |
| #define UART_UCR1_RXDMAEN_SHIFT 8 |
| #define UART_UCR1_RRDYEN_MASK 0x200u |
| #define UART_UCR1_RRDYEN_SHIFT 9 |
| #define UART_UCR1_ICD_MASK 0xC00u |
| #define UART_UCR1_ICD_SHIFT 10 |
| #define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR1_ICD_SHIFT))&UART_UCR1_ICD_MASK) |
| #define UART_UCR1_IDEN_MASK 0x1000u |
| #define UART_UCR1_IDEN_SHIFT 12 |
| #define UART_UCR1_TRDYEN_MASK 0x2000u |
| #define UART_UCR1_TRDYEN_SHIFT 13 |
| #define UART_UCR1_ADBR_MASK 0x4000u |
| #define UART_UCR1_ADBR_SHIFT 14 |
| #define UART_UCR1_ADEN_MASK 0x8000u |
| #define UART_UCR1_ADEN_SHIFT 15 |
| /* UCR2 Bit Fields */ |
| #define UART_UCR2_SRST_MASK 0x1u |
| #define UART_UCR2_SRST_SHIFT 0 |
| #define UART_UCR2_RXEN_MASK 0x2u |
| #define UART_UCR2_RXEN_SHIFT 1 |
| #define UART_UCR2_TXEN_MASK 0x4u |
| #define UART_UCR2_TXEN_SHIFT 2 |
| #define UART_UCR2_ATEN_MASK 0x8u |
| #define UART_UCR2_ATEN_SHIFT 3 |
| #define UART_UCR2_RTSEN_MASK 0x10u |
| #define UART_UCR2_RTSEN_SHIFT 4 |
| #define UART_UCR2_WS_MASK 0x20u |
| #define UART_UCR2_WS_SHIFT 5 |
| #define UART_UCR2_STPB_MASK 0x40u |
| #define UART_UCR2_STPB_SHIFT 6 |
| #define UART_UCR2_PROE_MASK 0x80u |
| #define UART_UCR2_PROE_SHIFT 7 |
| #define UART_UCR2_PREN_MASK 0x100u |
| #define UART_UCR2_PREN_SHIFT 8 |
| #define UART_UCR2_RTEC_MASK 0x600u |
| #define UART_UCR2_RTEC_SHIFT 9 |
| #define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR2_RTEC_SHIFT))&UART_UCR2_RTEC_MASK) |
| #define UART_UCR2_ESCEN_MASK 0x800u |
| #define UART_UCR2_ESCEN_SHIFT 11 |
| #define UART_UCR2_CTS_MASK 0x1000u |
| #define UART_UCR2_CTS_SHIFT 12 |
| #define UART_UCR2_CTSC_MASK 0x2000u |
| #define UART_UCR2_CTSC_SHIFT 13 |
| #define UART_UCR2_IRTS_MASK 0x4000u |
| #define UART_UCR2_IRTS_SHIFT 14 |
| #define UART_UCR2_ESCI_MASK 0x8000u |
| #define UART_UCR2_ESCI_SHIFT 15 |
| /* UCR3 Bit Fields */ |
| #define UART_UCR3_ACIEN_MASK 0x1u |
| #define UART_UCR3_ACIEN_SHIFT 0 |
| #define UART_UCR3_INVT_MASK 0x2u |
| #define UART_UCR3_INVT_SHIFT 1 |
| #define UART_UCR3_RXDMUXSEL_MASK 0x4u |
| #define UART_UCR3_RXDMUXSEL_SHIFT 2 |
| #define UART_UCR3_DTRDEN_MASK 0x8u |
| #define UART_UCR3_DTRDEN_SHIFT 3 |
| #define UART_UCR3_AWAKEN_MASK 0x10u |
| #define UART_UCR3_AWAKEN_SHIFT 4 |
| #define UART_UCR3_AIRINTEN_MASK 0x20u |
| #define UART_UCR3_AIRINTEN_SHIFT 5 |
| #define UART_UCR3_RXDSEN_MASK 0x40u |
| #define UART_UCR3_RXDSEN_SHIFT 6 |
| #define UART_UCR3_ADNIMP_MASK 0x80u |
| #define UART_UCR3_ADNIMP_SHIFT 7 |
| #define UART_UCR3_RI_MASK 0x100u |
| #define UART_UCR3_RI_SHIFT 8 |
| #define UART_UCR3_DCD_MASK 0x200u |
| #define UART_UCR3_DCD_SHIFT 9 |
| #define UART_UCR3_DSR_MASK 0x400u |
| #define UART_UCR3_DSR_SHIFT 10 |
| #define UART_UCR3_FRAERREN_MASK 0x800u |
| #define UART_UCR3_FRAERREN_SHIFT 11 |
| #define UART_UCR3_PARERREN_MASK 0x1000u |
| #define UART_UCR3_PARERREN_SHIFT 12 |
| #define UART_UCR3_DTREN_MASK 0x2000u |
| #define UART_UCR3_DTREN_SHIFT 13 |
| #define UART_UCR3_DPEC_MASK 0xC000u |
| #define UART_UCR3_DPEC_SHIFT 14 |
| #define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR3_DPEC_SHIFT))&UART_UCR3_DPEC_MASK) |
| /* UCR4 Bit Fields */ |
| #define UART_UCR4_DREN_MASK 0x1u |
| #define UART_UCR4_DREN_SHIFT 0 |
| #define UART_UCR4_OREN_MASK 0x2u |
| #define UART_UCR4_OREN_SHIFT 1 |
| #define UART_UCR4_BKEN_MASK 0x4u |
| #define UART_UCR4_BKEN_SHIFT 2 |
| #define UART_UCR4_TCEN_MASK 0x8u |
| #define UART_UCR4_TCEN_SHIFT 3 |
| #define UART_UCR4_LPBYP_MASK 0x10u |
| #define UART_UCR4_LPBYP_SHIFT 4 |
| #define UART_UCR4_IRSC_MASK 0x20u |
| #define UART_UCR4_IRSC_SHIFT 5 |
| #define UART_UCR4_IDDMAEN_MASK 0x40u |
| #define UART_UCR4_IDDMAEN_SHIFT 6 |
| #define UART_UCR4_WKEN_MASK 0x80u |
| #define UART_UCR4_WKEN_SHIFT 7 |
| #define UART_UCR4_ENIRI_MASK 0x100u |
| #define UART_UCR4_ENIRI_SHIFT 8 |
| #define UART_UCR4_INVR_MASK 0x200u |
| #define UART_UCR4_INVR_SHIFT 9 |
| #define UART_UCR4_CTSTL_MASK 0xFC00u |
| #define UART_UCR4_CTSTL_SHIFT 10 |
| #define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR4_CTSTL_SHIFT))&UART_UCR4_CTSTL_MASK) |
| /* UFCR Bit Fields */ |
| #define UART_UFCR_RXTL_MASK 0x3Fu |
| #define UART_UFCR_RXTL_SHIFT 0 |
| #define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RXTL_SHIFT))&UART_UFCR_RXTL_MASK) |
| #define UART_UFCR_DCEDTE_MASK 0x40u |
| #define UART_UFCR_DCEDTE_SHIFT 6 |
| #define UART_UFCR_RFDIV_MASK 0x380u |
| #define UART_UFCR_RFDIV_SHIFT 7 |
| #define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RFDIV_SHIFT))&UART_UFCR_RFDIV_MASK) |
| #define UART_UFCR_TXTL_MASK 0xFC00u |
| #define UART_UFCR_TXTL_SHIFT 10 |
| #define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_TXTL_SHIFT))&UART_UFCR_TXTL_MASK) |
| /* USR1 Bit Fields */ |
| #define UART_USR1_SAD_MASK 0x8u |
| #define UART_USR1_SAD_SHIFT 3 |
| #define UART_USR1_AWAKE_MASK 0x10u |
| #define UART_USR1_AWAKE_SHIFT 4 |
| #define UART_USR1_AIRINT_MASK 0x20u |
| #define UART_USR1_AIRINT_SHIFT 5 |
| #define UART_USR1_RXDS_MASK 0x40u |
| #define UART_USR1_RXDS_SHIFT 6 |
| #define UART_USR1_DTRD_MASK 0x80u |
| #define UART_USR1_DTRD_SHIFT 7 |
| #define UART_USR1_AGTIM_MASK 0x100u |
| #define UART_USR1_AGTIM_SHIFT 8 |
| #define UART_USR1_RRDY_MASK 0x200u |
| #define UART_USR1_RRDY_SHIFT 9 |
| #define UART_USR1_FRAMERR_MASK 0x400u |
| #define UART_USR1_FRAMERR_SHIFT 10 |
| #define UART_USR1_ESCF_MASK 0x800u |
| #define UART_USR1_ESCF_SHIFT 11 |
| #define UART_USR1_RTSD_MASK 0x1000u |
| #define UART_USR1_RTSD_SHIFT 12 |
| #define UART_USR1_TRDY_MASK 0x2000u |
| #define UART_USR1_TRDY_SHIFT 13 |
| #define UART_USR1_RTSS_MASK 0x4000u |
| #define UART_USR1_RTSS_SHIFT 14 |
| #define UART_USR1_PARITYERR_MASK 0x8000u |
| #define UART_USR1_PARITYERR_SHIFT 15 |
| /* USR2 Bit Fields */ |
| #define UART_USR2_RDR_MASK 0x1u |
| #define UART_USR2_RDR_SHIFT 0 |
| #define UART_USR2_ORE_MASK 0x2u |
| #define UART_USR2_ORE_SHIFT 1 |
| #define UART_USR2_BRCD_MASK 0x4u |
| #define UART_USR2_BRCD_SHIFT 2 |
| #define UART_USR2_TXDC_MASK 0x8u |
| #define UART_USR2_TXDC_SHIFT 3 |
| #define UART_USR2_RTSF_MASK 0x10u |
| #define UART_USR2_RTSF_SHIFT 4 |
| #define UART_USR2_DCDIN_MASK 0x20u |
| #define UART_USR2_DCDIN_SHIFT 5 |
| #define UART_USR2_DCDDELT_MASK 0x40u |
| #define UART_USR2_DCDDELT_SHIFT 6 |
| #define UART_USR2_WAKE_MASK 0x80u |
| #define UART_USR2_WAKE_SHIFT 7 |
| #define UART_USR2_IRINT_MASK 0x100u |
| #define UART_USR2_IRINT_SHIFT 8 |
| #define UART_USR2_RIIN_MASK 0x200u |
| #define UART_USR2_RIIN_SHIFT 9 |
| #define UART_USR2_RIDELT_MASK 0x400u |
| #define UART_USR2_RIDELT_SHIFT 10 |
| #define UART_USR2_ACST_MASK 0x800u |
| #define UART_USR2_ACST_SHIFT 11 |
| #define UART_USR2_IDLE_MASK 0x1000u |
| #define UART_USR2_IDLE_SHIFT 12 |
| #define UART_USR2_DTRF_MASK 0x2000u |
| #define UART_USR2_DTRF_SHIFT 13 |
| #define UART_USR2_TXFE_MASK 0x4000u |
| #define UART_USR2_TXFE_SHIFT 14 |
| #define UART_USR2_ADET_MASK 0x8000u |
| #define UART_USR2_ADET_SHIFT 15 |
| /* UESC Bit Fields */ |
| #define UART_UESC_ESC_CHAR_MASK 0xFFu |
| #define UART_UESC_ESC_CHAR_SHIFT 0 |
| #define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x))<<UART_UESC_ESC_CHAR_SHIFT))&UART_UESC_ESC_CHAR_MASK) |
| /* UTIM Bit Fields */ |
| #define UART_UTIM_TIM_MASK 0xFFFu |
| #define UART_UTIM_TIM_SHIFT 0 |
| #define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x))<<UART_UTIM_TIM_SHIFT))&UART_UTIM_TIM_MASK) |
| /* UBIR Bit Fields */ |
| #define UART_UBIR_INC_MASK 0xFFFFu |
| #define UART_UBIR_INC_SHIFT 0 |
| #define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x))<<UART_UBIR_INC_SHIFT))&UART_UBIR_INC_MASK) |
| /* UBMR Bit Fields */ |
| #define UART_UBMR_MOD_MASK 0xFFFFu |
| #define UART_UBMR_MOD_SHIFT 0 |
| #define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x))<<UART_UBMR_MOD_SHIFT))&UART_UBMR_MOD_MASK) |
| /* UBRC Bit Fields */ |
| #define UART_UBRC_BCNT_MASK 0xFFFFu |
| #define UART_UBRC_BCNT_SHIFT 0 |
| #define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x))<<UART_UBRC_BCNT_SHIFT))&UART_UBRC_BCNT_MASK) |
| /* ONEMS Bit Fields */ |
| #define UART_ONEMS_ONEMS_MASK 0xFFFFFFu |
| #define UART_ONEMS_ONEMS_SHIFT 0 |
| #define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x))<<UART_ONEMS_ONEMS_SHIFT))&UART_ONEMS_ONEMS_MASK) |
| /* UTS Bit Fields */ |
| #define UART_UTS_SOFTRST_MASK 0x1u |
| #define UART_UTS_SOFTRST_SHIFT 0 |
| #define UART_UTS_RXFULL_MASK 0x8u |
| #define UART_UTS_RXFULL_SHIFT 3 |
| #define UART_UTS_TXFULL_MASK 0x10u |
| #define UART_UTS_TXFULL_SHIFT 4 |
| #define UART_UTS_RXEMPTY_MASK 0x20u |
| #define UART_UTS_RXEMPTY_SHIFT 5 |
| #define UART_UTS_TXEMPTY_MASK 0x40u |
| #define UART_UTS_TXEMPTY_SHIFT 6 |
| #define UART_UTS_RXDBG_MASK 0x200u |
| #define UART_UTS_RXDBG_SHIFT 9 |
| #define UART_UTS_LOOPIR_MASK 0x400u |
| #define UART_UTS_LOOPIR_SHIFT 10 |
| #define UART_UTS_DBGEN_MASK 0x800u |
| #define UART_UTS_DBGEN_SHIFT 11 |
| #define UART_UTS_LOOP_MASK 0x1000u |
| #define UART_UTS_LOOP_SHIFT 12 |
| #define UART_UTS_FRCPERR_MASK 0x2000u |
| #define UART_UTS_FRCPERR_SHIFT 13 |
| /* UMCR Bit Fields */ |
| #define UART_UMCR_MDEN_MASK 0x1u |
| #define UART_UMCR_MDEN_SHIFT 0 |
| #define UART_UMCR_SLAM_MASK 0x2u |
| #define UART_UMCR_SLAM_SHIFT 1 |
| #define UART_UMCR_TXB8_MASK 0x4u |
| #define UART_UMCR_TXB8_SHIFT 2 |
| #define UART_UMCR_SADEN_MASK 0x8u |
| #define UART_UMCR_SADEN_SHIFT 3 |
| #define UART_UMCR_SLADDR_MASK 0xFF00u |
| #define UART_UMCR_SLADDR_SHIFT 8 |
| #define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x))<<UART_UMCR_SLADDR_SHIFT))&UART_UMCR_SLADDR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group UART_Register_Masks */ |
| |
| /* UART - Peripheral instance base addresses */ |
| /** Peripheral UART1 base address */ |
| #define UART1_BASE (0x42020000u) |
| /** Peripheral UART1 base pointer */ |
| #define UART1 ((UART_Type *)UART1_BASE) |
| #define UART1_BASE_PTR (UART1) |
| /** Peripheral UART2 base address */ |
| #define UART2_BASE (0x421E8000u) |
| /** Peripheral UART2 base pointer */ |
| #define UART2 ((UART_Type *)UART2_BASE) |
| #define UART2_BASE_PTR (UART2) |
| /** Peripheral UART3 base address */ |
| #define UART3_BASE (0x421EC000u) |
| /** Peripheral UART3 base pointer */ |
| #define UART3 ((UART_Type *)UART3_BASE) |
| #define UART3_BASE_PTR (UART3) |
| /** Peripheral UART4 base address */ |
| #define UART4_BASE (0x421F0000u) |
| /** Peripheral UART4 base pointer */ |
| #define UART4 ((UART_Type *)UART4_BASE) |
| #define UART4_BASE_PTR (UART4) |
| /** Peripheral UART5 base address */ |
| #define UART5_BASE (0x421F4000u) |
| /** Peripheral UART5 base pointer */ |
| #define UART5 ((UART_Type *)UART5_BASE) |
| #define UART5_BASE_PTR (UART5) |
| /** Peripheral UART6 base address */ |
| #define UART6_BASE (0x422A0000u) |
| /** Peripheral UART6 base pointer */ |
| #define UART6 ((UART_Type *)UART6_BASE) |
| #define UART6_BASE_PTR (UART6) |
| /** Array initializer of UART peripheral base addresses */ |
| #define UART_BASE_ADDRS { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE } |
| /** Array initializer of UART peripheral base pointers */ |
| #define UART_BASE_PTRS { UART1, UART2, UART3, UART4, UART5, UART6 } |
| /** Interrupt vectors for the UART peripheral type */ |
| #define UART_IRQS { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- UART - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros |
| * @{ |
| */ |
| |
| /* UART - Register instance definitions */ |
| /* UART1 */ |
| #define UART1_URXD UART_URXD_REG(UART1_BASE_PTR) |
| #define UART1_UTXD UART_UTXD_REG(UART1_BASE_PTR) |
| #define UART1_UCR1 UART_UCR1_REG(UART1_BASE_PTR) |
| #define UART1_UCR2 UART_UCR2_REG(UART1_BASE_PTR) |
| #define UART1_UCR3 UART_UCR3_REG(UART1_BASE_PTR) |
| #define UART1_UCR4 UART_UCR4_REG(UART1_BASE_PTR) |
| #define UART1_UFCR UART_UFCR_REG(UART1_BASE_PTR) |
| #define UART1_USR1 UART_USR1_REG(UART1_BASE_PTR) |
| #define UART1_USR2 UART_USR2_REG(UART1_BASE_PTR) |
| #define UART1_UESC UART_UESC_REG(UART1_BASE_PTR) |
| #define UART1_UTIM UART_UTIM_REG(UART1_BASE_PTR) |
| #define UART1_UBIR UART_UBIR_REG(UART1_BASE_PTR) |
| #define UART1_UBMR UART_UBMR_REG(UART1_BASE_PTR) |
| #define UART1_UBRC UART_UBRC_REG(UART1_BASE_PTR) |
| #define UART1_ONEMS UART_ONEMS_REG(UART1_BASE_PTR) |
| #define UART1_UTS UART_UTS_REG(UART1_BASE_PTR) |
| #define UART1_UMCR UART_UMCR_REG(UART1_BASE_PTR) |
| /* UART2 */ |
| #define UART2_URXD UART_URXD_REG(UART2_BASE_PTR) |
| #define UART2_UTXD UART_UTXD_REG(UART2_BASE_PTR) |
| #define UART2_UCR1 UART_UCR1_REG(UART2_BASE_PTR) |
| #define UART2_UCR2 UART_UCR2_REG(UART2_BASE_PTR) |
| #define UART2_UCR3 UART_UCR3_REG(UART2_BASE_PTR) |
| #define UART2_UCR4 UART_UCR4_REG(UART2_BASE_PTR) |
| #define UART2_UFCR UART_UFCR_REG(UART2_BASE_PTR) |
| #define UART2_USR1 UART_USR1_REG(UART2_BASE_PTR) |
| #define UART2_USR2 UART_USR2_REG(UART2_BASE_PTR) |
| #define UART2_UESC UART_UESC_REG(UART2_BASE_PTR) |
| #define UART2_UTIM UART_UTIM_REG(UART2_BASE_PTR) |
| #define UART2_UBIR UART_UBIR_REG(UART2_BASE_PTR) |
| #define UART2_UBMR UART_UBMR_REG(UART2_BASE_PTR) |
| #define UART2_UBRC UART_UBRC_REG(UART2_BASE_PTR) |
| #define UART2_ONEMS UART_ONEMS_REG(UART2_BASE_PTR) |
| #define UART2_UTS UART_UTS_REG(UART2_BASE_PTR) |
| #define UART2_UMCR UART_UMCR_REG(UART2_BASE_PTR) |
| /* UART3 */ |
| #define UART3_URXD UART_URXD_REG(UART3_BASE_PTR) |
| #define UART3_UTXD UART_UTXD_REG(UART3_BASE_PTR) |
| #define UART3_UCR1 UART_UCR1_REG(UART3_BASE_PTR) |
| #define UART3_UCR2 UART_UCR2_REG(UART3_BASE_PTR) |
| #define UART3_UCR3 UART_UCR3_REG(UART3_BASE_PTR) |
| #define UART3_UCR4 UART_UCR4_REG(UART3_BASE_PTR) |
| #define UART3_UFCR UART_UFCR_REG(UART3_BASE_PTR) |
| #define UART3_USR1 UART_USR1_REG(UART3_BASE_PTR) |
| #define UART3_USR2 UART_USR2_REG(UART3_BASE_PTR) |
| #define UART3_UESC UART_UESC_REG(UART3_BASE_PTR) |
| #define UART3_UTIM UART_UTIM_REG(UART3_BASE_PTR) |
| #define UART3_UBIR UART_UBIR_REG(UART3_BASE_PTR) |
| #define UART3_UBMR UART_UBMR_REG(UART3_BASE_PTR) |
| #define UART3_UBRC UART_UBRC_REG(UART3_BASE_PTR) |
| #define UART3_ONEMS UART_ONEMS_REG(UART3_BASE_PTR) |
| #define UART3_UTS UART_UTS_REG(UART3_BASE_PTR) |
| #define UART3_UMCR UART_UMCR_REG(UART3_BASE_PTR) |
| /* UART4 */ |
| #define UART4_URXD UART_URXD_REG(UART4_BASE_PTR) |
| #define UART4_UTXD UART_UTXD_REG(UART4_BASE_PTR) |
| #define UART4_UCR1 UART_UCR1_REG(UART4_BASE_PTR) |
| #define UART4_UCR2 UART_UCR2_REG(UART4_BASE_PTR) |
| #define UART4_UCR3 UART_UCR3_REG(UART4_BASE_PTR) |
| #define UART4_UCR4 UART_UCR4_REG(UART4_BASE_PTR) |
| #define UART4_UFCR UART_UFCR_REG(UART4_BASE_PTR) |
| #define UART4_USR1 UART_USR1_REG(UART4_BASE_PTR) |
| #define UART4_USR2 UART_USR2_REG(UART4_BASE_PTR) |
| #define UART4_UESC UART_UESC_REG(UART4_BASE_PTR) |
| #define UART4_UTIM UART_UTIM_REG(UART4_BASE_PTR) |
| #define UART4_UBIR UART_UBIR_REG(UART4_BASE_PTR) |
| #define UART4_UBMR UART_UBMR_REG(UART4_BASE_PTR) |
| #define UART4_UBRC UART_UBRC_REG(UART4_BASE_PTR) |
| #define UART4_ONEMS UART_ONEMS_REG(UART4_BASE_PTR) |
| #define UART4_UTS UART_UTS_REG(UART4_BASE_PTR) |
| #define UART4_UMCR UART_UMCR_REG(UART4_BASE_PTR) |
| /* UART5 */ |
| #define UART5_URXD UART_URXD_REG(UART5_BASE_PTR) |
| #define UART5_UTXD UART_UTXD_REG(UART5_BASE_PTR) |
| #define UART5_UCR1 UART_UCR1_REG(UART5_BASE_PTR) |
| #define UART5_UCR2 UART_UCR2_REG(UART5_BASE_PTR) |
| #define UART5_UCR3 UART_UCR3_REG(UART5_BASE_PTR) |
| #define UART5_UCR4 UART_UCR4_REG(UART5_BASE_PTR) |
| #define UART5_UFCR UART_UFCR_REG(UART5_BASE_PTR) |
| #define UART5_USR1 UART_USR1_REG(UART5_BASE_PTR) |
| #define UART5_USR2 UART_USR2_REG(UART5_BASE_PTR) |
| #define UART5_UESC UART_UESC_REG(UART5_BASE_PTR) |
| #define UART5_UTIM UART_UTIM_REG(UART5_BASE_PTR) |
| #define UART5_UBIR UART_UBIR_REG(UART5_BASE_PTR) |
| #define UART5_UBMR UART_UBMR_REG(UART5_BASE_PTR) |
| #define UART5_UBRC UART_UBRC_REG(UART5_BASE_PTR) |
| #define UART5_ONEMS UART_ONEMS_REG(UART5_BASE_PTR) |
| #define UART5_UTS UART_UTS_REG(UART5_BASE_PTR) |
| #define UART5_UMCR UART_UMCR_REG(UART5_BASE_PTR) |
| /* UART6 */ |
| #define UART6_URXD UART_URXD_REG(UART6_BASE_PTR) |
| #define UART6_UTXD UART_UTXD_REG(UART6_BASE_PTR) |
| #define UART6_UCR1 UART_UCR1_REG(UART6_BASE_PTR) |
| #define UART6_UCR2 UART_UCR2_REG(UART6_BASE_PTR) |
| #define UART6_UCR3 UART_UCR3_REG(UART6_BASE_PTR) |
| #define UART6_UCR4 UART_UCR4_REG(UART6_BASE_PTR) |
| #define UART6_UFCR UART_UFCR_REG(UART6_BASE_PTR) |
| #define UART6_USR1 UART_USR1_REG(UART6_BASE_PTR) |
| #define UART6_USR2 UART_USR2_REG(UART6_BASE_PTR) |
| #define UART6_UESC UART_UESC_REG(UART6_BASE_PTR) |
| #define UART6_UTIM UART_UTIM_REG(UART6_BASE_PTR) |
| #define UART6_UBIR UART_UBIR_REG(UART6_BASE_PTR) |
| #define UART6_UBMR UART_UBMR_REG(UART6_BASE_PTR) |
| #define UART6_UBRC UART_UBRC_REG(UART6_BASE_PTR) |
| #define UART6_ONEMS UART_ONEMS_REG(UART6_BASE_PTR) |
| #define UART6_UTS UART_UTS_REG(UART6_BASE_PTR) |
| #define UART6_UMCR UART_UMCR_REG(UART6_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group UART_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group UART_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBC_Peripheral_Access_Layer USBC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** USBC - Register Layout Typedef */ |
| typedef struct { |
| __I uint32_t UOG1_ID; /**< Identification register, offset: 0x0 */ |
| __I uint32_t UOG1_HWGENERAL; /**< Hardware General, offset: 0x4 */ |
| __I uint32_t UOG1_HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ |
| __I uint32_t UOG1_HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ |
| __I uint32_t UOG1_HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ |
| __I uint32_t UOG1_HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ |
| uint8_t RESERVED_0[104]; |
| __IO uint32_t UOG1_GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ |
| __IO uint32_t UOG1_GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ |
| __IO uint32_t UOG1_GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ |
| __IO uint32_t UOG1_GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ |
| __IO uint32_t UOG1_SBUSCFG; /**< System Bus Config, offset: 0x90 */ |
| uint8_t RESERVED_1[108]; |
| __I uint8_t UOG1_CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ |
| uint8_t RESERVED_2[1]; |
| __I uint16_t UOG1_HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ |
| __I uint32_t UOG1_HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ |
| __I uint32_t UOG1_HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ |
| uint8_t RESERVED_3[20]; |
| __I uint16_t UOG1_DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ |
| uint8_t RESERVED_4[2]; |
| __I uint32_t UOG1_DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ |
| uint8_t RESERVED_5[24]; |
| __IO uint32_t UOG1_USBCMD; /**< USB Command Register, offset: 0x140 */ |
| __IO uint32_t UOG1_USBSTS; /**< USB Status Register, offset: 0x144 */ |
| __IO uint32_t UOG1_USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ |
| __IO uint32_t UOG1_FRINDEX; /**< USB Frame Index, offset: 0x14C */ |
| uint8_t RESERVED_6[4]; |
| union { /* offset: 0x154 */ |
| __IO uint32_t UOG1_PERIODICLISTBASE; /**< Frame List Base Address,offset: 0x154 */ |
| __IO uint32_t UOG1_DEVICEADDR; /**< Device Address,offset: 0x154 */ |
| struct { /* offset: 0x158 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t UOG1_ASYNCLISTADDR; /**< Next Asynch. Address,offset: 0x158 */ |
| } UOG1_ASYNCLISTADDR; |
| struct { /* offset: 0x158 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t UOG1_ENDPTLISTADDR; /**< Endpoint List Address,offset: 0x158 */ |
| } UOG1_ENDPTLISTADDR; |
| }; |
| uint8_t RESERVED_7[4]; |
| __IO uint32_t UOG1_BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ |
| __IO uint32_t UOG1_TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ |
| uint8_t RESERVED_8[16]; |
| __IO uint32_t UOG1_ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ |
| __IO uint32_t UOG1_ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ |
| __IO uint32_t UOG1_CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ |
| __IO uint32_t UOG1_PORTSC1; /**< Port Status & Control, offset: 0x184 */ |
| uint8_t RESERVED_9[28]; |
| __IO uint32_t UOG1_OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ |
| __IO uint32_t UOG1_USBMODE; /**< USB Device Mode, offset: 0x1A8 */ |
| __IO uint32_t UOG1_ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ |
| __IO uint32_t UOG1_ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ |
| __IO uint32_t UOG1_ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ |
| __I uint32_t UOG1_ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ |
| __IO uint32_t UOG1_ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ |
| __IO uint32_t UOG1_ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ |
| __IO uint32_t UOG1_ENDPTCTRL1; /**< Endpoint Control 1, offset: 0x1C4 */ |
| __IO uint32_t UOG1_ENDPTCTRL2; /**< Endpoint Control 2, offset: 0x1C8 */ |
| __IO uint32_t UOG1_ENDPTCTRL3; /**< Endpoint Control 3, offset: 0x1CC */ |
| __IO uint32_t UOG1_ENDPTCTRL4; /**< Endpoint Control 4, offset: 0x1D0 */ |
| __IO uint32_t UOG1_ENDPTCTRL5; /**< Endpoint Control 5, offset: 0x1D4 */ |
| __IO uint32_t UOG1_ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x1D8 */ |
| __IO uint32_t UOG1_ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x1DC */ |
| uint8_t RESERVED_10[32]; |
| __I uint32_t UOG2_ID; /**< Identification register, offset: 0x200 */ |
| __I uint32_t UOG2_HWGENERAL; /**< Hardware General, offset: 0x204 */ |
| __I uint32_t UOG2_HWHOST; /**< Host Hardware Parameters, offset: 0x208 */ |
| __I uint32_t UOG2_HWDEVICE; /**< Device Hardware Parameters, offset: 0x20C */ |
| __I uint32_t UOG2_HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x210 */ |
| __I uint32_t UOG2_HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x214 */ |
| uint8_t RESERVED_11[104]; |
| __IO uint32_t UOG2_GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x280 */ |
| __IO uint32_t UOG2_GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x284 */ |
| __IO uint32_t UOG2_GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x288 */ |
| __IO uint32_t UOG2_GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x28C */ |
| __IO uint32_t UOG2_SBUSCFG; /**< System Bus Config, offset: 0x290 */ |
| uint8_t RESERVED_12[108]; |
| __I uint8_t UOG2_CAPLENGTH; /**< Capability Registers Length, offset: 0x300 */ |
| uint8_t RESERVED_13[1]; |
| __I uint16_t UOG2_HCIVERSION; /**< Host Controller Interface Version, offset: 0x302 */ |
| __I uint32_t UOG2_HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x304 */ |
| __I uint32_t UOG2_HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x308 */ |
| uint8_t RESERVED_14[20]; |
| __I uint16_t UOG2_DCIVERSION; /**< Device Controller Interface Version, offset: 0x320 */ |
| uint8_t RESERVED_15[2]; |
| __I uint32_t UOG2_DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x324 */ |
| uint8_t RESERVED_16[24]; |
| __IO uint32_t UOG2_USBCMD; /**< USB Command Register, offset: 0x340 */ |
| __IO uint32_t UOG2_USBSTS; /**< USB Status Register, offset: 0x344 */ |
| __IO uint32_t UOG2_USBINTR; /**< Interrupt Enable Register, offset: 0x348 */ |
| __IO uint32_t UOG2_FRINDEX; /**< USB Frame Index, offset: 0x34C */ |
| uint8_t RESERVED_17[4]; |
| union { /* offset: 0x354 */ |
| __IO uint32_t UOG2_PERIODICLISTBASE; /**< Frame List Base Address,offset: 0x354 */ |
| __IO uint32_t UOG2_DEVICEADDR; /**< Device Address,offset: 0x354 */ |
| struct { /* offset: 0x358 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t UOG2_ASYNCLISTADDR; /**< Next Asynch. Address,offset: 0x358 */ |
| } UOG2_ASYNCLISTADDR; |
| struct { /* offset: 0x358 */ |
| uint8_t RESERVED_0[4]; |
| __IO uint32_t UOG2_ENDPTLISTADDR; /**< Endpoint List Address,offset: 0x358 */ |
| } UOG2_ENDPTLISTADDR; |
| }; |
| uint8_t RESERVED_18[4]; |
| __IO uint32_t UOG2_BURSTSIZE; /**< Programmable Burst Size, offset: 0x360 */ |
| __IO uint32_t UOG2_TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x364 */ |
| uint8_t RESERVED_19[16]; |
| __IO uint32_t UOG2_ENDPTNAK; /**< Endpoint NAK, offset: 0x378 */ |
| __IO uint32_t UOG2_ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x37C */ |
| __IO uint32_t UOG2_CONFIGFLAG; /**< Configure Flag Register, offset: 0x380 */ |
| __IO uint32_t UOG2_PORTSC1; /**< Port Status & Control, offset: 0x384 */ |
| uint8_t RESERVED_20[28]; |
| __IO uint32_t UOG2_OTGSC; /**< On-The-Go Status & control, offset: 0x3A4 */ |
| __IO uint32_t UOG2_USBMODE; /**< USB Device Mode, offset: 0x3A8 */ |
| __IO uint32_t UOG2_ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x3AC */ |
| __IO uint32_t UOG2_ENDPTPRIME; /**< Endpoint Prime, offset: 0x3B0 */ |
| __IO uint32_t UOG2_ENDPTFLUSH; /**< Endpoint Flush, offset: 0x3B4 */ |
| __I uint32_t UOG2_ENDPTSTAT; /**< Endpoint Status, offset: 0x3B8 */ |
| __IO uint32_t UOG2_ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x3BC */ |
| __IO uint32_t UOG2_ENDPTCTRL0; /**< Endpoint Control0, offset: 0x3C0 */ |
| __IO uint32_t UOG2_ENDPTCTRL1; /**< Endpoint Control 1, offset: 0x3C4 */ |
| __IO uint32_t UOG2_ENDPTCTRL2; /**< Endpoint Control 2, offset: 0x3C8 */ |
| __IO uint32_t UOG2_ENDPTCTRL3; /**< Endpoint Control 3, offset: 0x3CC */ |
| __IO uint32_t UOG2_ENDPTCTRL4; /**< Endpoint Control 4, offset: 0x3D0 */ |
| __IO uint32_t UOG2_ENDPTCTRL5; /**< Endpoint Control 5, offset: 0x3D4 */ |
| __IO uint32_t UOG2_ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x3D8 */ |
| __IO uint32_t UOG2_ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x3DC */ |
| uint8_t RESERVED_21[32]; |
| __I uint32_t UH1_ID; /**< Identification register, offset: 0x400 */ |
| __I uint32_t UH1_HWGENERAL; /**< Hardware General, offset: 0x404 */ |
| __I uint32_t UH1_HWHOST; /**< Host Hardware Parameters, offset: 0x408 */ |
| uint8_t RESERVED_22[4]; |
| __I uint32_t UH1_HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x410 */ |
| __I uint32_t UH1_HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x414 */ |
| uint8_t RESERVED_23[104]; |
| __IO uint32_t UH1_GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x480 */ |
| __IO uint32_t UH1_GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x484 */ |
| __IO uint32_t UH1_GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x488 */ |
| __IO uint32_t UH1_GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x48C */ |
| __IO uint32_t UH1_SBUSCFG; /**< System Bus Config, offset: 0x490 */ |
| uint8_t RESERVED_24[108]; |
| __I uint8_t UH1_CAPLENGTH; /**< Capability Registers Length, offset: 0x500 */ |
| uint8_t RESERVED_25[1]; |
| __I uint16_t UH1_HCIVERSION; /**< Host Controller Interface Version, offset: 0x502 */ |
| __I uint32_t UH1_HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x504 */ |
| __I uint32_t UH1_HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x508 */ |
| uint8_t RESERVED_26[52]; |
| __IO uint32_t UH1_USBCMD; /**< USB Command Register, offset: 0x540 */ |
| __IO uint32_t UH1_USBSTS; /**< USB Status Register, offset: 0x544 */ |
| __IO uint32_t UH1_USBINTR; /**< Interrupt Enable Register, offset: 0x548 */ |
| __IO uint32_t UH1_FRINDEX; /**< USB Frame Index, offset: 0x54C */ |
| uint8_t RESERVED_27[4]; |
| __IO uint32_t UH1_PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x554 */ |
| __IO uint32_t UH1_ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x558 */ |
| uint8_t RESERVED_28[4]; |
| __IO uint32_t UH1_BURSTSIZE; /**< Programmable Burst Size, offset: 0x560 */ |
| __IO uint32_t UH1_TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x564 */ |
| uint8_t RESERVED_29[24]; |
| __IO uint32_t UH1_CONFIGFLAG; /**< Configure Flag Register, offset: 0x580 */ |
| __IO uint32_t UH1_PORTSC1; /**< Port Status & Control, offset: 0x584 */ |
| uint8_t RESERVED_30[32]; |
| __IO uint32_t UH1_USBMODE; /**< USB Device Mode, offset: 0x5A8 */ |
| } USBC_Type, *USBC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBC_Register_Accessor_Macros USBC - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBC - Register accessors */ |
| #define USBC_UOG1_ID_REG(base) ((base)->UOG1_ID) |
| #define USBC_UOG1_HWGENERAL_REG(base) ((base)->UOG1_HWGENERAL) |
| #define USBC_UOG1_HWHOST_REG(base) ((base)->UOG1_HWHOST) |
| #define USBC_UOG1_HWDEVICE_REG(base) ((base)->UOG1_HWDEVICE) |
| #define USBC_UOG1_HWTXBUF_REG(base) ((base)->UOG1_HWTXBUF) |
| #define USBC_UOG1_HWRXBUF_REG(base) ((base)->UOG1_HWRXBUF) |
| #define USBC_UOG1_GPTIMER0LD_REG(base) ((base)->UOG1_GPTIMER0LD) |
| #define USBC_UOG1_GPTIMER0CTRL_REG(base) ((base)->UOG1_GPTIMER0CTRL) |
| #define USBC_UOG1_GPTIMER1LD_REG(base) ((base)->UOG1_GPTIMER1LD) |
| #define USBC_UOG1_GPTIMER1CTRL_REG(base) ((base)->UOG1_GPTIMER1CTRL) |
| #define USBC_UOG1_SBUSCFG_REG(base) ((base)->UOG1_SBUSCFG) |
| #define USBC_UOG1_CAPLENGTH_REG(base) ((base)->UOG1_CAPLENGTH) |
| #define USBC_UOG1_HCIVERSION_REG(base) ((base)->UOG1_HCIVERSION) |
| #define USBC_UOG1_HCSPARAMS_REG(base) ((base)->UOG1_HCSPARAMS) |
| #define USBC_UOG1_HCCPARAMS_REG(base) ((base)->UOG1_HCCPARAMS) |
| #define USBC_UOG1_DCIVERSION_REG(base) ((base)->UOG1_DCIVERSION) |
| #define USBC_UOG1_DCCPARAMS_REG(base) ((base)->UOG1_DCCPARAMS) |
| #define USBC_UOG1_USBCMD_REG(base) ((base)->UOG1_USBCMD) |
| #define USBC_UOG1_USBSTS_REG(base) ((base)->UOG1_USBSTS) |
| #define USBC_UOG1_USBINTR_REG(base) ((base)->UOG1_USBINTR) |
| #define USBC_UOG1_FRINDEX_REG(base) ((base)->UOG1_FRINDEX) |
| #define USBC_UOG1_PERIODICLISTBASE_REG(base) ((base)->UOG1_PERIODICLISTBASE) |
| #define USBC_UOG1_DEVICEADDR_REG(base) ((base)->UOG1_DEVICEADDR) |
| #define USBC_UOG1_ASYNCLISTADDR_REG(base) ((base)->UOG1_ASYNCLISTADDR.UOG1_ASYNCLISTADDR) |
| #define USBC_UOG1_ENDPTLISTADDR_REG(base) ((base)->UOG1_ENDPTLISTADDR.UOG1_ENDPTLISTADDR) |
| #define USBC_UOG1_BURSTSIZE_REG(base) ((base)->UOG1_BURSTSIZE) |
| #define USBC_UOG1_TXFILLTUNING_REG(base) ((base)->UOG1_TXFILLTUNING) |
| #define USBC_UOG1_ENDPTNAK_REG(base) ((base)->UOG1_ENDPTNAK) |
| #define USBC_UOG1_ENDPTNAKEN_REG(base) ((base)->UOG1_ENDPTNAKEN) |
| #define USBC_UOG1_CONFIGFLAG_REG(base) ((base)->UOG1_CONFIGFLAG) |
| #define USBC_UOG1_PORTSC1_REG(base) ((base)->UOG1_PORTSC1) |
| #define USBC_UOG1_OTGSC_REG(base) ((base)->UOG1_OTGSC) |
| #define USBC_UOG1_USBMODE_REG(base) ((base)->UOG1_USBMODE) |
| #define USBC_UOG1_ENDPTSETUPSTAT_REG(base) ((base)->UOG1_ENDPTSETUPSTAT) |
| #define USBC_UOG1_ENDPTPRIME_REG(base) ((base)->UOG1_ENDPTPRIME) |
| #define USBC_UOG1_ENDPTFLUSH_REG(base) ((base)->UOG1_ENDPTFLUSH) |
| #define USBC_UOG1_ENDPTSTAT_REG(base) ((base)->UOG1_ENDPTSTAT) |
| #define USBC_UOG1_ENDPTCOMPLETE_REG(base) ((base)->UOG1_ENDPTCOMPLETE) |
| #define USBC_UOG1_ENDPTCTRL0_REG(base) ((base)->UOG1_ENDPTCTRL0) |
| #define USBC_UOG1_ENDPTCTRL1_REG(base) ((base)->UOG1_ENDPTCTRL1) |
| #define USBC_UOG1_ENDPTCTRL2_REG(base) ((base)->UOG1_ENDPTCTRL2) |
| #define USBC_UOG1_ENDPTCTRL3_REG(base) ((base)->UOG1_ENDPTCTRL3) |
| #define USBC_UOG1_ENDPTCTRL4_REG(base) ((base)->UOG1_ENDPTCTRL4) |
| #define USBC_UOG1_ENDPTCTRL5_REG(base) ((base)->UOG1_ENDPTCTRL5) |
| #define USBC_UOG1_ENDPTCTRL6_REG(base) ((base)->UOG1_ENDPTCTRL6) |
| #define USBC_UOG1_ENDPTCTRL7_REG(base) ((base)->UOG1_ENDPTCTRL7) |
| #define USBC_UOG2_ID_REG(base) ((base)->UOG2_ID) |
| #define USBC_UOG2_HWGENERAL_REG(base) ((base)->UOG2_HWGENERAL) |
| #define USBC_UOG2_HWHOST_REG(base) ((base)->UOG2_HWHOST) |
| #define USBC_UOG2_HWDEVICE_REG(base) ((base)->UOG2_HWDEVICE) |
| #define USBC_UOG2_HWTXBUF_REG(base) ((base)->UOG2_HWTXBUF) |
| #define USBC_UOG2_HWRXBUF_REG(base) ((base)->UOG2_HWRXBUF) |
| #define USBC_UOG2_GPTIMER0LD_REG(base) ((base)->UOG2_GPTIMER0LD) |
| #define USBC_UOG2_GPTIMER0CTRL_REG(base) ((base)->UOG2_GPTIMER0CTRL) |
| #define USBC_UOG2_GPTIMER1LD_REG(base) ((base)->UOG2_GPTIMER1LD) |
| #define USBC_UOG2_GPTIMER1CTRL_REG(base) ((base)->UOG2_GPTIMER1CTRL) |
| #define USBC_UOG2_SBUSCFG_REG(base) ((base)->UOG2_SBUSCFG) |
| #define USBC_UOG2_CAPLENGTH_REG(base) ((base)->UOG2_CAPLENGTH) |
| #define USBC_UOG2_HCIVERSION_REG(base) ((base)->UOG2_HCIVERSION) |
| #define USBC_UOG2_HCSPARAMS_REG(base) ((base)->UOG2_HCSPARAMS) |
| #define USBC_UOG2_HCCPARAMS_REG(base) ((base)->UOG2_HCCPARAMS) |
| #define USBC_UOG2_DCIVERSION_REG(base) ((base)->UOG2_DCIVERSION) |
| #define USBC_UOG2_DCCPARAMS_REG(base) ((base)->UOG2_DCCPARAMS) |
| #define USBC_UOG2_USBCMD_REG(base) ((base)->UOG2_USBCMD) |
| #define USBC_UOG2_USBSTS_REG(base) ((base)->UOG2_USBSTS) |
| #define USBC_UOG2_USBINTR_REG(base) ((base)->UOG2_USBINTR) |
| #define USBC_UOG2_FRINDEX_REG(base) ((base)->UOG2_FRINDEX) |
| #define USBC_UOG2_PERIODICLISTBASE_REG(base) ((base)->UOG2_PERIODICLISTBASE) |
| #define USBC_UOG2_DEVICEADDR_REG(base) ((base)->UOG2_DEVICEADDR) |
| #define USBC_UOG2_ASYNCLISTADDR_REG(base) ((base)->UOG2_ASYNCLISTADDR.UOG2_ASYNCLISTADDR) |
| #define USBC_UOG2_ENDPTLISTADDR_REG(base) ((base)->UOG2_ENDPTLISTADDR.UOG2_ENDPTLISTADDR) |
| #define USBC_UOG2_BURSTSIZE_REG(base) ((base)->UOG2_BURSTSIZE) |
| #define USBC_UOG2_TXFILLTUNING_REG(base) ((base)->UOG2_TXFILLTUNING) |
| #define USBC_UOG2_ENDPTNAK_REG(base) ((base)->UOG2_ENDPTNAK) |
| #define USBC_UOG2_ENDPTNAKEN_REG(base) ((base)->UOG2_ENDPTNAKEN) |
| #define USBC_UOG2_CONFIGFLAG_REG(base) ((base)->UOG2_CONFIGFLAG) |
| #define USBC_UOG2_PORTSC1_REG(base) ((base)->UOG2_PORTSC1) |
| #define USBC_UOG2_OTGSC_REG(base) ((base)->UOG2_OTGSC) |
| #define USBC_UOG2_USBMODE_REG(base) ((base)->UOG2_USBMODE) |
| #define USBC_UOG2_ENDPTSETUPSTAT_REG(base) ((base)->UOG2_ENDPTSETUPSTAT) |
| #define USBC_UOG2_ENDPTPRIME_REG(base) ((base)->UOG2_ENDPTPRIME) |
| #define USBC_UOG2_ENDPTFLUSH_REG(base) ((base)->UOG2_ENDPTFLUSH) |
| #define USBC_UOG2_ENDPTSTAT_REG(base) ((base)->UOG2_ENDPTSTAT) |
| #define USBC_UOG2_ENDPTCOMPLETE_REG(base) ((base)->UOG2_ENDPTCOMPLETE) |
| #define USBC_UOG2_ENDPTCTRL0_REG(base) ((base)->UOG2_ENDPTCTRL0) |
| #define USBC_UOG2_ENDPTCTRL1_REG(base) ((base)->UOG2_ENDPTCTRL1) |
| #define USBC_UOG2_ENDPTCTRL2_REG(base) ((base)->UOG2_ENDPTCTRL2) |
| #define USBC_UOG2_ENDPTCTRL3_REG(base) ((base)->UOG2_ENDPTCTRL3) |
| #define USBC_UOG2_ENDPTCTRL4_REG(base) ((base)->UOG2_ENDPTCTRL4) |
| #define USBC_UOG2_ENDPTCTRL5_REG(base) ((base)->UOG2_ENDPTCTRL5) |
| #define USBC_UOG2_ENDPTCTRL6_REG(base) ((base)->UOG2_ENDPTCTRL6) |
| #define USBC_UOG2_ENDPTCTRL7_REG(base) ((base)->UOG2_ENDPTCTRL7) |
| #define USBC_UH1_ID_REG(base) ((base)->UH1_ID) |
| #define USBC_UH1_HWGENERAL_REG(base) ((base)->UH1_HWGENERAL) |
| #define USBC_UH1_HWHOST_REG(base) ((base)->UH1_HWHOST) |
| #define USBC_UH1_HWTXBUF_REG(base) ((base)->UH1_HWTXBUF) |
| #define USBC_UH1_HWRXBUF_REG(base) ((base)->UH1_HWRXBUF) |
| #define USBC_UH1_GPTIMER0LD_REG(base) ((base)->UH1_GPTIMER0LD) |
| #define USBC_UH1_GPTIMER0CTRL_REG(base) ((base)->UH1_GPTIMER0CTRL) |
| #define USBC_UH1_GPTIMER1LD_REG(base) ((base)->UH1_GPTIMER1LD) |
| #define USBC_UH1_GPTIMER1CTRL_REG(base) ((base)->UH1_GPTIMER1CTRL) |
| #define USBC_UH1_SBUSCFG_REG(base) ((base)->UH1_SBUSCFG) |
| #define USBC_UH1_CAPLENGTH_REG(base) ((base)->UH1_CAPLENGTH) |
| #define USBC_UH1_HCIVERSION_REG(base) ((base)->UH1_HCIVERSION) |
| #define USBC_UH1_HCSPARAMS_REG(base) ((base)->UH1_HCSPARAMS) |
| #define USBC_UH1_HCCPARAMS_REG(base) ((base)->UH1_HCCPARAMS) |
| #define USBC_UH1_USBCMD_REG(base) ((base)->UH1_USBCMD) |
| #define USBC_UH1_USBSTS_REG(base) ((base)->UH1_USBSTS) |
| #define USBC_UH1_USBINTR_REG(base) ((base)->UH1_USBINTR) |
| #define USBC_UH1_FRINDEX_REG(base) ((base)->UH1_FRINDEX) |
| #define USBC_UH1_PERIODICLISTBASE_REG(base) ((base)->UH1_PERIODICLISTBASE) |
| #define USBC_UH1_ASYNCLISTADDR_REG(base) ((base)->UH1_ASYNCLISTADDR) |
| #define USBC_UH1_BURSTSIZE_REG(base) ((base)->UH1_BURSTSIZE) |
| #define USBC_UH1_TXFILLTUNING_REG(base) ((base)->UH1_TXFILLTUNING) |
| #define USBC_UH1_CONFIGFLAG_REG(base) ((base)->UH1_CONFIGFLAG) |
| #define USBC_UH1_PORTSC1_REG(base) ((base)->UH1_PORTSC1) |
| #define USBC_UH1_USBMODE_REG(base) ((base)->UH1_USBMODE) |
| |
| /*! |
| * @} |
| */ /* end of group USBC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBC_Register_Masks USBC Register Masks |
| * @{ |
| */ |
| |
| /* UOG1_ID Bit Fields */ |
| #define USBC_UOG1_ID_ID_MASK 0x3Fu |
| #define USBC_UOG1_ID_ID_SHIFT 0 |
| #define USBC_UOG1_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_ID_SHIFT))&USBC_UOG1_ID_ID_MASK) |
| #define USBC_UOG1_ID_NID_MASK 0x3F00u |
| #define USBC_UOG1_ID_NID_SHIFT 8 |
| #define USBC_UOG1_ID_NID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_NID_SHIFT))&USBC_UOG1_ID_NID_MASK) |
| #define USBC_UOG1_ID_REVISION_MASK 0xFF0000u |
| #define USBC_UOG1_ID_REVISION_SHIFT 16 |
| #define USBC_UOG1_ID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ID_REVISION_SHIFT))&USBC_UOG1_ID_REVISION_MASK) |
| /* UOG1_HWGENERAL Bit Fields */ |
| #define USBC_UOG1_HWGENERAL_PHYW_MASK 0x30u |
| #define USBC_UOG1_HWGENERAL_PHYW_SHIFT 4 |
| #define USBC_UOG1_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_PHYW_SHIFT))&USBC_UOG1_HWGENERAL_PHYW_MASK) |
| #define USBC_UOG1_HWGENERAL_PHYM_MASK 0x1C0u |
| #define USBC_UOG1_HWGENERAL_PHYM_SHIFT 6 |
| #define USBC_UOG1_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_PHYM_SHIFT))&USBC_UOG1_HWGENERAL_PHYM_MASK) |
| #define USBC_UOG1_HWGENERAL_SM_MASK 0x600u |
| #define USBC_UOG1_HWGENERAL_SM_SHIFT 9 |
| #define USBC_UOG1_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWGENERAL_SM_SHIFT))&USBC_UOG1_HWGENERAL_SM_MASK) |
| /* UOG1_HWHOST Bit Fields */ |
| #define USBC_UOG1_HWHOST_HC_MASK 0x1u |
| #define USBC_UOG1_HWHOST_HC_SHIFT 0 |
| #define USBC_UOG1_HWHOST_NPORT_MASK 0xEu |
| #define USBC_UOG1_HWHOST_NPORT_SHIFT 1 |
| #define USBC_UOG1_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWHOST_NPORT_SHIFT))&USBC_UOG1_HWHOST_NPORT_MASK) |
| /* UOG1_HWDEVICE Bit Fields */ |
| #define USBC_UOG1_HWDEVICE_DC_MASK 0x1u |
| #define USBC_UOG1_HWDEVICE_DC_SHIFT 0 |
| #define USBC_UOG1_HWDEVICE_DEVEP_MASK 0x3Eu |
| #define USBC_UOG1_HWDEVICE_DEVEP_SHIFT 1 |
| #define USBC_UOG1_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWDEVICE_DEVEP_SHIFT))&USBC_UOG1_HWDEVICE_DEVEP_MASK) |
| /* UOG1_HWTXBUF Bit Fields */ |
| #define USBC_UOG1_HWTXBUF_TXBURST_MASK 0xFFu |
| #define USBC_UOG1_HWTXBUF_TXBURST_SHIFT 0 |
| #define USBC_UOG1_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWTXBUF_TXBURST_SHIFT))&USBC_UOG1_HWTXBUF_TXBURST_MASK) |
| #define USBC_UOG1_HWTXBUF_TXCHANADD_MASK 0xFF0000u |
| #define USBC_UOG1_HWTXBUF_TXCHANADD_SHIFT 16 |
| #define USBC_UOG1_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWTXBUF_TXCHANADD_SHIFT))&USBC_UOG1_HWTXBUF_TXCHANADD_MASK) |
| /* UOG1_HWRXBUF Bit Fields */ |
| #define USBC_UOG1_HWRXBUF_RXBURST_MASK 0xFFu |
| #define USBC_UOG1_HWRXBUF_RXBURST_SHIFT 0 |
| #define USBC_UOG1_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWRXBUF_RXBURST_SHIFT))&USBC_UOG1_HWRXBUF_RXBURST_MASK) |
| #define USBC_UOG1_HWRXBUF_RXADD_MASK 0xFF00u |
| #define USBC_UOG1_HWRXBUF_RXADD_SHIFT 8 |
| #define USBC_UOG1_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HWRXBUF_RXADD_SHIFT))&USBC_UOG1_HWRXBUF_RXADD_MASK) |
| /* UOG1_GPTIMER0LD Bit Fields */ |
| #define USBC_UOG1_GPTIMER0LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UOG1_GPTIMER0LD_GPTLD_SHIFT 0 |
| #define USBC_UOG1_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER0LD_GPTLD_SHIFT))&USBC_UOG1_GPTIMER0LD_GPTLD_MASK) |
| /* UOG1_GPTIMER0CTRL Bit Fields */ |
| #define USBC_UOG1_GPTIMER0CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UOG1_GPTIMER0CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UOG1_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UOG1_GPTIMER0CTRL_GPTCNT_MASK) |
| #define USBC_UOG1_GPTIMER0CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UOG1_GPTIMER0CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UOG1_GPTIMER0CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UOG1_GPTIMER0CTRL_GPTRST_SHIFT 30 |
| #define USBC_UOG1_GPTIMER0CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UOG1_GPTIMER0CTRL_GPTRUN_SHIFT 31 |
| /* UOG1_GPTIMER1LD Bit Fields */ |
| #define USBC_UOG1_GPTIMER1LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UOG1_GPTIMER1LD_GPTLD_SHIFT 0 |
| #define USBC_UOG1_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER1LD_GPTLD_SHIFT))&USBC_UOG1_GPTIMER1LD_GPTLD_MASK) |
| /* UOG1_GPTIMER1CTRL Bit Fields */ |
| #define USBC_UOG1_GPTIMER1CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UOG1_GPTIMER1CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UOG1_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UOG1_GPTIMER1CTRL_GPTCNT_MASK) |
| #define USBC_UOG1_GPTIMER1CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UOG1_GPTIMER1CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UOG1_GPTIMER1CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UOG1_GPTIMER1CTRL_GPTRST_SHIFT 30 |
| #define USBC_UOG1_GPTIMER1CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UOG1_GPTIMER1CTRL_GPTRUN_SHIFT 31 |
| /* UOG1_SBUSCFG Bit Fields */ |
| #define USBC_UOG1_SBUSCFG_AHBBRST_MASK 0x7u |
| #define USBC_UOG1_SBUSCFG_AHBBRST_SHIFT 0 |
| #define USBC_UOG1_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_SBUSCFG_AHBBRST_SHIFT))&USBC_UOG1_SBUSCFG_AHBBRST_MASK) |
| /* UOG1_CAPLENGTH Bit Fields */ |
| #define USBC_UOG1_CAPLENGTH_CAPLENGTH_MASK 0xFFu |
| #define USBC_UOG1_CAPLENGTH_CAPLENGTH_SHIFT 0 |
| #define USBC_UOG1_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x))<<USBC_UOG1_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UOG1_CAPLENGTH_CAPLENGTH_MASK) |
| /* UOG1_HCIVERSION Bit Fields */ |
| #define USBC_UOG1_HCIVERSION_HCIVERSION_MASK 0xFFFFu |
| #define USBC_UOG1_HCIVERSION_HCIVERSION_SHIFT 0 |
| #define USBC_UOG1_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBC_UOG1_HCIVERSION_HCIVERSION_SHIFT))&USBC_UOG1_HCIVERSION_HCIVERSION_MASK) |
| /* UOG1_HCSPARAMS Bit Fields */ |
| #define USBC_UOG1_HCSPARAMS_N_PORTS_MASK 0xFu |
| #define USBC_UOG1_HCSPARAMS_N_PORTS_SHIFT 0 |
| #define USBC_UOG1_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PORTS_SHIFT))&USBC_UOG1_HCSPARAMS_N_PORTS_MASK) |
| #define USBC_UOG1_HCSPARAMS_PPC_MASK 0x10u |
| #define USBC_UOG1_HCSPARAMS_PPC_SHIFT 4 |
| #define USBC_UOG1_HCSPARAMS_N_PCC_MASK 0xF00u |
| #define USBC_UOG1_HCSPARAMS_N_PCC_SHIFT 8 |
| #define USBC_UOG1_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PCC_SHIFT))&USBC_UOG1_HCSPARAMS_N_PCC_MASK) |
| #define USBC_UOG1_HCSPARAMS_N_CC_MASK 0xF000u |
| #define USBC_UOG1_HCSPARAMS_N_CC_SHIFT 12 |
| #define USBC_UOG1_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_CC_SHIFT))&USBC_UOG1_HCSPARAMS_N_CC_MASK) |
| #define USBC_UOG1_HCSPARAMS_PI_MASK 0x10000u |
| #define USBC_UOG1_HCSPARAMS_PI_SHIFT 16 |
| #define USBC_UOG1_HCSPARAMS_N_PTT_MASK 0xF00000u |
| #define USBC_UOG1_HCSPARAMS_N_PTT_SHIFT 20 |
| #define USBC_UOG1_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_PTT_SHIFT))&USBC_UOG1_HCSPARAMS_N_PTT_MASK) |
| #define USBC_UOG1_HCSPARAMS_N_TT_MASK 0xF000000u |
| #define USBC_UOG1_HCSPARAMS_N_TT_SHIFT 24 |
| #define USBC_UOG1_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCSPARAMS_N_TT_SHIFT))&USBC_UOG1_HCSPARAMS_N_TT_MASK) |
| /* UOG1_HCCPARAMS Bit Fields */ |
| #define USBC_UOG1_HCCPARAMS_ADC_MASK 0x1u |
| #define USBC_UOG1_HCCPARAMS_ADC_SHIFT 0 |
| #define USBC_UOG1_HCCPARAMS_PFL_MASK 0x2u |
| #define USBC_UOG1_HCCPARAMS_PFL_SHIFT 1 |
| #define USBC_UOG1_HCCPARAMS_ASP_MASK 0x4u |
| #define USBC_UOG1_HCCPARAMS_ASP_SHIFT 2 |
| #define USBC_UOG1_HCCPARAMS_IST_MASK 0xF0u |
| #define USBC_UOG1_HCCPARAMS_IST_SHIFT 4 |
| #define USBC_UOG1_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCCPARAMS_IST_SHIFT))&USBC_UOG1_HCCPARAMS_IST_MASK) |
| #define USBC_UOG1_HCCPARAMS_EECP_MASK 0xFF00u |
| #define USBC_UOG1_HCCPARAMS_EECP_SHIFT 8 |
| #define USBC_UOG1_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_HCCPARAMS_EECP_SHIFT))&USBC_UOG1_HCCPARAMS_EECP_MASK) |
| /* UOG1_DCIVERSION Bit Fields */ |
| #define USBC_UOG1_DCIVERSION_DCIVERSION_MASK 0xFFFFu |
| #define USBC_UOG1_DCIVERSION_DCIVERSION_SHIFT 0 |
| #define USBC_UOG1_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBC_UOG1_DCIVERSION_DCIVERSION_SHIFT))&USBC_UOG1_DCIVERSION_DCIVERSION_MASK) |
| /* UOG1_DCCPARAMS Bit Fields */ |
| #define USBC_UOG1_DCCPARAMS_DEN_MASK 0x1Fu |
| #define USBC_UOG1_DCCPARAMS_DEN_SHIFT 0 |
| #define USBC_UOG1_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_DCCPARAMS_DEN_SHIFT))&USBC_UOG1_DCCPARAMS_DEN_MASK) |
| #define USBC_UOG1_DCCPARAMS_DC_MASK 0x80u |
| #define USBC_UOG1_DCCPARAMS_DC_SHIFT 7 |
| #define USBC_UOG1_DCCPARAMS_HC_MASK 0x100u |
| #define USBC_UOG1_DCCPARAMS_HC_SHIFT 8 |
| /* UOG1_USBCMD Bit Fields */ |
| #define USBC_UOG1_USBCMD_RS_MASK 0x1u |
| #define USBC_UOG1_USBCMD_RS_SHIFT 0 |
| #define USBC_UOG1_USBCMD_RST_MASK 0x2u |
| #define USBC_UOG1_USBCMD_RST_SHIFT 1 |
| #define USBC_UOG1_USBCMD_FS_1_MASK 0xCu |
| #define USBC_UOG1_USBCMD_FS_1_SHIFT 2 |
| #define USBC_UOG1_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_FS_1_SHIFT))&USBC_UOG1_USBCMD_FS_1_MASK) |
| #define USBC_UOG1_USBCMD_PSE_MASK 0x10u |
| #define USBC_UOG1_USBCMD_PSE_SHIFT 4 |
| #define USBC_UOG1_USBCMD_ASE_MASK 0x20u |
| #define USBC_UOG1_USBCMD_ASE_SHIFT 5 |
| #define USBC_UOG1_USBCMD_IAA_MASK 0x40u |
| #define USBC_UOG1_USBCMD_IAA_SHIFT 6 |
| #define USBC_UOG1_USBCMD_ASP_MASK 0x300u |
| #define USBC_UOG1_USBCMD_ASP_SHIFT 8 |
| #define USBC_UOG1_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_ASP_SHIFT))&USBC_UOG1_USBCMD_ASP_MASK) |
| #define USBC_UOG1_USBCMD_ASPE_MASK 0x800u |
| #define USBC_UOG1_USBCMD_ASPE_SHIFT 11 |
| #define USBC_UOG1_USBCMD_SUTW_MASK 0x2000u |
| #define USBC_UOG1_USBCMD_SUTW_SHIFT 13 |
| #define USBC_UOG1_USBCMD_ATDTW_MASK 0x4000u |
| #define USBC_UOG1_USBCMD_ATDTW_SHIFT 14 |
| #define USBC_UOG1_USBCMD_FS_2_MASK 0x8000u |
| #define USBC_UOG1_USBCMD_FS_2_SHIFT 15 |
| #define USBC_UOG1_USBCMD_ITC_MASK 0xFF0000u |
| #define USBC_UOG1_USBCMD_ITC_SHIFT 16 |
| #define USBC_UOG1_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBCMD_ITC_SHIFT))&USBC_UOG1_USBCMD_ITC_MASK) |
| /* UOG1_USBSTS Bit Fields */ |
| #define USBC_UOG1_USBSTS_UI_MASK 0x1u |
| #define USBC_UOG1_USBSTS_UI_SHIFT 0 |
| #define USBC_UOG1_USBSTS_UEI_MASK 0x2u |
| #define USBC_UOG1_USBSTS_UEI_SHIFT 1 |
| #define USBC_UOG1_USBSTS_PCI_MASK 0x4u |
| #define USBC_UOG1_USBSTS_PCI_SHIFT 2 |
| #define USBC_UOG1_USBSTS_FRI_MASK 0x8u |
| #define USBC_UOG1_USBSTS_FRI_SHIFT 3 |
| #define USBC_UOG1_USBSTS_SEI_MASK 0x10u |
| #define USBC_UOG1_USBSTS_SEI_SHIFT 4 |
| #define USBC_UOG1_USBSTS_AAI_MASK 0x20u |
| #define USBC_UOG1_USBSTS_AAI_SHIFT 5 |
| #define USBC_UOG1_USBSTS_URI_MASK 0x40u |
| #define USBC_UOG1_USBSTS_URI_SHIFT 6 |
| #define USBC_UOG1_USBSTS_SRI_MASK 0x80u |
| #define USBC_UOG1_USBSTS_SRI_SHIFT 7 |
| #define USBC_UOG1_USBSTS_SLI_MASK 0x100u |
| #define USBC_UOG1_USBSTS_SLI_SHIFT 8 |
| #define USBC_UOG1_USBSTS_ULPII_MASK 0x400u |
| #define USBC_UOG1_USBSTS_ULPII_SHIFT 10 |
| #define USBC_UOG1_USBSTS_HCH_MASK 0x1000u |
| #define USBC_UOG1_USBSTS_HCH_SHIFT 12 |
| #define USBC_UOG1_USBSTS_RCL_MASK 0x2000u |
| #define USBC_UOG1_USBSTS_RCL_SHIFT 13 |
| #define USBC_UOG1_USBSTS_PS_MASK 0x4000u |
| #define USBC_UOG1_USBSTS_PS_SHIFT 14 |
| #define USBC_UOG1_USBSTS_AS_MASK 0x8000u |
| #define USBC_UOG1_USBSTS_AS_SHIFT 15 |
| #define USBC_UOG1_USBSTS_NAKI_MASK 0x10000u |
| #define USBC_UOG1_USBSTS_NAKI_SHIFT 16 |
| #define USBC_UOG1_USBSTS_TI0_MASK 0x1000000u |
| #define USBC_UOG1_USBSTS_TI0_SHIFT 24 |
| #define USBC_UOG1_USBSTS_TI1_MASK 0x2000000u |
| #define USBC_UOG1_USBSTS_TI1_SHIFT 25 |
| /* UOG1_USBINTR Bit Fields */ |
| #define USBC_UOG1_USBINTR_UE_MASK 0x1u |
| #define USBC_UOG1_USBINTR_UE_SHIFT 0 |
| #define USBC_UOG1_USBINTR_UEE_MASK 0x2u |
| #define USBC_UOG1_USBINTR_UEE_SHIFT 1 |
| #define USBC_UOG1_USBINTR_PCE_MASK 0x4u |
| #define USBC_UOG1_USBINTR_PCE_SHIFT 2 |
| #define USBC_UOG1_USBINTR_FRE_MASK 0x8u |
| #define USBC_UOG1_USBINTR_FRE_SHIFT 3 |
| #define USBC_UOG1_USBINTR_SEE_MASK 0x10u |
| #define USBC_UOG1_USBINTR_SEE_SHIFT 4 |
| #define USBC_UOG1_USBINTR_AAE_MASK 0x20u |
| #define USBC_UOG1_USBINTR_AAE_SHIFT 5 |
| #define USBC_UOG1_USBINTR_URE_MASK 0x40u |
| #define USBC_UOG1_USBINTR_URE_SHIFT 6 |
| #define USBC_UOG1_USBINTR_SRE_MASK 0x80u |
| #define USBC_UOG1_USBINTR_SRE_SHIFT 7 |
| #define USBC_UOG1_USBINTR_SLE_MASK 0x100u |
| #define USBC_UOG1_USBINTR_SLE_SHIFT 8 |
| #define USBC_UOG1_USBINTR_ULPIE_MASK 0x400u |
| #define USBC_UOG1_USBINTR_ULPIE_SHIFT 10 |
| #define USBC_UOG1_USBINTR_NAKE_MASK 0x10000u |
| #define USBC_UOG1_USBINTR_NAKE_SHIFT 16 |
| #define USBC_UOG1_USBINTR_UAIE_MASK 0x40000u |
| #define USBC_UOG1_USBINTR_UAIE_SHIFT 18 |
| #define USBC_UOG1_USBINTR_UPIE_MASK 0x80000u |
| #define USBC_UOG1_USBINTR_UPIE_SHIFT 19 |
| #define USBC_UOG1_USBINTR_TIE0_MASK 0x1000000u |
| #define USBC_UOG1_USBINTR_TIE0_SHIFT 24 |
| #define USBC_UOG1_USBINTR_TIE1_MASK 0x2000000u |
| #define USBC_UOG1_USBINTR_TIE1_SHIFT 25 |
| /* UOG1_FRINDEX Bit Fields */ |
| #define USBC_UOG1_FRINDEX_FRINDEX_MASK 0x3FFFu |
| #define USBC_UOG1_FRINDEX_FRINDEX_SHIFT 0 |
| #define USBC_UOG1_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_FRINDEX_FRINDEX_SHIFT))&USBC_UOG1_FRINDEX_FRINDEX_MASK) |
| /* UOG1_PERIODICLISTBASE Bit Fields */ |
| #define USBC_UOG1_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u |
| #define USBC_UOG1_PERIODICLISTBASE_BASEADR_SHIFT 12 |
| #define USBC_UOG1_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UOG1_PERIODICLISTBASE_BASEADR_MASK) |
| /* UOG1_DEVICEADDR Bit Fields */ |
| #define USBC_UOG1_DEVICEADDR_USBADRA_MASK 0x1000000u |
| #define USBC_UOG1_DEVICEADDR_USBADRA_SHIFT 24 |
| #define USBC_UOG1_DEVICEADDR_USBADR_MASK 0xFE000000u |
| #define USBC_UOG1_DEVICEADDR_USBADR_SHIFT 25 |
| #define USBC_UOG1_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_DEVICEADDR_USBADR_SHIFT))&USBC_UOG1_DEVICEADDR_USBADR_MASK) |
| /* UOG1_ASYNCLISTADDR Bit Fields */ |
| #define USBC_UOG1_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u |
| #define USBC_UOG1_ASYNCLISTADDR_ASYBASE_SHIFT 5 |
| #define USBC_UOG1_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UOG1_ASYNCLISTADDR_ASYBASE_MASK) |
| /* UOG1_ENDPTLISTADDR Bit Fields */ |
| #define USBC_UOG1_ENDPTLISTADDR_EPBASE_MASK 0xFFFFF800u |
| #define USBC_UOG1_ENDPTLISTADDR_EPBASE_SHIFT 11 |
| #define USBC_UOG1_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTLISTADDR_EPBASE_SHIFT))&USBC_UOG1_ENDPTLISTADDR_EPBASE_MASK) |
| /* UOG1_BURSTSIZE Bit Fields */ |
| #define USBC_UOG1_BURSTSIZE_RXPBURST_MASK 0xFFu |
| #define USBC_UOG1_BURSTSIZE_RXPBURST_SHIFT 0 |
| #define USBC_UOG1_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_BURSTSIZE_RXPBURST_SHIFT))&USBC_UOG1_BURSTSIZE_RXPBURST_MASK) |
| #define USBC_UOG1_BURSTSIZE_TXPBURST_MASK 0x1FF00u |
| #define USBC_UOG1_BURSTSIZE_TXPBURST_SHIFT 8 |
| #define USBC_UOG1_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_BURSTSIZE_TXPBURST_SHIFT))&USBC_UOG1_BURSTSIZE_TXPBURST_MASK) |
| /* UOG1_TXFILLTUNING Bit Fields */ |
| #define USBC_UOG1_TXFILLTUNING_TXSCHOH_MASK 0xFFu |
| #define USBC_UOG1_TXFILLTUNING_TXSCHOH_SHIFT 0 |
| #define USBC_UOG1_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UOG1_TXFILLTUNING_TXSCHOH_MASK) |
| #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_MASK 0x1F00u |
| #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_SHIFT 8 |
| #define USBC_UOG1_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UOG1_TXFILLTUNING_TXSCHHEALTH_MASK) |
| #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_MASK 0x3F0000u |
| #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_SHIFT 16 |
| #define USBC_UOG1_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UOG1_TXFILLTUNING_TXFIFOTHRES_MASK) |
| /* UOG1_ENDPTNAK Bit Fields */ |
| #define USBC_UOG1_ENDPTNAK_EPRN_MASK 0xFFu |
| #define USBC_UOG1_ENDPTNAK_EPRN_SHIFT 0 |
| #define USBC_UOG1_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAK_EPRN_SHIFT))&USBC_UOG1_ENDPTNAK_EPRN_MASK) |
| #define USBC_UOG1_ENDPTNAK_EPTN_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTNAK_EPTN_SHIFT 16 |
| #define USBC_UOG1_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAK_EPTN_SHIFT))&USBC_UOG1_ENDPTNAK_EPTN_MASK) |
| /* UOG1_ENDPTNAKEN Bit Fields */ |
| #define USBC_UOG1_ENDPTNAKEN_EPRNE_MASK 0xFFu |
| #define USBC_UOG1_ENDPTNAKEN_EPRNE_SHIFT 0 |
| #define USBC_UOG1_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAKEN_EPRNE_SHIFT))&USBC_UOG1_ENDPTNAKEN_EPRNE_MASK) |
| #define USBC_UOG1_ENDPTNAKEN_EPTNE_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTNAKEN_EPTNE_SHIFT 16 |
| #define USBC_UOG1_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTNAKEN_EPTNE_SHIFT))&USBC_UOG1_ENDPTNAKEN_EPTNE_MASK) |
| /* UOG1_CONFIGFLAG Bit Fields */ |
| #define USBC_UOG1_CONFIGFLAG_CF_MASK 0x1u |
| #define USBC_UOG1_CONFIGFLAG_CF_SHIFT 0 |
| /* UOG1_PORTSC1 Bit Fields */ |
| #define USBC_UOG1_PORTSC1_CCS_MASK 0x1u |
| #define USBC_UOG1_PORTSC1_CCS_SHIFT 0 |
| #define USBC_UOG1_PORTSC1_CSC_MASK 0x2u |
| #define USBC_UOG1_PORTSC1_CSC_SHIFT 1 |
| #define USBC_UOG1_PORTSC1_PE_MASK 0x4u |
| #define USBC_UOG1_PORTSC1_PE_SHIFT 2 |
| #define USBC_UOG1_PORTSC1_PEC_MASK 0x8u |
| #define USBC_UOG1_PORTSC1_PEC_SHIFT 3 |
| #define USBC_UOG1_PORTSC1_OCA_MASK 0x10u |
| #define USBC_UOG1_PORTSC1_OCA_SHIFT 4 |
| #define USBC_UOG1_PORTSC1_OCC_MASK 0x20u |
| #define USBC_UOG1_PORTSC1_OCC_SHIFT 5 |
| #define USBC_UOG1_PORTSC1_FPR_MASK 0x40u |
| #define USBC_UOG1_PORTSC1_FPR_SHIFT 6 |
| #define USBC_UOG1_PORTSC1_SUSP_MASK 0x80u |
| #define USBC_UOG1_PORTSC1_SUSP_SHIFT 7 |
| #define USBC_UOG1_PORTSC1_PR_MASK 0x100u |
| #define USBC_UOG1_PORTSC1_PR_SHIFT 8 |
| #define USBC_UOG1_PORTSC1_HSP_MASK 0x200u |
| #define USBC_UOG1_PORTSC1_HSP_SHIFT 9 |
| #define USBC_UOG1_PORTSC1_LS_MASK 0xC00u |
| #define USBC_UOG1_PORTSC1_LS_SHIFT 10 |
| #define USBC_UOG1_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_LS_SHIFT))&USBC_UOG1_PORTSC1_LS_MASK) |
| #define USBC_UOG1_PORTSC1_PP_MASK 0x1000u |
| #define USBC_UOG1_PORTSC1_PP_SHIFT 12 |
| #define USBC_UOG1_PORTSC1_PO_MASK 0x2000u |
| #define USBC_UOG1_PORTSC1_PO_SHIFT 13 |
| #define USBC_UOG1_PORTSC1_PIC_MASK 0xC000u |
| #define USBC_UOG1_PORTSC1_PIC_SHIFT 14 |
| #define USBC_UOG1_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PIC_SHIFT))&USBC_UOG1_PORTSC1_PIC_MASK) |
| #define USBC_UOG1_PORTSC1_PTC_MASK 0xF0000u |
| #define USBC_UOG1_PORTSC1_PTC_SHIFT 16 |
| #define USBC_UOG1_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PTC_SHIFT))&USBC_UOG1_PORTSC1_PTC_MASK) |
| #define USBC_UOG1_PORTSC1_WKCN_MASK 0x100000u |
| #define USBC_UOG1_PORTSC1_WKCN_SHIFT 20 |
| #define USBC_UOG1_PORTSC1_WKDC_MASK 0x200000u |
| #define USBC_UOG1_PORTSC1_WKDC_SHIFT 21 |
| #define USBC_UOG1_PORTSC1_WKOC_MASK 0x400000u |
| #define USBC_UOG1_PORTSC1_WKOC_SHIFT 22 |
| #define USBC_UOG1_PORTSC1_PHCD_MASK 0x800000u |
| #define USBC_UOG1_PORTSC1_PHCD_SHIFT 23 |
| #define USBC_UOG1_PORTSC1_PFSC_MASK 0x1000000u |
| #define USBC_UOG1_PORTSC1_PFSC_SHIFT 24 |
| #define USBC_UOG1_PORTSC1_PTS_2_MASK 0x2000000u |
| #define USBC_UOG1_PORTSC1_PTS_2_SHIFT 25 |
| #define USBC_UOG1_PORTSC1_PSPD_MASK 0xC000000u |
| #define USBC_UOG1_PORTSC1_PSPD_SHIFT 26 |
| #define USBC_UOG1_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PSPD_SHIFT))&USBC_UOG1_PORTSC1_PSPD_MASK) |
| #define USBC_UOG1_PORTSC1_PTW_MASK 0x10000000u |
| #define USBC_UOG1_PORTSC1_PTW_SHIFT 28 |
| #define USBC_UOG1_PORTSC1_STS_MASK 0x20000000u |
| #define USBC_UOG1_PORTSC1_STS_SHIFT 29 |
| #define USBC_UOG1_PORTSC1_PTS_1_MASK 0xC0000000u |
| #define USBC_UOG1_PORTSC1_PTS_1_SHIFT 30 |
| #define USBC_UOG1_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_PORTSC1_PTS_1_SHIFT))&USBC_UOG1_PORTSC1_PTS_1_MASK) |
| /* UOG1_OTGSC Bit Fields */ |
| #define USBC_UOG1_OTGSC_VD_MASK 0x1u |
| #define USBC_UOG1_OTGSC_VD_SHIFT 0 |
| #define USBC_UOG1_OTGSC_VC_MASK 0x2u |
| #define USBC_UOG1_OTGSC_VC_SHIFT 1 |
| #define USBC_UOG1_OTGSC_OT_MASK 0x8u |
| #define USBC_UOG1_OTGSC_OT_SHIFT 3 |
| #define USBC_UOG1_OTGSC_DP_MASK 0x10u |
| #define USBC_UOG1_OTGSC_DP_SHIFT 4 |
| #define USBC_UOG1_OTGSC_IDPU_MASK 0x20u |
| #define USBC_UOG1_OTGSC_IDPU_SHIFT 5 |
| #define USBC_UOG1_OTGSC_ID_MASK 0x100u |
| #define USBC_UOG1_OTGSC_ID_SHIFT 8 |
| #define USBC_UOG1_OTGSC_AVV_MASK 0x200u |
| #define USBC_UOG1_OTGSC_AVV_SHIFT 9 |
| #define USBC_UOG1_OTGSC_ASV_MASK 0x400u |
| #define USBC_UOG1_OTGSC_ASV_SHIFT 10 |
| #define USBC_UOG1_OTGSC_BSV_MASK 0x800u |
| #define USBC_UOG1_OTGSC_BSV_SHIFT 11 |
| #define USBC_UOG1_OTGSC_BSE_MASK 0x1000u |
| #define USBC_UOG1_OTGSC_BSE_SHIFT 12 |
| #define USBC_UOG1_OTGSC_TOG_1MS_MASK 0x2000u |
| #define USBC_UOG1_OTGSC_TOG_1MS_SHIFT 13 |
| #define USBC_UOG1_OTGSC_DPS_MASK 0x4000u |
| #define USBC_UOG1_OTGSC_DPS_SHIFT 14 |
| #define USBC_UOG1_OTGSC_IDIS_MASK 0x10000u |
| #define USBC_UOG1_OTGSC_IDIS_SHIFT 16 |
| #define USBC_UOG1_OTGSC_AVVIS_MASK 0x20000u |
| #define USBC_UOG1_OTGSC_AVVIS_SHIFT 17 |
| #define USBC_UOG1_OTGSC_ASVIS_MASK 0x40000u |
| #define USBC_UOG1_OTGSC_ASVIS_SHIFT 18 |
| #define USBC_UOG1_OTGSC_BSVIS_MASK 0x80000u |
| #define USBC_UOG1_OTGSC_BSVIS_SHIFT 19 |
| #define USBC_UOG1_OTGSC_BSEIS_MASK 0x100000u |
| #define USBC_UOG1_OTGSC_BSEIS_SHIFT 20 |
| #define USBC_UOG1_OTGSC_STATUS_1MS_MASK 0x200000u |
| #define USBC_UOG1_OTGSC_STATUS_1MS_SHIFT 21 |
| #define USBC_UOG1_OTGSC_DPIS_MASK 0x400000u |
| #define USBC_UOG1_OTGSC_DPIS_SHIFT 22 |
| #define USBC_UOG1_OTGSC_IDIE_MASK 0x1000000u |
| #define USBC_UOG1_OTGSC_IDIE_SHIFT 24 |
| #define USBC_UOG1_OTGSC_AVVIE_MASK 0x2000000u |
| #define USBC_UOG1_OTGSC_AVVIE_SHIFT 25 |
| #define USBC_UOG1_OTGSC_ASVIE_MASK 0x4000000u |
| #define USBC_UOG1_OTGSC_ASVIE_SHIFT 26 |
| #define USBC_UOG1_OTGSC_BSVIE_MASK 0x8000000u |
| #define USBC_UOG1_OTGSC_BSVIE_SHIFT 27 |
| #define USBC_UOG1_OTGSC_BSEIE_MASK 0x10000000u |
| #define USBC_UOG1_OTGSC_BSEIE_SHIFT 28 |
| #define USBC_UOG1_OTGSC_EN_1MS_MASK 0x20000000u |
| #define USBC_UOG1_OTGSC_EN_1MS_SHIFT 29 |
| #define USBC_UOG1_OTGSC_DPIE_MASK 0x40000000u |
| #define USBC_UOG1_OTGSC_DPIE_SHIFT 30 |
| /* UOG1_USBMODE Bit Fields */ |
| #define USBC_UOG1_USBMODE_CM_MASK 0x3u |
| #define USBC_UOG1_USBMODE_CM_SHIFT 0 |
| #define USBC_UOG1_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_USBMODE_CM_SHIFT))&USBC_UOG1_USBMODE_CM_MASK) |
| #define USBC_UOG1_USBMODE_ES_MASK 0x4u |
| #define USBC_UOG1_USBMODE_ES_SHIFT 2 |
| #define USBC_UOG1_USBMODE_SLOM_MASK 0x8u |
| #define USBC_UOG1_USBMODE_SLOM_SHIFT 3 |
| #define USBC_UOG1_USBMODE_SDIS_MASK 0x10u |
| #define USBC_UOG1_USBMODE_SDIS_SHIFT 4 |
| /* UOG1_ENDPTSETUPSTAT Bit Fields */ |
| #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK 0xFFFFu |
| #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT 0 |
| #define USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USBC_UOG1_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) |
| /* UOG1_ENDPTPRIME Bit Fields */ |
| #define USBC_UOG1_ENDPTPRIME_PERB_MASK 0xFFu |
| #define USBC_UOG1_ENDPTPRIME_PERB_SHIFT 0 |
| #define USBC_UOG1_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTPRIME_PERB_SHIFT))&USBC_UOG1_ENDPTPRIME_PERB_MASK) |
| #define USBC_UOG1_ENDPTPRIME_PETB_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTPRIME_PETB_SHIFT 16 |
| #define USBC_UOG1_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTPRIME_PETB_SHIFT))&USBC_UOG1_ENDPTPRIME_PETB_MASK) |
| /* UOG1_ENDPTFLUSH Bit Fields */ |
| #define USBC_UOG1_ENDPTFLUSH_FERB_MASK 0xFFu |
| #define USBC_UOG1_ENDPTFLUSH_FERB_SHIFT 0 |
| #define USBC_UOG1_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTFLUSH_FERB_SHIFT))&USBC_UOG1_ENDPTFLUSH_FERB_MASK) |
| #define USBC_UOG1_ENDPTFLUSH_FETB_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTFLUSH_FETB_SHIFT 16 |
| #define USBC_UOG1_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTFLUSH_FETB_SHIFT))&USBC_UOG1_ENDPTFLUSH_FETB_MASK) |
| /* UOG1_ENDPTSTAT Bit Fields */ |
| #define USBC_UOG1_ENDPTSTAT_ERBR_MASK 0xFFu |
| #define USBC_UOG1_ENDPTSTAT_ERBR_SHIFT 0 |
| #define USBC_UOG1_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSTAT_ERBR_SHIFT))&USBC_UOG1_ENDPTSTAT_ERBR_MASK) |
| #define USBC_UOG1_ENDPTSTAT_ETBR_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTSTAT_ETBR_SHIFT 16 |
| #define USBC_UOG1_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTSTAT_ETBR_SHIFT))&USBC_UOG1_ENDPTSTAT_ETBR_MASK) |
| /* UOG1_ENDPTCOMPLETE Bit Fields */ |
| #define USBC_UOG1_ENDPTCOMPLETE_ERCE_MASK 0xFFu |
| #define USBC_UOG1_ENDPTCOMPLETE_ERCE_SHIFT 0 |
| #define USBC_UOG1_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCOMPLETE_ERCE_SHIFT))&USBC_UOG1_ENDPTCOMPLETE_ERCE_MASK) |
| #define USBC_UOG1_ENDPTCOMPLETE_ETCE_MASK 0xFF0000u |
| #define USBC_UOG1_ENDPTCOMPLETE_ETCE_SHIFT 16 |
| #define USBC_UOG1_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCOMPLETE_ETCE_SHIFT))&USBC_UOG1_ENDPTCOMPLETE_ETCE_MASK) |
| /* UOG1_ENDPTCTRL0 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL0_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL0_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL0_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL0_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL0_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL0_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL0_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL0_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL0_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL0_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL0_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL0_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL0_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL0_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL0_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL0_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL1 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL1_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL1_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL1_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL1_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL1_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL1_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL1_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL1_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL1_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL1_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL1_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL1_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL1_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL1_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL1_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL1_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL1_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL1_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL1_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL1_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL1_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL1_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL1_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL1_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL1_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL1_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL1_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL1_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL2 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL2_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL2_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL2_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL2_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL2_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL2_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL2_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL2_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL2_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL2_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL2_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL2_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL2_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL2_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL2_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL2_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL2_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL2_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL2_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL2_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL2_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL2_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL2_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL2_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL2_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL2_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL2_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL2_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL3 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL3_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL3_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL3_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL3_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL3_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL3_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL3_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL3_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL3_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL3_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL3_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL3_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL3_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL3_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL3_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL3_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL3_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL3_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL3_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL3_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL3_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL3_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL3_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL3_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL3_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL3_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL3_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL3_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL4 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL4_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL4_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL4_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL4_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL4_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL4_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL4_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL4_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL4_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL4_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL4_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL4_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL4_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL4_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL4_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL4_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL4_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL4_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL4_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL4_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL4_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL4_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL4_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL4_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL4_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL4_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL4_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL4_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL5 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL5_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL5_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL5_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL5_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL5_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL5_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL5_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL5_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL5_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL5_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL5_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL5_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL5_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL5_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL5_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL5_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL5_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL5_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL5_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL5_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL5_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL5_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL5_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL5_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL5_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL5_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL5_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL5_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL6 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL6_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL6_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL6_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL6_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL6_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL6_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL6_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL6_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL6_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL6_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL6_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL6_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL6_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL6_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL6_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL6_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL6_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL6_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL6_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL6_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL6_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL6_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL6_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL6_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL6_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL6_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL6_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL6_TXE_SHIFT 23 |
| /* UOG1_ENDPTCTRL7 Bit Fields */ |
| #define USBC_UOG1_ENDPTCTRL7_RXS_MASK 0x1u |
| #define USBC_UOG1_ENDPTCTRL7_RXS_SHIFT 0 |
| #define USBC_UOG1_ENDPTCTRL7_RXD_MASK 0x2u |
| #define USBC_UOG1_ENDPTCTRL7_RXD_SHIFT 1 |
| #define USBC_UOG1_ENDPTCTRL7_RXT_MASK 0xCu |
| #define USBC_UOG1_ENDPTCTRL7_RXT_SHIFT 2 |
| #define USBC_UOG1_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL7_RXT_SHIFT))&USBC_UOG1_ENDPTCTRL7_RXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL7_RXI_MASK 0x20u |
| #define USBC_UOG1_ENDPTCTRL7_RXI_SHIFT 5 |
| #define USBC_UOG1_ENDPTCTRL7_RXR_MASK 0x40u |
| #define USBC_UOG1_ENDPTCTRL7_RXR_SHIFT 6 |
| #define USBC_UOG1_ENDPTCTRL7_RXE_MASK 0x80u |
| #define USBC_UOG1_ENDPTCTRL7_RXE_SHIFT 7 |
| #define USBC_UOG1_ENDPTCTRL7_TXS_MASK 0x10000u |
| #define USBC_UOG1_ENDPTCTRL7_TXS_SHIFT 16 |
| #define USBC_UOG1_ENDPTCTRL7_TXD_MASK 0x20000u |
| #define USBC_UOG1_ENDPTCTRL7_TXD_SHIFT 17 |
| #define USBC_UOG1_ENDPTCTRL7_TXT_MASK 0xC0000u |
| #define USBC_UOG1_ENDPTCTRL7_TXT_SHIFT 18 |
| #define USBC_UOG1_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG1_ENDPTCTRL7_TXT_SHIFT))&USBC_UOG1_ENDPTCTRL7_TXT_MASK) |
| #define USBC_UOG1_ENDPTCTRL7_TXI_MASK 0x200000u |
| #define USBC_UOG1_ENDPTCTRL7_TXI_SHIFT 21 |
| #define USBC_UOG1_ENDPTCTRL7_TXR_MASK 0x400000u |
| #define USBC_UOG1_ENDPTCTRL7_TXR_SHIFT 22 |
| #define USBC_UOG1_ENDPTCTRL7_TXE_MASK 0x800000u |
| #define USBC_UOG1_ENDPTCTRL7_TXE_SHIFT 23 |
| /* UOG2_ID Bit Fields */ |
| #define USBC_UOG2_ID_ID_MASK 0x3Fu |
| #define USBC_UOG2_ID_ID_SHIFT 0 |
| #define USBC_UOG2_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_ID_SHIFT))&USBC_UOG2_ID_ID_MASK) |
| #define USBC_UOG2_ID_NID_MASK 0x3F00u |
| #define USBC_UOG2_ID_NID_SHIFT 8 |
| #define USBC_UOG2_ID_NID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_NID_SHIFT))&USBC_UOG2_ID_NID_MASK) |
| #define USBC_UOG2_ID_REVISION_MASK 0xFF0000u |
| #define USBC_UOG2_ID_REVISION_SHIFT 16 |
| #define USBC_UOG2_ID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ID_REVISION_SHIFT))&USBC_UOG2_ID_REVISION_MASK) |
| /* UOG2_HWGENERAL Bit Fields */ |
| #define USBC_UOG2_HWGENERAL_PHYW_MASK 0x30u |
| #define USBC_UOG2_HWGENERAL_PHYW_SHIFT 4 |
| #define USBC_UOG2_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_PHYW_SHIFT))&USBC_UOG2_HWGENERAL_PHYW_MASK) |
| #define USBC_UOG2_HWGENERAL_PHYM_MASK 0x1C0u |
| #define USBC_UOG2_HWGENERAL_PHYM_SHIFT 6 |
| #define USBC_UOG2_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_PHYM_SHIFT))&USBC_UOG2_HWGENERAL_PHYM_MASK) |
| #define USBC_UOG2_HWGENERAL_SM_MASK 0x600u |
| #define USBC_UOG2_HWGENERAL_SM_SHIFT 9 |
| #define USBC_UOG2_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWGENERAL_SM_SHIFT))&USBC_UOG2_HWGENERAL_SM_MASK) |
| /* UOG2_HWHOST Bit Fields */ |
| #define USBC_UOG2_HWHOST_HC_MASK 0x1u |
| #define USBC_UOG2_HWHOST_HC_SHIFT 0 |
| #define USBC_UOG2_HWHOST_NPORT_MASK 0xEu |
| #define USBC_UOG2_HWHOST_NPORT_SHIFT 1 |
| #define USBC_UOG2_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWHOST_NPORT_SHIFT))&USBC_UOG2_HWHOST_NPORT_MASK) |
| /* UOG2_HWDEVICE Bit Fields */ |
| #define USBC_UOG2_HWDEVICE_DC_MASK 0x1u |
| #define USBC_UOG2_HWDEVICE_DC_SHIFT 0 |
| #define USBC_UOG2_HWDEVICE_DEVEP_MASK 0x3Eu |
| #define USBC_UOG2_HWDEVICE_DEVEP_SHIFT 1 |
| #define USBC_UOG2_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWDEVICE_DEVEP_SHIFT))&USBC_UOG2_HWDEVICE_DEVEP_MASK) |
| /* UOG2_HWTXBUF Bit Fields */ |
| #define USBC_UOG2_HWTXBUF_TXBURST_MASK 0xFFu |
| #define USBC_UOG2_HWTXBUF_TXBURST_SHIFT 0 |
| #define USBC_UOG2_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWTXBUF_TXBURST_SHIFT))&USBC_UOG2_HWTXBUF_TXBURST_MASK) |
| #define USBC_UOG2_HWTXBUF_TXCHANADD_MASK 0xFF0000u |
| #define USBC_UOG2_HWTXBUF_TXCHANADD_SHIFT 16 |
| #define USBC_UOG2_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWTXBUF_TXCHANADD_SHIFT))&USBC_UOG2_HWTXBUF_TXCHANADD_MASK) |
| /* UOG2_HWRXBUF Bit Fields */ |
| #define USBC_UOG2_HWRXBUF_RXBURST_MASK 0xFFu |
| #define USBC_UOG2_HWRXBUF_RXBURST_SHIFT 0 |
| #define USBC_UOG2_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWRXBUF_RXBURST_SHIFT))&USBC_UOG2_HWRXBUF_RXBURST_MASK) |
| #define USBC_UOG2_HWRXBUF_RXADD_MASK 0xFF00u |
| #define USBC_UOG2_HWRXBUF_RXADD_SHIFT 8 |
| #define USBC_UOG2_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HWRXBUF_RXADD_SHIFT))&USBC_UOG2_HWRXBUF_RXADD_MASK) |
| /* UOG2_GPTIMER0LD Bit Fields */ |
| #define USBC_UOG2_GPTIMER0LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UOG2_GPTIMER0LD_GPTLD_SHIFT 0 |
| #define USBC_UOG2_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER0LD_GPTLD_SHIFT))&USBC_UOG2_GPTIMER0LD_GPTLD_MASK) |
| /* UOG2_GPTIMER0CTRL Bit Fields */ |
| #define USBC_UOG2_GPTIMER0CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UOG2_GPTIMER0CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UOG2_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UOG2_GPTIMER0CTRL_GPTCNT_MASK) |
| #define USBC_UOG2_GPTIMER0CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UOG2_GPTIMER0CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UOG2_GPTIMER0CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UOG2_GPTIMER0CTRL_GPTRST_SHIFT 30 |
| #define USBC_UOG2_GPTIMER0CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UOG2_GPTIMER0CTRL_GPTRUN_SHIFT 31 |
| /* UOG2_GPTIMER1LD Bit Fields */ |
| #define USBC_UOG2_GPTIMER1LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UOG2_GPTIMER1LD_GPTLD_SHIFT 0 |
| #define USBC_UOG2_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER1LD_GPTLD_SHIFT))&USBC_UOG2_GPTIMER1LD_GPTLD_MASK) |
| /* UOG2_GPTIMER1CTRL Bit Fields */ |
| #define USBC_UOG2_GPTIMER1CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UOG2_GPTIMER1CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UOG2_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UOG2_GPTIMER1CTRL_GPTCNT_MASK) |
| #define USBC_UOG2_GPTIMER1CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UOG2_GPTIMER1CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UOG2_GPTIMER1CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UOG2_GPTIMER1CTRL_GPTRST_SHIFT 30 |
| #define USBC_UOG2_GPTIMER1CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UOG2_GPTIMER1CTRL_GPTRUN_SHIFT 31 |
| /* UOG2_SBUSCFG Bit Fields */ |
| #define USBC_UOG2_SBUSCFG_AHBBRST_MASK 0x7u |
| #define USBC_UOG2_SBUSCFG_AHBBRST_SHIFT 0 |
| #define USBC_UOG2_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_SBUSCFG_AHBBRST_SHIFT))&USBC_UOG2_SBUSCFG_AHBBRST_MASK) |
| /* UOG2_CAPLENGTH Bit Fields */ |
| #define USBC_UOG2_CAPLENGTH_CAPLENGTH_MASK 0xFFu |
| #define USBC_UOG2_CAPLENGTH_CAPLENGTH_SHIFT 0 |
| #define USBC_UOG2_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x))<<USBC_UOG2_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UOG2_CAPLENGTH_CAPLENGTH_MASK) |
| /* UOG2_HCIVERSION Bit Fields */ |
| #define USBC_UOG2_HCIVERSION_HCIVERSION_MASK 0xFFFFu |
| #define USBC_UOG2_HCIVERSION_HCIVERSION_SHIFT 0 |
| #define USBC_UOG2_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBC_UOG2_HCIVERSION_HCIVERSION_SHIFT))&USBC_UOG2_HCIVERSION_HCIVERSION_MASK) |
| /* UOG2_HCSPARAMS Bit Fields */ |
| #define USBC_UOG2_HCSPARAMS_N_PORTS_MASK 0xFu |
| #define USBC_UOG2_HCSPARAMS_N_PORTS_SHIFT 0 |
| #define USBC_UOG2_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PORTS_SHIFT))&USBC_UOG2_HCSPARAMS_N_PORTS_MASK) |
| #define USBC_UOG2_HCSPARAMS_PPC_MASK 0x10u |
| #define USBC_UOG2_HCSPARAMS_PPC_SHIFT 4 |
| #define USBC_UOG2_HCSPARAMS_N_PCC_MASK 0xF00u |
| #define USBC_UOG2_HCSPARAMS_N_PCC_SHIFT 8 |
| #define USBC_UOG2_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PCC_SHIFT))&USBC_UOG2_HCSPARAMS_N_PCC_MASK) |
| #define USBC_UOG2_HCSPARAMS_N_CC_MASK 0xF000u |
| #define USBC_UOG2_HCSPARAMS_N_CC_SHIFT 12 |
| #define USBC_UOG2_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_CC_SHIFT))&USBC_UOG2_HCSPARAMS_N_CC_MASK) |
| #define USBC_UOG2_HCSPARAMS_PI_MASK 0x10000u |
| #define USBC_UOG2_HCSPARAMS_PI_SHIFT 16 |
| #define USBC_UOG2_HCSPARAMS_N_PTT_MASK 0xF00000u |
| #define USBC_UOG2_HCSPARAMS_N_PTT_SHIFT 20 |
| #define USBC_UOG2_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_PTT_SHIFT))&USBC_UOG2_HCSPARAMS_N_PTT_MASK) |
| #define USBC_UOG2_HCSPARAMS_N_TT_MASK 0xF000000u |
| #define USBC_UOG2_HCSPARAMS_N_TT_SHIFT 24 |
| #define USBC_UOG2_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCSPARAMS_N_TT_SHIFT))&USBC_UOG2_HCSPARAMS_N_TT_MASK) |
| /* UOG2_HCCPARAMS Bit Fields */ |
| #define USBC_UOG2_HCCPARAMS_ADC_MASK 0x1u |
| #define USBC_UOG2_HCCPARAMS_ADC_SHIFT 0 |
| #define USBC_UOG2_HCCPARAMS_PFL_MASK 0x2u |
| #define USBC_UOG2_HCCPARAMS_PFL_SHIFT 1 |
| #define USBC_UOG2_HCCPARAMS_ASP_MASK 0x4u |
| #define USBC_UOG2_HCCPARAMS_ASP_SHIFT 2 |
| #define USBC_UOG2_HCCPARAMS_IST_MASK 0xF0u |
| #define USBC_UOG2_HCCPARAMS_IST_SHIFT 4 |
| #define USBC_UOG2_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCCPARAMS_IST_SHIFT))&USBC_UOG2_HCCPARAMS_IST_MASK) |
| #define USBC_UOG2_HCCPARAMS_EECP_MASK 0xFF00u |
| #define USBC_UOG2_HCCPARAMS_EECP_SHIFT 8 |
| #define USBC_UOG2_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_HCCPARAMS_EECP_SHIFT))&USBC_UOG2_HCCPARAMS_EECP_MASK) |
| /* UOG2_DCIVERSION Bit Fields */ |
| #define USBC_UOG2_DCIVERSION_DCIVERSION_MASK 0xFFFFu |
| #define USBC_UOG2_DCIVERSION_DCIVERSION_SHIFT 0 |
| #define USBC_UOG2_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBC_UOG2_DCIVERSION_DCIVERSION_SHIFT))&USBC_UOG2_DCIVERSION_DCIVERSION_MASK) |
| /* UOG2_DCCPARAMS Bit Fields */ |
| #define USBC_UOG2_DCCPARAMS_DEN_MASK 0x1Fu |
| #define USBC_UOG2_DCCPARAMS_DEN_SHIFT 0 |
| #define USBC_UOG2_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_DCCPARAMS_DEN_SHIFT))&USBC_UOG2_DCCPARAMS_DEN_MASK) |
| #define USBC_UOG2_DCCPARAMS_DC_MASK 0x80u |
| #define USBC_UOG2_DCCPARAMS_DC_SHIFT 7 |
| #define USBC_UOG2_DCCPARAMS_HC_MASK 0x100u |
| #define USBC_UOG2_DCCPARAMS_HC_SHIFT 8 |
| /* UOG2_USBCMD Bit Fields */ |
| #define USBC_UOG2_USBCMD_RS_MASK 0x1u |
| #define USBC_UOG2_USBCMD_RS_SHIFT 0 |
| #define USBC_UOG2_USBCMD_RST_MASK 0x2u |
| #define USBC_UOG2_USBCMD_RST_SHIFT 1 |
| #define USBC_UOG2_USBCMD_FS_1_MASK 0xCu |
| #define USBC_UOG2_USBCMD_FS_1_SHIFT 2 |
| #define USBC_UOG2_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_FS_1_SHIFT))&USBC_UOG2_USBCMD_FS_1_MASK) |
| #define USBC_UOG2_USBCMD_PSE_MASK 0x10u |
| #define USBC_UOG2_USBCMD_PSE_SHIFT 4 |
| #define USBC_UOG2_USBCMD_ASE_MASK 0x20u |
| #define USBC_UOG2_USBCMD_ASE_SHIFT 5 |
| #define USBC_UOG2_USBCMD_IAA_MASK 0x40u |
| #define USBC_UOG2_USBCMD_IAA_SHIFT 6 |
| #define USBC_UOG2_USBCMD_ASP_MASK 0x300u |
| #define USBC_UOG2_USBCMD_ASP_SHIFT 8 |
| #define USBC_UOG2_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_ASP_SHIFT))&USBC_UOG2_USBCMD_ASP_MASK) |
| #define USBC_UOG2_USBCMD_ASPE_MASK 0x800u |
| #define USBC_UOG2_USBCMD_ASPE_SHIFT 11 |
| #define USBC_UOG2_USBCMD_SUTW_MASK 0x2000u |
| #define USBC_UOG2_USBCMD_SUTW_SHIFT 13 |
| #define USBC_UOG2_USBCMD_ATDTW_MASK 0x4000u |
| #define USBC_UOG2_USBCMD_ATDTW_SHIFT 14 |
| #define USBC_UOG2_USBCMD_FS_2_MASK 0x8000u |
| #define USBC_UOG2_USBCMD_FS_2_SHIFT 15 |
| #define USBC_UOG2_USBCMD_ITC_MASK 0xFF0000u |
| #define USBC_UOG2_USBCMD_ITC_SHIFT 16 |
| #define USBC_UOG2_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBCMD_ITC_SHIFT))&USBC_UOG2_USBCMD_ITC_MASK) |
| /* UOG2_USBSTS Bit Fields */ |
| #define USBC_UOG2_USBSTS_UI_MASK 0x1u |
| #define USBC_UOG2_USBSTS_UI_SHIFT 0 |
| #define USBC_UOG2_USBSTS_UEI_MASK 0x2u |
| #define USBC_UOG2_USBSTS_UEI_SHIFT 1 |
| #define USBC_UOG2_USBSTS_PCI_MASK 0x4u |
| #define USBC_UOG2_USBSTS_PCI_SHIFT 2 |
| #define USBC_UOG2_USBSTS_FRI_MASK 0x8u |
| #define USBC_UOG2_USBSTS_FRI_SHIFT 3 |
| #define USBC_UOG2_USBSTS_SEI_MASK 0x10u |
| #define USBC_UOG2_USBSTS_SEI_SHIFT 4 |
| #define USBC_UOG2_USBSTS_AAI_MASK 0x20u |
| #define USBC_UOG2_USBSTS_AAI_SHIFT 5 |
| #define USBC_UOG2_USBSTS_URI_MASK 0x40u |
| #define USBC_UOG2_USBSTS_URI_SHIFT 6 |
| #define USBC_UOG2_USBSTS_SRI_MASK 0x80u |
| #define USBC_UOG2_USBSTS_SRI_SHIFT 7 |
| #define USBC_UOG2_USBSTS_SLI_MASK 0x100u |
| #define USBC_UOG2_USBSTS_SLI_SHIFT 8 |
| #define USBC_UOG2_USBSTS_ULPII_MASK 0x400u |
| #define USBC_UOG2_USBSTS_ULPII_SHIFT 10 |
| #define USBC_UOG2_USBSTS_HCH_MASK 0x1000u |
| #define USBC_UOG2_USBSTS_HCH_SHIFT 12 |
| #define USBC_UOG2_USBSTS_RCL_MASK 0x2000u |
| #define USBC_UOG2_USBSTS_RCL_SHIFT 13 |
| #define USBC_UOG2_USBSTS_PS_MASK 0x4000u |
| #define USBC_UOG2_USBSTS_PS_SHIFT 14 |
| #define USBC_UOG2_USBSTS_AS_MASK 0x8000u |
| #define USBC_UOG2_USBSTS_AS_SHIFT 15 |
| #define USBC_UOG2_USBSTS_NAKI_MASK 0x10000u |
| #define USBC_UOG2_USBSTS_NAKI_SHIFT 16 |
| #define USBC_UOG2_USBSTS_TI0_MASK 0x1000000u |
| #define USBC_UOG2_USBSTS_TI0_SHIFT 24 |
| #define USBC_UOG2_USBSTS_TI1_MASK 0x2000000u |
| #define USBC_UOG2_USBSTS_TI1_SHIFT 25 |
| /* UOG2_USBINTR Bit Fields */ |
| #define USBC_UOG2_USBINTR_UE_MASK 0x1u |
| #define USBC_UOG2_USBINTR_UE_SHIFT 0 |
| #define USBC_UOG2_USBINTR_UEE_MASK 0x2u |
| #define USBC_UOG2_USBINTR_UEE_SHIFT 1 |
| #define USBC_UOG2_USBINTR_PCE_MASK 0x4u |
| #define USBC_UOG2_USBINTR_PCE_SHIFT 2 |
| #define USBC_UOG2_USBINTR_FRE_MASK 0x8u |
| #define USBC_UOG2_USBINTR_FRE_SHIFT 3 |
| #define USBC_UOG2_USBINTR_SEE_MASK 0x10u |
| #define USBC_UOG2_USBINTR_SEE_SHIFT 4 |
| #define USBC_UOG2_USBINTR_AAE_MASK 0x20u |
| #define USBC_UOG2_USBINTR_AAE_SHIFT 5 |
| #define USBC_UOG2_USBINTR_URE_MASK 0x40u |
| #define USBC_UOG2_USBINTR_URE_SHIFT 6 |
| #define USBC_UOG2_USBINTR_SRE_MASK 0x80u |
| #define USBC_UOG2_USBINTR_SRE_SHIFT 7 |
| #define USBC_UOG2_USBINTR_SLE_MASK 0x100u |
| #define USBC_UOG2_USBINTR_SLE_SHIFT 8 |
| #define USBC_UOG2_USBINTR_ULPIE_MASK 0x400u |
| #define USBC_UOG2_USBINTR_ULPIE_SHIFT 10 |
| #define USBC_UOG2_USBINTR_NAKE_MASK 0x10000u |
| #define USBC_UOG2_USBINTR_NAKE_SHIFT 16 |
| #define USBC_UOG2_USBINTR_UAIE_MASK 0x40000u |
| #define USBC_UOG2_USBINTR_UAIE_SHIFT 18 |
| #define USBC_UOG2_USBINTR_UPIE_MASK 0x80000u |
| #define USBC_UOG2_USBINTR_UPIE_SHIFT 19 |
| #define USBC_UOG2_USBINTR_TIE0_MASK 0x1000000u |
| #define USBC_UOG2_USBINTR_TIE0_SHIFT 24 |
| #define USBC_UOG2_USBINTR_TIE1_MASK 0x2000000u |
| #define USBC_UOG2_USBINTR_TIE1_SHIFT 25 |
| /* UOG2_FRINDEX Bit Fields */ |
| #define USBC_UOG2_FRINDEX_FRINDEX_MASK 0x3FFFu |
| #define USBC_UOG2_FRINDEX_FRINDEX_SHIFT 0 |
| #define USBC_UOG2_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_FRINDEX_FRINDEX_SHIFT))&USBC_UOG2_FRINDEX_FRINDEX_MASK) |
| /* UOG2_PERIODICLISTBASE Bit Fields */ |
| #define USBC_UOG2_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u |
| #define USBC_UOG2_PERIODICLISTBASE_BASEADR_SHIFT 12 |
| #define USBC_UOG2_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UOG2_PERIODICLISTBASE_BASEADR_MASK) |
| /* UOG2_DEVICEADDR Bit Fields */ |
| #define USBC_UOG2_DEVICEADDR_USBADRA_MASK 0x1000000u |
| #define USBC_UOG2_DEVICEADDR_USBADRA_SHIFT 24 |
| #define USBC_UOG2_DEVICEADDR_USBADR_MASK 0xFE000000u |
| #define USBC_UOG2_DEVICEADDR_USBADR_SHIFT 25 |
| #define USBC_UOG2_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_DEVICEADDR_USBADR_SHIFT))&USBC_UOG2_DEVICEADDR_USBADR_MASK) |
| /* UOG2_ASYNCLISTADDR Bit Fields */ |
| #define USBC_UOG2_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u |
| #define USBC_UOG2_ASYNCLISTADDR_ASYBASE_SHIFT 5 |
| #define USBC_UOG2_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UOG2_ASYNCLISTADDR_ASYBASE_MASK) |
| /* UOG2_ENDPTLISTADDR Bit Fields */ |
| #define USBC_UOG2_ENDPTLISTADDR_EPBASE_MASK 0xFFFFF800u |
| #define USBC_UOG2_ENDPTLISTADDR_EPBASE_SHIFT 11 |
| #define USBC_UOG2_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTLISTADDR_EPBASE_SHIFT))&USBC_UOG2_ENDPTLISTADDR_EPBASE_MASK) |
| /* UOG2_BURSTSIZE Bit Fields */ |
| #define USBC_UOG2_BURSTSIZE_RXPBURST_MASK 0xFFu |
| #define USBC_UOG2_BURSTSIZE_RXPBURST_SHIFT 0 |
| #define USBC_UOG2_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_BURSTSIZE_RXPBURST_SHIFT))&USBC_UOG2_BURSTSIZE_RXPBURST_MASK) |
| #define USBC_UOG2_BURSTSIZE_TXPBURST_MASK 0x1FF00u |
| #define USBC_UOG2_BURSTSIZE_TXPBURST_SHIFT 8 |
| #define USBC_UOG2_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_BURSTSIZE_TXPBURST_SHIFT))&USBC_UOG2_BURSTSIZE_TXPBURST_MASK) |
| /* UOG2_TXFILLTUNING Bit Fields */ |
| #define USBC_UOG2_TXFILLTUNING_TXSCHOH_MASK 0xFFu |
| #define USBC_UOG2_TXFILLTUNING_TXSCHOH_SHIFT 0 |
| #define USBC_UOG2_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UOG2_TXFILLTUNING_TXSCHOH_MASK) |
| #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_MASK 0x1F00u |
| #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_SHIFT 8 |
| #define USBC_UOG2_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UOG2_TXFILLTUNING_TXSCHHEALTH_MASK) |
| #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_MASK 0x3F0000u |
| #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_SHIFT 16 |
| #define USBC_UOG2_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UOG2_TXFILLTUNING_TXFIFOTHRES_MASK) |
| /* UOG2_ENDPTNAK Bit Fields */ |
| #define USBC_UOG2_ENDPTNAK_EPRN_MASK 0xFFu |
| #define USBC_UOG2_ENDPTNAK_EPRN_SHIFT 0 |
| #define USBC_UOG2_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAK_EPRN_SHIFT))&USBC_UOG2_ENDPTNAK_EPRN_MASK) |
| #define USBC_UOG2_ENDPTNAK_EPTN_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTNAK_EPTN_SHIFT 16 |
| #define USBC_UOG2_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAK_EPTN_SHIFT))&USBC_UOG2_ENDPTNAK_EPTN_MASK) |
| /* UOG2_ENDPTNAKEN Bit Fields */ |
| #define USBC_UOG2_ENDPTNAKEN_EPRNE_MASK 0xFFu |
| #define USBC_UOG2_ENDPTNAKEN_EPRNE_SHIFT 0 |
| #define USBC_UOG2_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAKEN_EPRNE_SHIFT))&USBC_UOG2_ENDPTNAKEN_EPRNE_MASK) |
| #define USBC_UOG2_ENDPTNAKEN_EPTNE_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTNAKEN_EPTNE_SHIFT 16 |
| #define USBC_UOG2_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTNAKEN_EPTNE_SHIFT))&USBC_UOG2_ENDPTNAKEN_EPTNE_MASK) |
| /* UOG2_CONFIGFLAG Bit Fields */ |
| #define USBC_UOG2_CONFIGFLAG_CF_MASK 0x1u |
| #define USBC_UOG2_CONFIGFLAG_CF_SHIFT 0 |
| /* UOG2_PORTSC1 Bit Fields */ |
| #define USBC_UOG2_PORTSC1_CCS_MASK 0x1u |
| #define USBC_UOG2_PORTSC1_CCS_SHIFT 0 |
| #define USBC_UOG2_PORTSC1_CSC_MASK 0x2u |
| #define USBC_UOG2_PORTSC1_CSC_SHIFT 1 |
| #define USBC_UOG2_PORTSC1_PE_MASK 0x4u |
| #define USBC_UOG2_PORTSC1_PE_SHIFT 2 |
| #define USBC_UOG2_PORTSC1_PEC_MASK 0x8u |
| #define USBC_UOG2_PORTSC1_PEC_SHIFT 3 |
| #define USBC_UOG2_PORTSC1_OCA_MASK 0x10u |
| #define USBC_UOG2_PORTSC1_OCA_SHIFT 4 |
| #define USBC_UOG2_PORTSC1_OCC_MASK 0x20u |
| #define USBC_UOG2_PORTSC1_OCC_SHIFT 5 |
| #define USBC_UOG2_PORTSC1_FPR_MASK 0x40u |
| #define USBC_UOG2_PORTSC1_FPR_SHIFT 6 |
| #define USBC_UOG2_PORTSC1_SUSP_MASK 0x80u |
| #define USBC_UOG2_PORTSC1_SUSP_SHIFT 7 |
| #define USBC_UOG2_PORTSC1_PR_MASK 0x100u |
| #define USBC_UOG2_PORTSC1_PR_SHIFT 8 |
| #define USBC_UOG2_PORTSC1_HSP_MASK 0x200u |
| #define USBC_UOG2_PORTSC1_HSP_SHIFT 9 |
| #define USBC_UOG2_PORTSC1_LS_MASK 0xC00u |
| #define USBC_UOG2_PORTSC1_LS_SHIFT 10 |
| #define USBC_UOG2_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_LS_SHIFT))&USBC_UOG2_PORTSC1_LS_MASK) |
| #define USBC_UOG2_PORTSC1_PP_MASK 0x1000u |
| #define USBC_UOG2_PORTSC1_PP_SHIFT 12 |
| #define USBC_UOG2_PORTSC1_PO_MASK 0x2000u |
| #define USBC_UOG2_PORTSC1_PO_SHIFT 13 |
| #define USBC_UOG2_PORTSC1_PIC_MASK 0xC000u |
| #define USBC_UOG2_PORTSC1_PIC_SHIFT 14 |
| #define USBC_UOG2_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PIC_SHIFT))&USBC_UOG2_PORTSC1_PIC_MASK) |
| #define USBC_UOG2_PORTSC1_PTC_MASK 0xF0000u |
| #define USBC_UOG2_PORTSC1_PTC_SHIFT 16 |
| #define USBC_UOG2_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PTC_SHIFT))&USBC_UOG2_PORTSC1_PTC_MASK) |
| #define USBC_UOG2_PORTSC1_WKCN_MASK 0x100000u |
| #define USBC_UOG2_PORTSC1_WKCN_SHIFT 20 |
| #define USBC_UOG2_PORTSC1_WKDC_MASK 0x200000u |
| #define USBC_UOG2_PORTSC1_WKDC_SHIFT 21 |
| #define USBC_UOG2_PORTSC1_WKOC_MASK 0x400000u |
| #define USBC_UOG2_PORTSC1_WKOC_SHIFT 22 |
| #define USBC_UOG2_PORTSC1_PHCD_MASK 0x800000u |
| #define USBC_UOG2_PORTSC1_PHCD_SHIFT 23 |
| #define USBC_UOG2_PORTSC1_PFSC_MASK 0x1000000u |
| #define USBC_UOG2_PORTSC1_PFSC_SHIFT 24 |
| #define USBC_UOG2_PORTSC1_PTS_2_MASK 0x2000000u |
| #define USBC_UOG2_PORTSC1_PTS_2_SHIFT 25 |
| #define USBC_UOG2_PORTSC1_PSPD_MASK 0xC000000u |
| #define USBC_UOG2_PORTSC1_PSPD_SHIFT 26 |
| #define USBC_UOG2_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PSPD_SHIFT))&USBC_UOG2_PORTSC1_PSPD_MASK) |
| #define USBC_UOG2_PORTSC1_PTW_MASK 0x10000000u |
| #define USBC_UOG2_PORTSC1_PTW_SHIFT 28 |
| #define USBC_UOG2_PORTSC1_STS_MASK 0x20000000u |
| #define USBC_UOG2_PORTSC1_STS_SHIFT 29 |
| #define USBC_UOG2_PORTSC1_PTS_1_MASK 0xC0000000u |
| #define USBC_UOG2_PORTSC1_PTS_1_SHIFT 30 |
| #define USBC_UOG2_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_PORTSC1_PTS_1_SHIFT))&USBC_UOG2_PORTSC1_PTS_1_MASK) |
| /* UOG2_OTGSC Bit Fields */ |
| #define USBC_UOG2_OTGSC_VD_MASK 0x1u |
| #define USBC_UOG2_OTGSC_VD_SHIFT 0 |
| #define USBC_UOG2_OTGSC_VC_MASK 0x2u |
| #define USBC_UOG2_OTGSC_VC_SHIFT 1 |
| #define USBC_UOG2_OTGSC_OT_MASK 0x8u |
| #define USBC_UOG2_OTGSC_OT_SHIFT 3 |
| #define USBC_UOG2_OTGSC_DP_MASK 0x10u |
| #define USBC_UOG2_OTGSC_DP_SHIFT 4 |
| #define USBC_UOG2_OTGSC_IDPU_MASK 0x20u |
| #define USBC_UOG2_OTGSC_IDPU_SHIFT 5 |
| #define USBC_UOG2_OTGSC_ID_MASK 0x100u |
| #define USBC_UOG2_OTGSC_ID_SHIFT 8 |
| #define USBC_UOG2_OTGSC_AVV_MASK 0x200u |
| #define USBC_UOG2_OTGSC_AVV_SHIFT 9 |
| #define USBC_UOG2_OTGSC_ASV_MASK 0x400u |
| #define USBC_UOG2_OTGSC_ASV_SHIFT 10 |
| #define USBC_UOG2_OTGSC_BSV_MASK 0x800u |
| #define USBC_UOG2_OTGSC_BSV_SHIFT 11 |
| #define USBC_UOG2_OTGSC_BSE_MASK 0x1000u |
| #define USBC_UOG2_OTGSC_BSE_SHIFT 12 |
| #define USBC_UOG2_OTGSC_TOG_1MS_MASK 0x2000u |
| #define USBC_UOG2_OTGSC_TOG_1MS_SHIFT 13 |
| #define USBC_UOG2_OTGSC_DPS_MASK 0x4000u |
| #define USBC_UOG2_OTGSC_DPS_SHIFT 14 |
| #define USBC_UOG2_OTGSC_IDIS_MASK 0x10000u |
| #define USBC_UOG2_OTGSC_IDIS_SHIFT 16 |
| #define USBC_UOG2_OTGSC_AVVIS_MASK 0x20000u |
| #define USBC_UOG2_OTGSC_AVVIS_SHIFT 17 |
| #define USBC_UOG2_OTGSC_ASVIS_MASK 0x40000u |
| #define USBC_UOG2_OTGSC_ASVIS_SHIFT 18 |
| #define USBC_UOG2_OTGSC_BSVIS_MASK 0x80000u |
| #define USBC_UOG2_OTGSC_BSVIS_SHIFT 19 |
| #define USBC_UOG2_OTGSC_BSEIS_MASK 0x100000u |
| #define USBC_UOG2_OTGSC_BSEIS_SHIFT 20 |
| #define USBC_UOG2_OTGSC_STATUS_1MS_MASK 0x200000u |
| #define USBC_UOG2_OTGSC_STATUS_1MS_SHIFT 21 |
| #define USBC_UOG2_OTGSC_DPIS_MASK 0x400000u |
| #define USBC_UOG2_OTGSC_DPIS_SHIFT 22 |
| #define USBC_UOG2_OTGSC_IDIE_MASK 0x1000000u |
| #define USBC_UOG2_OTGSC_IDIE_SHIFT 24 |
| #define USBC_UOG2_OTGSC_AVVIE_MASK 0x2000000u |
| #define USBC_UOG2_OTGSC_AVVIE_SHIFT 25 |
| #define USBC_UOG2_OTGSC_ASVIE_MASK 0x4000000u |
| #define USBC_UOG2_OTGSC_ASVIE_SHIFT 26 |
| #define USBC_UOG2_OTGSC_BSVIE_MASK 0x8000000u |
| #define USBC_UOG2_OTGSC_BSVIE_SHIFT 27 |
| #define USBC_UOG2_OTGSC_BSEIE_MASK 0x10000000u |
| #define USBC_UOG2_OTGSC_BSEIE_SHIFT 28 |
| #define USBC_UOG2_OTGSC_EN_1MS_MASK 0x20000000u |
| #define USBC_UOG2_OTGSC_EN_1MS_SHIFT 29 |
| #define USBC_UOG2_OTGSC_DPIE_MASK 0x40000000u |
| #define USBC_UOG2_OTGSC_DPIE_SHIFT 30 |
| /* UOG2_USBMODE Bit Fields */ |
| #define USBC_UOG2_USBMODE_CM_MASK 0x3u |
| #define USBC_UOG2_USBMODE_CM_SHIFT 0 |
| #define USBC_UOG2_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_USBMODE_CM_SHIFT))&USBC_UOG2_USBMODE_CM_MASK) |
| #define USBC_UOG2_USBMODE_ES_MASK 0x4u |
| #define USBC_UOG2_USBMODE_ES_SHIFT 2 |
| #define USBC_UOG2_USBMODE_SLOM_MASK 0x8u |
| #define USBC_UOG2_USBMODE_SLOM_SHIFT 3 |
| #define USBC_UOG2_USBMODE_SDIS_MASK 0x10u |
| #define USBC_UOG2_USBMODE_SDIS_SHIFT 4 |
| /* UOG2_ENDPTSETUPSTAT Bit Fields */ |
| #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK 0xFFFFu |
| #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT 0 |
| #define USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USBC_UOG2_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) |
| /* UOG2_ENDPTPRIME Bit Fields */ |
| #define USBC_UOG2_ENDPTPRIME_PERB_MASK 0xFFu |
| #define USBC_UOG2_ENDPTPRIME_PERB_SHIFT 0 |
| #define USBC_UOG2_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTPRIME_PERB_SHIFT))&USBC_UOG2_ENDPTPRIME_PERB_MASK) |
| #define USBC_UOG2_ENDPTPRIME_PETB_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTPRIME_PETB_SHIFT 16 |
| #define USBC_UOG2_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTPRIME_PETB_SHIFT))&USBC_UOG2_ENDPTPRIME_PETB_MASK) |
| /* UOG2_ENDPTFLUSH Bit Fields */ |
| #define USBC_UOG2_ENDPTFLUSH_FERB_MASK 0xFFu |
| #define USBC_UOG2_ENDPTFLUSH_FERB_SHIFT 0 |
| #define USBC_UOG2_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTFLUSH_FERB_SHIFT))&USBC_UOG2_ENDPTFLUSH_FERB_MASK) |
| #define USBC_UOG2_ENDPTFLUSH_FETB_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTFLUSH_FETB_SHIFT 16 |
| #define USBC_UOG2_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTFLUSH_FETB_SHIFT))&USBC_UOG2_ENDPTFLUSH_FETB_MASK) |
| /* UOG2_ENDPTSTAT Bit Fields */ |
| #define USBC_UOG2_ENDPTSTAT_ERBR_MASK 0xFFu |
| #define USBC_UOG2_ENDPTSTAT_ERBR_SHIFT 0 |
| #define USBC_UOG2_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSTAT_ERBR_SHIFT))&USBC_UOG2_ENDPTSTAT_ERBR_MASK) |
| #define USBC_UOG2_ENDPTSTAT_ETBR_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTSTAT_ETBR_SHIFT 16 |
| #define USBC_UOG2_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTSTAT_ETBR_SHIFT))&USBC_UOG2_ENDPTSTAT_ETBR_MASK) |
| /* UOG2_ENDPTCOMPLETE Bit Fields */ |
| #define USBC_UOG2_ENDPTCOMPLETE_ERCE_MASK 0xFFu |
| #define USBC_UOG2_ENDPTCOMPLETE_ERCE_SHIFT 0 |
| #define USBC_UOG2_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCOMPLETE_ERCE_SHIFT))&USBC_UOG2_ENDPTCOMPLETE_ERCE_MASK) |
| #define USBC_UOG2_ENDPTCOMPLETE_ETCE_MASK 0xFF0000u |
| #define USBC_UOG2_ENDPTCOMPLETE_ETCE_SHIFT 16 |
| #define USBC_UOG2_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCOMPLETE_ETCE_SHIFT))&USBC_UOG2_ENDPTCOMPLETE_ETCE_MASK) |
| /* UOG2_ENDPTCTRL0 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL0_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL0_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL0_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL0_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL0_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL0_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL0_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL0_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL0_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL0_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL0_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL0_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL0_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL0_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL0_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL0_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL1 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL1_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL1_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL1_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL1_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL1_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL1_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL1_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL1_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL1_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL1_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL1_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL1_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL1_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL1_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL1_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL1_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL1_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL1_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL1_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL1_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL1_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL1_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL1_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL1_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL1_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL1_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL1_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL1_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL2 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL2_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL2_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL2_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL2_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL2_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL2_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL2_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL2_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL2_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL2_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL2_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL2_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL2_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL2_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL2_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL2_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL2_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL2_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL2_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL2_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL2_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL2_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL2_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL2_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL2_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL2_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL2_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL2_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL3 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL3_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL3_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL3_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL3_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL3_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL3_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL3_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL3_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL3_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL3_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL3_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL3_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL3_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL3_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL3_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL3_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL3_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL3_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL3_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL3_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL3_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL3_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL3_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL3_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL3_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL3_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL3_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL3_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL4 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL4_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL4_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL4_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL4_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL4_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL4_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL4_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL4_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL4_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL4_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL4_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL4_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL4_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL4_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL4_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL4_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL4_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL4_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL4_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL4_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL4_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL4_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL4_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL4_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL4_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL4_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL4_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL4_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL5 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL5_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL5_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL5_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL5_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL5_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL5_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL5_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL5_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL5_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL5_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL5_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL5_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL5_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL5_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL5_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL5_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL5_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL5_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL5_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL5_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL5_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL5_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL5_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL5_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL5_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL5_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL5_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL5_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL6 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL6_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL6_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL6_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL6_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL6_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL6_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL6_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL6_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL6_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL6_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL6_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL6_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL6_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL6_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL6_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL6_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL6_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL6_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL6_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL6_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL6_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL6_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL6_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL6_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL6_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL6_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL6_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL6_TXE_SHIFT 23 |
| /* UOG2_ENDPTCTRL7 Bit Fields */ |
| #define USBC_UOG2_ENDPTCTRL7_RXS_MASK 0x1u |
| #define USBC_UOG2_ENDPTCTRL7_RXS_SHIFT 0 |
| #define USBC_UOG2_ENDPTCTRL7_RXD_MASK 0x2u |
| #define USBC_UOG2_ENDPTCTRL7_RXD_SHIFT 1 |
| #define USBC_UOG2_ENDPTCTRL7_RXT_MASK 0xCu |
| #define USBC_UOG2_ENDPTCTRL7_RXT_SHIFT 2 |
| #define USBC_UOG2_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL7_RXT_SHIFT))&USBC_UOG2_ENDPTCTRL7_RXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL7_RXI_MASK 0x20u |
| #define USBC_UOG2_ENDPTCTRL7_RXI_SHIFT 5 |
| #define USBC_UOG2_ENDPTCTRL7_RXR_MASK 0x40u |
| #define USBC_UOG2_ENDPTCTRL7_RXR_SHIFT 6 |
| #define USBC_UOG2_ENDPTCTRL7_RXE_MASK 0x80u |
| #define USBC_UOG2_ENDPTCTRL7_RXE_SHIFT 7 |
| #define USBC_UOG2_ENDPTCTRL7_TXS_MASK 0x10000u |
| #define USBC_UOG2_ENDPTCTRL7_TXS_SHIFT 16 |
| #define USBC_UOG2_ENDPTCTRL7_TXD_MASK 0x20000u |
| #define USBC_UOG2_ENDPTCTRL7_TXD_SHIFT 17 |
| #define USBC_UOG2_ENDPTCTRL7_TXT_MASK 0xC0000u |
| #define USBC_UOG2_ENDPTCTRL7_TXT_SHIFT 18 |
| #define USBC_UOG2_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UOG2_ENDPTCTRL7_TXT_SHIFT))&USBC_UOG2_ENDPTCTRL7_TXT_MASK) |
| #define USBC_UOG2_ENDPTCTRL7_TXI_MASK 0x200000u |
| #define USBC_UOG2_ENDPTCTRL7_TXI_SHIFT 21 |
| #define USBC_UOG2_ENDPTCTRL7_TXR_MASK 0x400000u |
| #define USBC_UOG2_ENDPTCTRL7_TXR_SHIFT 22 |
| #define USBC_UOG2_ENDPTCTRL7_TXE_MASK 0x800000u |
| #define USBC_UOG2_ENDPTCTRL7_TXE_SHIFT 23 |
| /* UH1_ID Bit Fields */ |
| #define USBC_UH1_ID_ID_MASK 0x3Fu |
| #define USBC_UH1_ID_ID_SHIFT 0 |
| #define USBC_UH1_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_ID_SHIFT))&USBC_UH1_ID_ID_MASK) |
| #define USBC_UH1_ID_NID_MASK 0x3F00u |
| #define USBC_UH1_ID_NID_SHIFT 8 |
| #define USBC_UH1_ID_NID(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_NID_SHIFT))&USBC_UH1_ID_NID_MASK) |
| #define USBC_UH1_ID_REVISION_MASK 0xFF0000u |
| #define USBC_UH1_ID_REVISION_SHIFT 16 |
| #define USBC_UH1_ID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ID_REVISION_SHIFT))&USBC_UH1_ID_REVISION_MASK) |
| /* UH1_HWGENERAL Bit Fields */ |
| #define USBC_UH1_HWGENERAL_PHYW_MASK 0x30u |
| #define USBC_UH1_HWGENERAL_PHYW_SHIFT 4 |
| #define USBC_UH1_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_PHYW_SHIFT))&USBC_UH1_HWGENERAL_PHYW_MASK) |
| #define USBC_UH1_HWGENERAL_PHYM_MASK 0x1C0u |
| #define USBC_UH1_HWGENERAL_PHYM_SHIFT 6 |
| #define USBC_UH1_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_PHYM_SHIFT))&USBC_UH1_HWGENERAL_PHYM_MASK) |
| #define USBC_UH1_HWGENERAL_SM_MASK 0x600u |
| #define USBC_UH1_HWGENERAL_SM_SHIFT 9 |
| #define USBC_UH1_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWGENERAL_SM_SHIFT))&USBC_UH1_HWGENERAL_SM_MASK) |
| /* UH1_HWHOST Bit Fields */ |
| #define USBC_UH1_HWHOST_HC_MASK 0x1u |
| #define USBC_UH1_HWHOST_HC_SHIFT 0 |
| #define USBC_UH1_HWHOST_NPORT_MASK 0xEu |
| #define USBC_UH1_HWHOST_NPORT_SHIFT 1 |
| #define USBC_UH1_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWHOST_NPORT_SHIFT))&USBC_UH1_HWHOST_NPORT_MASK) |
| /* UH1_HWTXBUF Bit Fields */ |
| #define USBC_UH1_HWTXBUF_TXBURST_MASK 0xFFu |
| #define USBC_UH1_HWTXBUF_TXBURST_SHIFT 0 |
| #define USBC_UH1_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWTXBUF_TXBURST_SHIFT))&USBC_UH1_HWTXBUF_TXBURST_MASK) |
| #define USBC_UH1_HWTXBUF_TXCHANADD_MASK 0xFF0000u |
| #define USBC_UH1_HWTXBUF_TXCHANADD_SHIFT 16 |
| #define USBC_UH1_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWTXBUF_TXCHANADD_SHIFT))&USBC_UH1_HWTXBUF_TXCHANADD_MASK) |
| /* UH1_HWRXBUF Bit Fields */ |
| #define USBC_UH1_HWRXBUF_RXBURST_MASK 0xFFu |
| #define USBC_UH1_HWRXBUF_RXBURST_SHIFT 0 |
| #define USBC_UH1_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWRXBUF_RXBURST_SHIFT))&USBC_UH1_HWRXBUF_RXBURST_MASK) |
| #define USBC_UH1_HWRXBUF_RXADD_MASK 0xFF00u |
| #define USBC_UH1_HWRXBUF_RXADD_SHIFT 8 |
| #define USBC_UH1_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HWRXBUF_RXADD_SHIFT))&USBC_UH1_HWRXBUF_RXADD_MASK) |
| /* UH1_GPTIMER0LD Bit Fields */ |
| #define USBC_UH1_GPTIMER0LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UH1_GPTIMER0LD_GPTLD_SHIFT 0 |
| #define USBC_UH1_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER0LD_GPTLD_SHIFT))&USBC_UH1_GPTIMER0LD_GPTLD_MASK) |
| /* UH1_GPTIMER0CTRL Bit Fields */ |
| #define USBC_UH1_GPTIMER0CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UH1_GPTIMER0CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UH1_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER0CTRL_GPTCNT_SHIFT))&USBC_UH1_GPTIMER0CTRL_GPTCNT_MASK) |
| #define USBC_UH1_GPTIMER0CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UH1_GPTIMER0CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UH1_GPTIMER0CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UH1_GPTIMER0CTRL_GPTRST_SHIFT 30 |
| #define USBC_UH1_GPTIMER0CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UH1_GPTIMER0CTRL_GPTRUN_SHIFT 31 |
| /* UH1_GPTIMER1LD Bit Fields */ |
| #define USBC_UH1_GPTIMER1LD_GPTLD_MASK 0xFFFFFFu |
| #define USBC_UH1_GPTIMER1LD_GPTLD_SHIFT 0 |
| #define USBC_UH1_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER1LD_GPTLD_SHIFT))&USBC_UH1_GPTIMER1LD_GPTLD_MASK) |
| /* UH1_GPTIMER1CTRL Bit Fields */ |
| #define USBC_UH1_GPTIMER1CTRL_GPTCNT_MASK 0xFFFFFFu |
| #define USBC_UH1_GPTIMER1CTRL_GPTCNT_SHIFT 0 |
| #define USBC_UH1_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_GPTIMER1CTRL_GPTCNT_SHIFT))&USBC_UH1_GPTIMER1CTRL_GPTCNT_MASK) |
| #define USBC_UH1_GPTIMER1CTRL_GPTMODE_MASK 0x1000000u |
| #define USBC_UH1_GPTIMER1CTRL_GPTMODE_SHIFT 24 |
| #define USBC_UH1_GPTIMER1CTRL_GPTRST_MASK 0x40000000u |
| #define USBC_UH1_GPTIMER1CTRL_GPTRST_SHIFT 30 |
| #define USBC_UH1_GPTIMER1CTRL_GPTRUN_MASK 0x80000000u |
| #define USBC_UH1_GPTIMER1CTRL_GPTRUN_SHIFT 31 |
| /* UH1_SBUSCFG Bit Fields */ |
| #define USBC_UH1_SBUSCFG_AHBBRST_MASK 0x7u |
| #define USBC_UH1_SBUSCFG_AHBBRST_SHIFT 0 |
| #define USBC_UH1_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_SBUSCFG_AHBBRST_SHIFT))&USBC_UH1_SBUSCFG_AHBBRST_MASK) |
| /* UH1_CAPLENGTH Bit Fields */ |
| #define USBC_UH1_CAPLENGTH_CAPLENGTH_MASK 0xFFu |
| #define USBC_UH1_CAPLENGTH_CAPLENGTH_SHIFT 0 |
| #define USBC_UH1_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x))<<USBC_UH1_CAPLENGTH_CAPLENGTH_SHIFT))&USBC_UH1_CAPLENGTH_CAPLENGTH_MASK) |
| /* UH1_HCIVERSION Bit Fields */ |
| #define USBC_UH1_HCIVERSION_HCIVERSION_MASK 0xFFFFu |
| #define USBC_UH1_HCIVERSION_HCIVERSION_SHIFT 0 |
| #define USBC_UH1_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USBC_UH1_HCIVERSION_HCIVERSION_SHIFT))&USBC_UH1_HCIVERSION_HCIVERSION_MASK) |
| /* UH1_HCSPARAMS Bit Fields */ |
| #define USBC_UH1_HCSPARAMS_N_PORTS_MASK 0xFu |
| #define USBC_UH1_HCSPARAMS_N_PORTS_SHIFT 0 |
| #define USBC_UH1_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PORTS_SHIFT))&USBC_UH1_HCSPARAMS_N_PORTS_MASK) |
| #define USBC_UH1_HCSPARAMS_PPC_MASK 0x10u |
| #define USBC_UH1_HCSPARAMS_PPC_SHIFT 4 |
| #define USBC_UH1_HCSPARAMS_N_PCC_MASK 0xF00u |
| #define USBC_UH1_HCSPARAMS_N_PCC_SHIFT 8 |
| #define USBC_UH1_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PCC_SHIFT))&USBC_UH1_HCSPARAMS_N_PCC_MASK) |
| #define USBC_UH1_HCSPARAMS_N_CC_MASK 0xF000u |
| #define USBC_UH1_HCSPARAMS_N_CC_SHIFT 12 |
| #define USBC_UH1_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_CC_SHIFT))&USBC_UH1_HCSPARAMS_N_CC_MASK) |
| #define USBC_UH1_HCSPARAMS_PI_MASK 0x10000u |
| #define USBC_UH1_HCSPARAMS_PI_SHIFT 16 |
| #define USBC_UH1_HCSPARAMS_N_PTT_MASK 0xF00000u |
| #define USBC_UH1_HCSPARAMS_N_PTT_SHIFT 20 |
| #define USBC_UH1_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_PTT_SHIFT))&USBC_UH1_HCSPARAMS_N_PTT_MASK) |
| #define USBC_UH1_HCSPARAMS_N_TT_MASK 0xF000000u |
| #define USBC_UH1_HCSPARAMS_N_TT_SHIFT 24 |
| #define USBC_UH1_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCSPARAMS_N_TT_SHIFT))&USBC_UH1_HCSPARAMS_N_TT_MASK) |
| /* UH1_HCCPARAMS Bit Fields */ |
| #define USBC_UH1_HCCPARAMS_ADC_MASK 0x1u |
| #define USBC_UH1_HCCPARAMS_ADC_SHIFT 0 |
| #define USBC_UH1_HCCPARAMS_PFL_MASK 0x2u |
| #define USBC_UH1_HCCPARAMS_PFL_SHIFT 1 |
| #define USBC_UH1_HCCPARAMS_ASP_MASK 0x4u |
| #define USBC_UH1_HCCPARAMS_ASP_SHIFT 2 |
| #define USBC_UH1_HCCPARAMS_IST_MASK 0xF0u |
| #define USBC_UH1_HCCPARAMS_IST_SHIFT 4 |
| #define USBC_UH1_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCCPARAMS_IST_SHIFT))&USBC_UH1_HCCPARAMS_IST_MASK) |
| #define USBC_UH1_HCCPARAMS_EECP_MASK 0xFF00u |
| #define USBC_UH1_HCCPARAMS_EECP_SHIFT 8 |
| #define USBC_UH1_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_HCCPARAMS_EECP_SHIFT))&USBC_UH1_HCCPARAMS_EECP_MASK) |
| /* UH1_USBCMD Bit Fields */ |
| #define USBC_UH1_USBCMD_RS_MASK 0x1u |
| #define USBC_UH1_USBCMD_RS_SHIFT 0 |
| #define USBC_UH1_USBCMD_RST_MASK 0x2u |
| #define USBC_UH1_USBCMD_RST_SHIFT 1 |
| #define USBC_UH1_USBCMD_FS_1_MASK 0xCu |
| #define USBC_UH1_USBCMD_FS_1_SHIFT 2 |
| #define USBC_UH1_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_FS_1_SHIFT))&USBC_UH1_USBCMD_FS_1_MASK) |
| #define USBC_UH1_USBCMD_PSE_MASK 0x10u |
| #define USBC_UH1_USBCMD_PSE_SHIFT 4 |
| #define USBC_UH1_USBCMD_ASE_MASK 0x20u |
| #define USBC_UH1_USBCMD_ASE_SHIFT 5 |
| #define USBC_UH1_USBCMD_IAA_MASK 0x40u |
| #define USBC_UH1_USBCMD_IAA_SHIFT 6 |
| #define USBC_UH1_USBCMD_ASP_MASK 0x300u |
| #define USBC_UH1_USBCMD_ASP_SHIFT 8 |
| #define USBC_UH1_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_ASP_SHIFT))&USBC_UH1_USBCMD_ASP_MASK) |
| #define USBC_UH1_USBCMD_ASPE_MASK 0x800u |
| #define USBC_UH1_USBCMD_ASPE_SHIFT 11 |
| #define USBC_UH1_USBCMD_SUTW_MASK 0x2000u |
| #define USBC_UH1_USBCMD_SUTW_SHIFT 13 |
| #define USBC_UH1_USBCMD_ATDTW_MASK 0x4000u |
| #define USBC_UH1_USBCMD_ATDTW_SHIFT 14 |
| #define USBC_UH1_USBCMD_FS_2_MASK 0x8000u |
| #define USBC_UH1_USBCMD_FS_2_SHIFT 15 |
| #define USBC_UH1_USBCMD_ITC_MASK 0xFF0000u |
| #define USBC_UH1_USBCMD_ITC_SHIFT 16 |
| #define USBC_UH1_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBCMD_ITC_SHIFT))&USBC_UH1_USBCMD_ITC_MASK) |
| /* UH1_USBSTS Bit Fields */ |
| #define USBC_UH1_USBSTS_UI_MASK 0x1u |
| #define USBC_UH1_USBSTS_UI_SHIFT 0 |
| #define USBC_UH1_USBSTS_UEI_MASK 0x2u |
| #define USBC_UH1_USBSTS_UEI_SHIFT 1 |
| #define USBC_UH1_USBSTS_PCI_MASK 0x4u |
| #define USBC_UH1_USBSTS_PCI_SHIFT 2 |
| #define USBC_UH1_USBSTS_FRI_MASK 0x8u |
| #define USBC_UH1_USBSTS_FRI_SHIFT 3 |
| #define USBC_UH1_USBSTS_SEI_MASK 0x10u |
| #define USBC_UH1_USBSTS_SEI_SHIFT 4 |
| #define USBC_UH1_USBSTS_AAI_MASK 0x20u |
| #define USBC_UH1_USBSTS_AAI_SHIFT 5 |
| #define USBC_UH1_USBSTS_URI_MASK 0x40u |
| #define USBC_UH1_USBSTS_URI_SHIFT 6 |
| #define USBC_UH1_USBSTS_SRI_MASK 0x80u |
| #define USBC_UH1_USBSTS_SRI_SHIFT 7 |
| #define USBC_UH1_USBSTS_SLI_MASK 0x100u |
| #define USBC_UH1_USBSTS_SLI_SHIFT 8 |
| #define USBC_UH1_USBSTS_ULPII_MASK 0x400u |
| #define USBC_UH1_USBSTS_ULPII_SHIFT 10 |
| #define USBC_UH1_USBSTS_HCH_MASK 0x1000u |
| #define USBC_UH1_USBSTS_HCH_SHIFT 12 |
| #define USBC_UH1_USBSTS_RCL_MASK 0x2000u |
| #define USBC_UH1_USBSTS_RCL_SHIFT 13 |
| #define USBC_UH1_USBSTS_PS_MASK 0x4000u |
| #define USBC_UH1_USBSTS_PS_SHIFT 14 |
| #define USBC_UH1_USBSTS_AS_MASK 0x8000u |
| #define USBC_UH1_USBSTS_AS_SHIFT 15 |
| #define USBC_UH1_USBSTS_NAKI_MASK 0x10000u |
| #define USBC_UH1_USBSTS_NAKI_SHIFT 16 |
| #define USBC_UH1_USBSTS_TI0_MASK 0x1000000u |
| #define USBC_UH1_USBSTS_TI0_SHIFT 24 |
| #define USBC_UH1_USBSTS_TI1_MASK 0x2000000u |
| #define USBC_UH1_USBSTS_TI1_SHIFT 25 |
| /* UH1_USBINTR Bit Fields */ |
| #define USBC_UH1_USBINTR_UE_MASK 0x1u |
| #define USBC_UH1_USBINTR_UE_SHIFT 0 |
| #define USBC_UH1_USBINTR_UEE_MASK 0x2u |
| #define USBC_UH1_USBINTR_UEE_SHIFT 1 |
| #define USBC_UH1_USBINTR_PCE_MASK 0x4u |
| #define USBC_UH1_USBINTR_PCE_SHIFT 2 |
| #define USBC_UH1_USBINTR_FRE_MASK 0x8u |
| #define USBC_UH1_USBINTR_FRE_SHIFT 3 |
| #define USBC_UH1_USBINTR_SEE_MASK 0x10u |
| #define USBC_UH1_USBINTR_SEE_SHIFT 4 |
| #define USBC_UH1_USBINTR_AAE_MASK 0x20u |
| #define USBC_UH1_USBINTR_AAE_SHIFT 5 |
| #define USBC_UH1_USBINTR_URE_MASK 0x40u |
| #define USBC_UH1_USBINTR_URE_SHIFT 6 |
| #define USBC_UH1_USBINTR_SRE_MASK 0x80u |
| #define USBC_UH1_USBINTR_SRE_SHIFT 7 |
| #define USBC_UH1_USBINTR_SLE_MASK 0x100u |
| #define USBC_UH1_USBINTR_SLE_SHIFT 8 |
| #define USBC_UH1_USBINTR_ULPIE_MASK 0x400u |
| #define USBC_UH1_USBINTR_ULPIE_SHIFT 10 |
| #define USBC_UH1_USBINTR_NAKE_MASK 0x10000u |
| #define USBC_UH1_USBINTR_NAKE_SHIFT 16 |
| #define USBC_UH1_USBINTR_UAIE_MASK 0x40000u |
| #define USBC_UH1_USBINTR_UAIE_SHIFT 18 |
| #define USBC_UH1_USBINTR_UPIE_MASK 0x80000u |
| #define USBC_UH1_USBINTR_UPIE_SHIFT 19 |
| #define USBC_UH1_USBINTR_TIE0_MASK 0x1000000u |
| #define USBC_UH1_USBINTR_TIE0_SHIFT 24 |
| #define USBC_UH1_USBINTR_TIE1_MASK 0x2000000u |
| #define USBC_UH1_USBINTR_TIE1_SHIFT 25 |
| /* UH1_FRINDEX Bit Fields */ |
| #define USBC_UH1_FRINDEX_FRINDEX_MASK 0x3FFFu |
| #define USBC_UH1_FRINDEX_FRINDEX_SHIFT 0 |
| #define USBC_UH1_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_FRINDEX_FRINDEX_SHIFT))&USBC_UH1_FRINDEX_FRINDEX_MASK) |
| /* UH1_PERIODICLISTBASE Bit Fields */ |
| #define USBC_UH1_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u |
| #define USBC_UH1_PERIODICLISTBASE_BASEADR_SHIFT 12 |
| #define USBC_UH1_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PERIODICLISTBASE_BASEADR_SHIFT))&USBC_UH1_PERIODICLISTBASE_BASEADR_MASK) |
| /* UH1_ASYNCLISTADDR Bit Fields */ |
| #define USBC_UH1_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u |
| #define USBC_UH1_ASYNCLISTADDR_ASYBASE_SHIFT 5 |
| #define USBC_UH1_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_ASYNCLISTADDR_ASYBASE_SHIFT))&USBC_UH1_ASYNCLISTADDR_ASYBASE_MASK) |
| /* UH1_BURSTSIZE Bit Fields */ |
| #define USBC_UH1_BURSTSIZE_RXPBURST_MASK 0xFFu |
| #define USBC_UH1_BURSTSIZE_RXPBURST_SHIFT 0 |
| #define USBC_UH1_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_BURSTSIZE_RXPBURST_SHIFT))&USBC_UH1_BURSTSIZE_RXPBURST_MASK) |
| #define USBC_UH1_BURSTSIZE_TXPBURST_MASK 0x1FF00u |
| #define USBC_UH1_BURSTSIZE_TXPBURST_SHIFT 8 |
| #define USBC_UH1_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_BURSTSIZE_TXPBURST_SHIFT))&USBC_UH1_BURSTSIZE_TXPBURST_MASK) |
| /* UH1_TXFILLTUNING Bit Fields */ |
| #define USBC_UH1_TXFILLTUNING_TXSCHOH_MASK 0xFFu |
| #define USBC_UH1_TXFILLTUNING_TXSCHOH_SHIFT 0 |
| #define USBC_UH1_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXSCHOH_SHIFT))&USBC_UH1_TXFILLTUNING_TXSCHOH_MASK) |
| #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH_MASK 0x1F00u |
| #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH_SHIFT 8 |
| #define USBC_UH1_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USBC_UH1_TXFILLTUNING_TXSCHHEALTH_MASK) |
| #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES_MASK 0x3F0000u |
| #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES_SHIFT 16 |
| #define USBC_UH1_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USBC_UH1_TXFILLTUNING_TXFIFOTHRES_MASK) |
| /* UH1_CONFIGFLAG Bit Fields */ |
| #define USBC_UH1_CONFIGFLAG_CF_MASK 0x1u |
| #define USBC_UH1_CONFIGFLAG_CF_SHIFT 0 |
| /* UH1_PORTSC1 Bit Fields */ |
| #define USBC_UH1_PORTSC1_CCS_MASK 0x1u |
| #define USBC_UH1_PORTSC1_CCS_SHIFT 0 |
| #define USBC_UH1_PORTSC1_CSC_MASK 0x2u |
| #define USBC_UH1_PORTSC1_CSC_SHIFT 1 |
| #define USBC_UH1_PORTSC1_PE_MASK 0x4u |
| #define USBC_UH1_PORTSC1_PE_SHIFT 2 |
| #define USBC_UH1_PORTSC1_PEC_MASK 0x8u |
| #define USBC_UH1_PORTSC1_PEC_SHIFT 3 |
| #define USBC_UH1_PORTSC1_OCA_MASK 0x10u |
| #define USBC_UH1_PORTSC1_OCA_SHIFT 4 |
| #define USBC_UH1_PORTSC1_OCC_MASK 0x20u |
| #define USBC_UH1_PORTSC1_OCC_SHIFT 5 |
| #define USBC_UH1_PORTSC1_FPR_MASK 0x40u |
| #define USBC_UH1_PORTSC1_FPR_SHIFT 6 |
| #define USBC_UH1_PORTSC1_SUSP_MASK 0x80u |
| #define USBC_UH1_PORTSC1_SUSP_SHIFT 7 |
| #define USBC_UH1_PORTSC1_PR_MASK 0x100u |
| #define USBC_UH1_PORTSC1_PR_SHIFT 8 |
| #define USBC_UH1_PORTSC1_HSP_MASK 0x200u |
| #define USBC_UH1_PORTSC1_HSP_SHIFT 9 |
| #define USBC_UH1_PORTSC1_LS_MASK 0xC00u |
| #define USBC_UH1_PORTSC1_LS_SHIFT 10 |
| #define USBC_UH1_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_LS_SHIFT))&USBC_UH1_PORTSC1_LS_MASK) |
| #define USBC_UH1_PORTSC1_PP_MASK 0x1000u |
| #define USBC_UH1_PORTSC1_PP_SHIFT 12 |
| #define USBC_UH1_PORTSC1_PO_MASK 0x2000u |
| #define USBC_UH1_PORTSC1_PO_SHIFT 13 |
| #define USBC_UH1_PORTSC1_PIC_MASK 0xC000u |
| #define USBC_UH1_PORTSC1_PIC_SHIFT 14 |
| #define USBC_UH1_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PIC_SHIFT))&USBC_UH1_PORTSC1_PIC_MASK) |
| #define USBC_UH1_PORTSC1_PTC_MASK 0xF0000u |
| #define USBC_UH1_PORTSC1_PTC_SHIFT 16 |
| #define USBC_UH1_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PTC_SHIFT))&USBC_UH1_PORTSC1_PTC_MASK) |
| #define USBC_UH1_PORTSC1_WKCN_MASK 0x100000u |
| #define USBC_UH1_PORTSC1_WKCN_SHIFT 20 |
| #define USBC_UH1_PORTSC1_WKDC_MASK 0x200000u |
| #define USBC_UH1_PORTSC1_WKDC_SHIFT 21 |
| #define USBC_UH1_PORTSC1_WKOC_MASK 0x400000u |
| #define USBC_UH1_PORTSC1_WKOC_SHIFT 22 |
| #define USBC_UH1_PORTSC1_PHCD_MASK 0x800000u |
| #define USBC_UH1_PORTSC1_PHCD_SHIFT 23 |
| #define USBC_UH1_PORTSC1_PFSC_MASK 0x1000000u |
| #define USBC_UH1_PORTSC1_PFSC_SHIFT 24 |
| #define USBC_UH1_PORTSC1_PTS_2_MASK 0x2000000u |
| #define USBC_UH1_PORTSC1_PTS_2_SHIFT 25 |
| #define USBC_UH1_PORTSC1_PSPD_MASK 0xC000000u |
| #define USBC_UH1_PORTSC1_PSPD_SHIFT 26 |
| #define USBC_UH1_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PSPD_SHIFT))&USBC_UH1_PORTSC1_PSPD_MASK) |
| #define USBC_UH1_PORTSC1_PTW_MASK 0x10000000u |
| #define USBC_UH1_PORTSC1_PTW_SHIFT 28 |
| #define USBC_UH1_PORTSC1_STS_MASK 0x20000000u |
| #define USBC_UH1_PORTSC1_STS_SHIFT 29 |
| #define USBC_UH1_PORTSC1_PTS_1_MASK 0xC0000000u |
| #define USBC_UH1_PORTSC1_PTS_1_SHIFT 30 |
| #define USBC_UH1_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_PORTSC1_PTS_1_SHIFT))&USBC_UH1_PORTSC1_PTS_1_MASK) |
| /* UH1_USBMODE Bit Fields */ |
| #define USBC_UH1_USBMODE_CM_MASK 0x3u |
| #define USBC_UH1_USBMODE_CM_SHIFT 0 |
| #define USBC_UH1_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x))<<USBC_UH1_USBMODE_CM_SHIFT))&USBC_UH1_USBMODE_CM_MASK) |
| #define USBC_UH1_USBMODE_ES_MASK 0x4u |
| #define USBC_UH1_USBMODE_ES_SHIFT 2 |
| #define USBC_UH1_USBMODE_SLOM_MASK 0x8u |
| #define USBC_UH1_USBMODE_SLOM_SHIFT 3 |
| #define USBC_UH1_USBMODE_SDIS_MASK 0x10u |
| #define USBC_UH1_USBMODE_SDIS_SHIFT 4 |
| |
| /*! |
| * @} |
| */ /* end of group USBC_Register_Masks */ |
| |
| /* USBC - Peripheral instance base addresses */ |
| /** Peripheral USBC base address */ |
| #define USBC_BASE (0x42184000u) |
| /** Peripheral USBC base pointer */ |
| #define USBC ((USBC_Type *)USBC_BASE) |
| #define USBC_BASE_PTR (USBC) |
| /** Array initializer of USBC peripheral base addresses */ |
| #define USBC_BASE_ADDRS { USBC_BASE } |
| /** Array initializer of USBC peripheral base pointers */ |
| #define USBC_BASE_PTRS { USBC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBC_Register_Accessor_Macros USBC - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBC - Register instance definitions */ |
| /* USBC */ |
| #define USBC_UOG1_ID USBC_UOG1_ID_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HWGENERAL USBC_UOG1_HWGENERAL_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HWHOST USBC_UOG1_HWHOST_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HWDEVICE USBC_UOG1_HWDEVICE_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HWTXBUF USBC_UOG1_HWTXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HWRXBUF USBC_UOG1_HWRXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_GPTIMER0LD USBC_UOG1_GPTIMER0LD_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_GPTIMER0CTRL USBC_UOG1_GPTIMER0CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_GPTIMER1LD USBC_UOG1_GPTIMER1LD_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_GPTIMER1CTRL USBC_UOG1_GPTIMER1CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_SBUSCFG USBC_UOG1_SBUSCFG_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_CAPLENGTH USBC_UOG1_CAPLENGTH_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HCIVERSION USBC_UOG1_HCIVERSION_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HCSPARAMS USBC_UOG1_HCSPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_HCCPARAMS USBC_UOG1_HCCPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_DCIVERSION USBC_UOG1_DCIVERSION_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_DCCPARAMS USBC_UOG1_DCCPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_USBCMD USBC_UOG1_USBCMD_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_USBSTS USBC_UOG1_USBSTS_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_USBINTR USBC_UOG1_USBINTR_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_FRINDEX USBC_UOG1_FRINDEX_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_PERIODICLISTBASE USBC_UOG1_PERIODICLISTBASE_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_DEVICEADDR USBC_UOG1_DEVICEADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ASYNCLISTADDR USBC_UOG1_ASYNCLISTADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTLISTADDR USBC_UOG1_ENDPTLISTADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_BURSTSIZE USBC_UOG1_BURSTSIZE_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_TXFILLTUNING USBC_UOG1_TXFILLTUNING_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTNAK USBC_UOG1_ENDPTNAK_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTNAKEN USBC_UOG1_ENDPTNAKEN_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_CONFIGFLAG USBC_UOG1_CONFIGFLAG_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_PORTSC1 USBC_UOG1_PORTSC1_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_OTGSC USBC_UOG1_OTGSC_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_USBMODE USBC_UOG1_USBMODE_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTSETUPSTAT USBC_UOG1_ENDPTSETUPSTAT_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTPRIME USBC_UOG1_ENDPTPRIME_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTFLUSH USBC_UOG1_ENDPTFLUSH_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTSTAT USBC_UOG1_ENDPTSTAT_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCOMPLETE USBC_UOG1_ENDPTCOMPLETE_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL0 USBC_UOG1_ENDPTCTRL0_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL1 USBC_UOG1_ENDPTCTRL1_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL2 USBC_UOG1_ENDPTCTRL2_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL3 USBC_UOG1_ENDPTCTRL3_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL4 USBC_UOG1_ENDPTCTRL4_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL5 USBC_UOG1_ENDPTCTRL5_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL6 USBC_UOG1_ENDPTCTRL6_REG(USBC_BASE_PTR) |
| #define USBC_UOG1_ENDPTCTRL7 USBC_UOG1_ENDPTCTRL7_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ID USBC_UOG2_ID_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HWGENERAL USBC_UOG2_HWGENERAL_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HWHOST USBC_UOG2_HWHOST_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HWDEVICE USBC_UOG2_HWDEVICE_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HWTXBUF USBC_UOG2_HWTXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HWRXBUF USBC_UOG2_HWRXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_GPTIMER0LD USBC_UOG2_GPTIMER0LD_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_GPTIMER0CTRL USBC_UOG2_GPTIMER0CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_GPTIMER1LD USBC_UOG2_GPTIMER1LD_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_GPTIMER1CTRL USBC_UOG2_GPTIMER1CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_SBUSCFG USBC_UOG2_SBUSCFG_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_CAPLENGTH USBC_UOG2_CAPLENGTH_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HCIVERSION USBC_UOG2_HCIVERSION_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HCSPARAMS USBC_UOG2_HCSPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_HCCPARAMS USBC_UOG2_HCCPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_DCIVERSION USBC_UOG2_DCIVERSION_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_DCCPARAMS USBC_UOG2_DCCPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_USBCMD USBC_UOG2_USBCMD_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_USBSTS USBC_UOG2_USBSTS_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_USBINTR USBC_UOG2_USBINTR_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_FRINDEX USBC_UOG2_FRINDEX_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_PERIODICLISTBASE USBC_UOG2_PERIODICLISTBASE_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_DEVICEADDR USBC_UOG2_DEVICEADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ASYNCLISTADDR USBC_UOG2_ASYNCLISTADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTLISTADDR USBC_UOG2_ENDPTLISTADDR_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_BURSTSIZE USBC_UOG2_BURSTSIZE_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_TXFILLTUNING USBC_UOG2_TXFILLTUNING_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTNAK USBC_UOG2_ENDPTNAK_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTNAKEN USBC_UOG2_ENDPTNAKEN_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_CONFIGFLAG USBC_UOG2_CONFIGFLAG_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_PORTSC1 USBC_UOG2_PORTSC1_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_OTGSC USBC_UOG2_OTGSC_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_USBMODE USBC_UOG2_USBMODE_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTSETUPSTAT USBC_UOG2_ENDPTSETUPSTAT_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTPRIME USBC_UOG2_ENDPTPRIME_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTFLUSH USBC_UOG2_ENDPTFLUSH_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTSTAT USBC_UOG2_ENDPTSTAT_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCOMPLETE USBC_UOG2_ENDPTCOMPLETE_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL0 USBC_UOG2_ENDPTCTRL0_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL1 USBC_UOG2_ENDPTCTRL1_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL2 USBC_UOG2_ENDPTCTRL2_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL3 USBC_UOG2_ENDPTCTRL3_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL4 USBC_UOG2_ENDPTCTRL4_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL5 USBC_UOG2_ENDPTCTRL5_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL6 USBC_UOG2_ENDPTCTRL6_REG(USBC_BASE_PTR) |
| #define USBC_UOG2_ENDPTCTRL7 USBC_UOG2_ENDPTCTRL7_REG(USBC_BASE_PTR) |
| #define USBC_UH1_ID USBC_UH1_ID_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HWGENERAL USBC_UH1_HWGENERAL_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HWHOST USBC_UH1_HWHOST_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HWTXBUF USBC_UH1_HWTXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HWRXBUF USBC_UH1_HWRXBUF_REG(USBC_BASE_PTR) |
| #define USBC_UH1_GPTIMER0LD USBC_UH1_GPTIMER0LD_REG(USBC_BASE_PTR) |
| #define USBC_UH1_GPTIMER0CTRL USBC_UH1_GPTIMER0CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UH1_GPTIMER1LD USBC_UH1_GPTIMER1LD_REG(USBC_BASE_PTR) |
| #define USBC_UH1_GPTIMER1CTRL USBC_UH1_GPTIMER1CTRL_REG(USBC_BASE_PTR) |
| #define USBC_UH1_SBUSCFG USBC_UH1_SBUSCFG_REG(USBC_BASE_PTR) |
| #define USBC_UH1_CAPLENGTH USBC_UH1_CAPLENGTH_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HCIVERSION USBC_UH1_HCIVERSION_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HCSPARAMS USBC_UH1_HCSPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UH1_HCCPARAMS USBC_UH1_HCCPARAMS_REG(USBC_BASE_PTR) |
| #define USBC_UH1_USBCMD USBC_UH1_USBCMD_REG(USBC_BASE_PTR) |
| #define USBC_UH1_USBSTS USBC_UH1_USBSTS_REG(USBC_BASE_PTR) |
| #define USBC_UH1_USBINTR USBC_UH1_USBINTR_REG(USBC_BASE_PTR) |
| #define USBC_UH1_FRINDEX USBC_UH1_FRINDEX_REG(USBC_BASE_PTR) |
| #define USBC_UH1_PERIODICLISTBASE USBC_UH1_PERIODICLISTBASE_REG(USBC_BASE_PTR) |
| #define USBC_UH1_ASYNCLISTADDR USBC_UH1_ASYNCLISTADDR_REG(USBC_BASE_PTR) |
| #define USBC_UH1_BURSTSIZE USBC_UH1_BURSTSIZE_REG(USBC_BASE_PTR) |
| #define USBC_UH1_TXFILLTUNING USBC_UH1_TXFILLTUNING_REG(USBC_BASE_PTR) |
| #define USBC_UH1_CONFIGFLAG USBC_UH1_CONFIGFLAG_REG(USBC_BASE_PTR) |
| #define USBC_UH1_PORTSC1 USBC_UH1_PORTSC1_REG(USBC_BASE_PTR) |
| #define USBC_UH1_USBMODE USBC_UH1_USBMODE_REG(USBC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group USBC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group USBC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBNC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** USBNC - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[572]; |
| __I uint32_t USB_x_PHY_STS; /**< , offset: 0x23C */ |
| uint8_t RESERVED_1[20]; |
| __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ |
| uint8_t RESERVED_2[1448]; |
| __IO uint32_t USB_OTG1_CTRL; /**< USB OTG1 Control Register, offset: 0x800 */ |
| __IO uint32_t USB_OTG2_CTRL; /**< USB OTG2 Control Register, offset: 0x804 */ |
| __IO uint32_t USB_UH_CTRL; /**< USB Host Control Register, offset: 0x808 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t USB_UH_HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x810 */ |
| uint8_t RESERVED_4[4]; |
| __IO uint32_t USB_OTG1_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register, offset: 0x818 */ |
| __IO uint32_t USB_OTG2_PHY_CTRL_0; /**< OTG2 UTMI PHY Control 0 Register, offset: 0x81C */ |
| } USBNC_Type, *USBNC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBNC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBNC - Register accessors */ |
| #define USBNC_USB_x_PHY_STS_REG(base) ((base)->USB_x_PHY_STS) |
| #define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) |
| #define USBNC_USB_OTG1_CTRL_REG(base) ((base)->USB_OTG1_CTRL) |
| #define USBNC_USB_OTG2_CTRL_REG(base) ((base)->USB_OTG2_CTRL) |
| #define USBNC_USB_UH_CTRL_REG(base) ((base)->USB_UH_CTRL) |
| #define USBNC_USB_UH_HSIC_CTRL_REG(base) ((base)->USB_UH_HSIC_CTRL) |
| #define USBNC_USB_OTG1_PHY_CTRL_0_REG(base) ((base)->USB_OTG1_PHY_CTRL_0) |
| #define USBNC_USB_OTG2_PHY_CTRL_0_REG(base) ((base)->USB_OTG2_PHY_CTRL_0) |
| |
| /*! |
| * @} |
| */ /* end of group USBNC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBNC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBNC_Register_Masks USBNC Register Masks |
| * @{ |
| */ |
| |
| /* USB_x_PHY_STS Bit Fields */ |
| #define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u |
| #define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 |
| #define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT))&USBNC_USB_x_PHY_STS_LINE_STATE_MASK) |
| #define USBNC_USB_x_PHY_STS_SESS_VLD_MASK 0x4u |
| #define USBNC_USB_x_PHY_STS_SESS_VLD_SHIFT 2 |
| #define USBNC_USB_x_PHY_STS_VBUS_VLD_MASK 0x8u |
| #define USBNC_USB_x_PHY_STS_VBUS_VLD_SHIFT 3 |
| #define USBNC_USB_x_PHY_STS_ID_DIG_MASK 0x10u |
| #define USBNC_USB_x_PHY_STS_ID_DIG_SHIFT 4 |
| #define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_MASK 0x20000000u |
| #define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_SHIFT 29 |
| /* ADP_CFG2 Bit Fields */ |
| #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK 0x7Fu |
| #define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT 0 |
| #define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK) |
| #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK 0x80u |
| #define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT 7 |
| #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK 0xFF00u |
| #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT 8 |
| #define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK) |
| #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK 0xFF0000u |
| #define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT 16 |
| #define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT))&USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK) |
| /* USB_OTG1_CTRL Bit Fields */ |
| #define USBNC_USB_OTG1_CTRL_OVER_CUR_DIS_MASK 0x80u |
| #define USBNC_USB_OTG1_CTRL_OVER_CUR_DIS_SHIFT 7 |
| #define USBNC_USB_OTG1_CTRL_OVER_CUR_POL_MASK 0x100u |
| #define USBNC_USB_OTG1_CTRL_OVER_CUR_POL_SHIFT 8 |
| #define USBNC_USB_OTG1_CTRL_PWR_POL_MASK 0x200u |
| #define USBNC_USB_OTG1_CTRL_PWR_POL_SHIFT 9 |
| #define USBNC_USB_OTG1_CTRL_WIE_MASK 0x400u |
| #define USBNC_USB_OTG1_CTRL_WIE_SHIFT 10 |
| #define USBNC_USB_OTG1_CTRL_WKUP_SW_EN_MASK 0x4000u |
| #define USBNC_USB_OTG1_CTRL_WKUP_SW_EN_SHIFT 14 |
| #define USBNC_USB_OTG1_CTRL_WKUP_SW_MASK 0x8000u |
| #define USBNC_USB_OTG1_CTRL_WKUP_SW_SHIFT 15 |
| #define USBNC_USB_OTG1_CTRL_WKUP_ID_EN_MASK 0x10000u |
| #define USBNC_USB_OTG1_CTRL_WKUP_ID_EN_SHIFT 16 |
| #define USBNC_USB_OTG1_CTRL_WKUP_VBUS_EN_MASK 0x20000u |
| #define USBNC_USB_OTG1_CTRL_WKUP_VBUS_EN_SHIFT 17 |
| #define USBNC_USB_OTG1_CTRL_WIR_MASK 0x80000000u |
| #define USBNC_USB_OTG1_CTRL_WIR_SHIFT 31 |
| /* USB_OTG2_CTRL Bit Fields */ |
| #define USBNC_USB_OTG2_CTRL_OVER_CUR_DIS_MASK 0x80u |
| #define USBNC_USB_OTG2_CTRL_OVER_CUR_DIS_SHIFT 7 |
| #define USBNC_USB_OTG2_CTRL_OVER_CUR_POL_MASK 0x100u |
| #define USBNC_USB_OTG2_CTRL_OVER_CUR_POL_SHIFT 8 |
| #define USBNC_USB_OTG2_CTRL_PWR_POL_MASK 0x200u |
| #define USBNC_USB_OTG2_CTRL_PWR_POL_SHIFT 9 |
| #define USBNC_USB_OTG2_CTRL_WIE_MASK 0x400u |
| #define USBNC_USB_OTG2_CTRL_WIE_SHIFT 10 |
| #define USBNC_USB_OTG2_CTRL_WKUP_SW_EN_MASK 0x4000u |
| #define USBNC_USB_OTG2_CTRL_WKUP_SW_EN_SHIFT 14 |
| #define USBNC_USB_OTG2_CTRL_WKUP_SW_MASK 0x8000u |
| #define USBNC_USB_OTG2_CTRL_WKUP_SW_SHIFT 15 |
| #define USBNC_USB_OTG2_CTRL_WKUP_ID_EN_MASK 0x10000u |
| #define USBNC_USB_OTG2_CTRL_WKUP_ID_EN_SHIFT 16 |
| #define USBNC_USB_OTG2_CTRL_WKUP_VBUS_EN_MASK 0x20000u |
| #define USBNC_USB_OTG2_CTRL_WKUP_VBUS_EN_SHIFT 17 |
| #define USBNC_USB_OTG2_CTRL_WIR_MASK 0x80000000u |
| #define USBNC_USB_OTG2_CTRL_WIR_SHIFT 31 |
| /* USB_UH_CTRL Bit Fields */ |
| #define USBNC_USB_UH_CTRL_WIE_MASK 0x400u |
| #define USBNC_USB_UH_CTRL_WIE_SHIFT 10 |
| #define USBNC_USB_UH_CTRL_RESET_MASK 0x800u |
| #define USBNC_USB_UH_CTRL_RESET_SHIFT 11 |
| #define USBNC_USB_UH_CTRL_SUSPENDM_MASK 0x1000u |
| #define USBNC_USB_UH_CTRL_SUSPENDM_SHIFT 12 |
| #define USBNC_USB_UH_CTRL_480M_CLK_ON_MASK 0x2000u |
| #define USBNC_USB_UH_CTRL_480M_CLK_ON_SHIFT 13 |
| #define USBNC_USB_UH_CTRL_WKUP_SW_EN_MASK 0x4000u |
| #define USBNC_USB_UH_CTRL_WKUP_SW_EN_SHIFT 14 |
| #define USBNC_USB_UH_CTRL_WKUP_SW_MASK 0x8000u |
| #define USBNC_USB_UH_CTRL_WKUP_SW_SHIFT 15 |
| #define USBNC_USB_UH_CTRL_WIR_MASK 0x80000000u |
| #define USBNC_USB_UH_CTRL_WIR_SHIFT 31 |
| /* USB_UH_HSIC_CTRL Bit Fields */ |
| #define USBNC_USB_UH_HSIC_CTRL_HSIC_CLK_ON_MASK 0x800u |
| #define USBNC_USB_UH_HSIC_CTRL_HSIC_CLK_ON_SHIFT 11 |
| #define USBNC_USB_UH_HSIC_CTRL_HSIC_EN_MASK 0x1000u |
| #define USBNC_USB_UH_HSIC_CTRL_HSIC_EN_SHIFT 12 |
| #define USBNC_USB_UH_HSIC_CTRL_CLK_VLD_MASK 0x80000000u |
| #define USBNC_USB_UH_HSIC_CTRL_CLK_VLD_SHIFT 31 |
| /* USB_OTG1_PHY_CTRL_0 Bit Fields */ |
| #define USBNC_USB_OTG1_PHY_CTRL_0_UTMI_CLK_VLD_MASK 0x80000000u |
| #define USBNC_USB_OTG1_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT 31 |
| /* USB_OTG2_PHY_CTRL_0 Bit Fields */ |
| #define USBNC_USB_OTG2_PHY_CTRL_0_UTMI_CLK_VLD_MASK 0x80000000u |
| #define USBNC_USB_OTG2_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT 31 |
| |
| /*! |
| * @} |
| */ /* end of group USBNC_Register_Masks */ |
| |
| /* USBNC - Peripheral instance base addresses */ |
| /** Peripheral USBNC base address */ |
| #define USBNC_BASE (0x42184000u) |
| /** Peripheral USBNC base pointer */ |
| #define USBNC ((USBNC_Type *)USBNC_BASE) |
| #define USBNC_BASE_PTR (USBNC) |
| /** Array initializer of USBNC peripheral base addresses */ |
| #define USBNC_BASE_ADDRS { USBNC_BASE } |
| /** Array initializer of USBNC peripheral base pointers */ |
| #define USBNC_BASE_PTRS { USBNC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBNC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBNC - Register instance definitions */ |
| /* USBNC */ |
| #define USBNC_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC_BASE_PTR) |
| #define USBNC_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_OTG1_CTRL USBNC_USB_OTG1_CTRL_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_OTG2_CTRL USBNC_USB_OTG2_CTRL_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_UH_CTRL USBNC_USB_UH_CTRL_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_UH_HSIC_CTRL USBNC_USB_UH_HSIC_CTRL_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_OTG1_PHY_CTRL_0 USBNC_USB_OTG1_PHY_CTRL_0_REG(USBNC_BASE_PTR) |
| #define USBNC_USB_OTG2_PHY_CTRL_0 USBNC_USB_OTG2_PHY_CTRL_0_REG(USBNC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group USBNC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group USBNC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBPHY Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** USBPHY - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ |
| __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ |
| __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ |
| __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ |
| __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ |
| __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ |
| __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ |
| __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ |
| __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ |
| __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ |
| __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ |
| __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ |
| __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ |
| __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ |
| __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ |
| __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ |
| __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ |
| uint8_t RESERVED_0[12]; |
| __IO uint32_t DEBUG; /**< USB PHY Debug Register, offset: 0x50 */ |
| __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ |
| __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ |
| __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ |
| __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ |
| uint8_t RESERVED_1[12]; |
| __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ |
| __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ |
| __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ |
| __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ |
| __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ |
| } USBPHY_Type, *USBPHY_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBPHY - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBPHY - Register accessors */ |
| #define USBPHY_PWD_REG(base) ((base)->PWD) |
| #define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) |
| #define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) |
| #define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) |
| #define USBPHY_TX_REG(base) ((base)->TX) |
| #define USBPHY_TX_SET_REG(base) ((base)->TX_SET) |
| #define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) |
| #define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) |
| #define USBPHY_RX_REG(base) ((base)->RX) |
| #define USBPHY_RX_SET_REG(base) ((base)->RX_SET) |
| #define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) |
| #define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) |
| #define USBPHY_CTRL_REG(base) ((base)->CTRL) |
| #define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) |
| #define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) |
| #define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) |
| #define USBPHY_STATUS_REG(base) ((base)->STATUS) |
| #define USBPHY_DEBUG_REG(base) ((base)->DEBUG) |
| #define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) |
| #define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) |
| #define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) |
| #define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) |
| #define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) |
| #define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) |
| #define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) |
| #define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) |
| #define USBPHY_VERSION_REG(base) ((base)->VERSION) |
| |
| /*! |
| * @} |
| */ /* end of group USBPHY_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBPHY Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBPHY_Register_Masks USBPHY Register Masks |
| * @{ |
| */ |
| |
| /* PWD Bit Fields */ |
| #define USBPHY_PWD_RSVD0_MASK 0x3FFu |
| #define USBPHY_PWD_RSVD0_SHIFT 0 |
| #define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD0_SHIFT))&USBPHY_PWD_RSVD0_MASK) |
| #define USBPHY_PWD_TXPWDFS_MASK 0x400u |
| #define USBPHY_PWD_TXPWDFS_SHIFT 10 |
| #define USBPHY_PWD_TXPWDIBIAS_MASK 0x800u |
| #define USBPHY_PWD_TXPWDIBIAS_SHIFT 11 |
| #define USBPHY_PWD_TXPWDV2I_MASK 0x1000u |
| #define USBPHY_PWD_TXPWDV2I_SHIFT 12 |
| #define USBPHY_PWD_RSVD1_MASK 0x1E000u |
| #define USBPHY_PWD_RSVD1_SHIFT 13 |
| #define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD1_SHIFT))&USBPHY_PWD_RSVD1_MASK) |
| #define USBPHY_PWD_RXPWDENV_MASK 0x20000u |
| #define USBPHY_PWD_RXPWDENV_SHIFT 17 |
| #define USBPHY_PWD_RXPWD1PT1_MASK 0x40000u |
| #define USBPHY_PWD_RXPWD1PT1_SHIFT 18 |
| #define USBPHY_PWD_RXPWDDIFF_MASK 0x80000u |
| #define USBPHY_PWD_RXPWDDIFF_SHIFT 19 |
| #define USBPHY_PWD_RXPWDRX_MASK 0x100000u |
| #define USBPHY_PWD_RXPWDRX_SHIFT 20 |
| #define USBPHY_PWD_RSVD2_MASK 0xFFE00000u |
| #define USBPHY_PWD_RSVD2_SHIFT 21 |
| #define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD2_SHIFT))&USBPHY_PWD_RSVD2_MASK) |
| /* PWD_SET Bit Fields */ |
| #define USBPHY_PWD_SET_RSVD0_MASK 0x3FFu |
| #define USBPHY_PWD_SET_RSVD0_SHIFT 0 |
| #define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD0_SHIFT))&USBPHY_PWD_SET_RSVD0_MASK) |
| #define USBPHY_PWD_SET_TXPWDFS_MASK 0x400u |
| #define USBPHY_PWD_SET_TXPWDFS_SHIFT 10 |
| #define USBPHY_PWD_SET_TXPWDIBIAS_MASK 0x800u |
| #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT 11 |
| #define USBPHY_PWD_SET_TXPWDV2I_MASK 0x1000u |
| #define USBPHY_PWD_SET_TXPWDV2I_SHIFT 12 |
| #define USBPHY_PWD_SET_RSVD1_MASK 0x1E000u |
| #define USBPHY_PWD_SET_RSVD1_SHIFT 13 |
| #define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD1_SHIFT))&USBPHY_PWD_SET_RSVD1_MASK) |
| #define USBPHY_PWD_SET_RXPWDENV_MASK 0x20000u |
| #define USBPHY_PWD_SET_RXPWDENV_SHIFT 17 |
| #define USBPHY_PWD_SET_RXPWD1PT1_MASK 0x40000u |
| #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT 18 |
| #define USBPHY_PWD_SET_RXPWDDIFF_MASK 0x80000u |
| #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT 19 |
| #define USBPHY_PWD_SET_RXPWDRX_MASK 0x100000u |
| #define USBPHY_PWD_SET_RXPWDRX_SHIFT 20 |
| #define USBPHY_PWD_SET_RSVD2_MASK 0xFFE00000u |
| #define USBPHY_PWD_SET_RSVD2_SHIFT 21 |
| #define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD2_SHIFT))&USBPHY_PWD_SET_RSVD2_MASK) |
| /* PWD_CLR Bit Fields */ |
| #define USBPHY_PWD_CLR_RSVD0_MASK 0x3FFu |
| #define USBPHY_PWD_CLR_RSVD0_SHIFT 0 |
| #define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD0_SHIFT))&USBPHY_PWD_CLR_RSVD0_MASK) |
| #define USBPHY_PWD_CLR_TXPWDFS_MASK 0x400u |
| #define USBPHY_PWD_CLR_TXPWDFS_SHIFT 10 |
| #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK 0x800u |
| #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT 11 |
| #define USBPHY_PWD_CLR_TXPWDV2I_MASK 0x1000u |
| #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT 12 |
| #define USBPHY_PWD_CLR_RSVD1_MASK 0x1E000u |
| #define USBPHY_PWD_CLR_RSVD1_SHIFT 13 |
| #define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD1_SHIFT))&USBPHY_PWD_CLR_RSVD1_MASK) |
| #define USBPHY_PWD_CLR_RXPWDENV_MASK 0x20000u |
| #define USBPHY_PWD_CLR_RXPWDENV_SHIFT 17 |
| #define USBPHY_PWD_CLR_RXPWD1PT1_MASK 0x40000u |
| #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT 18 |
| #define USBPHY_PWD_CLR_RXPWDDIFF_MASK 0x80000u |
| #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT 19 |
| #define USBPHY_PWD_CLR_RXPWDRX_MASK 0x100000u |
| #define USBPHY_PWD_CLR_RXPWDRX_SHIFT 20 |
| #define USBPHY_PWD_CLR_RSVD2_MASK 0xFFE00000u |
| #define USBPHY_PWD_CLR_RSVD2_SHIFT 21 |
| #define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD2_SHIFT))&USBPHY_PWD_CLR_RSVD2_MASK) |
| /* PWD_TOG Bit Fields */ |
| #define USBPHY_PWD_TOG_RSVD0_MASK 0x3FFu |
| #define USBPHY_PWD_TOG_RSVD0_SHIFT 0 |
| #define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD0_SHIFT))&USBPHY_PWD_TOG_RSVD0_MASK) |
| #define USBPHY_PWD_TOG_TXPWDFS_MASK 0x400u |
| #define USBPHY_PWD_TOG_TXPWDFS_SHIFT 10 |
| #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK 0x800u |
| #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT 11 |
| #define USBPHY_PWD_TOG_TXPWDV2I_MASK 0x1000u |
| #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT 12 |
| #define USBPHY_PWD_TOG_RSVD1_MASK 0x1E000u |
| #define USBPHY_PWD_TOG_RSVD1_SHIFT 13 |
| #define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD1_SHIFT))&USBPHY_PWD_TOG_RSVD1_MASK) |
| #define USBPHY_PWD_TOG_RXPWDENV_MASK 0x20000u |
| #define USBPHY_PWD_TOG_RXPWDENV_SHIFT 17 |
| #define USBPHY_PWD_TOG_RXPWD1PT1_MASK 0x40000u |
| #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT 18 |
| #define USBPHY_PWD_TOG_RXPWDDIFF_MASK 0x80000u |
| #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT 19 |
| #define USBPHY_PWD_TOG_RXPWDRX_MASK 0x100000u |
| #define USBPHY_PWD_TOG_RXPWDRX_SHIFT 20 |
| #define USBPHY_PWD_TOG_RSVD2_MASK 0xFFE00000u |
| #define USBPHY_PWD_TOG_RSVD2_SHIFT 21 |
| #define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD2_SHIFT))&USBPHY_PWD_TOG_RSVD2_MASK) |
| /* TX Bit Fields */ |
| #define USBPHY_TX_D_CAL_MASK 0xFu |
| #define USBPHY_TX_D_CAL_SHIFT 0 |
| #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_D_CAL_SHIFT))&USBPHY_TX_D_CAL_MASK) |
| #define USBPHY_TX_RSVD0_MASK 0xF0u |
| #define USBPHY_TX_RSVD0_SHIFT 4 |
| #define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD0_SHIFT))&USBPHY_TX_RSVD0_MASK) |
| #define USBPHY_TX_TXCAL45DN_MASK 0xF00u |
| #define USBPHY_TX_TXCAL45DN_SHIFT 8 |
| #define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DN_SHIFT))&USBPHY_TX_TXCAL45DN_MASK) |
| #define USBPHY_TX_RSVD1_MASK 0xF000u |
| #define USBPHY_TX_RSVD1_SHIFT 12 |
| #define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD1_SHIFT))&USBPHY_TX_RSVD1_MASK) |
| #define USBPHY_TX_TXCAL45DP_MASK 0xF0000u |
| #define USBPHY_TX_TXCAL45DP_SHIFT 16 |
| #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DP_SHIFT))&USBPHY_TX_TXCAL45DP_MASK) |
| #define USBPHY_TX_RSVD2_MASK 0x3F00000u |
| #define USBPHY_TX_RSVD2_SHIFT 20 |
| #define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD2_SHIFT))&USBPHY_TX_RSVD2_MASK) |
| #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK 0x1C000000u |
| #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT 26 |
| #define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) |
| #define USBPHY_TX_RSVD5_MASK 0xE0000000u |
| #define USBPHY_TX_RSVD5_SHIFT 29 |
| #define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD5_SHIFT))&USBPHY_TX_RSVD5_MASK) |
| /* TX_SET Bit Fields */ |
| #define USBPHY_TX_SET_D_CAL_MASK 0xFu |
| #define USBPHY_TX_SET_D_CAL_SHIFT 0 |
| #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_D_CAL_SHIFT))&USBPHY_TX_SET_D_CAL_MASK) |
| #define USBPHY_TX_SET_RSVD0_MASK 0xF0u |
| #define USBPHY_TX_SET_RSVD0_SHIFT 4 |
| #define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD0_SHIFT))&USBPHY_TX_SET_RSVD0_MASK) |
| #define USBPHY_TX_SET_TXCAL45DN_MASK 0xF00u |
| #define USBPHY_TX_SET_TXCAL45DN_SHIFT 8 |
| #define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DN_SHIFT))&USBPHY_TX_SET_TXCAL45DN_MASK) |
| #define USBPHY_TX_SET_RSVD1_MASK 0xF000u |
| #define USBPHY_TX_SET_RSVD1_SHIFT 12 |
| #define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD1_SHIFT))&USBPHY_TX_SET_RSVD1_MASK) |
| #define USBPHY_TX_SET_TXCAL45DP_MASK 0xF0000u |
| #define USBPHY_TX_SET_TXCAL45DP_SHIFT 16 |
| #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DP_SHIFT))&USBPHY_TX_SET_TXCAL45DP_MASK) |
| #define USBPHY_TX_SET_RSVD2_MASK 0x3F00000u |
| #define USBPHY_TX_SET_RSVD2_SHIFT 20 |
| #define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD2_SHIFT))&USBPHY_TX_SET_RSVD2_MASK) |
| #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK 0x1C000000u |
| #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT 26 |
| #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) |
| #define USBPHY_TX_SET_RSVD5_MASK 0xE0000000u |
| #define USBPHY_TX_SET_RSVD5_SHIFT 29 |
| #define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD5_SHIFT))&USBPHY_TX_SET_RSVD5_MASK) |
| /* TX_CLR Bit Fields */ |
| #define USBPHY_TX_CLR_D_CAL_MASK 0xFu |
| #define USBPHY_TX_CLR_D_CAL_SHIFT 0 |
| #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_D_CAL_SHIFT))&USBPHY_TX_CLR_D_CAL_MASK) |
| #define USBPHY_TX_CLR_RSVD0_MASK 0xF0u |
| #define USBPHY_TX_CLR_RSVD0_SHIFT 4 |
| #define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD0_SHIFT))&USBPHY_TX_CLR_RSVD0_MASK) |
| #define USBPHY_TX_CLR_TXCAL45DN_MASK 0xF00u |
| #define USBPHY_TX_CLR_TXCAL45DN_SHIFT 8 |
| #define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DN_SHIFT))&USBPHY_TX_CLR_TXCAL45DN_MASK) |
| #define USBPHY_TX_CLR_RSVD1_MASK 0xF000u |
| #define USBPHY_TX_CLR_RSVD1_SHIFT 12 |
| #define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD1_SHIFT))&USBPHY_TX_CLR_RSVD1_MASK) |
| #define USBPHY_TX_CLR_TXCAL45DP_MASK 0xF0000u |
| #define USBPHY_TX_CLR_TXCAL45DP_SHIFT 16 |
| #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DP_SHIFT))&USBPHY_TX_CLR_TXCAL45DP_MASK) |
| #define USBPHY_TX_CLR_RSVD2_MASK 0x3F00000u |
| #define USBPHY_TX_CLR_RSVD2_SHIFT 20 |
| #define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD2_SHIFT))&USBPHY_TX_CLR_RSVD2_MASK) |
| #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK 0x1C000000u |
| #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT 26 |
| #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) |
| #define USBPHY_TX_CLR_RSVD5_MASK 0xE0000000u |
| #define USBPHY_TX_CLR_RSVD5_SHIFT 29 |
| #define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD5_SHIFT))&USBPHY_TX_CLR_RSVD5_MASK) |
| /* TX_TOG Bit Fields */ |
| #define USBPHY_TX_TOG_D_CAL_MASK 0xFu |
| #define USBPHY_TX_TOG_D_CAL_SHIFT 0 |
| #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_D_CAL_SHIFT))&USBPHY_TX_TOG_D_CAL_MASK) |
| #define USBPHY_TX_TOG_RSVD0_MASK 0xF0u |
| #define USBPHY_TX_TOG_RSVD0_SHIFT 4 |
| #define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD0_SHIFT))&USBPHY_TX_TOG_RSVD0_MASK) |
| #define USBPHY_TX_TOG_TXCAL45DN_MASK 0xF00u |
| #define USBPHY_TX_TOG_TXCAL45DN_SHIFT 8 |
| #define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DN_SHIFT))&USBPHY_TX_TOG_TXCAL45DN_MASK) |
| #define USBPHY_TX_TOG_RSVD1_MASK 0xF000u |
| #define USBPHY_TX_TOG_RSVD1_SHIFT 12 |
| #define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD1_SHIFT))&USBPHY_TX_TOG_RSVD1_MASK) |
| #define USBPHY_TX_TOG_TXCAL45DP_MASK 0xF0000u |
| #define USBPHY_TX_TOG_TXCAL45DP_SHIFT 16 |
| #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DP_SHIFT))&USBPHY_TX_TOG_TXCAL45DP_MASK) |
| #define USBPHY_TX_TOG_RSVD2_MASK 0x3F00000u |
| #define USBPHY_TX_TOG_RSVD2_SHIFT 20 |
| #define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD2_SHIFT))&USBPHY_TX_TOG_RSVD2_MASK) |
| #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK 0x1C000000u |
| #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT 26 |
| #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) |
| #define USBPHY_TX_TOG_RSVD5_MASK 0xE0000000u |
| #define USBPHY_TX_TOG_RSVD5_SHIFT 29 |
| #define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD5_SHIFT))&USBPHY_TX_TOG_RSVD5_MASK) |
| /* RX Bit Fields */ |
| #define USBPHY_RX_ENVADJ_MASK 0x7u |
| #define USBPHY_RX_ENVADJ_SHIFT 0 |
| #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_ENVADJ_SHIFT))&USBPHY_RX_ENVADJ_MASK) |
| #define USBPHY_RX_RSVD0_MASK 0x8u |
| #define USBPHY_RX_RSVD0_SHIFT 3 |
| #define USBPHY_RX_DISCONADJ_MASK 0x70u |
| #define USBPHY_RX_DISCONADJ_SHIFT 4 |
| #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_DISCONADJ_SHIFT))&USBPHY_RX_DISCONADJ_MASK) |
| #define USBPHY_RX_RSVD1_MASK 0x3FFF80u |
| #define USBPHY_RX_RSVD1_SHIFT 7 |
| #define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD1_SHIFT))&USBPHY_RX_RSVD1_MASK) |
| #define USBPHY_RX_RXDBYPASS_MASK 0x400000u |
| #define USBPHY_RX_RXDBYPASS_SHIFT 22 |
| #define USBPHY_RX_RSVD2_MASK 0xFF800000u |
| #define USBPHY_RX_RSVD2_SHIFT 23 |
| #define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD2_SHIFT))&USBPHY_RX_RSVD2_MASK) |
| /* RX_SET Bit Fields */ |
| #define USBPHY_RX_SET_ENVADJ_MASK 0x7u |
| #define USBPHY_RX_SET_ENVADJ_SHIFT 0 |
| #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_ENVADJ_SHIFT))&USBPHY_RX_SET_ENVADJ_MASK) |
| #define USBPHY_RX_SET_RSVD0_MASK 0x8u |
| #define USBPHY_RX_SET_RSVD0_SHIFT 3 |
| #define USBPHY_RX_SET_DISCONADJ_MASK 0x70u |
| #define USBPHY_RX_SET_DISCONADJ_SHIFT 4 |
| #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_DISCONADJ_SHIFT))&USBPHY_RX_SET_DISCONADJ_MASK) |
| #define USBPHY_RX_SET_RSVD1_MASK 0x3FFF80u |
| #define USBPHY_RX_SET_RSVD1_SHIFT 7 |
| #define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD1_SHIFT))&USBPHY_RX_SET_RSVD1_MASK) |
| #define USBPHY_RX_SET_RXDBYPASS_MASK 0x400000u |
| #define USBPHY_RX_SET_RXDBYPASS_SHIFT 22 |
| #define USBPHY_RX_SET_RSVD2_MASK 0xFF800000u |
| #define USBPHY_RX_SET_RSVD2_SHIFT 23 |
| #define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD2_SHIFT))&USBPHY_RX_SET_RSVD2_MASK) |
| /* RX_CLR Bit Fields */ |
| #define USBPHY_RX_CLR_ENVADJ_MASK 0x7u |
| #define USBPHY_RX_CLR_ENVADJ_SHIFT 0 |
| #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_ENVADJ_SHIFT))&USBPHY_RX_CLR_ENVADJ_MASK) |
| #define USBPHY_RX_CLR_RSVD0_MASK 0x8u |
| #define USBPHY_RX_CLR_RSVD0_SHIFT 3 |
| #define USBPHY_RX_CLR_DISCONADJ_MASK 0x70u |
| #define USBPHY_RX_CLR_DISCONADJ_SHIFT 4 |
| #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_DISCONADJ_SHIFT))&USBPHY_RX_CLR_DISCONADJ_MASK) |
| #define USBPHY_RX_CLR_RSVD1_MASK 0x3FFF80u |
| #define USBPHY_RX_CLR_RSVD1_SHIFT 7 |
| #define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD1_SHIFT))&USBPHY_RX_CLR_RSVD1_MASK) |
| #define USBPHY_RX_CLR_RXDBYPASS_MASK 0x400000u |
| #define USBPHY_RX_CLR_RXDBYPASS_SHIFT 22 |
| #define USBPHY_RX_CLR_RSVD2_MASK 0xFF800000u |
| #define USBPHY_RX_CLR_RSVD2_SHIFT 23 |
| #define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD2_SHIFT))&USBPHY_RX_CLR_RSVD2_MASK) |
| /* RX_TOG Bit Fields */ |
| #define USBPHY_RX_TOG_ENVADJ_MASK 0x7u |
| #define USBPHY_RX_TOG_ENVADJ_SHIFT 0 |
| #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_ENVADJ_SHIFT))&USBPHY_RX_TOG_ENVADJ_MASK) |
| #define USBPHY_RX_TOG_RSVD0_MASK 0x8u |
| #define USBPHY_RX_TOG_RSVD0_SHIFT 3 |
| #define USBPHY_RX_TOG_DISCONADJ_MASK 0x70u |
| #define USBPHY_RX_TOG_DISCONADJ_SHIFT 4 |
| #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_DISCONADJ_SHIFT))&USBPHY_RX_TOG_DISCONADJ_MASK) |
| #define USBPHY_RX_TOG_RSVD1_MASK 0x3FFF80u |
| #define USBPHY_RX_TOG_RSVD1_SHIFT 7 |
| #define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD1_SHIFT))&USBPHY_RX_TOG_RSVD1_MASK) |
| #define USBPHY_RX_TOG_RXDBYPASS_MASK 0x400000u |
| #define USBPHY_RX_TOG_RXDBYPASS_SHIFT 22 |
| #define USBPHY_RX_TOG_RSVD2_MASK 0xFF800000u |
| #define USBPHY_RX_TOG_RSVD2_SHIFT 23 |
| #define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD2_SHIFT))&USBPHY_RX_TOG_RSVD2_MASK) |
| /* CTRL Bit Fields */ |
| #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK 0x1u |
| #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT 0 |
| #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK 0x2u |
| #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT 1 |
| #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK 0x4u |
| #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT 2 |
| #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK 0x8u |
| #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT 3 |
| #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK 0x10u |
| #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT 4 |
| #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK 0x20u |
| #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT 5 |
| #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK 0x40u |
| #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT 6 |
| #define USBPHY_CTRL_ENOTGIDDETECT_MASK 0x80u |
| #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT 7 |
| #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK 0x100u |
| #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT 8 |
| #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK 0x200u |
| #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT 9 |
| #define USBPHY_CTRL_RESUME_IRQ_MASK 0x400u |
| #define USBPHY_CTRL_RESUME_IRQ_SHIFT 10 |
| #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK 0x800u |
| #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT 11 |
| #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK 0x1000u |
| #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT 12 |
| #define USBPHY_CTRL_DATA_ON_LRADC_MASK 0x2000u |
| #define USBPHY_CTRL_DATA_ON_LRADC_SHIFT 13 |
| #define USBPHY_CTRL_ENUTMILEVEL2_MASK 0x4000u |
| #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT 14 |
| #define USBPHY_CTRL_ENUTMILEVEL3_MASK 0x8000u |
| #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT 15 |
| #define USBPHY_CTRL_ENIRQWAKEUP_MASK 0x10000u |
| #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT 16 |
| #define USBPHY_CTRL_WAKEUP_IRQ_MASK 0x20000u |
| #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT 17 |
| #define USBPHY_CTRL_RSVD0_MASK 0x40000u |
| #define USBPHY_CTRL_RSVD0_SHIFT 18 |
| #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK 0x80000u |
| #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT 19 |
| #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK 0x100000u |
| #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT 20 |
| #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK 0x200000u |
| #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT 21 |
| #define USBPHY_CTRL_ENIDCHG_WKUP_MASK 0x400000u |
| #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT 22 |
| #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK 0x800000u |
| #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT 23 |
| #define USBPHY_CTRL_FSDLL_RST_EN_MASK 0x1000000u |
| #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT 24 |
| #define USBPHY_CTRL_RSVD1_MASK 0x6000000u |
| #define USBPHY_CTRL_RSVD1_SHIFT 25 |
| #define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_RSVD1_SHIFT))&USBPHY_CTRL_RSVD1_MASK) |
| #define USBPHY_CTRL_OTG_ID_VALUE_MASK 0x8000000u |
| #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT 27 |
| #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK 0x10000000u |
| #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT 28 |
| #define USBPHY_CTRL_UTMI_SUSPENDM_MASK 0x20000000u |
| #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT 29 |
| #define USBPHY_CTRL_CLKGATE_MASK 0x40000000u |
| #define USBPHY_CTRL_CLKGATE_SHIFT 30 |
| #define USBPHY_CTRL_SFTRST_MASK 0x80000000u |
| #define USBPHY_CTRL_SFTRST_SHIFT 31 |
| /* CTRL_SET Bit Fields */ |
| #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK 0x1u |
| #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT 0 |
| #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK 0x2u |
| #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT 1 |
| #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK 0x4u |
| #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT 2 |
| #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK 0x8u |
| #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT 3 |
| #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK 0x10u |
| #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT 4 |
| #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK 0x20u |
| #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT 5 |
| #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK 0x40u |
| #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT 6 |
| #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK 0x80u |
| #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT 7 |
| #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK 0x100u |
| #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT 8 |
| #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK 0x200u |
| #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT 9 |
| #define USBPHY_CTRL_SET_RESUME_IRQ_MASK 0x400u |
| #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT 10 |
| #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK 0x800u |
| #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT 11 |
| #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK 0x1000u |
| #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT 12 |
| #define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK 0x2000u |
| #define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT 13 |
| #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK 0x4000u |
| #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT 14 |
| #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK 0x8000u |
| #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT 15 |
| #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK 0x10000u |
| #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT 16 |
| #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK 0x20000u |
| #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT 17 |
| #define USBPHY_CTRL_SET_RSVD0_MASK 0x40000u |
| #define USBPHY_CTRL_SET_RSVD0_SHIFT 18 |
| #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK 0x80000u |
| #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT 19 |
| #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK 0x100000u |
| #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT 20 |
| #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK 0x200000u |
| #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT 21 |
| #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK 0x400000u |
| #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT 22 |
| #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK 0x800000u |
| #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT 23 |
| #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK 0x1000000u |
| #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT 24 |
| #define USBPHY_CTRL_SET_RSVD1_MASK 0x6000000u |
| #define USBPHY_CTRL_SET_RSVD1_SHIFT 25 |
| #define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_SET_RSVD1_SHIFT))&USBPHY_CTRL_SET_RSVD1_MASK) |
| #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK 0x8000000u |
| #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT 27 |
| #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK 0x10000000u |
| #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT 28 |
| #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK 0x20000000u |
| #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT 29 |
| #define USBPHY_CTRL_SET_CLKGATE_MASK 0x40000000u |
| #define USBPHY_CTRL_SET_CLKGATE_SHIFT 30 |
| #define USBPHY_CTRL_SET_SFTRST_MASK 0x80000000u |
| #define USBPHY_CTRL_SET_SFTRST_SHIFT 31 |
| /* CTRL_CLR Bit Fields */ |
| #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK 0x1u |
| #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT 0 |
| #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK 0x2u |
| #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT 1 |
| #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK 0x4u |
| #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT 2 |
| #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK 0x8u |
| #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT 3 |
| #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK 0x10u |
| #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT 4 |
| #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK 0x20u |
| #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT 5 |
| #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK 0x40u |
| #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT 6 |
| #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK 0x80u |
| #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT 7 |
| #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK 0x100u |
| #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT 8 |
| #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK 0x200u |
| #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT 9 |
| #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK 0x400u |
| #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT 10 |
| #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK 0x800u |
| #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT 11 |
| #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK 0x1000u |
| #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT 12 |
| #define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK 0x2000u |
| #define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT 13 |
| #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK 0x4000u |
| #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT 14 |
| #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK 0x8000u |
| #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT 15 |
| #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK 0x10000u |
| #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT 16 |
| #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK 0x20000u |
| #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT 17 |
| #define USBPHY_CTRL_CLR_RSVD0_MASK 0x40000u |
| #define USBPHY_CTRL_CLR_RSVD0_SHIFT 18 |
| #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK 0x80000u |
| #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT 19 |
| #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK 0x100000u |
| #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT 20 |
| #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK 0x200000u |
| #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT 21 |
| #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK 0x400000u |
| #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT 22 |
| #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK 0x800000u |
| #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT 23 |
| #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK 0x1000000u |
| #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT 24 |
| #define USBPHY_CTRL_CLR_RSVD1_MASK 0x6000000u |
| #define USBPHY_CTRL_CLR_RSVD1_SHIFT 25 |
| #define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_CLR_RSVD1_SHIFT))&USBPHY_CTRL_CLR_RSVD1_MASK) |
| #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK 0x8000000u |
| #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT 27 |
| #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK 0x10000000u |
| #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT 28 |
| #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK 0x20000000u |
| #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT 29 |
| #define USBPHY_CTRL_CLR_CLKGATE_MASK 0x40000000u |
| #define USBPHY_CTRL_CLR_CLKGATE_SHIFT 30 |
| #define USBPHY_CTRL_CLR_SFTRST_MASK 0x80000000u |
| #define USBPHY_CTRL_CLR_SFTRST_SHIFT 31 |
| /* CTRL_TOG Bit Fields */ |
| #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK 0x1u |
| #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT 0 |
| #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK 0x2u |
| #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT 1 |
| #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK 0x4u |
| #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT 2 |
| #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK 0x8u |
| #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT 3 |
| #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK 0x10u |
| #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT 4 |
| #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK 0x20u |
| #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT 5 |
| #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK 0x40u |
| #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT 6 |
| #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK 0x80u |
| #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT 7 |
| #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK 0x100u |
| #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT 8 |
| #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK 0x200u |
| #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT 9 |
| #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK 0x400u |
| #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT 10 |
| #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK 0x800u |
| #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT 11 |
| #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK 0x1000u |
| #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT 12 |
| #define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK 0x2000u |
| #define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT 13 |
| #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK 0x4000u |
| #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT 14 |
| #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK 0x8000u |
| #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT 15 |
| #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK 0x10000u |
| #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT 16 |
| #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK 0x20000u |
| #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT 17 |
| #define USBPHY_CTRL_TOG_RSVD0_MASK 0x40000u |
| #define USBPHY_CTRL_TOG_RSVD0_SHIFT 18 |
| #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK 0x80000u |
| #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT 19 |
| #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK 0x100000u |
| #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT 20 |
| #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK 0x200000u |
| #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT 21 |
| #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK 0x400000u |
| #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT 22 |
| #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK 0x800000u |
| #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT 23 |
| #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK 0x1000000u |
| #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT 24 |
| #define USBPHY_CTRL_TOG_RSVD1_MASK 0x6000000u |
| #define USBPHY_CTRL_TOG_RSVD1_SHIFT 25 |
| #define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_TOG_RSVD1_SHIFT))&USBPHY_CTRL_TOG_RSVD1_MASK) |
| #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK 0x8000000u |
| #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT 27 |
| #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK 0x10000000u |
| #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT 28 |
| #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK 0x20000000u |
| #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT 29 |
| #define USBPHY_CTRL_TOG_CLKGATE_MASK 0x40000000u |
| #define USBPHY_CTRL_TOG_CLKGATE_SHIFT 30 |
| #define USBPHY_CTRL_TOG_SFTRST_MASK 0x80000000u |
| #define USBPHY_CTRL_TOG_SFTRST_SHIFT 31 |
| /* STATUS Bit Fields */ |
| #define USBPHY_STATUS_RSVD0_MASK 0x7u |
| #define USBPHY_STATUS_RSVD0_SHIFT 0 |
| #define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD0_SHIFT))&USBPHY_STATUS_RSVD0_MASK) |
| #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK 0x8u |
| #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT 3 |
| #define USBPHY_STATUS_RSVD1_MASK 0x30u |
| #define USBPHY_STATUS_RSVD1_SHIFT 4 |
| #define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD1_SHIFT))&USBPHY_STATUS_RSVD1_MASK) |
| #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK 0x40u |
| #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT 6 |
| #define USBPHY_STATUS_RSVD2_MASK 0x80u |
| #define USBPHY_STATUS_RSVD2_SHIFT 7 |
| #define USBPHY_STATUS_OTGID_STATUS_MASK 0x100u |
| #define USBPHY_STATUS_OTGID_STATUS_SHIFT 8 |
| #define USBPHY_STATUS_RSVD3_MASK 0x200u |
| #define USBPHY_STATUS_RSVD3_SHIFT 9 |
| #define USBPHY_STATUS_RESUME_STATUS_MASK 0x400u |
| #define USBPHY_STATUS_RESUME_STATUS_SHIFT 10 |
| #define USBPHY_STATUS_RSVD4_MASK 0xFFFFF800u |
| #define USBPHY_STATUS_RSVD4_SHIFT 11 |
| #define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD4_SHIFT))&USBPHY_STATUS_RSVD4_MASK) |
| /* DEBUG Bit Fields */ |
| #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK 0x1u |
| #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT 0 |
| #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK 0x2u |
| #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT 1 |
| #define USBPHY_DEBUG_HSTPULLDOWN_MASK 0xCu |
| #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT 2 |
| #define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_HSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK 0x30u |
| #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT 4 |
| #define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_ENHSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_RSVD0_MASK 0xC0u |
| #define USBPHY_DEBUG_RSVD0_SHIFT 6 |
| #define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK) |
| #define USBPHY_DEBUG_TX2RXCOUNT_MASK 0xF00u |
| #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT 8 |
| #define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TX2RXCOUNT_MASK) |
| #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK 0x1000u |
| #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT 12 |
| #define USBPHY_DEBUG_RSVD1_MASK 0xE000u |
| #define USBPHY_DEBUG_RSVD1_SHIFT 13 |
| #define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD1_SHIFT))&USBPHY_DEBUG_RSVD1_MASK) |
| #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK 0x1F0000u |
| #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT 16 |
| #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) |
| #define USBPHY_DEBUG_RSVD2_MASK 0xE00000u |
| #define USBPHY_DEBUG_RSVD2_SHIFT 21 |
| #define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD2_SHIFT))&USBPHY_DEBUG_RSVD2_MASK) |
| #define USBPHY_DEBUG_ENSQUELCHRESET_MASK 0x1000000u |
| #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT 24 |
| #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK 0x1E000000u |
| #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT 25 |
| #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) |
| #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK 0x20000000u |
| #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT 29 |
| #define USBPHY_DEBUG_CLKGATE_MASK 0x40000000u |
| #define USBPHY_DEBUG_CLKGATE_SHIFT 30 |
| #define USBPHY_DEBUG_RSVD3_MASK 0x80000000u |
| #define USBPHY_DEBUG_RSVD3_SHIFT 31 |
| /* DEBUG_SET Bit Fields */ |
| #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK 0x1u |
| #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT 0 |
| #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK 0x2u |
| #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT 1 |
| #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK 0xCu |
| #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT 2 |
| #define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK 0x30u |
| #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT 4 |
| #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_SET_RSVD0_MASK 0xC0u |
| #define USBPHY_DEBUG_SET_RSVD0_SHIFT 6 |
| #define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD0_SHIFT))&USBPHY_DEBUG_SET_RSVD0_MASK) |
| #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK 0xF00u |
| #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT 8 |
| #define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) |
| #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK 0x1000u |
| #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT 12 |
| #define USBPHY_DEBUG_SET_RSVD1_MASK 0xE000u |
| #define USBPHY_DEBUG_SET_RSVD1_SHIFT 13 |
| #define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD1_SHIFT))&USBPHY_DEBUG_SET_RSVD1_MASK) |
| #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK 0x1F0000u |
| #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT 16 |
| #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) |
| #define USBPHY_DEBUG_SET_RSVD2_MASK 0xE00000u |
| #define USBPHY_DEBUG_SET_RSVD2_SHIFT 21 |
| #define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD2_SHIFT))&USBPHY_DEBUG_SET_RSVD2_MASK) |
| #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK 0x1000000u |
| #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT 24 |
| #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK 0x1E000000u |
| #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT 25 |
| #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) |
| #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK 0x20000000u |
| #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT 29 |
| #define USBPHY_DEBUG_SET_CLKGATE_MASK 0x40000000u |
| #define USBPHY_DEBUG_SET_CLKGATE_SHIFT 30 |
| #define USBPHY_DEBUG_SET_RSVD3_MASK 0x80000000u |
| #define USBPHY_DEBUG_SET_RSVD3_SHIFT 31 |
| /* DEBUG_CLR Bit Fields */ |
| #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK 0x1u |
| #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT 0 |
| #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK 0x2u |
| #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT 1 |
| #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK 0xCu |
| #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT 2 |
| #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK 0x30u |
| #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT 4 |
| #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_CLR_RSVD0_MASK 0xC0u |
| #define USBPHY_DEBUG_CLR_RSVD0_SHIFT 6 |
| #define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD0_SHIFT))&USBPHY_DEBUG_CLR_RSVD0_MASK) |
| #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK 0xF00u |
| #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT 8 |
| #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) |
| #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK 0x1000u |
| #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT 12 |
| #define USBPHY_DEBUG_CLR_RSVD1_MASK 0xE000u |
| #define USBPHY_DEBUG_CLR_RSVD1_SHIFT 13 |
| #define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD1_SHIFT))&USBPHY_DEBUG_CLR_RSVD1_MASK) |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK 0x1F0000u |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT 16 |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) |
| #define USBPHY_DEBUG_CLR_RSVD2_MASK 0xE00000u |
| #define USBPHY_DEBUG_CLR_RSVD2_SHIFT 21 |
| #define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD2_SHIFT))&USBPHY_DEBUG_CLR_RSVD2_MASK) |
| #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK 0x1000000u |
| #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT 24 |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK 0x1E000000u |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT 25 |
| #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) |
| #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK 0x20000000u |
| #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT 29 |
| #define USBPHY_DEBUG_CLR_CLKGATE_MASK 0x40000000u |
| #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT 30 |
| #define USBPHY_DEBUG_CLR_RSVD3_MASK 0x80000000u |
| #define USBPHY_DEBUG_CLR_RSVD3_SHIFT 31 |
| /* DEBUG_TOG Bit Fields */ |
| #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK 0x1u |
| #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT 0 |
| #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK 0x2u |
| #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT 1 |
| #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK 0xCu |
| #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT 2 |
| #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK 0x30u |
| #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT 4 |
| #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) |
| #define USBPHY_DEBUG_TOG_RSVD0_MASK 0xC0u |
| #define USBPHY_DEBUG_TOG_RSVD0_SHIFT 6 |
| #define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD0_SHIFT))&USBPHY_DEBUG_TOG_RSVD0_MASK) |
| #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK 0xF00u |
| #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT 8 |
| #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) |
| #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK 0x1000u |
| #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT 12 |
| #define USBPHY_DEBUG_TOG_RSVD1_MASK 0xE000u |
| #define USBPHY_DEBUG_TOG_RSVD1_SHIFT 13 |
| #define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD1_SHIFT))&USBPHY_DEBUG_TOG_RSVD1_MASK) |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK 0x1F0000u |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT 16 |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) |
| #define USBPHY_DEBUG_TOG_RSVD2_MASK 0xE00000u |
| #define USBPHY_DEBUG_TOG_RSVD2_SHIFT 21 |
| #define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD2_SHIFT))&USBPHY_DEBUG_TOG_RSVD2_MASK) |
| #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK 0x1000000u |
| #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT 24 |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK 0x1E000000u |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT 25 |
| #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) |
| #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK 0x20000000u |
| #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT 29 |
| #define USBPHY_DEBUG_TOG_CLKGATE_MASK 0x40000000u |
| #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT 30 |
| #define USBPHY_DEBUG_TOG_RSVD3_MASK 0x80000000u |
| #define USBPHY_DEBUG_TOG_RSVD3_SHIFT 31 |
| /* DEBUG0_STATUS Bit Fields */ |
| #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK 0xFFFFu |
| #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT 0 |
| #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) |
| #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK 0x3FF0000u |
| #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT 16 |
| #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) |
| #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK 0xFC000000u |
| #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT 26 |
| #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) |
| /* DEBUG1 Bit Fields */ |
| #define USBPHY_DEBUG1_RSVD0_MASK 0x1FFFu |
| #define USBPHY_DEBUG1_RSVD0_SHIFT 0 |
| #define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD0_SHIFT))&USBPHY_DEBUG1_RSVD0_MASK) |
| #define USBPHY_DEBUG1_ENTAILADJVD_MASK 0x6000u |
| #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT 13 |
| #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_ENTAILADJVD_MASK) |
| #define USBPHY_DEBUG1_RSVD1_MASK 0xFFFF8000u |
| #define USBPHY_DEBUG1_RSVD1_SHIFT 15 |
| #define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD1_SHIFT))&USBPHY_DEBUG1_RSVD1_MASK) |
| /* DEBUG1_SET Bit Fields */ |
| #define USBPHY_DEBUG1_SET_RSVD0_MASK 0x1FFFu |
| #define USBPHY_DEBUG1_SET_RSVD0_SHIFT 0 |
| #define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD0_SHIFT))&USBPHY_DEBUG1_SET_RSVD0_MASK) |
| #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK 0x6000u |
| #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT 13 |
| #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) |
| #define USBPHY_DEBUG1_SET_RSVD1_MASK 0xFFFF8000u |
| #define USBPHY_DEBUG1_SET_RSVD1_SHIFT 15 |
| #define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD1_SHIFT))&USBPHY_DEBUG1_SET_RSVD1_MASK) |
| /* DEBUG1_CLR Bit Fields */ |
| #define USBPHY_DEBUG1_CLR_RSVD0_MASK 0x1FFFu |
| #define USBPHY_DEBUG1_CLR_RSVD0_SHIFT 0 |
| #define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD0_SHIFT))&USBPHY_DEBUG1_CLR_RSVD0_MASK) |
| #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK 0x6000u |
| #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT 13 |
| #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) |
| #define USBPHY_DEBUG1_CLR_RSVD1_MASK 0xFFFF8000u |
| #define USBPHY_DEBUG1_CLR_RSVD1_SHIFT 15 |
| #define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD1_SHIFT))&USBPHY_DEBUG1_CLR_RSVD1_MASK) |
| /* DEBUG1_TOG Bit Fields */ |
| #define USBPHY_DEBUG1_TOG_RSVD0_MASK 0x1FFFu |
| #define USBPHY_DEBUG1_TOG_RSVD0_SHIFT 0 |
| #define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD0_SHIFT))&USBPHY_DEBUG1_TOG_RSVD0_MASK) |
| #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK 0x6000u |
| #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT 13 |
| #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) |
| #define USBPHY_DEBUG1_TOG_RSVD1_MASK 0xFFFF8000u |
| #define USBPHY_DEBUG1_TOG_RSVD1_SHIFT 15 |
| #define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD1_SHIFT))&USBPHY_DEBUG1_TOG_RSVD1_MASK) |
| /* VERSION Bit Fields */ |
| #define USBPHY_VERSION_STEP_MASK 0xFFFFu |
| #define USBPHY_VERSION_STEP_SHIFT 0 |
| #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_STEP_SHIFT))&USBPHY_VERSION_STEP_MASK) |
| #define USBPHY_VERSION_MINOR_MASK 0xFF0000u |
| #define USBPHY_VERSION_MINOR_SHIFT 16 |
| #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MINOR_SHIFT))&USBPHY_VERSION_MINOR_MASK) |
| #define USBPHY_VERSION_MAJOR_MASK 0xFF000000u |
| #define USBPHY_VERSION_MAJOR_SHIFT 24 |
| #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MAJOR_SHIFT))&USBPHY_VERSION_MAJOR_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group USBPHY_Register_Masks */ |
| |
| /* USBPHY - Peripheral instance base addresses */ |
| /** Peripheral USBPHY1 base address */ |
| #define USBPHY1_BASE (0x420C9000u) |
| /** Peripheral USBPHY1 base pointer */ |
| #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) |
| #define USBPHY1_BASE_PTR (USBPHY1) |
| /** Peripheral USBPHY2 base address */ |
| #define USBPHY2_BASE (0x420CA000u) |
| /** Peripheral USBPHY2 base pointer */ |
| #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) |
| #define USBPHY2_BASE_PTR (USBPHY2) |
| /** Array initializer of USBPHY peripheral base addresses */ |
| #define USBPHY_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE } |
| /** Array initializer of USBPHY peripheral base pointers */ |
| #define USBPHY_BASE_PTRS { USBPHY1, USBPHY2 } |
| |
| /* ---------------------------------------------------------------------------- |
| -- USBPHY - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros |
| * @{ |
| */ |
| |
| /* USBPHY - Register instance definitions */ |
| /* USBPHY1 */ |
| #define USBPHY1_PWD USBPHY_PWD_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_PWD_SET USBPHY_PWD_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_TX USBPHY_TX_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_TX_SET USBPHY_TX_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_TX_CLR USBPHY_TX_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_TX_TOG USBPHY_TX_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_RX USBPHY_RX_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_RX_SET USBPHY_RX_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_RX_CLR USBPHY_RX_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_RX_TOG USBPHY_RX_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_CTRL USBPHY_CTRL_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_STATUS USBPHY_STATUS_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG USBPHY_DEBUG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG1 USBPHY_DEBUG1_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY1_BASE_PTR) |
| #define USBPHY1_VERSION USBPHY_VERSION_REG(USBPHY1_BASE_PTR) |
| /* USBPHY2 */ |
| #define USBPHY2_PWD USBPHY_PWD_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_PWD_SET USBPHY_PWD_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_TX USBPHY_TX_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_TX_SET USBPHY_TX_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_TX_CLR USBPHY_TX_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_TX_TOG USBPHY_TX_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_RX USBPHY_RX_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_RX_SET USBPHY_RX_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_RX_CLR USBPHY_RX_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_RX_TOG USBPHY_RX_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_CTRL USBPHY_CTRL_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_STATUS USBPHY_STATUS_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG USBPHY_DEBUG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG1 USBPHY_DEBUG1_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY2_BASE_PTR) |
| #define USBPHY2_VERSION USBPHY_VERSION_REG(USBPHY2_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group USBPHY_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group USBPHY_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USB_ANALOG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** USB_ANALOG - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[416]; |
| __IO uint32_t USB1_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x1A0 */ |
| __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x1A4 */ |
| __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x1A8 */ |
| __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x1AC */ |
| __IO uint32_t USB1_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x1B0 */ |
| __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x1B4 */ |
| __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x1B8 */ |
| __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x1BC */ |
| __I uint32_t USB1_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x1C0 */ |
| uint8_t RESERVED_1[12]; |
| __I uint32_t USB1_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x1D0 */ |
| uint8_t RESERVED_2[28]; |
| __IO uint32_t USB1_MISC; /**< USB Misc Register, offset: 0x1F0 */ |
| __IO uint32_t USB1_MISC_SET; /**< USB Misc Register, offset: 0x1F4 */ |
| __IO uint32_t USB1_MISC_CLR; /**< USB Misc Register, offset: 0x1F8 */ |
| __IO uint32_t USB1_MISC_TOG; /**< USB Misc Register, offset: 0x1FC */ |
| __IO uint32_t USB2_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x200 */ |
| __IO uint32_t USB2_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x204 */ |
| __IO uint32_t USB2_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x208 */ |
| __IO uint32_t USB2_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x20C */ |
| __IO uint32_t USB2_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x210 */ |
| __IO uint32_t USB2_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x214 */ |
| __IO uint32_t USB2_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x218 */ |
| __IO uint32_t USB2_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x21C */ |
| __I uint32_t USB2_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x220 */ |
| uint8_t RESERVED_3[12]; |
| __I uint32_t USB2_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x230 */ |
| uint8_t RESERVED_4[28]; |
| __IO uint32_t USB2_MISC; /**< USB Misc Register, offset: 0x250 */ |
| __IO uint32_t USB2_MISC_SET; /**< USB Misc Register, offset: 0x254 */ |
| __IO uint32_t USB2_MISC_CLR; /**< USB Misc Register, offset: 0x258 */ |
| __IO uint32_t USB2_MISC_TOG; /**< USB Misc Register, offset: 0x25C */ |
| __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ |
| } USB_ANALOG_Type, *USB_ANALOG_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- USB_ANALOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* USB_ANALOG - Register accessors */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_REG(base) ((base)->USB1_VBUS_DETECT) |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) |
| #define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) |
| #define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) |
| #define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) |
| #define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) |
| #define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) |
| #define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) |
| #define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) |
| #define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) |
| #define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) |
| #define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) |
| #define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) |
| #define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) |
| |
| /*! |
| * @} |
| */ /* end of group USB_ANALOG_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- USB_ANALOG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks |
| * @{ |
| */ |
| |
| /* USB1_VBUS_DETECT Bit Fields */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 |
| /* USB1_VBUS_DETECT_SET Bit Fields */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 |
| /* USB1_VBUS_DETECT_CLR Bit Fields */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 |
| /* USB1_VBUS_DETECT_TOG Bit Fields */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 |
| /* USB1_CHRG_DETECT Bit Fields */ |
| #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB1_CHRG_DETECT_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_EN_B_SHIFT 20 |
| /* USB1_CHRG_DETECT_SET Bit Fields */ |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_SHIFT 20 |
| /* USB1_CHRG_DETECT_CLR Bit Fields */ |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_SHIFT 20 |
| /* USB1_CHRG_DETECT_TOG Bit Fields */ |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_SHIFT 20 |
| /* USB1_VBUS_DETECT_STAT Bit Fields */ |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_MASK 0x1u |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_SHIFT 0 |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_MASK 0x2u |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_SHIFT 1 |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_MASK 0x4u |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_SHIFT 2 |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 |
| /* USB1_CHRG_DETECT_STAT Bit Fields */ |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 |
| /* USB1_MISC Bit Fields */ |
| #define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB1_MISC_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB1_MISC_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_SHIFT 30 |
| /* USB1_MISC_SET Bit Fields */ |
| #define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_SHIFT 30 |
| /* USB1_MISC_CLR Bit Fields */ |
| #define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_SHIFT 30 |
| /* USB1_MISC_TOG Bit Fields */ |
| #define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_SHIFT 30 |
| /* USB2_VBUS_DETECT Bit Fields */ |
| #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 |
| /* USB2_VBUS_DETECT_SET Bit Fields */ |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 |
| /* USB2_VBUS_DETECT_CLR Bit Fields */ |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 |
| /* USB2_VBUS_DETECT_TOG Bit Fields */ |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 |
| /* USB2_CHRG_DETECT Bit Fields */ |
| #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB2_CHRG_DETECT_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_EN_B_SHIFT 20 |
| /* USB2_CHRG_DETECT_SET Bit Fields */ |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_SHIFT 20 |
| /* USB2_CHRG_DETECT_CLR Bit Fields */ |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_SHIFT 20 |
| /* USB2_CHRG_DETECT_TOG Bit Fields */ |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_MASK 0x100000u |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_SHIFT 20 |
| /* USB2_VBUS_DETECT_STAT Bit Fields */ |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_MASK 0x1u |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_SHIFT 0 |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_MASK 0x2u |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_SHIFT 1 |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_MASK 0x4u |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_SHIFT 2 |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 |
| /* USB2_CHRG_DETECT_STAT Bit Fields */ |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 |
| /* USB2_MISC Bit Fields */ |
| #define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB2_MISC_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB2_MISC_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_SHIFT 30 |
| /* USB2_MISC_SET Bit Fields */ |
| #define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_SHIFT 30 |
| /* USB2_MISC_CLR Bit Fields */ |
| #define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_SHIFT 30 |
| /* USB2_MISC_TOG Bit Fields */ |
| #define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u |
| #define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 |
| #define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_MASK 0x2u |
| #define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_SHIFT 1 |
| #define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u |
| #define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_SHIFT 30 |
| /* DIGPROG Bit Fields */ |
| #define USB_ANALOG_DIGPROG_MINOR_MASK 0xFFu |
| #define USB_ANALOG_DIGPROG_MINOR_SHIFT 0 |
| #define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MINOR_SHIFT))&USB_ANALOG_DIGPROG_MINOR_MASK) |
| #define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK 0xFF00u |
| #define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT 8 |
| #define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) |
| #define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK 0xFF0000u |
| #define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT 16 |
| #define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group USB_ANALOG_Register_Masks */ |
| |
| /* USB_ANALOG - Peripheral instance base addresses */ |
| /** Peripheral USB_ANALOG base address */ |
| #define USB_ANALOG_BASE (0x420C8000u) |
| /** Peripheral USB_ANALOG base pointer */ |
| #define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) |
| #define USB_ANALOG_BASE_PTR (USB_ANALOG) |
| /** Array initializer of USB_ANALOG peripheral base addresses */ |
| #define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } |
| /** Array initializer of USB_ANALOG peripheral base pointers */ |
| #define USB_ANALOG_BASE_PTRS { USB_ANALOG } |
| |
| /* ---------------------------------------------------------------------------- |
| -- USB_ANALOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* USB_ANALOG - Register instance definitions */ |
| /* USB_ANALOG */ |
| #define USB_ANALOG_USB1_VBUS_DETECT USB_ANALOG_USB1_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_VBUS_DETECT_SET USB_ANALOG_USB1_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_VBUS_DETECT_CLR USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_VBUS_DETECT_TOG USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_CHRG_DETECT USB_ANALOG_USB1_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_CHRG_DETECT_SET USB_ANALOG_USB1_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_CHRG_DETECT_CLR USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_CHRG_DETECT_TOG USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_VBUS_DETECT_STAT USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_CHRG_DETECT_STAT USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_MISC USB_ANALOG_USB1_MISC_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_MISC_SET USB_ANALOG_USB1_MISC_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_MISC_CLR USB_ANALOG_USB1_MISC_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB1_MISC_TOG USB_ANALOG_USB1_MISC_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_VBUS_DETECT USB_ANALOG_USB2_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_VBUS_DETECT_SET USB_ANALOG_USB2_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_VBUS_DETECT_CLR USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_VBUS_DETECT_TOG USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_CHRG_DETECT USB_ANALOG_USB2_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_CHRG_DETECT_SET USB_ANALOG_USB2_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_CHRG_DETECT_CLR USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_CHRG_DETECT_TOG USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_VBUS_DETECT_STAT USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_CHRG_DETECT_STAT USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_MISC USB_ANALOG_USB2_MISC_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_MISC_SET USB_ANALOG_USB2_MISC_SET_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_MISC_CLR USB_ANALOG_USB2_MISC_CLR_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_USB2_MISC_TOG USB_ANALOG_USB2_MISC_TOG_REG(USB_ANALOG_BASE_PTR) |
| #define USB_ANALOG_DIGPROG USB_ANALOG_DIGPROG_REG(USB_ANALOG_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group USB_ANALOG_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group USB_ANALOG_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- VDEC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup VDEC_Peripheral_Access_Layer VDEC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** VDEC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t CFC1; /**< 2D Comb Filter Control 1, offset: 0x0 */ |
| uint8_t RESERVED_0[32]; |
| __IO uint32_t BRSTGT; /**< Burst GATE, offset: 0x24 */ |
| uint8_t RESERVED_1[24]; |
| __IO uint32_t HZPOS; /**< Horizontal Position, offset: 0x40 */ |
| __IO uint32_t VRTPOS; /**< Vertical Position, offset: 0x44 */ |
| uint8_t RESERVED_2[12]; |
| __IO uint32_t HVSHFT; /**< Output Conditioning and HV Shift, offset: 0x54 */ |
| __IO uint32_t HSIGS; /**< HSync Ignore Start, offset: 0x58 */ |
| __IO uint32_t HSIGE; /**< HSync Ignore End, offset: 0x5C */ |
| __IO uint32_t VSCON1; /**< VSync Control 1, offset: 0x60 */ |
| __IO uint32_t VSCON2; /**< VSync Control 2, offset: 0x64 */ |
| uint8_t RESERVED_3[4]; |
| __IO uint32_t YCDEL; /**< Y/C Delay and Chroma Debug, offset: 0x6C */ |
| __IO uint32_t AFTCLP; /**< After Clamp, offset: 0x70 */ |
| uint8_t RESERVED_4[4]; |
| __IO uint32_t DCOFF; /**< DC Offset, offset: 0x78 */ |
| uint8_t RESERVED_5[8]; |
| __IO uint32_t CSID; /**< Chroma Swap, Invert, and Debug, offset: 0x84 */ |
| __IO uint32_t CBGN; /**< Cb Gain, offset: 0x88 */ |
| __IO uint32_t CRGN; /**< Cr Gain, offset: 0x8C */ |
| __IO uint32_t CNTR; /**< Contrast, offset: 0x90 */ |
| __IO uint32_t BRT; /**< Brightness, offset: 0x94 */ |
| __IO uint32_t HUE; /**< Hue, offset: 0x98 */ |
| __IO uint32_t CHBTH; /**< Chroma Burst Threshold, offset: 0x9C */ |
| uint8_t RESERVED_6[4]; |
| __IO uint32_t SHPIMP; /**< Sharpness Improvement, offset: 0xA4 */ |
| __IO uint32_t CHPLLIM; /**< Chroma PLL and Input Mode, offset: 0xA8 */ |
| __I uint32_t VIDMOD; /**< Video Mode, offset: 0xAC */ |
| __I uint32_t VIDSTS; /**< Video Status, offset: 0xB0 */ |
| __I uint32_t NOISE; /**< Noise Detector, offset: 0xB4 */ |
| __IO uint32_t STDDBG; /**< Standards and Debug, offset: 0xB8 */ |
| __IO uint32_t MANOVR; /**< Manual Override, offset: 0xBC */ |
| uint8_t RESERVED_7[8]; |
| __IO uint32_t VSSGTH; /**< VSync and Signal Thresholds, offset: 0xC8 */ |
| uint8_t RESERVED_8[4]; |
| __IO uint32_t DBGFBH; /**< Debug Framebuffer, offset: 0xD0 */ |
| __IO uint32_t DBGFBL; /**< Debug Framebuffer 2, offset: 0xD4 */ |
| __IO uint32_t HACTS; /**< H Active Start, offset: 0xD8 */ |
| __IO uint32_t HACTE; /**< H Active End, offset: 0xDC */ |
| __IO uint32_t VACTS; /**< V Active Start, offset: 0xE0 */ |
| __IO uint32_t VACTE; /**< V Active End, offset: 0xE4 */ |
| uint8_t RESERVED_9[4]; |
| __IO uint32_t HSTIP; /**< HSync Tip, offset: 0xEC */ |
| uint8_t RESERVED_10[8]; |
| __IO uint32_t BLSCRCR; /**< Bluescreen Cr, offset: 0xF8 */ |
| __IO uint32_t BLSCRCB; /**< Bluescreen Cb, offset: 0xFC */ |
| uint8_t RESERVED_11[4]; |
| __IO uint32_t LMAGC2; /**< Luma AGC Control 2, offset: 0x104 */ |
| uint8_t RESERVED_12[4]; |
| __IO uint32_t CHAGC2; /**< Chroma AGC Control 2, offset: 0x10C */ |
| uint8_t RESERVED_13[4]; |
| __IO uint32_t MINTH; /**< Minimum Threshold, offset: 0x114 */ |
| uint8_t RESERVED_14[4]; |
| __I uint32_t VFRQOH; /**< Vertical Lines High, offset: 0x11C */ |
| __I uint32_t VFRQOL; /**< Vertical Lines Low, offset: 0x120 */ |
| uint8_t RESERVED_15[508]; |
| __IO uint32_t ASYNCLKFREQ1; /**< Asynchclk Frequency 1, offset: 0x320 */ |
| __IO uint32_t ASYNCLKFREQ2; /**< Asynchclk Frequency 2, offset: 0x324 */ |
| __IO uint32_t ASYNCLKFREQ3; /**< Asynchclk Frequency 3, offset: 0x328 */ |
| __IO uint32_t ASYNCLKFREQ4; /**< Asynchclk Frequency 4, offset: 0x32C */ |
| } VDEC_Type, *VDEC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- VDEC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup VDEC_Register_Accessor_Macros VDEC - Register accessor macros |
| * @{ |
| */ |
| |
| /* VDEC - Register accessors */ |
| #define VDEC_CFC1_REG(base) ((base)->CFC1) |
| #define VDEC_BRSTGT_REG(base) ((base)->BRSTGT) |
| #define VDEC_HZPOS_REG(base) ((base)->HZPOS) |
| #define VDEC_VRTPOS_REG(base) ((base)->VRTPOS) |
| #define VDEC_HVSHFT_REG(base) ((base)->HVSHFT) |
| #define VDEC_HSIGS_REG(base) ((base)->HSIGS) |
| #define VDEC_HSIGE_REG(base) ((base)->HSIGE) |
| #define VDEC_VSCON1_REG(base) ((base)->VSCON1) |
| #define VDEC_VSCON2_REG(base) ((base)->VSCON2) |
| #define VDEC_YCDEL_REG(base) ((base)->YCDEL) |
| #define VDEC_AFTCLP_REG(base) ((base)->AFTCLP) |
| #define VDEC_DCOFF_REG(base) ((base)->DCOFF) |
| #define VDEC_CSID_REG(base) ((base)->CSID) |
| #define VDEC_CBGN_REG(base) ((base)->CBGN) |
| #define VDEC_CRGN_REG(base) ((base)->CRGN) |
| #define VDEC_CNTR_REG(base) ((base)->CNTR) |
| #define VDEC_BRT_REG(base) ((base)->BRT) |
| #define VDEC_HUE_REG(base) ((base)->HUE) |
| #define VDEC_CHBTH_REG(base) ((base)->CHBTH) |
| #define VDEC_SHPIMP_REG(base) ((base)->SHPIMP) |
| #define VDEC_CHPLLIM_REG(base) ((base)->CHPLLIM) |
| #define VDEC_VIDMOD_REG(base) ((base)->VIDMOD) |
| #define VDEC_VIDSTS_REG(base) ((base)->VIDSTS) |
| #define VDEC_NOISE_REG(base) ((base)->NOISE) |
| #define VDEC_STDDBG_REG(base) ((base)->STDDBG) |
| #define VDEC_MANOVR_REG(base) ((base)->MANOVR) |
| #define VDEC_VSSGTH_REG(base) ((base)->VSSGTH) |
| #define VDEC_DBGFBH_REG(base) ((base)->DBGFBH) |
| #define VDEC_DBGFBL_REG(base) ((base)->DBGFBL) |
| #define VDEC_HACTS_REG(base) ((base)->HACTS) |
| #define VDEC_HACTE_REG(base) ((base)->HACTE) |
| #define VDEC_VACTS_REG(base) ((base)->VACTS) |
| #define VDEC_VACTE_REG(base) ((base)->VACTE) |
| #define VDEC_HSTIP_REG(base) ((base)->HSTIP) |
| #define VDEC_BLSCRCR_REG(base) ((base)->BLSCRCR) |
| #define VDEC_BLSCRCB_REG(base) ((base)->BLSCRCB) |
| #define VDEC_LMAGC2_REG(base) ((base)->LMAGC2) |
| #define VDEC_CHAGC2_REG(base) ((base)->CHAGC2) |
| #define VDEC_MINTH_REG(base) ((base)->MINTH) |
| #define VDEC_VFRQOH_REG(base) ((base)->VFRQOH) |
| #define VDEC_VFRQOL_REG(base) ((base)->VFRQOL) |
| #define VDEC_ASYNCLKFREQ1_REG(base) ((base)->ASYNCLKFREQ1) |
| #define VDEC_ASYNCLKFREQ2_REG(base) ((base)->ASYNCLKFREQ2) |
| #define VDEC_ASYNCLKFREQ3_REG(base) ((base)->ASYNCLKFREQ3) |
| #define VDEC_ASYNCLKFREQ4_REG(base) ((base)->ASYNCLKFREQ4) |
| |
| /*! |
| * @} |
| */ /* end of group VDEC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- VDEC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup VDEC_Register_Masks VDEC Register Masks |
| * @{ |
| */ |
| |
| /* CFC1 Bit Fields */ |
| #define VDEC_CFC1_rc_combmode_override_MASK 0xFu |
| #define VDEC_CFC1_rc_combmode_override_SHIFT 0 |
| #define VDEC_CFC1_rc_combmode_override(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_combmode_override_SHIFT))&VDEC_CFC1_rc_combmode_override_MASK) |
| #define VDEC_CFC1_rc_debugout_MASK 0xF0u |
| #define VDEC_CFC1_rc_debugout_SHIFT 4 |
| #define VDEC_CFC1_rc_debugout(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CFC1_rc_debugout_SHIFT))&VDEC_CFC1_rc_debugout_MASK) |
| /* BRSTGT Bit Fields */ |
| #define VDEC_BRSTGT_rc_cburststart_MASK 0xFFu |
| #define VDEC_BRSTGT_rc_cburststart_SHIFT 0 |
| #define VDEC_BRSTGT_rc_cburststart(x) (((uint32_t)(((uint32_t)(x))<<VDEC_BRSTGT_rc_cburststart_SHIFT))&VDEC_BRSTGT_rc_cburststart_MASK) |
| /* HZPOS Bit Fields */ |
| #define VDEC_HZPOS_ro_hpramp_cmp_MASK 0xFFu |
| #define VDEC_HZPOS_ro_hpramp_cmp_SHIFT 0 |
| #define VDEC_HZPOS_ro_hpramp_cmp(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HZPOS_ro_hpramp_cmp_SHIFT))&VDEC_HZPOS_ro_hpramp_cmp_MASK) |
| /* VRTPOS Bit Fields */ |
| #define VDEC_VRTPOS_ro_vline_cmp_MASK 0xFFu |
| #define VDEC_VRTPOS_ro_vline_cmp_SHIFT 0 |
| #define VDEC_VRTPOS_ro_vline_cmp(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VRTPOS_ro_vline_cmp_SHIFT))&VDEC_VRTPOS_ro_vline_cmp_MASK) |
| /* HVSHFT Bit Fields */ |
| #define VDEC_HVSHFT_ro_hzero_sel_MASK 0x1u |
| #define VDEC_HVSHFT_ro_hzero_sel_SHIFT 0 |
| #define VDEC_HVSHFT_ro_invfield_MASK 0x2u |
| #define VDEC_HVSHFT_ro_invfield_SHIFT 1 |
| #define VDEC_HVSHFT_ro_vzero_sel_MASK 0x10u |
| #define VDEC_HVSHFT_ro_vzero_sel_SHIFT 4 |
| #define VDEC_HVSHFT_ro_useactive_MASK 0x20u |
| #define VDEC_HVSHFT_ro_useactive_SHIFT 5 |
| #define VDEC_HVSHFT_antialias_dis_MASK 0x40u |
| #define VDEC_HVSHFT_antialias_dis_SHIFT 6 |
| /* HSIGS Bit Fields */ |
| #define VDEC_HSIGS_rv_ignorestart_MASK 0xFFu |
| #define VDEC_HSIGS_rv_ignorestart_SHIFT 0 |
| #define VDEC_HSIGS_rv_ignorestart(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGS_rv_ignorestart_SHIFT))&VDEC_HSIGS_rv_ignorestart_MASK) |
| /* HSIGE Bit Fields */ |
| #define VDEC_HSIGE_rv_ignoreend_MASK 0xFFu |
| #define VDEC_HSIGE_rv_ignoreend_SHIFT 0 |
| #define VDEC_HSIGE_rv_ignoreend(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HSIGE_rv_ignoreend_SHIFT))&VDEC_HSIGE_rv_ignoreend_MASK) |
| /* VSCON1 Bit Fields */ |
| #define VDEC_VSCON1_rh_vdet_dbg_MASK 0x7u |
| #define VDEC_VSCON1_rh_vdet_dbg_SHIFT 0 |
| #define VDEC_VSCON1_rh_vdet_dbg(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON1_rh_vdet_dbg_SHIFT))&VDEC_VSCON1_rh_vdet_dbg_MASK) |
| #define VDEC_VSCON1_rh_robust625det_MASK 0x8u |
| #define VDEC_VSCON1_rh_robust625det_SHIFT 3 |
| #define VDEC_VSCON1_rh_dis_vsyncdetect_MASK 0x10u |
| #define VDEC_VSCON1_rh_dis_vsyncdetect_SHIFT 4 |
| #define VDEC_VSCON1_rh_vsynchalfmode_MASK 0x20u |
| #define VDEC_VSCON1_rh_vsynchalfmode_SHIFT 5 |
| #define VDEC_VSCON1_rh_modadd_dis_MASK 0x40u |
| #define VDEC_VSCON1_rh_modadd_dis_SHIFT 6 |
| #define VDEC_VSCON1_rh_8or16_MASK 0x80u |
| #define VDEC_VSCON1_rh_8or16_SHIFT 7 |
| /* VSCON2 Bit Fields */ |
| #define VDEC_VSCON2_rh_vcr_phasethr_MASK 0x3u |
| #define VDEC_VSCON2_rh_vcr_phasethr_SHIFT 0 |
| #define VDEC_VSCON2_rh_vcr_phasethr(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_phasethr_SHIFT))&VDEC_VSCON2_rh_vcr_phasethr_MASK) |
| #define VDEC_VSCON2_rh_vcr_force_dis_MASK 0xCu |
| #define VDEC_VSCON2_rh_vcr_force_dis_SHIFT 2 |
| #define VDEC_VSCON2_rh_vcr_force_dis(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_vcr_force_dis_SHIFT))&VDEC_VSCON2_rh_vcr_force_dis_MASK) |
| #define VDEC_VSCON2_rh_hsw_coring_MASK 0x30u |
| #define VDEC_VSCON2_rh_hsw_coring_SHIFT 4 |
| #define VDEC_VSCON2_rh_hsw_coring(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSCON2_rh_hsw_coring_SHIFT))&VDEC_VSCON2_rh_hsw_coring_MASK) |
| #define VDEC_VSCON2_rh_smooth_hsw_MASK 0x40u |
| #define VDEC_VSCON2_rh_smooth_hsw_SHIFT 6 |
| #define VDEC_VSCON2_rh_disable_hsw_MASK 0x80u |
| #define VDEC_VSCON2_rh_disable_hsw_SHIFT 7 |
| /* YCDEL Bit Fields */ |
| #define VDEC_YCDEL_rd_nopalave_MASK 0x1u |
| #define VDEC_YCDEL_rd_nopalave_SHIFT 0 |
| #define VDEC_YCDEL_rd_narrow_MASK 0x2u |
| #define VDEC_YCDEL_rd_narrow_SHIFT 1 |
| #define VDEC_YCDEL_rd_wide_MASK 0x4u |
| #define VDEC_YCDEL_rd_wide_SHIFT 2 |
| #define VDEC_YCDEL_rd_lumadel_MASK 0xF0u |
| #define VDEC_YCDEL_rd_lumadel_SHIFT 4 |
| #define VDEC_YCDEL_rd_lumadel(x) (((uint32_t)(((uint32_t)(x))<<VDEC_YCDEL_rd_lumadel_SHIFT))&VDEC_YCDEL_rd_lumadel_MASK) |
| /* AFTCLP Bit Fields */ |
| #define VDEC_AFTCLP_rh_shortframe_MASK 0x1u |
| #define VDEC_AFTCLP_rh_shortframe_SHIFT 0 |
| #define VDEC_AFTCLP_rl_disoffset_MASK 0x2u |
| #define VDEC_AFTCLP_rl_disoffset_SHIFT 1 |
| #define VDEC_AFTCLP_rl_resetoffset_MASK 0x4u |
| #define VDEC_AFTCLP_rl_resetoffset_SHIFT 2 |
| #define VDEC_AFTCLP_rc_afterclamp_update_en_MASK 0x10u |
| #define VDEC_AFTCLP_rc_afterclamp_update_en_SHIFT 4 |
| #define VDEC_AFTCLP_rc_midfield_dis_MASK 0x20u |
| #define VDEC_AFTCLP_rc_midfield_dis_SHIFT 5 |
| #define VDEC_AFTCLP_rc_aoutoafterclamp_dis_MASK 0x40u |
| #define VDEC_AFTCLP_rc_aoutoafterclamp_dis_SHIFT 6 |
| /* DCOFF Bit Fields */ |
| #define VDEC_DCOFF_rl_dcoffsetI_MASK 0x3u |
| #define VDEC_DCOFF_rl_dcoffsetI_SHIFT 0 |
| #define VDEC_DCOFF_rl_dcoffsetI(x) (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetI_SHIFT))&VDEC_DCOFF_rl_dcoffsetI_MASK) |
| #define VDEC_DCOFF_rl_linemeasure_dis_MASK 0x8u |
| #define VDEC_DCOFF_rl_linemeasure_dis_SHIFT 3 |
| #define VDEC_DCOFF_rl_dcoffsetP_MASK 0x70u |
| #define VDEC_DCOFF_rl_dcoffsetP_SHIFT 4 |
| #define VDEC_DCOFF_rl_dcoffsetP(x) (((uint32_t)(((uint32_t)(x))<<VDEC_DCOFF_rl_dcoffsetP_SHIFT))&VDEC_DCOFF_rl_dcoffsetP_MASK) |
| /* CSID Bit Fields */ |
| #define VDEC_CSID_rd_swapcrcb_MASK 0x1u |
| #define VDEC_CSID_rd_swapcrcb_SHIFT 0 |
| #define VDEC_CSID_rd_invcr_MASK 0x2u |
| #define VDEC_CSID_rd_invcr_SHIFT 1 |
| #define VDEC_CSID_rd_invcb_MASK 0x4u |
| #define VDEC_CSID_rd_invcb_SHIFT 2 |
| #define VDEC_CSID_rd_nopalhue_MASK 0x8u |
| #define VDEC_CSID_rd_nopalhue_SHIFT 3 |
| #define VDEC_CSID_rd_bypasshilbert_MASK 0x80u |
| #define VDEC_CSID_rd_bypasshilbert_SHIFT 7 |
| /* CBGN Bit Fields */ |
| #define VDEC_CBGN_rd_cbgain_MASK 0xFFu |
| #define VDEC_CBGN_rd_cbgain_SHIFT 0 |
| #define VDEC_CBGN_rd_cbgain(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CBGN_rd_cbgain_SHIFT))&VDEC_CBGN_rd_cbgain_MASK) |
| /* CRGN Bit Fields */ |
| #define VDEC_CRGN_rd_crgain_MASK 0xFFu |
| #define VDEC_CRGN_rd_crgain_SHIFT 0 |
| #define VDEC_CRGN_rd_crgain(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CRGN_rd_crgain_SHIFT))&VDEC_CRGN_rd_crgain_MASK) |
| /* CNTR Bit Fields */ |
| #define VDEC_CNTR_rd_lumagain_MASK 0xFFu |
| #define VDEC_CNTR_rd_lumagain_SHIFT 0 |
| #define VDEC_CNTR_rd_lumagain(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CNTR_rd_lumagain_SHIFT))&VDEC_CNTR_rd_lumagain_MASK) |
| /* BRT Bit Fields */ |
| #define VDEC_BRT_rc_blacklevel_MASK 0xFFu |
| #define VDEC_BRT_rc_blacklevel_SHIFT 0 |
| #define VDEC_BRT_rc_blacklevel(x) (((uint32_t)(((uint32_t)(x))<<VDEC_BRT_rc_blacklevel_SHIFT))&VDEC_BRT_rc_blacklevel_MASK) |
| /* HUE Bit Fields */ |
| #define VDEC_HUE_rd_ch_thresh_MASK 0xFFu |
| #define VDEC_HUE_rd_ch_thresh_SHIFT 0 |
| #define VDEC_HUE_rd_ch_thresh(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HUE_rd_ch_thresh_SHIFT))&VDEC_HUE_rd_ch_thresh_MASK) |
| /* CHBTH Bit Fields */ |
| #define VDEC_CHBTH_rd_ch_thresh_MASK 0xFFu |
| #define VDEC_CHBTH_rd_ch_thresh_SHIFT 0 |
| #define VDEC_CHBTH_rd_ch_thresh(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CHBTH_rd_ch_thresh_SHIFT))&VDEC_CHBTH_rd_ch_thresh_MASK) |
| /* SHPIMP Bit Fields */ |
| #define VDEC_SHPIMP_rd_peak_MASK 0xFu |
| #define VDEC_SHPIMP_rd_peak_SHIFT 0 |
| #define VDEC_SHPIMP_rd_peak(x) (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_peak_SHIFT))&VDEC_SHPIMP_rd_peak_MASK) |
| #define VDEC_SHPIMP_rd_slope_MASK 0xF0u |
| #define VDEC_SHPIMP_rd_slope_SHIFT 4 |
| #define VDEC_SHPIMP_rd_slope(x) (((uint32_t)(((uint32_t)(x))<<VDEC_SHPIMP_rd_slope_SHIFT))&VDEC_SHPIMP_rd_slope_MASK) |
| /* CHPLLIM Bit Fields */ |
| #define VDEC_CHPLLIM_rd_inputcables_MASK 0x7u |
| #define VDEC_CHPLLIM_rd_inputcables_SHIFT 0 |
| #define VDEC_CHPLLIM_rd_inputcables(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_inputcables_SHIFT))&VDEC_CHPLLIM_rd_inputcables_MASK) |
| #define VDEC_CHPLLIM_rd_locked_force_MASK 0x8u |
| #define VDEC_CHPLLIM_rd_locked_force_SHIFT 3 |
| #define VDEC_CHPLLIM_rd_chlock_atten_MASK 0x70u |
| #define VDEC_CHPLLIM_rd_chlock_atten_SHIFT 4 |
| #define VDEC_CHPLLIM_rd_chlock_atten(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CHPLLIM_rd_chlock_atten_SHIFT))&VDEC_CHPLLIM_rd_chlock_atten_MASK) |
| /* VIDMOD Bit Fields */ |
| #define VDEC_VIDMOD_havesignal_MASK 0x1u |
| #define VDEC_VIDMOD_havesignal_SHIFT 0 |
| #define VDEC_VIDMOD_Hlocked_MASK 0x2u |
| #define VDEC_VIDMOD_Hlocked_SHIFT 1 |
| #define VDEC_VIDMOD_chroma_MASK 0x4u |
| #define VDEC_VIDMOD_chroma_SHIFT 2 |
| #define VDEC_VIDMOD_ch_locked_MASK 0x8u |
| #define VDEC_VIDMOD_ch_locked_SHIFT 3 |
| #define VDEC_VIDMOD_m625_MASK 0x10u |
| #define VDEC_VIDMOD_m625_SHIFT 4 |
| #define VDEC_VIDMOD_F443_MASK 0x40u |
| #define VDEC_VIDMOD_F443_SHIFT 6 |
| #define VDEC_VIDMOD_Pal_MASK 0x80u |
| #define VDEC_VIDMOD_Pal_SHIFT 7 |
| /* VIDSTS Bit Fields */ |
| #define VDEC_VIDSTS_Nonarith_MASK 0x1u |
| #define VDEC_VIDSTS_Nonarith_SHIFT 0 |
| #define VDEC_VIDSTS_Nonarith3D_MASK 0x2u |
| #define VDEC_VIDSTS_Nonarith3D_SHIFT 1 |
| #define VDEC_VIDSTS_Vcrdetect_MASK 0x4u |
| #define VDEC_VIDSTS_Vcrdetect_SHIFT 2 |
| /* NOISE Bit Fields */ |
| #define VDEC_NOISE_Noise_MASK 0xFFu |
| #define VDEC_NOISE_Noise_SHIFT 0 |
| #define VDEC_NOISE_Noise(x) (((uint32_t)(((uint32_t)(x))<<VDEC_NOISE_Noise_SHIFT))&VDEC_NOISE_Noise_MASK) |
| /* STDDBG Bit Fields */ |
| #define VDEC_STDDBG_standard_filter_MASK 0x3u |
| #define VDEC_STDDBG_standard_filter_SHIFT 0 |
| #define VDEC_STDDBG_standard_filter(x) (((uint32_t)(((uint32_t)(x))<<VDEC_STDDBG_standard_filter_SHIFT))&VDEC_STDDBG_standard_filter_MASK) |
| #define VDEC_STDDBG_force_havesignal_MASK 0x8u |
| #define VDEC_STDDBG_force_havesignal_SHIFT 3 |
| #define VDEC_STDDBG_force_2dntsc443_MASK 0x20u |
| #define VDEC_STDDBG_force_2dntsc443_SHIFT 5 |
| #define VDEC_STDDBG_ntscj_MASK 0x40u |
| #define VDEC_STDDBG_ntscj_SHIFT 6 |
| #define VDEC_STDDBG_rd_fc_maual_MASK 0x80u |
| #define VDEC_STDDBG_rd_fc_maual_SHIFT 7 |
| /* MANOVR Bit Fields */ |
| #define VDEC_MANOVR_manual_625_MASK 0x1u |
| #define VDEC_MANOVR_manual_625_SHIFT 0 |
| #define VDEC_MANOVR_four43_manual_MASK 0x4u |
| #define VDEC_MANOVR_four43_manual_SHIFT 2 |
| #define VDEC_MANOVR_pal_manual_MASK 0x8u |
| #define VDEC_MANOVR_pal_manual_SHIFT 3 |
| #define VDEC_MANOVR_line625_override_MASK 0x10u |
| #define VDEC_MANOVR_line625_override_SHIFT 4 |
| #define VDEC_MANOVR_f443_override_MASK 0x40u |
| #define VDEC_MANOVR_f443_override_SHIFT 6 |
| #define VDEC_MANOVR_pal_override_MASK 0x80u |
| #define VDEC_MANOVR_pal_override_SHIFT 7 |
| /* VSSGTH Bit Fields */ |
| #define VDEC_VSSGTH_nosigthresh_MASK 0x7u |
| #define VDEC_VSSGTH_nosigthresh_SHIFT 0 |
| #define VDEC_VSSGTH_nosigthresh(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_nosigthresh_SHIFT))&VDEC_VSSGTH_nosigthresh_MASK) |
| #define VDEC_VSSGTH_rh_vsynclength_MASK 0xF0u |
| #define VDEC_VSSGTH_rh_vsynclength_SHIFT 4 |
| #define VDEC_VSSGTH_rh_vsynclength(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VSSGTH_rh_vsynclength_SHIFT))&VDEC_VSSGTH_rh_vsynclength_MASK) |
| /* DBGFBH Bit Fields */ |
| #define VDEC_DBGFBH_clamp_delayH_MASK 0x3u |
| #define VDEC_DBGFBH_clamp_delayH_SHIFT 0 |
| #define VDEC_DBGFBH_clamp_delayH(x) (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBH_clamp_delayH_SHIFT))&VDEC_DBGFBH_clamp_delayH_MASK) |
| /* DBGFBL Bit Fields */ |
| #define VDEC_DBGFBL_clamp_delayL_MASK 0xFFu |
| #define VDEC_DBGFBL_clamp_delayL_SHIFT 0 |
| #define VDEC_DBGFBL_clamp_delayL(x) (((uint32_t)(((uint32_t)(x))<<VDEC_DBGFBL_clamp_delayL_SHIFT))&VDEC_DBGFBL_clamp_delayL_MASK) |
| /* HACTS Bit Fields */ |
| #define VDEC_HACTS_ro_hactivestart_MASK 0xFFu |
| #define VDEC_HACTS_ro_hactivestart_SHIFT 0 |
| #define VDEC_HACTS_ro_hactivestart(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HACTS_ro_hactivestart_SHIFT))&VDEC_HACTS_ro_hactivestart_MASK) |
| /* HACTE Bit Fields */ |
| #define VDEC_HACTE_ro_hactiveend_MASK 0xFFu |
| #define VDEC_HACTE_ro_hactiveend_SHIFT 0 |
| #define VDEC_HACTE_ro_hactiveend(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HACTE_ro_hactiveend_SHIFT))&VDEC_HACTE_ro_hactiveend_MASK) |
| /* VACTS Bit Fields */ |
| #define VDEC_VACTS_ro_vactivestart_MASK 0xFFu |
| #define VDEC_VACTS_ro_vactivestart_SHIFT 0 |
| #define VDEC_VACTS_ro_vactivestart(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VACTS_ro_vactivestart_SHIFT))&VDEC_VACTS_ro_vactivestart_MASK) |
| /* VACTE Bit Fields */ |
| #define VDEC_VACTE_ro_vactiveend_MASK 0xFFu |
| #define VDEC_VACTE_ro_vactiveend_SHIFT 0 |
| #define VDEC_VACTE_ro_vactiveend(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VACTE_ro_vactiveend_SHIFT))&VDEC_VACTE_ro_vactiveend_MASK) |
| /* HSTIP Bit Fields */ |
| #define VDEC_HSTIP_rh_tipgate_start_MASK 0xFFu |
| #define VDEC_HSTIP_rh_tipgate_start_SHIFT 0 |
| #define VDEC_HSTIP_rh_tipgate_start(x) (((uint32_t)(((uint32_t)(x))<<VDEC_HSTIP_rh_tipgate_start_SHIFT))&VDEC_HSTIP_rh_tipgate_start_MASK) |
| /* BLSCRCR Bit Fields */ |
| #define VDEC_BLSCRCR_bluescreen_y_MASK 0xFFu |
| #define VDEC_BLSCRCR_bluescreen_y_SHIFT 0 |
| #define VDEC_BLSCRCR_bluescreen_y(x) (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCR_bluescreen_y_SHIFT))&VDEC_BLSCRCR_bluescreen_y_MASK) |
| /* BLSCRCB Bit Fields */ |
| #define VDEC_BLSCRCB_bluescreen_cb_MASK 0xFFu |
| #define VDEC_BLSCRCB_bluescreen_cb_SHIFT 0 |
| #define VDEC_BLSCRCB_bluescreen_cb(x) (((uint32_t)(((uint32_t)(x))<<VDEC_BLSCRCB_bluescreen_cb_SHIFT))&VDEC_BLSCRCB_bluescreen_cb_MASK) |
| /* LMAGC2 Bit Fields */ |
| #define VDEC_LMAGC2_ragc_target_MASK 0xFFu |
| #define VDEC_LMAGC2_ragc_target_SHIFT 0 |
| #define VDEC_LMAGC2_ragc_target(x) (((uint32_t)(((uint32_t)(x))<<VDEC_LMAGC2_ragc_target_SHIFT))&VDEC_LMAGC2_ragc_target_MASK) |
| /* CHAGC2 Bit Fields */ |
| #define VDEC_CHAGC2_rd_chagc_target_MASK 0xFFu |
| #define VDEC_CHAGC2_rd_chagc_target_SHIFT 0 |
| #define VDEC_CHAGC2_rd_chagc_target(x) (((uint32_t)(((uint32_t)(x))<<VDEC_CHAGC2_rd_chagc_target_SHIFT))&VDEC_CHAGC2_rd_chagc_target_MASK) |
| /* MINTH Bit Fields */ |
| #define VDEC_MINTH_minthresh_MASK 0xFFu |
| #define VDEC_MINTH_minthresh_SHIFT 0 |
| #define VDEC_MINTH_minthresh(x) (((uint32_t)(((uint32_t)(x))<<VDEC_MINTH_minthresh_SHIFT))&VDEC_MINTH_minthresh_MASK) |
| /* VFRQOH Bit Fields */ |
| #define VDEC_VFRQOH_vfreqo_MASK 0xFu |
| #define VDEC_VFRQOH_vfreqo_SHIFT 0 |
| #define VDEC_VFRQOH_vfreqo(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOH_vfreqo_SHIFT))&VDEC_VFRQOH_vfreqo_MASK) |
| /* VFRQOL Bit Fields */ |
| #define VDEC_VFRQOL_vfreqo_MASK 0xFFu |
| #define VDEC_VFRQOL_vfreqo_SHIFT 0 |
| #define VDEC_VFRQOL_vfreqo(x) (((uint32_t)(((uint32_t)(x))<<VDEC_VFRQOL_vfreqo_SHIFT))&VDEC_VFRQOL_vfreqo_MASK) |
| /* ASYNCLKFREQ1 Bit Fields */ |
| #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_MASK 0xFFu |
| #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_SHIFT 0 |
| #define VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ1_ASYNCHCLK_FREQUENCY_MASK) |
| /* ASYNCLKFREQ2 Bit Fields */ |
| #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_MASK 0xFFu |
| #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_SHIFT 0 |
| #define VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ2_ASYNCHCLK_FREQUENCY_MASK) |
| /* ASYNCLKFREQ3 Bit Fields */ |
| #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_MASK 0xFFu |
| #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_SHIFT 0 |
| #define VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ3_ASYNCHCLK_FREQUENCY_MASK) |
| /* ASYNCLKFREQ4 Bit Fields */ |
| #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_MASK 0xFFu |
| #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_SHIFT 0 |
| #define VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY(x) (((uint32_t)(((uint32_t)(x))<<VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_SHIFT))&VDEC_ASYNCLKFREQ4_ASYNCHCLK_FREQUENCY_MASK) |
| |
| /*! |
| * @} |
| */ /* end of group VDEC_Register_Masks */ |
| |
| /* VDEC - Peripheral instance base addresses */ |
| /** Peripheral VDEC base address */ |
| #define VDEC_BASE (0x4222C000u) |
| /** Peripheral VDEC base pointer */ |
| #define VDEC ((VDEC_Type *)VDEC_BASE) |
| #define VDEC_BASE_PTR (VDEC) |
| /** Array initializer of VDEC peripheral base addresses */ |
| #define VDEC_BASE_ADDRS { VDEC_BASE } |
| /** Array initializer of VDEC peripheral base pointers */ |
| #define VDEC_BASE_PTRS { VDEC } |
| |
| /* ---------------------------------------------------------------------------- |
| -- VDEC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup VDEC_Register_Accessor_Macros VDEC - Register accessor macros |
| * @{ |
| */ |
| |
| /* VDEC - Register instance definitions */ |
| /* VDEC */ |
| #define VDEC_CFC1 VDEC_CFC1_REG(VDEC_BASE_PTR) |
| #define VDEC_BRSTGT VDEC_BRSTGT_REG(VDEC_BASE_PTR) |
| #define VDEC_HZPOS VDEC_HZPOS_REG(VDEC_BASE_PTR) |
| #define VDEC_VRTPOS VDEC_VRTPOS_REG(VDEC_BASE_PTR) |
| #define VDEC_HVSHFT VDEC_HVSHFT_REG(VDEC_BASE_PTR) |
| #define VDEC_HSIGS VDEC_HSIGS_REG(VDEC_BASE_PTR) |
| #define VDEC_HSIGE VDEC_HSIGE_REG(VDEC_BASE_PTR) |
| #define VDEC_VSCON1 VDEC_VSCON1_REG(VDEC_BASE_PTR) |
| #define VDEC_VSCON2 VDEC_VSCON2_REG(VDEC_BASE_PTR) |
| #define VDEC_YCDEL VDEC_YCDEL_REG(VDEC_BASE_PTR) |
| #define VDEC_AFTCLP VDEC_AFTCLP_REG(VDEC_BASE_PTR) |
| #define VDEC_DCOFF VDEC_DCOFF_REG(VDEC_BASE_PTR) |
| #define VDEC_CSID VDEC_CSID_REG(VDEC_BASE_PTR) |
| #define VDEC_CBGN VDEC_CBGN_REG(VDEC_BASE_PTR) |
| #define VDEC_CRGN VDEC_CRGN_REG(VDEC_BASE_PTR) |
| #define VDEC_CNTR VDEC_CNTR_REG(VDEC_BASE_PTR) |
| #define VDEC_BRT VDEC_BRT_REG(VDEC_BASE_PTR) |
| #define VDEC_HUE VDEC_HUE_REG(VDEC_BASE_PTR) |
| #define VDEC_CHBTH VDEC_CHBTH_REG(VDEC_BASE_PTR) |
| #define VDEC_SHPIMP VDEC_SHPIMP_REG(VDEC_BASE_PTR) |
| #define VDEC_CHPLLIM VDEC_CHPLLIM_REG(VDEC_BASE_PTR) |
| #define VDEC_VIDMOD VDEC_VIDMOD_REG(VDEC_BASE_PTR) |
| #define VDEC_VIDSTS VDEC_VIDSTS_REG(VDEC_BASE_PTR) |
| #define VDEC_NOISE VDEC_NOISE_REG(VDEC_BASE_PTR) |
| #define VDEC_STDDBG VDEC_STDDBG_REG(VDEC_BASE_PTR) |
| #define VDEC_MANOVR VDEC_MANOVR_REG(VDEC_BASE_PTR) |
| #define VDEC_VSSGTH VDEC_VSSGTH_REG(VDEC_BASE_PTR) |
| #define VDEC_DBGFBH VDEC_DBGFBH_REG(VDEC_BASE_PTR) |
| #define VDEC_DBGFBL VDEC_DBGFBL_REG(VDEC_BASE_PTR) |
| #define VDEC_HACTS VDEC_HACTS_REG(VDEC_BASE_PTR) |
| #define VDEC_HACTE VDEC_HACTE_REG(VDEC_BASE_PTR) |
| #define VDEC_VACTS VDEC_VACTS_REG(VDEC_BASE_PTR) |
| #define VDEC_VACTE VDEC_VACTE_REG(VDEC_BASE_PTR) |
| #define VDEC_HSTIP VDEC_HSTIP_REG(VDEC_BASE_PTR) |
| #define VDEC_BLSCRCR VDEC_BLSCRCR_REG(VDEC_BASE_PTR) |
| #define VDEC_BLSCRCB VDEC_BLSCRCB_REG(VDEC_BASE_PTR) |
| #define VDEC_LMAGC2 VDEC_LMAGC2_REG(VDEC_BASE_PTR) |
| #define VDEC_CHAGC2 VDEC_CHAGC2_REG(VDEC_BASE_PTR) |
| #define VDEC_MINTH VDEC_MINTH_REG(VDEC_BASE_PTR) |
| #define VDEC_VFRQOH VDEC_VFRQOH_REG(VDEC_BASE_PTR) |
| #define VDEC_VFRQOL VDEC_VFRQOL_REG(VDEC_BASE_PTR) |
| #define VDEC_ASYNCLKFREQ1 VDEC_ASYNCLKFREQ1_REG(VDEC_BASE_PTR) |
| #define VDEC_ASYNCLKFREQ2 VDEC_ASYNCLKFREQ2_REG(VDEC_BASE_PTR) |
| #define VDEC_ASYNCLKFREQ3 VDEC_ASYNCLKFREQ3_REG(VDEC_BASE_PTR) |
| #define VDEC_ASYNCLKFREQ4 VDEC_ASYNCLKFREQ4_REG(VDEC_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group VDEC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group VDEC_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** WDOG - Register Layout Typedef */ |
| typedef struct { |
| __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ |
| __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ |
| __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ |
| __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ |
| __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ |
| } WDOG_Type, *WDOG_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* WDOG - Register accessors */ |
| #define WDOG_WCR_REG(base) ((base)->WCR) |
| #define WDOG_WSR_REG(base) ((base)->WSR) |
| #define WDOG_WRSR_REG(base) ((base)->WRSR) |
| #define WDOG_WICR_REG(base) ((base)->WICR) |
| #define WDOG_WMCR_REG(base) ((base)->WMCR) |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Register_Masks WDOG Register Masks |
| * @{ |
| */ |
| |
| /* WCR Bit Fields */ |
| #define WDOG_WCR_WDZST_MASK 0x1u |
| #define WDOG_WCR_WDZST_SHIFT 0 |
| #define WDOG_WCR_WDBG_MASK 0x2u |
| #define WDOG_WCR_WDBG_SHIFT 1 |
| #define WDOG_WCR_WDE_MASK 0x4u |
| #define WDOG_WCR_WDE_SHIFT 2 |
| #define WDOG_WCR_WDT_MASK 0x8u |
| #define WDOG_WCR_WDT_SHIFT 3 |
| #define WDOG_WCR_SRS_MASK 0x10u |
| #define WDOG_WCR_SRS_SHIFT 4 |
| #define WDOG_WCR_WDA_MASK 0x20u |
| #define WDOG_WCR_WDA_SHIFT 5 |
| #define WDOG_WCR_SRE_MASK 0x40u |
| #define WDOG_WCR_SRE_SHIFT 6 |
| #define WDOG_WCR_WDW_MASK 0x80u |
| #define WDOG_WCR_WDW_SHIFT 7 |
| #define WDOG_WCR_WT_MASK 0xFF00u |
| #define WDOG_WCR_WT_SHIFT 8 |
| #define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WCR_WT_SHIFT))&WDOG_WCR_WT_MASK) |
| /* WSR Bit Fields */ |
| #define WDOG_WSR_WSR_MASK 0xFFFFu |
| #define WDOG_WSR_WSR_SHIFT 0 |
| #define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WSR_WSR_SHIFT))&WDOG_WSR_WSR_MASK) |
| /* WRSR Bit Fields */ |
| #define WDOG_WRSR_SFTW_MASK 0x1u |
| #define WDOG_WRSR_SFTW_SHIFT 0 |
| #define WDOG_WRSR_TOUT_MASK 0x2u |
| #define WDOG_WRSR_TOUT_SHIFT 1 |
| #define WDOG_WRSR_POR_MASK 0x10u |
| #define WDOG_WRSR_POR_SHIFT 4 |
| /* WICR Bit Fields */ |
| #define WDOG_WICR_WICT_MASK 0xFFu |
| #define WDOG_WICR_WICT_SHIFT 0 |
| #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WICR_WICT_SHIFT))&WDOG_WICR_WICT_MASK) |
| #define WDOG_WICR_WTIS_MASK 0x4000u |
| #define WDOG_WICR_WTIS_SHIFT 14 |
| #define WDOG_WICR_WIE_MASK 0x8000u |
| #define WDOG_WICR_WIE_SHIFT 15 |
| /* WMCR Bit Fields */ |
| #define WDOG_WMCR_PDE_MASK 0x1u |
| #define WDOG_WMCR_PDE_SHIFT 0 |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Register_Masks */ |
| |
| /* WDOG - Peripheral instance base addresses */ |
| /** Peripheral WDOG1 base address */ |
| #define WDOG1_BASE (0x420BC000u) |
| /** Peripheral WDOG1 base pointer */ |
| #define WDOG1 ((WDOG_Type *)WDOG1_BASE) |
| #define WDOG1_BASE_PTR (WDOG1) |
| /** Peripheral WDOG2 base address */ |
| #define WDOG2_BASE (0x420C0000u) |
| /** Peripheral WDOG2 base pointer */ |
| #define WDOG2 ((WDOG_Type *)WDOG2_BASE) |
| #define WDOG2_BASE_PTR (WDOG2) |
| /** Peripheral WDOG3 base address */ |
| #define WDOG3_BASE (0x42288000u) |
| /** Peripheral WDOG3 base pointer */ |
| #define WDOG3 ((WDOG_Type *)WDOG3_BASE) |
| #define WDOG3_BASE_PTR (WDOG3) |
| /** Array initializer of WDOG peripheral base addresses */ |
| #define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } |
| /** Array initializer of WDOG peripheral base pointers */ |
| #define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3 } |
| /** Interrupt vectors for the WDOG peripheral type */ |
| #define WDOG_IRQS { WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- WDOG - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros |
| * @{ |
| */ |
| |
| /* WDOG - Register instance definitions */ |
| /* WDOG1 */ |
| #define WDOG1_WCR WDOG_WCR_REG(WDOG1_BASE_PTR) |
| #define WDOG1_WSR WDOG_WSR_REG(WDOG1_BASE_PTR) |
| #define WDOG1_WRSR WDOG_WRSR_REG(WDOG1_BASE_PTR) |
| #define WDOG1_WICR WDOG_WICR_REG(WDOG1_BASE_PTR) |
| #define WDOG1_WMCR WDOG_WMCR_REG(WDOG1_BASE_PTR) |
| /* WDOG2 */ |
| #define WDOG2_WCR WDOG_WCR_REG(WDOG2_BASE_PTR) |
| #define WDOG2_WSR WDOG_WSR_REG(WDOG2_BASE_PTR) |
| #define WDOG2_WRSR WDOG_WRSR_REG(WDOG2_BASE_PTR) |
| #define WDOG2_WICR WDOG_WICR_REG(WDOG2_BASE_PTR) |
| #define WDOG2_WMCR WDOG_WMCR_REG(WDOG2_BASE_PTR) |
| /* WDOG3 */ |
| #define WDOG3_WCR WDOG_WCR_REG(WDOG3_BASE_PTR) |
| #define WDOG3_WSR WDOG_WSR_REG(WDOG3_BASE_PTR) |
| #define WDOG3_WRSR WDOG_WRSR_REG(WDOG3_BASE_PTR) |
| #define WDOG3_WICR WDOG_WICR_REG(WDOG3_BASE_PTR) |
| #define WDOG3_WMCR WDOG_WMCR_REG(WDOG3_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group WDOG_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC24M Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** XTALOSC24M - Register Layout Typedef */ |
| typedef struct { |
| uint8_t RESERVED_0[336]; |
| __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ |
| uint8_t RESERVED_1[284]; |
| __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ |
| __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ |
| __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ |
| __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ |
| uint8_t RESERVED_2[32]; |
| __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ |
| __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ |
| __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ |
| __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ |
| __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ |
| __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ |
| __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ |
| __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ |
| __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ |
| __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ |
| __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ |
| __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ |
| } XTALOSC24M_Type, *XTALOSC24M_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC24M - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC24M_Register_Accessor_Macros XTALOSC24M - Register accessor macros |
| * @{ |
| */ |
| |
| /* XTALOSC24M - Register accessors */ |
| #define XTALOSC24M_MISC0_REG(base) ((base)->MISC0) |
| #define XTALOSC24M_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) |
| #define XTALOSC24M_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) |
| #define XTALOSC24M_OSC_CONFIG0_REG(base) ((base)->OSC_CONFIG0) |
| #define XTALOSC24M_OSC_CONFIG0_SET_REG(base) ((base)->OSC_CONFIG0_SET) |
| #define XTALOSC24M_OSC_CONFIG0_CLR_REG(base) ((base)->OSC_CONFIG0_CLR) |
| #define XTALOSC24M_OSC_CONFIG0_TOG_REG(base) ((base)->OSC_CONFIG0_TOG) |
| #define XTALOSC24M_OSC_CONFIG1_REG(base) ((base)->OSC_CONFIG1) |
| #define XTALOSC24M_OSC_CONFIG1_SET_REG(base) ((base)->OSC_CONFIG1_SET) |
| #define XTALOSC24M_OSC_CONFIG1_CLR_REG(base) ((base)->OSC_CONFIG1_CLR) |
| #define XTALOSC24M_OSC_CONFIG1_TOG_REG(base) ((base)->OSC_CONFIG1_TOG) |
| #define XTALOSC24M_OSC_CONFIG2_REG(base) ((base)->OSC_CONFIG2) |
| #define XTALOSC24M_OSC_CONFIG2_SET_REG(base) ((base)->OSC_CONFIG2_SET) |
| #define XTALOSC24M_OSC_CONFIG2_CLR_REG(base) ((base)->OSC_CONFIG2_CLR) |
| #define XTALOSC24M_OSC_CONFIG2_TOG_REG(base) ((base)->OSC_CONFIG2_TOG) |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC24M_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC24M Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks |
| * @{ |
| */ |
| |
| /* MISC0 Bit Fields */ |
| #define XTALOSC24M_MISC0_REFTOP_PWD_MASK 0x1u |
| #define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT 0 |
| #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u |
| #define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 |
| #define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK 0x70u |
| #define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT 4 |
| #define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT))&XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) |
| #define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK 0x80u |
| #define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT 7 |
| #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK 0xC00u |
| #define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT 10 |
| #define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT))&XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) |
| #define XTALOSC24M_MISC0_RTC_RINGOSC_EN_MASK 0x1000u |
| #define XTALOSC24M_MISC0_RTC_RINGOSC_EN_SHIFT 12 |
| #define XTALOSC24M_MISC0_OSC_I_MASK 0x6000u |
| #define XTALOSC24M_MISC0_OSC_I_SHIFT 13 |
| #define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_OSC_I_SHIFT))&XTALOSC24M_MISC0_OSC_I_MASK) |
| #define XTALOSC24M_MISC0_OSC_XTALOK_MASK 0x8000u |
| #define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT 15 |
| #define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK 0x10000u |
| #define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT 16 |
| #define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK 0x2000000u |
| #define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT 25 |
| #define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK 0x1C000000u |
| #define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT 26 |
| #define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT))&XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) |
| #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK 0x20000000u |
| #define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT 29 |
| #define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK 0x40000000u |
| #define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT 30 |
| #define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK 0x80000000u |
| #define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT 31 |
| /* LOWPWR_CTRL Bit Fields */ |
| #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK 0x1u |
| #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT 0 |
| #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK 0xEu |
| #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT 1 |
| #define XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK 0x10u |
| #define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT 4 |
| #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK 0x20u |
| #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT 5 |
| #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK 0x40u |
| #define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT 6 |
| #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u |
| #define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 |
| #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u |
| #define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 |
| #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u |
| #define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 |
| #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u |
| #define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 |
| #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x20000u |
| #define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 17 |
| #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x40000u |
| #define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 18 |
| /* LOWPWR_CTRL_SET Bit Fields */ |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK 0x1u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT 0 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK 0xEu |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT 1 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK 0x10u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT 4 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK 0x20u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT 5 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK 0x40u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT 6 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x20000u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 17 |
| #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x40000u |
| #define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 18 |
| /* LOWPWR_CTRL_CLR Bit Fields */ |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK 0x1u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT 0 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK 0xEu |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT 1 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK 0x10u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT 4 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK 0x20u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT 5 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK 0x40u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT 6 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x20000u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 17 |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x40000u |
| #define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 18 |
| /* LOWPWR_CTRL_TOG Bit Fields */ |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK 0x1u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT 0 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK 0xEu |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT 1 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT))&XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK 0x10u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT 4 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK 0x20u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT 5 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK 0x40u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT 6 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK 0x80u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT 7 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK 0x2000u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT 13 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK 0xC000u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT 14 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK 0x10000u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT 16 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x20000u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 17 |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x40000u |
| #define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 18 |
| /* OSC_CONFIG0 Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG0_START_MASK 0x1u |
| #define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK 0x2u |
| #define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1 |
| #define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK 0x4u |
| #define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT 2 |
| #define XTALOSC24M_OSC_CONFIG0_INVERT_MASK 0x8u |
| #define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT 3 |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK 0xFF0u |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4 |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xF000u |
| #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12 |
| #define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xF0000u |
| #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK 0xFF000000u |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 |
| #define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) |
| /* OSC_CONFIG0_SET Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG0_SET_START_MASK 0x1u |
| #define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK 0x2u |
| #define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT 1 |
| #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK 0x4u |
| #define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT 2 |
| #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK 0x8u |
| #define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT 3 |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK 0xFF0u |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT 4 |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK 0xF000u |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT 12 |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK 0xF0000u |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK 0xFF000000u |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT 24 |
| #define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) |
| /* OSC_CONFIG0_CLR Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK 0x1u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK 0x2u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT 1 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK 0x4u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT 2 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK 0x8u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT 3 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK 0xFF0u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT 4 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK 0xF000u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT 12 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK 0xF0000u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK 0xFF000000u |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT 24 |
| #define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) |
| /* OSC_CONFIG0_TOG Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK 0x1u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK 0x2u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT 1 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK 0x4u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT 2 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK 0x8u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT 3 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK 0xFF0u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT 4 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK 0xF000u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT 12 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK 0xF0000u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK 0xFF000000u |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT 24 |
| #define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) |
| /* OSC_CONFIG1 Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK 0xFFF00000u |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 |
| #define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) |
| /* OSC_CONFIG1_SET Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK 0xFFF00000u |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT 20 |
| #define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) |
| /* OSC_CONFIG1_CLR Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK 0xFFF00000u |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT 20 |
| #define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) |
| /* OSC_CONFIG1_TOG Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK 0xFFF00000u |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT 20 |
| #define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT))&XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) |
| /* OSC_CONFIG2 Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK 0x10000u |
| #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK 0x20000u |
| #define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT 17 |
| #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK 0x80000000u |
| #define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT 31 |
| /* OSC_CONFIG2_SET Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK 0x10000u |
| #define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK 0x20000u |
| #define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT 17 |
| #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK 0x80000000u |
| #define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT 31 |
| /* OSC_CONFIG2_CLR Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK 0x10000u |
| #define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK 0x20000u |
| #define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT 17 |
| #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK 0x80000000u |
| #define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT 31 |
| /* OSC_CONFIG2_TOG Bit Fields */ |
| #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK 0xFFFu |
| #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT 0 |
| #define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT))&XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) |
| #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK 0x10000u |
| #define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT 16 |
| #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK 0x20000u |
| #define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT 17 |
| #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK 0x80000000u |
| #define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT 31 |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC24M_Register_Masks */ |
| |
| /* XTALOSC24M - Peripheral instance base addresses */ |
| /** Peripheral XTALOSC24M base address */ |
| #define XTALOSC24M_BASE (0x420C8000u) |
| /** Peripheral XTALOSC24M base pointer */ |
| #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) |
| #define XTALOSC24M_BASE_PTR (XTALOSC24M) |
| /** Array initializer of XTALOSC24M peripheral base addresses */ |
| #define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } |
| /** Array initializer of XTALOSC24M peripheral base pointers */ |
| #define XTALOSC24M_BASE_PTRS { XTALOSC24M } |
| |
| /* ---------------------------------------------------------------------------- |
| -- XTALOSC24M - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup XTALOSC24M_Register_Accessor_Macros XTALOSC24M - Register accessor macros |
| * @{ |
| */ |
| |
| /* XTALOSC24M - Register instance definitions */ |
| /* XTALOSC24M */ |
| #define XTALOSC24M_MISC0 XTALOSC24M_MISC0_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_LOWPWR_CTRL XTALOSC24M_LOWPWR_CTRL_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_LOWPWR_CTRL_SET XTALOSC24M_LOWPWR_CTRL_SET_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_LOWPWR_CTRL_CLR XTALOSC24M_LOWPWR_CTRL_CLR_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_LOWPWR_CTRL_TOG XTALOSC24M_LOWPWR_CTRL_TOG_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG0 XTALOSC24M_OSC_CONFIG0_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG0_SET XTALOSC24M_OSC_CONFIG0_SET_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG0_CLR XTALOSC24M_OSC_CONFIG0_CLR_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG0_TOG XTALOSC24M_OSC_CONFIG0_TOG_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG1 XTALOSC24M_OSC_CONFIG1_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG1_SET XTALOSC24M_OSC_CONFIG1_SET_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG1_CLR XTALOSC24M_OSC_CONFIG1_CLR_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG1_TOG XTALOSC24M_OSC_CONFIG1_TOG_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG2 XTALOSC24M_OSC_CONFIG2_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG2_SET XTALOSC24M_OSC_CONFIG2_SET_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG2_CLR XTALOSC24M_OSC_CONFIG2_CLR_REG(XTALOSC24M_BASE_PTR) |
| #define XTALOSC24M_OSC_CONFIG2_TOG XTALOSC24M_OSC_CONFIG2_TOG_REG(XTALOSC24M_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC24M_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group XTALOSC24M_Peripheral */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- uSDHC Peripheral Access Layer |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup uSDHC_Peripheral_Access_Layer uSDHC Peripheral Access Layer |
| * @{ |
| */ |
| |
| /** uSDHC - Register Layout Typedef */ |
| typedef struct { |
| __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ |
| __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ |
| __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ |
| __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ |
| __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ |
| __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ |
| __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ |
| __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ |
| __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ |
| __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ |
| __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ |
| __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ |
| __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ |
| __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ |
| __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ |
| __I uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ |
| __I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ |
| __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ |
| __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ |
| uint8_t RESERVED_0[4]; |
| __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ |
| __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ |
| __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ |
| uint8_t RESERVED_1[4]; |
| __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ |
| __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ |
| __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ |
| uint8_t RESERVED_2[84]; |
| __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ |
| __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ |
| __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ |
| __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ |
| } uSDHC_Type, *uSDHC_MemMapPtr; |
| |
| /* ---------------------------------------------------------------------------- |
| -- uSDHC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros |
| * @{ |
| */ |
| |
| /* uSDHC - Register accessors */ |
| #define uSDHC_DS_ADDR_REG(base) ((base)->DS_ADDR) |
| #define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) |
| #define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) |
| #define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) |
| #define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) |
| #define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) |
| #define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) |
| #define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) |
| #define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) |
| #define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) |
| #define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) |
| #define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) |
| #define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) |
| #define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) |
| #define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) |
| #define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) |
| #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) |
| #define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) |
| #define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) |
| #define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) |
| #define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) |
| #define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) |
| #define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) |
| #define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) |
| #define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) |
| #define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) |
| #define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) |
| #define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) |
| |
| /*! |
| * @} |
| */ /* end of group uSDHC_Register_Accessor_Macros */ |
| |
| /* ---------------------------------------------------------------------------- |
| -- uSDHC Register Masks |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup uSDHC_Register_Masks uSDHC Register Masks |
| * @{ |
| */ |
| |
| /* DS_ADDR Bit Fields */ |
| #define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu |
| #define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 |
| #define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DS_ADDR_DS_ADDR_SHIFT))&uSDHC_DS_ADDR_DS_ADDR_MASK) |
| /* BLK_ATT Bit Fields */ |
| #define uSDHC_BLK_ATT_BLKSIZE_MASK 0x1FFFu |
| #define uSDHC_BLK_ATT_BLKSIZE_SHIFT 0 |
| #define uSDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKSIZE_SHIFT))&uSDHC_BLK_ATT_BLKSIZE_MASK) |
| #define uSDHC_BLK_ATT_BLKCNT_MASK 0xFFFF0000u |
| #define uSDHC_BLK_ATT_BLKCNT_SHIFT 16 |
| #define uSDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKCNT_SHIFT))&uSDHC_BLK_ATT_BLKCNT_MASK) |
| /* CMD_ARG Bit Fields */ |
| #define uSDHC_CMD_ARG_CMDARG_MASK 0xFFFFFFFFu |
| #define uSDHC_CMD_ARG_CMDARG_SHIFT 0 |
| #define uSDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_ARG_CMDARG_SHIFT))&uSDHC_CMD_ARG_CMDARG_MASK) |
| /* CMD_XFR_TYP Bit Fields */ |
| #define uSDHC_CMD_XFR_TYP_RSPTYP_MASK 0x30000u |
| #define uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT 16 |
| #define uSDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT))&uSDHC_CMD_XFR_TYP_RSPTYP_MASK) |
| #define uSDHC_CMD_XFR_TYP_CCCEN_MASK 0x80000u |
| #define uSDHC_CMD_XFR_TYP_CCCEN_SHIFT 19 |
| #define uSDHC_CMD_XFR_TYP_CICEN_MASK 0x100000u |
| #define uSDHC_CMD_XFR_TYP_CICEN_SHIFT 20 |
| #define uSDHC_CMD_XFR_TYP_DPSEL_MASK 0x200000u |
| #define uSDHC_CMD_XFR_TYP_DPSEL_SHIFT 21 |
| #define uSDHC_CMD_XFR_TYP_CMDTYP_MASK 0xC00000u |
| #define uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT 22 |
| #define uSDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT))&uSDHC_CMD_XFR_TYP_CMDTYP_MASK) |
| #define uSDHC_CMD_XFR_TYP_CMDINX_MASK 0x3F000000u |
| #define uSDHC_CMD_XFR_TYP_CMDINX_SHIFT 24 |
| #define uSDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDINX_SHIFT))&uSDHC_CMD_XFR_TYP_CMDINX_MASK) |
| /* CMD_RSP0 Bit Fields */ |
| #define uSDHC_CMD_RSP0_CMDRSP0_MASK 0xFFFFFFFFu |
| #define uSDHC_CMD_RSP0_CMDRSP0_SHIFT 0 |
| #define uSDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP0_CMDRSP0_SHIFT))&uSDHC_CMD_RSP0_CMDRSP0_MASK) |
| /* CMD_RSP1 Bit Fields */ |
| #define uSDHC_CMD_RSP1_CMDRSP1_MASK 0xFFFFFFFFu |
| #define uSDHC_CMD_RSP1_CMDRSP1_SHIFT 0 |
| #define uSDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP1_CMDRSP1_SHIFT))&uSDHC_CMD_RSP1_CMDRSP1_MASK) |
| /* CMD_RSP2 Bit Fields */ |
| #define uSDHC_CMD_RSP2_CMDRSP2_MASK 0xFFFFFFFFu |
| #define uSDHC_CMD_RSP2_CMDRSP2_SHIFT 0 |
| #define uSDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP2_CMDRSP2_SHIFT))&uSDHC_CMD_RSP2_CMDRSP2_MASK) |
| /* CMD_RSP3 Bit Fields */ |
| #define uSDHC_CMD_RSP3_CMDRSP3_MASK 0xFFFFFFFFu |
| #define uSDHC_CMD_RSP3_CMDRSP3_SHIFT 0 |
| #define uSDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP3_CMDRSP3_SHIFT))&uSDHC_CMD_RSP3_CMDRSP3_MASK) |
| /* DATA_BUFF_ACC_PORT Bit Fields */ |
| #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK 0xFFFFFFFFu |
| #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT 0 |
| #define uSDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT))&uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) |
| /* PRES_STATE Bit Fields */ |
| #define uSDHC_PRES_STATE_CIHB_MASK 0x1u |
| #define uSDHC_PRES_STATE_CIHB_SHIFT 0 |
| #define uSDHC_PRES_STATE_CDIHB_MASK 0x2u |
| #define uSDHC_PRES_STATE_CDIHB_SHIFT 1 |
| #define uSDHC_PRES_STATE_DLA_MASK 0x4u |
| #define uSDHC_PRES_STATE_DLA_SHIFT 2 |
| #define uSDHC_PRES_STATE_SDSTB_MASK 0x8u |
| #define uSDHC_PRES_STATE_SDSTB_SHIFT 3 |
| #define uSDHC_PRES_STATE_IPGOFF_MASK 0x10u |
| #define uSDHC_PRES_STATE_IPGOFF_SHIFT 4 |
| #define uSDHC_PRES_STATE_HCKOFF_MASK 0x20u |
| #define uSDHC_PRES_STATE_HCKOFF_SHIFT 5 |
| #define uSDHC_PRES_STATE_PEROFF_MASK 0x40u |
| #define uSDHC_PRES_STATE_PEROFF_SHIFT 6 |
| #define uSDHC_PRES_STATE_SDOFF_MASK 0x80u |
| #define uSDHC_PRES_STATE_SDOFF_SHIFT 7 |
| #define uSDHC_PRES_STATE_WTA_MASK 0x100u |
| #define uSDHC_PRES_STATE_WTA_SHIFT 8 |
| #define uSDHC_PRES_STATE_RTA_MASK 0x200u |
| #define uSDHC_PRES_STATE_RTA_SHIFT 9 |
| #define uSDHC_PRES_STATE_BWEN_MASK 0x400u |
| #define uSDHC_PRES_STATE_BWEN_SHIFT 10 |
| #define uSDHC_PRES_STATE_BREN_MASK 0x800u |
| #define uSDHC_PRES_STATE_BREN_SHIFT 11 |
| #define uSDHC_PRES_STATE_RTR_MASK 0x1000u |
| #define uSDHC_PRES_STATE_RTR_SHIFT 12 |
| #define uSDHC_PRES_STATE_TSCD_MASK 0x8000u |
| #define uSDHC_PRES_STATE_TSCD_SHIFT 15 |
| #define uSDHC_PRES_STATE_CINST_MASK 0x10000u |
| #define uSDHC_PRES_STATE_CINST_SHIFT 16 |
| #define uSDHC_PRES_STATE_CDPL_MASK 0x40000u |
| #define uSDHC_PRES_STATE_CDPL_SHIFT 18 |
| #define uSDHC_PRES_STATE_WPSPL_MASK 0x80000u |
| #define uSDHC_PRES_STATE_WPSPL_SHIFT 19 |
| #define uSDHC_PRES_STATE_CLSL_MASK 0x800000u |
| #define uSDHC_PRES_STATE_CLSL_SHIFT 23 |
| #define uSDHC_PRES_STATE_DLSL_MASK 0xFF000000u |
| #define uSDHC_PRES_STATE_DLSL_SHIFT 24 |
| #define uSDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PRES_STATE_DLSL_SHIFT))&uSDHC_PRES_STATE_DLSL_MASK) |
| /* PROT_CTRL Bit Fields */ |
| #define uSDHC_PROT_CTRL_LCTL_MASK 0x1u |
| #define uSDHC_PROT_CTRL_LCTL_SHIFT 0 |
| #define uSDHC_PROT_CTRL_DTW_MASK 0x6u |
| #define uSDHC_PROT_CTRL_DTW_SHIFT 1 |
| #define uSDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DTW_SHIFT))&uSDHC_PROT_CTRL_DTW_MASK) |
| #define uSDHC_PROT_CTRL_D3CD_MASK 0x8u |
| #define uSDHC_PROT_CTRL_D3CD_SHIFT 3 |
| #define uSDHC_PROT_CTRL_EMODE_MASK 0x30u |
| #define uSDHC_PROT_CTRL_EMODE_SHIFT 4 |
| #define uSDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_EMODE_SHIFT))&uSDHC_PROT_CTRL_EMODE_MASK) |
| #define uSDHC_PROT_CTRL_CDTL_MASK 0x40u |
| #define uSDHC_PROT_CTRL_CDTL_SHIFT 6 |
| #define uSDHC_PROT_CTRL_CDSS_MASK 0x80u |
| #define uSDHC_PROT_CTRL_CDSS_SHIFT 7 |
| #define uSDHC_PROT_CTRL_DMASEL_MASK 0x300u |
| #define uSDHC_PROT_CTRL_DMASEL_SHIFT 8 |
| #define uSDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DMASEL_SHIFT))&uSDHC_PROT_CTRL_DMASEL_MASK) |
| #define uSDHC_PROT_CTRL_SABGREQ_MASK 0x10000u |
| #define uSDHC_PROT_CTRL_SABGREQ_SHIFT 16 |
| #define uSDHC_PROT_CTRL_CREQ_MASK 0x20000u |
| #define uSDHC_PROT_CTRL_CREQ_SHIFT 17 |
| #define uSDHC_PROT_CTRL_RWCTL_MASK 0x40000u |
| #define uSDHC_PROT_CTRL_RWCTL_SHIFT 18 |
| #define uSDHC_PROT_CTRL_IABG_MASK 0x80000u |
| #define uSDHC_PROT_CTRL_IABG_SHIFT 19 |
| #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK 0x100000u |
| #define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT 20 |
| #define uSDHC_PROT_CTRL_WECINT_MASK 0x1000000u |
| #define uSDHC_PROT_CTRL_WECINT_SHIFT 24 |
| #define uSDHC_PROT_CTRL_WECINS_MASK 0x2000000u |
| #define uSDHC_PROT_CTRL_WECINS_SHIFT 25 |
| #define uSDHC_PROT_CTRL_WECRM_MASK 0x4000000u |
| #define uSDHC_PROT_CTRL_WECRM_SHIFT 26 |
| #define uSDHC_PROT_CTRL_BURST_LEN_EN_MASK 0x38000000u |
| #define uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT 27 |
| #define uSDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT))&uSDHC_PROT_CTRL_BURST_LEN_EN_MASK) |
| #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK 0x40000000u |
| #define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT 30 |
| /* SYS_CTRL Bit Fields */ |
| #define uSDHC_SYS_CTRL_DVS_MASK 0xF0u |
| #define uSDHC_SYS_CTRL_DVS_SHIFT 4 |
| #define uSDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DVS_SHIFT))&uSDHC_SYS_CTRL_DVS_MASK) |
| #define uSDHC_SYS_CTRL_SDCLKFS_MASK 0xFF00u |
| #define uSDHC_SYS_CTRL_SDCLKFS_SHIFT 8 |
| #define uSDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_SDCLKFS_SHIFT))&uSDHC_SYS_CTRL_SDCLKFS_MASK) |
| #define uSDHC_SYS_CTRL_DTOCV_MASK 0xF0000u |
| #define uSDHC_SYS_CTRL_DTOCV_SHIFT 16 |
| #define uSDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DTOCV_SHIFT))&uSDHC_SYS_CTRL_DTOCV_MASK) |
| #define uSDHC_SYS_CTRL_IPP_RST_N_MASK 0x800000u |
| #define uSDHC_SYS_CTRL_IPP_RST_N_SHIFT 23 |
| #define uSDHC_SYS_CTRL_RSTA_MASK 0x1000000u |
| #define uSDHC_SYS_CTRL_RSTA_SHIFT 24 |
| #define uSDHC_SYS_CTRL_RSTC_MASK 0x2000000u |
| #define uSDHC_SYS_CTRL_RSTC_SHIFT 25 |
| #define uSDHC_SYS_CTRL_RSTD_MASK 0x4000000u |
| #define uSDHC_SYS_CTRL_RSTD_SHIFT 26 |
| #define uSDHC_SYS_CTRL_INITA_MASK 0x8000000u |
| #define uSDHC_SYS_CTRL_INITA_SHIFT 27 |
| #define uSDHC_SYS_CTRL_RSTT_MASK 0x10000000u |
| #define uSDHC_SYS_CTRL_RSTT_SHIFT 28 |
| /* INT_STATUS Bit Fields */ |
| #define uSDHC_INT_STATUS_CC_MASK 0x1u |
| #define uSDHC_INT_STATUS_CC_SHIFT 0 |
| #define uSDHC_INT_STATUS_TC_MASK 0x2u |
| #define uSDHC_INT_STATUS_TC_SHIFT 1 |
| #define uSDHC_INT_STATUS_BGE_MASK 0x4u |
| #define uSDHC_INT_STATUS_BGE_SHIFT 2 |
| #define uSDHC_INT_STATUS_DINT_MASK 0x8u |
| #define uSDHC_INT_STATUS_DINT_SHIFT 3 |
| #define uSDHC_INT_STATUS_BWR_MASK 0x10u |
| #define uSDHC_INT_STATUS_BWR_SHIFT 4 |
| #define uSDHC_INT_STATUS_BRR_MASK 0x20u |
| #define uSDHC_INT_STATUS_BRR_SHIFT 5 |
| #define uSDHC_INT_STATUS_CINS_MASK 0x40u |
| #define uSDHC_INT_STATUS_CINS_SHIFT 6 |
| #define uSDHC_INT_STATUS_CRM_MASK 0x80u |
| #define uSDHC_INT_STATUS_CRM_SHIFT 7 |
| #define uSDHC_INT_STATUS_CINT_MASK 0x100u |
| #define uSDHC_INT_STATUS_CINT_SHIFT 8 |
| #define uSDHC_INT_STATUS_RTE_MASK 0x1000u |
| #define uSDHC_INT_STATUS_RTE_SHIFT 12 |
| #define uSDHC_INT_STATUS_TP_MASK 0x4000u |
| #define uSDHC_INT_STATUS_TP_SHIFT 14 |
| #define uSDHC_INT_STATUS_CTOE_MASK 0x10000u |
| #define uSDHC_INT_STATUS_CTOE_SHIFT 16 |
| #define uSDHC_INT_STATUS_CCE_MASK 0x20000u |
| #define uSDHC_INT_STATUS_CCE_SHIFT 17 |
| #define uSDHC_INT_STATUS_CEBE_MASK 0x40000u |
| #define uSDHC_INT_STATUS_CEBE_SHIFT 18 |
| #define uSDHC_INT_STATUS_CIE_MASK 0x80000u |
| #define uSDHC_INT_STATUS_CIE_SHIFT 19 |
| #define uSDHC_INT_STATUS_DTOE_MASK 0x100000u |
| #define uSDHC_INT_STATUS_DTOE_SHIFT 20 |
| #define uSDHC_INT_STATUS_DCE_MASK 0x200000u |
| #define uSDHC_INT_STATUS_DCE_SHIFT 21 |
| #define uSDHC_INT_STATUS_DEBE_MASK 0x400000u |
| #define uSDHC_INT_STATUS_DEBE_SHIFT 22 |
| #define uSDHC_INT_STATUS_AC12E_MASK 0x1000000u |
| #define uSDHC_INT_STATUS_AC12E_SHIFT 24 |
| #define uSDHC_INT_STATUS_TNE_MASK 0x4000000u |
| #define uSDHC_INT_STATUS_TNE_SHIFT 26 |
| #define uSDHC_INT_STATUS_DMAE_MASK 0x10000000u |
| #define uSDHC_INT_STATUS_DMAE_SHIFT 28 |
| /* INT_STATUS_EN Bit Fields */ |
| #define uSDHC_INT_STATUS_EN_CCSEN_MASK 0x1u |
| #define uSDHC_INT_STATUS_EN_CCSEN_SHIFT 0 |
| #define uSDHC_INT_STATUS_EN_TCSEN_MASK 0x2u |
| #define uSDHC_INT_STATUS_EN_TCSEN_SHIFT 1 |
| #define uSDHC_INT_STATUS_EN_BGESEN_MASK 0x4u |
| #define uSDHC_INT_STATUS_EN_BGESEN_SHIFT 2 |
| #define uSDHC_INT_STATUS_EN_DINTSEN_MASK 0x8u |
| #define uSDHC_INT_STATUS_EN_DINTSEN_SHIFT 3 |
| #define uSDHC_INT_STATUS_EN_BWRSEN_MASK 0x10u |
| #define uSDHC_INT_STATUS_EN_BWRSEN_SHIFT 4 |
| #define uSDHC_INT_STATUS_EN_BRRSEN_MASK 0x20u |
| #define uSDHC_INT_STATUS_EN_BRRSEN_SHIFT 5 |
| #define uSDHC_INT_STATUS_EN_CINSSEN_MASK 0x40u |
| #define uSDHC_INT_STATUS_EN_CINSSEN_SHIFT 6 |
| #define uSDHC_INT_STATUS_EN_CRMSEN_MASK 0x80u |
| #define uSDHC_INT_STATUS_EN_CRMSEN_SHIFT 7 |
| #define uSDHC_INT_STATUS_EN_CINTSEN_MASK 0x100u |
| #define uSDHC_INT_STATUS_EN_CINTSEN_SHIFT 8 |
| #define uSDHC_INT_STATUS_EN_RTESEN_MASK 0x1000u |
| #define uSDHC_INT_STATUS_EN_RTESEN_SHIFT 12 |
| #define uSDHC_INT_STATUS_EN_TPSEN_MASK 0x4000u |
| #define uSDHC_INT_STATUS_EN_TPSEN_SHIFT 14 |
| #define uSDHC_INT_STATUS_EN_CTOESEN_MASK 0x10000u |
| #define uSDHC_INT_STATUS_EN_CTOESEN_SHIFT 16 |
| #define uSDHC_INT_STATUS_EN_CCESEN_MASK 0x20000u |
| #define uSDHC_INT_STATUS_EN_CCESEN_SHIFT 17 |
| #define uSDHC_INT_STATUS_EN_CEBESEN_MASK 0x40000u |
| #define uSDHC_INT_STATUS_EN_CEBESEN_SHIFT 18 |
| #define uSDHC_INT_STATUS_EN_CIESEN_MASK 0x80000u |
| #define uSDHC_INT_STATUS_EN_CIESEN_SHIFT 19 |
| #define uSDHC_INT_STATUS_EN_DTOESEN_MASK 0x100000u |
| #define uSDHC_INT_STATUS_EN_DTOESEN_SHIFT 20 |
| #define uSDHC_INT_STATUS_EN_DCESEN_MASK 0x200000u |
| #define uSDHC_INT_STATUS_EN_DCESEN_SHIFT 21 |
| #define uSDHC_INT_STATUS_EN_DEBESEN_MASK 0x400000u |
| #define uSDHC_INT_STATUS_EN_DEBESEN_SHIFT 22 |
| #define uSDHC_INT_STATUS_EN_AC12ESEN_MASK 0x1000000u |
| #define uSDHC_INT_STATUS_EN_AC12ESEN_SHIFT 24 |
| #define uSDHC_INT_STATUS_EN_TNESEN_MASK 0x4000000u |
| #define uSDHC_INT_STATUS_EN_TNESEN_SHIFT 26 |
| #define uSDHC_INT_STATUS_EN_DMAESEN_MASK 0x10000000u |
| #define uSDHC_INT_STATUS_EN_DMAESEN_SHIFT 28 |
| /* INT_SIGNAL_EN Bit Fields */ |
| #define uSDHC_INT_SIGNAL_EN_CCIEN_MASK 0x1u |
| #define uSDHC_INT_SIGNAL_EN_CCIEN_SHIFT 0 |
| #define uSDHC_INT_SIGNAL_EN_TCIEN_MASK 0x2u |
| #define uSDHC_INT_SIGNAL_EN_TCIEN_SHIFT 1 |
| #define uSDHC_INT_SIGNAL_EN_BGEIEN_MASK 0x4u |
| #define uSDHC_INT_SIGNAL_EN_BGEIEN_SHIFT 2 |
| #define uSDHC_INT_SIGNAL_EN_DINTIEN_MASK 0x8u |
| #define uSDHC_INT_SIGNAL_EN_DINTIEN_SHIFT 3 |
| #define uSDHC_INT_SIGNAL_EN_BWRIEN_MASK 0x10u |
| #define uSDHC_INT_SIGNAL_EN_BWRIEN_SHIFT 4 |
| #define uSDHC_INT_SIGNAL_EN_BRRIEN_MASK 0x20u |
| #define uSDHC_INT_SIGNAL_EN_BRRIEN_SHIFT 5 |
| #define uSDHC_INT_SIGNAL_EN_CINSIEN_MASK 0x40u |
| #define uSDHC_INT_SIGNAL_EN_CINSIEN_SHIFT 6 |
| #define uSDHC_INT_SIGNAL_EN_CRMIEN_MASK 0x80u |
| #define uSDHC_INT_SIGNAL_EN_CRMIEN_SHIFT 7 |
| #define uSDHC_INT_SIGNAL_EN_CINTIEN_MASK 0x100u |
| #define uSDHC_INT_SIGNAL_EN_CINTIEN_SHIFT 8 |
| #define uSDHC_INT_SIGNAL_EN_RTEIEN_MASK 0x1000u |
| #define uSDHC_INT_SIGNAL_EN_RTEIEN_SHIFT 12 |
| #define uSDHC_INT_SIGNAL_EN_TPIEN_MASK 0x4000u |
| #define uSDHC_INT_SIGNAL_EN_TPIEN_SHIFT 14 |
| #define uSDHC_INT_SIGNAL_EN_CTOEIEN_MASK 0x10000u |
| #define uSDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT 16 |
| #define uSDHC_INT_SIGNAL_EN_CCEIEN_MASK 0x20000u |
| #define uSDHC_INT_SIGNAL_EN_CCEIEN_SHIFT 17 |
| #define uSDHC_INT_SIGNAL_EN_CEBEIEN_MASK 0x40000u |
| #define uSDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT 18 |
| #define uSDHC_INT_SIGNAL_EN_CIEIEN_MASK 0x80000u |
| #define uSDHC_INT_SIGNAL_EN_CIEIEN_SHIFT 19 |
| #define uSDHC_INT_SIGNAL_EN_DTOEIEN_MASK 0x100000u |
| #define uSDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT 20 |
| #define uSDHC_INT_SIGNAL_EN_DCEIEN_MASK 0x200000u |
| #define uSDHC_INT_SIGNAL_EN_DCEIEN_SHIFT 21 |
| #define uSDHC_INT_SIGNAL_EN_DEBEIEN_MASK 0x400000u |
| #define uSDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT 22 |
| #define uSDHC_INT_SIGNAL_EN_AC12EIEN_MASK 0x1000000u |
| #define uSDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT 24 |
| #define uSDHC_INT_SIGNAL_EN_TNEIEN_MASK 0x4000000u |
| #define uSDHC_INT_SIGNAL_EN_TNEIEN_SHIFT 26 |
| #define uSDHC_INT_SIGNAL_EN_DMAEIEN_MASK 0x10000000u |
| #define uSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT 28 |
| /* AUTOCMD12_ERR_STATUS Bit Fields */ |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK 0x1u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT 0 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK 0x2u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT 1 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK 0x4u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT 2 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK 0x8u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT 3 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK 0x10u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT 4 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK 0x80u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT 7 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK 0x400000u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT 22 |
| #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK 0x800000u |
| #define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT 23 |
| /* HOST_CTRL_CAP Bit Fields */ |
| #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK 0x1u |
| #define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT 0 |
| #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK 0x2u |
| #define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT 1 |
| #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK 0x4u |
| #define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT 2 |
| #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK 0xF00u |
| #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT 8 |
| #define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT))&uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) |
| #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK 0x2000u |
| #define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT 13 |
| #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK 0xC000u |
| #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT 14 |
| #define uSDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT))&uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) |
| #define uSDHC_HOST_CTRL_CAP_MBL_MASK 0x70000u |
| #define uSDHC_HOST_CTRL_CAP_MBL_SHIFT 16 |
| #define uSDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_MBL_SHIFT))&uSDHC_HOST_CTRL_CAP_MBL_MASK) |
| #define uSDHC_HOST_CTRL_CAP_ADMAS_MASK 0x100000u |
| #define uSDHC_HOST_CTRL_CAP_ADMAS_SHIFT 20 |
| #define uSDHC_HOST_CTRL_CAP_HSS_MASK 0x200000u |
| #define uSDHC_HOST_CTRL_CAP_HSS_SHIFT 21 |
| #define uSDHC_HOST_CTRL_CAP_DMAS_MASK 0x400000u |
| #define uSDHC_HOST_CTRL_CAP_DMAS_SHIFT 22 |
| #define uSDHC_HOST_CTRL_CAP_SRS_MASK 0x800000u |
| #define uSDHC_HOST_CTRL_CAP_SRS_SHIFT 23 |
| #define uSDHC_HOST_CTRL_CAP_VS33_MASK 0x1000000u |
| #define uSDHC_HOST_CTRL_CAP_VS33_SHIFT 24 |
| #define uSDHC_HOST_CTRL_CAP_VS30_MASK 0x2000000u |
| #define uSDHC_HOST_CTRL_CAP_VS30_SHIFT 25 |
| #define uSDHC_HOST_CTRL_CAP_VS18_MASK 0x4000000u |
| #define uSDHC_HOST_CTRL_CAP_VS18_SHIFT 26 |
| /* WTMK_LVL Bit Fields */ |
| #define uSDHC_WTMK_LVL_RD_WML_MASK 0xFFu |
| #define uSDHC_WTMK_LVL_RD_WML_SHIFT 0 |
| #define uSDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_WML_SHIFT))&uSDHC_WTMK_LVL_RD_WML_MASK) |
| #define uSDHC_WTMK_LVL_RD_BRST_LEN_MASK 0x1F00u |
| #define uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT 8 |
| #define uSDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_RD_BRST_LEN_MASK) |
| #define uSDHC_WTMK_LVL_WR_WML_MASK 0xFF0000u |
| #define uSDHC_WTMK_LVL_WR_WML_SHIFT 16 |
| #define uSDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_WML_SHIFT))&uSDHC_WTMK_LVL_WR_WML_MASK) |
| #define uSDHC_WTMK_LVL_WR_BRST_LEN_MASK 0x1F000000u |
| #define uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT 24 |
| #define uSDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_WR_BRST_LEN_MASK) |
| /* MIX_CTRL Bit Fields */ |
| #define uSDHC_MIX_CTRL_DMAEN_MASK 0x1u |
| #define uSDHC_MIX_CTRL_DMAEN_SHIFT 0 |
| #define uSDHC_MIX_CTRL_BCEN_MASK 0x2u |
| #define uSDHC_MIX_CTRL_BCEN_SHIFT 1 |
| #define uSDHC_MIX_CTRL_AC12EN_MASK 0x4u |
| #define uSDHC_MIX_CTRL_AC12EN_SHIFT 2 |
| #define uSDHC_MIX_CTRL_DDR_EN_MASK 0x8u |
| #define uSDHC_MIX_CTRL_DDR_EN_SHIFT 3 |
| #define uSDHC_MIX_CTRL_DTDSEL_MASK 0x10u |
| #define uSDHC_MIX_CTRL_DTDSEL_SHIFT 4 |
| #define uSDHC_MIX_CTRL_MSBSEL_MASK 0x20u |
| #define uSDHC_MIX_CTRL_MSBSEL_SHIFT 5 |
| #define uSDHC_MIX_CTRL_NIBBLE_POS_MASK 0x40u |
| #define uSDHC_MIX_CTRL_NIBBLE_POS_SHIFT 6 |
| #define uSDHC_MIX_CTRL_AC23EN_MASK 0x80u |
| #define uSDHC_MIX_CTRL_AC23EN_SHIFT 7 |
| #define uSDHC_MIX_CTRL_EXE_TUNE_MASK 0x400000u |
| #define uSDHC_MIX_CTRL_EXE_TUNE_SHIFT 22 |
| #define uSDHC_MIX_CTRL_SMP_CLK_SEL_MASK 0x800000u |
| #define uSDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT 23 |
| #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_MASK 0x1000000u |
| #define uSDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT 24 |
| #define uSDHC_MIX_CTRL_FBCLK_SEL_MASK 0x2000000u |
| #define uSDHC_MIX_CTRL_FBCLK_SEL_SHIFT 25 |
| /* FORCE_EVENT Bit Fields */ |
| #define uSDHC_FORCE_EVENT_FEVTAC12NE_MASK 0x1u |
| #define uSDHC_FORCE_EVENT_FEVTAC12NE_SHIFT 0 |
| #define uSDHC_FORCE_EVENT_FEVTAC12TOE_MASK 0x2u |
| #define uSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT 1 |
| #define uSDHC_FORCE_EVENT_FEVTAC12CE_MASK 0x4u |
| #define uSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT 2 |
| #define uSDHC_FORCE_EVENT_FEVTAC12EBE_MASK 0x8u |
| #define uSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT 3 |
| #define uSDHC_FORCE_EVENT_FEVTAC12IE_MASK 0x10u |
| #define uSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT 4 |
| #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK 0x80u |
| #define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT 7 |
| #define uSDHC_FORCE_EVENT_FEVTCTOE_MASK 0x10000u |
| #define uSDHC_FORCE_EVENT_FEVTCTOE_SHIFT 16 |
| #define uSDHC_FORCE_EVENT_FEVTCCE_MASK 0x20000u |
| #define uSDHC_FORCE_EVENT_FEVTCCE_SHIFT 17 |
| #define uSDHC_FORCE_EVENT_FEVTCEBE_MASK 0x40000u |
| #define uSDHC_FORCE_EVENT_FEVTCEBE_SHIFT 18 |
| #define uSDHC_FORCE_EVENT_FEVTCIE_MASK 0x80000u |
| #define uSDHC_FORCE_EVENT_FEVTCIE_SHIFT 19 |
| #define uSDHC_FORCE_EVENT_FEVTDTOE_MASK 0x100000u |
| #define uSDHC_FORCE_EVENT_FEVTDTOE_SHIFT 20 |
| #define uSDHC_FORCE_EVENT_FEVTDCE_MASK 0x200000u |
| #define uSDHC_FORCE_EVENT_FEVTDCE_SHIFT 21 |
| #define uSDHC_FORCE_EVENT_FEVTDEBE_MASK 0x400000u |
| #define uSDHC_FORCE_EVENT_FEVTDEBE_SHIFT 22 |
| #define uSDHC_FORCE_EVENT_FEVTAC12E_MASK 0x1000000u |
| #define uSDHC_FORCE_EVENT_FEVTAC12E_SHIFT 24 |
| #define uSDHC_FORCE_EVENT_FEVTTNE_MASK 0x4000000u |
| #define uSDHC_FORCE_EVENT_FEVTTNE_SHIFT 26 |
| #define uSDHC_FORCE_EVENT_FEVTDMAE_MASK 0x10000000u |
| #define uSDHC_FORCE_EVENT_FEVTDMAE_SHIFT 28 |
| #define uSDHC_FORCE_EVENT_FEVTCINT_MASK 0x80000000u |
| #define uSDHC_FORCE_EVENT_FEVTCINT_SHIFT 31 |
| /* ADMA_ERR_STATUS Bit Fields */ |
| #define uSDHC_ADMA_ERR_STATUS_ADMAES_MASK 0x3u |
| #define uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT 0 |
| #define uSDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT))&uSDHC_ADMA_ERR_STATUS_ADMAES_MASK) |
| #define uSDHC_ADMA_ERR_STATUS_ADMALME_MASK 0x4u |
| #define uSDHC_ADMA_ERR_STATUS_ADMALME_SHIFT 2 |
| #define uSDHC_ADMA_ERR_STATUS_ADMADCE_MASK 0x8u |
| #define uSDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT 3 |
| /* ADMA_SYS_ADDR Bit Fields */ |
| #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK 0xFFFFFFFCu |
| #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT 2 |
| #define uSDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT))&uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) |
| /* DLL_CTRL Bit Fields */ |
| #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK 0x1u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT 0 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_MASK 0x2u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT 1 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK 0x78u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT 3 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) |
| #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK 0x80u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT 7 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT 8 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK 0x70000u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT 16 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) |
| #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u |
| #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 |
| #define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) |
| /* DLL_STATUS Bit Fields */ |
| #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK 0x1u |
| #define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT 0 |
| #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK 0x2u |
| #define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT 1 |
| #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK 0x1FCu |
| #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT 2 |
| #define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) |
| #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK 0xFE00u |
| #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT 9 |
| #define uSDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) |
| /* CLK_TUNE_CTRL_STATUS Bit Fields */ |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK 0xFu |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT 0 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK 0xF0u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT 4 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK 0x7F00u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT 8 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK 0x8000u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT 15 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK 0xF0000u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT 16 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK 0xF00000u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT 20 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK 0x7F000000u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT 24 |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK 0x80000000u |
| #define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT 31 |
| /* VEND_SPEC Bit Fields */ |
| #define uSDHC_VEND_SPEC_EXT_DMA_EN_MASK 0x1u |
| #define uSDHC_VEND_SPEC_EXT_DMA_EN_SHIFT 0 |
| #define uSDHC_VEND_SPEC_VSELECT_MASK 0x2u |
| #define uSDHC_VEND_SPEC_VSELECT_SHIFT 1 |
| #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK 0x4u |
| #define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT 2 |
| #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK 0x8u |
| #define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT 3 |
| #define uSDHC_VEND_SPEC_DAT3_CD_POL_MASK 0x10u |
| #define uSDHC_VEND_SPEC_DAT3_CD_POL_SHIFT 4 |
| #define uSDHC_VEND_SPEC_CD_POL_MASK 0x20u |
| #define uSDHC_VEND_SPEC_CD_POL_SHIFT 5 |
| #define uSDHC_VEND_SPEC_WP_POL_MASK 0x40u |
| #define uSDHC_VEND_SPEC_WP_POL_SHIFT 6 |
| #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK 0x80u |
| #define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT 7 |
| #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_MASK 0x100u |
| #define uSDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT 8 |
| #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK 0x800u |
| #define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT 11 |
| #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_MASK 0x1000u |
| #define uSDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT 12 |
| #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK 0x2000u |
| #define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT 13 |
| #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK 0x4000u |
| #define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT 14 |
| #define uSDHC_VEND_SPEC_CRC_CHK_DIS_MASK 0x8000u |
| #define uSDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT 15 |
| #define uSDHC_VEND_SPEC_INT_ST_VAL_MASK 0xFF0000u |
| #define uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT 16 |
| #define uSDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT))&uSDHC_VEND_SPEC_INT_ST_VAL_MASK) |
| #define uSDHC_VEND_SPEC_CMD_BYTE_EN_MASK 0x80000000u |
| #define uSDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT 31 |
| /* MMC_BOOT Bit Fields */ |
| #define uSDHC_MMC_BOOT_DTOCV_ACK_MASK 0xFu |
| #define uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT 0 |
| #define uSDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT))&uSDHC_MMC_BOOT_DTOCV_ACK_MASK) |
| #define uSDHC_MMC_BOOT_BOOT_ACK_MASK 0x10u |
| #define uSDHC_MMC_BOOT_BOOT_ACK_SHIFT 4 |
| #define uSDHC_MMC_BOOT_BOOT_MODE_MASK 0x20u |
| #define uSDHC_MMC_BOOT_BOOT_MODE_SHIFT 5 |
| #define uSDHC_MMC_BOOT_BOOT_EN_MASK 0x40u |
| #define uSDHC_MMC_BOOT_BOOT_EN_SHIFT 6 |
| #define uSDHC_MMC_BOOT_AUTO_SABG_EN_MASK 0x80u |
| #define uSDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT 7 |
| #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK 0x100u |
| #define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT 8 |
| #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK 0xFFFF0000u |
| #define uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT 16 |
| #define uSDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT))&uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) |
| /* VEND_SPEC2 Bit Fields */ |
| #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK 0x1u |
| #define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT 0 |
| #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_MASK 0x2u |
| #define uSDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT 1 |
| #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK 0x4u |
| #define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT 2 |
| #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK 0x8u |
| #define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT 3 |
| #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_MASK 0x10u |
| #define uSDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT 4 |
| #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_MASK 0x20u |
| #define uSDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT 5 |
| #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_MASK 0x40u |
| #define uSDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT 6 |
| #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK 0x80u |
| #define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT 7 |
| /* TUNING_CTRL Bit Fields */ |
| #define uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK 0xFFu |
| #define uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT 0 |
| #define uSDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK) |
| #define uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK 0xFF00u |
| #define uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT 8 |
| #define uSDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT))&uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK) |
| #define uSDHC_TUNING_CTRL_TUNING_STEP_MASK 0x70000u |
| #define uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT 16 |
| #define uSDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_STEP_MASK) |
| #define uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK 0x700000u |
| #define uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT 20 |
| #define uSDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT))&uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK) |
| #define uSDHC_TUNING_CTRL_STD_TUNING_EN_MASK 0x1000000u |
| #define uSDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT 24 |
| |
| /*! |
| * @} |
| */ /* end of group uSDHC_Register_Masks */ |
| |
| /* uSDHC - Peripheral instance base addresses */ |
| /** Peripheral uSDHC1 base address */ |
| #define uSDHC1_BASE (0x42190000u) |
| /** Peripheral uSDHC1 base pointer */ |
| #define uSDHC1 ((uSDHC_Type *)uSDHC1_BASE) |
| #define uSDHC1_BASE_PTR (uSDHC1) |
| /** Peripheral uSDHC2 base address */ |
| #define uSDHC2_BASE (0x42194000u) |
| /** Peripheral uSDHC2 base pointer */ |
| #define uSDHC2 ((uSDHC_Type *)uSDHC2_BASE) |
| #define uSDHC2_BASE_PTR (uSDHC2) |
| /** Peripheral uSDHC3 base address */ |
| #define uSDHC3_BASE (0x42198000u) |
| /** Peripheral uSDHC3 base pointer */ |
| #define uSDHC3 ((uSDHC_Type *)uSDHC3_BASE) |
| #define uSDHC3_BASE_PTR (uSDHC3) |
| /** Peripheral uSDHC4 base address */ |
| #define uSDHC4_BASE (0x4219C000u) |
| /** Peripheral uSDHC4 base pointer */ |
| #define uSDHC4 ((uSDHC_Type *)uSDHC4_BASE) |
| #define uSDHC4_BASE_PTR (uSDHC4) |
| /** Array initializer of uSDHC peripheral base addresses */ |
| #define uSDHC_BASE_ADDRS { uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE, uSDHC4_BASE } |
| /** Array initializer of uSDHC peripheral base pointers */ |
| #define uSDHC_BASE_PTRS { uSDHC1, uSDHC2, uSDHC3, uSDHC4 } |
| /** Interrupt vectors for the uSDHC peripheral type */ |
| #define uSDHC_IRQS { USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn, USDHC4_IRQn } |
| |
| /* ---------------------------------------------------------------------------- |
| -- uSDHC - Register accessor macros |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros |
| * @{ |
| */ |
| |
| /* uSDHC - Register instance definitions */ |
| /* uSDHC1 */ |
| #define uSDHC1_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC1_BASE_PTR) |
| #define uSDHC1_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC1_BASE_PTR) |
| /* uSDHC2 */ |
| #define uSDHC2_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC2_BASE_PTR) |
| #define uSDHC2_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC2_BASE_PTR) |
| /* uSDHC3 */ |
| #define uSDHC3_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC3_BASE_PTR) |
| #define uSDHC3_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC3_BASE_PTR) |
| /* uSDHC4 */ |
| #define uSDHC4_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC4_BASE_PTR) |
| #define uSDHC4_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC4_BASE_PTR) |
| |
| /*! |
| * @} |
| */ /* end of group uSDHC_Register_Accessor_Macros */ |
| |
| /*! |
| * @} |
| */ /* end of group uSDHC_Peripheral */ |
| |
| /* |
| ** End of section using anonymous unions |
| */ |
| |
| #if defined(__ARMCC_VERSION) |
| #pragma pop |
| #elif defined(__GNUC__) |
| /* leave anonymous unions enabled */ |
| #elif defined(__IAR_SYSTEMS_ICC__) |
| #pragma language=default |
| #else |
| #error Not supported compiler type |
| #endif |
| |
| /*! |
| * @} |
| */ /* end of group Peripheral_defines */ |
| |
| |
| /* ---------------------------------------------------------------------------- |
| -- Backward Compatibility |
| ---------------------------------------------------------------------------- */ |
| |
| /*! |
| * @addtogroup Backward_Compatibility_Symbols Backward Compatibility |
| * @{ |
| */ |
| |
| /* No backward compatibility issues. */ |
| |
| /*! |
| * @} |
| */ /* end of group Backward_Compatibility_Symbols */ |
| |
| |
| #else /* #if !defined(MCIMX6X_M4_H_) */ |
| /* There is already included the same memory map. Check if it is compatible (has the same major version) */ |
| #if (MCU_MEM_MAP_VERSION != 0x0100u) |
| #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) |
| #warning There are included two not compatible versions of memory maps. Please check possible differences. |
| #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ |
| #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ |
| #endif /* #if !defined(MCIMX6X_M4_H_) */ |
| |
| /* MCIMX6X_M4.h, eof. */ |
