tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/f1_pll_64_hsi_8.overlay

/*
 * Copyright (c) 2022 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after clear_clocks.overlay file.
 */

&clk_hsi {
	status = "okay";
};

&pll {
	mul = <16>;
	clocks = <&clk_hsi>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(64)>;
};