blob: ff9eac49dcaec69c2857aa423bf0821124be8b7f [file] [log] [blame]
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/* hsi_clk = 16MHz */
&clk_hsi {
hsi-div = <4>; /* HSISYS = 4Mhz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
ahb-prescaler = <1>;
clock-frequency = <DT_FREQ_M(4)>;
};