blob: 5d1d8d8786bf02901a8d8f81cc4f294a1528eeb9 [file] [log] [blame]
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <24>;
div-p = <2>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};