soc/arm/nxp_imx/rt/Kconfig.defconfig.series

# i.MX RT series

# Copyright (c) 2017-2021, NXP
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_IMX_RT

config SOC_SERIES
	default "rt"

config ROM_START_OFFSET
	default 0x400 if BOOTLOADER_MCUBOOT
	default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR

config PINCTRL_IMX
	default y if HAS_MCUX_IOMUXC
	depends on PINCTRL

config ADC_MCUX_12B1MSPS_SAR
	default y if HAS_MCUX_12B1MSPS_SAR
	depends on ADC

config LOG_BACKEND_SWO_FREQ_HZ
	default 7500000
	depends on LOG_BACKEND_SWO

if FLASH_MCUX_FLEXSPI_XIP

# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
	default FLASH_LOG_LEVEL_OFF
endchoice

choice MEMC_LOG_LEVEL_CHOICE
	default MEMC_LOG_LEVEL_OFF
endchoice

endif

# set the tick per sec as a divider of the GPT clock source
config SYS_CLOCK_TICKS_PER_SEC
	default 4096 if MCUX_GPT_TIMER

DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk)

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMX_RT10XX && CORTEX_M_SYSTICK
	default 32768 if MCUX_GPT_TIMER

config PM_MCUX_GPC
	default y if HAS_MCUX_GPC
	depends on SOC_SERIES_IMX_RT11XX && PM

# Don't allow SOC to sleep after tests complete when PM is enabled
config ZTEST_NO_YIELD
	default y if (ZTEST && PM)

if SOC_SERIES_IMX_RT10XX && PM

config CODE_DATA_RELOCATION
	default y

config PM_MCUX_GPC
	default y if HAS_MCUX_GPC

config PM_MCUX_DCDC
	default y if HAS_MCUX_DCDC

config PM_MCUX_PMU
	default y if HAS_MCUX_PMU

endif # SOC_SERIES_IMX_RT10XX && PM

if CODE_SEMC

config FLASH_SIZE
	default $(dt_node_reg_size_int,/memory@80000000,0,K)

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/memory@80000000)

endif # CODE_SEMC

if CODE_ITCM

config FLASH_SIZE
	default $(dt_node_reg_size_int,/soc/flexram@40028000/itcm@0,0,K) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K) if SOC_SERIES_IMX_RT10XX

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/soc/flexram@40028000/itcm@0) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0) if SOC_SERIES_IMX_RT10XX

endif # CODE_ITCM

if CODE_SRAM0

config FLASH_SIZE
	default $(dt_node_reg_size_int,/soc/memory@1ffe0000,0,K)

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/soc/memory@1ffe0000)

endif # CODE_SRAM0

if CODE_OCRAM

config FLASH_SIZE
	default $(dt_node_reg_size_int,/soc/ocram@20200000,0,K)

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/soc/ocram@20200000)

endif # CODE_OCRAM

if CODE_FLEXSPI

config FLASH_SIZE
	default $(dt_node_reg_size_int,/soc/spi@400cc000,1,K) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_size_int,/soc/spi@400a0000,1,K) if SOC_MIMXRT1011
	default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K) if SOC_SERIES_IMX_RT10XX

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/soc/spi@400cc000,1) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_addr_hex,/soc/spi@400a0000,1) if SOC_MIMXRT1011
	default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) if SOC_SERIES_IMX_RT10XX

endif # CODE_FLEXSPI

if CODE_FLEXSPI2

config FLASH_SIZE
	default $(dt_node_reg_size_int,/soc/spi@4000d000,1,K) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K) if SOC_SERIES_IMX_RT10XX

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,/soc/spi@4000d000,1) if SOC_SERIES_IMX_RT11XX
	default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1) if SOC_SERIES_IMX_RT10XX

endif # CODE_FLEXSPI2

choice USB_MCUX_CONTROLLER_TYPE
	default USB_DC_NXP_EHCI
endchoice

DT_CHOSEN_Z_DTCM := zephyr,dtcm

choice SEGGER_RTT_SECTION
	default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
	depends on USE_SEGGER_RTT
endchoice

choice SEGGER_SYSVIEW_SECTION
	default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
	depends on SEGGER_SYSTEMVIEW
endchoice

#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
config MBEDTLS
#config TINYCRYPT
	default y if CSPRING_ENABLED
	depends on ENTROPY_GENERATOR

if MBEDTLS
#
# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
# what the ztest_thread_stack defaults to.
#
config TEST_EXTRA_STACK_SIZE
	int
	default 1024
endif # MBEDTLS

source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"

endif # SOC_SERIES_IMX_RT