dts/arm/st/f0/stm32f030Xc.dtsi

/*
 * Copyright (c) 2018 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <st/f0/stm32f030X8.dtsi>

/ {
	sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(32)>;
	};

	soc {
		flash-controller@40022000 {
			flash0: flash@8000000 {
				erase-block-size = <2048>;
				reg = <0x08000000 DT_SIZE_K(256)>;
			};
		};

		/*
		 * USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
		 * configuration is not currently supported, so at most one of
		 * these may be enabled at a time. Enabling more than one will
		 * result in a build failure.
		 */
		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
			resets = <&rctl STM32_RESET(APB1, 18U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
			resets = <&rctl STM32_RESET(APB1, 19U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
			resets = <&rctl STM32_RESET(APB1, 20U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
			resets = <&rctl STM32_RESET(APB2, 5U)>;
			interrupts = <29 0>;
			status = "disabled";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
			resets = <&rctl STM32_RESET(APB1, 5U)>;
			interrupts = <18 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";
		};
	};
};