| /* |
| * Copyright (c) 2019 Linaro Ltd. |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * Copyright (c) 2024 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32l1_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/stm32f4_adc.h> |
| #include <zephyr/dt-bindings/reset/stm32l1_reset.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m3"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_msi: clk-msi { |
| #clock-cells = <0>; |
| compatible = "st,stm32l0-msi-clock"; |
| msi-range = <5>; /* 2.1MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(37)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32l0-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| |
| flash: flash-controller@40023c00 { |
| compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller"; |
| reg = <0x40023c00 0x400>; |
| interrupts = <4 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 15U)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32f4-nv-flash", "st,stm32-nv-flash", |
| "soc-nv-flash"; |
| |
| write-block-size = <4>; |
| /* maximum erase time(ms) for a 128B half-page |
| */ |
| max-erase-time = <4>; |
| }; |
| }; |
| |
| rcc: rcc@40023800 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40023800 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 28U)>; |
| prescaler = <32768>; |
| alarms-count = <2>; |
| alrm-exti-line = <17>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17U)>; |
| resets = <&rctl STM32_RESET(APB1, 17U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 18U)>; |
| resets = <&rctl STM32_RESET(APB1, 18U)>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 19U)>; |
| resets = <&rctl STM32_RESET(APB1, 19U)>; |
| interrupts = <48 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 20U)>; |
| resets = <&rctl STM32_RESET(APB1, 20U)>; |
| interrupts = <49 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21U)>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v1"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 22U)>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12U)>; |
| interrupts = <35 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 14U)>; |
| interrupts = <36 0>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14U)>; |
| resets = <&rctl STM32_RESET(APB2, 14U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@40012400 { |
| compatible = "st,stm32f4-adc", "st,stm32-adc"; |
| reg = <0x40012400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 9U)>, |
| <&rcc STM32_SRC_HSI NO_SEL>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <4 9 16 24 48 96 192 384>; |
| st,adc-clock-source = <ASYNC>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| dac1: dac@40007400 { |
| compatible = "st,stm32-dac"; |
| reg = <0x40007400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 29U)>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| exti: interrupt-controller@40010400 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40010400 0x400>; |
| num-lines = <16>; |
| interrupts = <6 0>, <7 0>, <8 0>, <9 0>, |
| <10 0>, <23 0>, <40 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5-9", "line10-15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 5>, <10 6>; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0U)>; |
| resets = <&rctl STM32_RESET(APB1, 0U)>; |
| interrupts = <28 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 1U)>; |
| resets = <&rctl STM32_RESET(APB1, 1U)>; |
| interrupts = <29 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 2U)>; |
| resets = <&rctl STM32_RESET(APB1, 2U)>; |
| interrupts = <30 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers9: timers@40010800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 2U)>; |
| resets = <&rctl STM32_RESET(APB2, 2U)>; |
| interrupts = <25 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers10: timers@40010c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 3U)>; |
| resets = <&rctl STM32_RESET(APB2, 3U)>; |
| interrupts = <26 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers11: timers@40011000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40011000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 4U)>; |
| resets = <&rctl STM32_RESET(APB2, 4U)>; |
| interrupts = <27 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| pinctrl: pin-controller@40020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40020000 0x2000>; |
| |
| gpioa: gpio@40020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; |
| }; |
| |
| gpiob: gpio@40020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; |
| }; |
| |
| gpioc: gpio@40020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; |
| }; |
| |
| gpiod: gpio@40020c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 3U)>; |
| }; |
| |
| gpioe: gpio@40021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 4U)>; |
| }; |
| |
| gpioh: gpio@40021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11U)>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| eeprom: eeprom@8080000{ |
| compatible = "st,stm32-eeprom"; |
| status = "disabled"; |
| }; |
| |
| dma1: dma@40026000 { |
| compatible = "st,stm32-dma-v2bis"; |
| #dma-cells = <2>; |
| reg = <0x40026000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 24U)>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FF800FA>; |
| ts-cal2-addr = <0x1FF800FE>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <110>; |
| ts-cal-vrefanalog = <3000>; |
| io-channels = <&adc1 16>; |
| status = "disabled"; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x1FF800F8>; |
| vrefint-cal-mv = <3000>; |
| io-channels = <&adc1 17>; |
| status = "disabled"; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus2: smbus2 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
