dts/arm/ti/j721e_main_r5.dtsi

/* Copyright (C) 2023 BeagleBoard.org Foundation
 * Copyright (C) 2023 S Prashanth
 * Copyright (c) 2024 Texas Instruments Incorporated
 *	Andrew Davis <afd@ti.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <freq.h>
#include <arm/armv7-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r5";
			reg = <0>;
		};
	};

	atcm: memory@0 {
		device_type = "memory";
		compatible = "zephyr,memory-region", "mmio-sram";
		reg = <0x00000000 DT_SIZE_K(32)>;
		zephyr,memory-region = "ATCM";
	};

	btcm: memory@41010000 {
		device_type = "memory";
		compatible = "zephyr,memory-region", "mmio-sram";
		reg = <0x41010000 DT_SIZE_K(32)>;
		zephyr,memory-region = "BTCM";
	};

	vim: interrupt-controller@ff80000 {
		#address-cells = <1>;
		compatible = "ti,vim";
		reg = <0x0ff80000 0x2800>;
		interrupt-controller;
		#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
		status = "okay";
	};

	pinctrl: pinctrl@11c000 {
		compatible = "ti,k3-pinctrl";
		reg = <0x0011c000 0x2b4>;
		status = "okay";
	};

	uart1: uart@2810000 {
		compatible = "ns16550";
		reg = <0x02810000 0x100>;
		clock-frequency = <48000000>;
		interrupts = <0 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&vim>;
		reg-shift = <2>;
		status = "disabled";
	};

	uart2: uart@2820000 {
		compatible = "ns16550";
		reg = <0x02820000 0x100>;
		clock-frequency = <48000000>;
		interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&vim>;
		reg-shift = <2>;
		status = "disabled";
	};

	systick_timer: timer@24c0000 {
		compatible = "ti,am654-timer";
		reg = <0x24c0000 0x70>;
		interrupts = <0 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&vim>;
		status = "disabled";
	};
};