| /* |
| * Copyright (c) 2024 Nordic Semiconductor ASA |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <nordic/nrf_common.dtsi> |
| |
| #include <zephyr/dt-bindings/adc/nrf-saadc.h> |
| #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h> |
| #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h> |
| #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h> |
| #include <zephyr/dt-bindings/misc/nordic-tddconf.h> |
| #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h> |
| #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h> |
| |
| /delete-node/ &sw_pwm; |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpuapp: cpu@2 { |
| compatible = "arm,cortex-m33"; |
| reg = <2>; |
| device_type = "cpu"; |
| clocks = <&cpuapp_hsfll>; |
| clock-frequency = <DT_FREQ_M(320)>; |
| cpu-power-states = <&idle &s2ram>; |
| }; |
| |
| cpurad: cpu@3 { |
| compatible = "arm,cortex-m33"; |
| reg = <3>; |
| device_type = "cpu"; |
| clocks = <&cpurad_hsfll>; |
| clock-frequency = <DT_FREQ_M(256)>; |
| }; |
| |
| cpuppr: cpu@d { |
| compatible = "nordic,vpr"; |
| reg = <13>; |
| device_type = "cpu"; |
| clocks = <&fll16m>; |
| clock-frequency = <DT_FREQ_M(16)>; |
| riscv,isa = "rv32emc"; |
| nordic,bus-width = <32>; |
| |
| cpuppr_vevif_rx: mailbox { |
| compatible = "nordic,nrf-vevif-task-rx"; |
| status = "disabled"; |
| interrupt-parent = <&cpuppr_clic>; |
| interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, |
| <1 NRF_DEFAULT_IRQ_PRIORITY>, |
| <2 NRF_DEFAULT_IRQ_PRIORITY>, |
| <3 NRF_DEFAULT_IRQ_PRIORITY>, |
| <4 NRF_DEFAULT_IRQ_PRIORITY>, |
| <5 NRF_DEFAULT_IRQ_PRIORITY>, |
| <6 NRF_DEFAULT_IRQ_PRIORITY>, |
| <7 NRF_DEFAULT_IRQ_PRIORITY>, |
| <8 NRF_DEFAULT_IRQ_PRIORITY>, |
| <9 NRF_DEFAULT_IRQ_PRIORITY>, |
| <10 NRF_DEFAULT_IRQ_PRIORITY>, |
| <11 NRF_DEFAULT_IRQ_PRIORITY>, |
| <12 NRF_DEFAULT_IRQ_PRIORITY>, |
| <13 NRF_DEFAULT_IRQ_PRIORITY>, |
| <14 NRF_DEFAULT_IRQ_PRIORITY>, |
| <15 NRF_DEFAULT_IRQ_PRIORITY>; |
| #mbox-cells = <1>; |
| nordic,tasks = <16>; |
| nordic,tasks-mask = <0xfffffff0>; |
| }; |
| }; |
| |
| cpuflpr: cpu@e { |
| compatible = "nordic,vpr"; |
| reg = <14>; |
| device_type = "cpu"; |
| clock-frequency = <DT_FREQ_M(320)>; |
| riscv,isa = "rv32emc"; |
| nordic,bus-width = <64>; |
| |
| cpuflpr_vevif_rx: mailbox { |
| compatible = "nordic,nrf-vevif-task-rx"; |
| status = "disabled"; |
| interrupt-parent = <&cpuflpr_clic>; |
| interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, |
| <1 NRF_DEFAULT_IRQ_PRIORITY>, |
| <2 NRF_DEFAULT_IRQ_PRIORITY>, |
| <3 NRF_DEFAULT_IRQ_PRIORITY>, |
| <4 NRF_DEFAULT_IRQ_PRIORITY>, |
| <5 NRF_DEFAULT_IRQ_PRIORITY>, |
| <6 NRF_DEFAULT_IRQ_PRIORITY>, |
| <7 NRF_DEFAULT_IRQ_PRIORITY>, |
| <8 NRF_DEFAULT_IRQ_PRIORITY>, |
| <9 NRF_DEFAULT_IRQ_PRIORITY>, |
| <10 NRF_DEFAULT_IRQ_PRIORITY>, |
| <11 NRF_DEFAULT_IRQ_PRIORITY>, |
| <12 NRF_DEFAULT_IRQ_PRIORITY>, |
| <13 NRF_DEFAULT_IRQ_PRIORITY>, |
| <14 NRF_DEFAULT_IRQ_PRIORITY>, |
| <15 NRF_DEFAULT_IRQ_PRIORITY>, |
| <16 NRF_DEFAULT_IRQ_PRIORITY>, |
| <17 NRF_DEFAULT_IRQ_PRIORITY>, |
| <18 NRF_DEFAULT_IRQ_PRIORITY>, |
| <19 NRF_DEFAULT_IRQ_PRIORITY>, |
| <20 NRF_DEFAULT_IRQ_PRIORITY>, |
| <21 NRF_DEFAULT_IRQ_PRIORITY>, |
| <22 NRF_DEFAULT_IRQ_PRIORITY>, |
| <23 NRF_DEFAULT_IRQ_PRIORITY>, |
| <24 NRF_DEFAULT_IRQ_PRIORITY>, |
| <25 NRF_DEFAULT_IRQ_PRIORITY>, |
| <26 NRF_DEFAULT_IRQ_PRIORITY>, |
| <27 NRF_DEFAULT_IRQ_PRIORITY>, |
| <28 NRF_DEFAULT_IRQ_PRIORITY>, |
| <29 NRF_DEFAULT_IRQ_PRIORITY>, |
| <30 NRF_DEFAULT_IRQ_PRIORITY>, |
| <31 NRF_DEFAULT_IRQ_PRIORITY>; |
| #mbox-cells = <1>; |
| nordic,tasks = <32>; |
| nordic,tasks-mask = <0xffff0000>; |
| }; |
| }; |
| |
| power-states { |
| idle: idle { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| min-residency-us = <100000>; |
| }; |
| |
| s2ram: s2ram { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-ram"; |
| min-residency-us = <800000>; |
| }; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| suit_storage_partition: memory@e1ed000 { |
| reg = <0xe1ed000 DT_SIZE_K(20)>; |
| }; |
| }; |
| |
| clocks { |
| hfxo: hfxo { |
| compatible = "nordic,nrf54h-hfxo"; |
| status = "disabled"; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_M(32)>; |
| }; |
| |
| lfxo: lfxo { |
| compatible = "nordic,nrf54h-lfxo"; |
| status = "disabled"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| |
| fll16m: fll16m { |
| compatible = "nordic,nrf-fll16m"; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_M(16)>; |
| open-loop-accuracy-ppm = <20000>; |
| closed-loop-base-accuracy-ppm = <5000>; |
| clocks = <&hfxo>, <&lfxo>; |
| clock-names = "hfxo", "lfxo"; |
| }; |
| |
| hsfll120: hsfll120 { |
| compatible = "fixed-clock"; |
| clocks = <&fll16m>; |
| #clock-cells = <0>; |
| clock-frequency = <DT_FREQ_M(320)>; |
| }; |
| |
| lfclk: lfclk { |
| compatible = "nordic,nrf-lfclk"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| status = "okay"; |
| lfrc-accuracy-ppm = <500>; |
| lflprc-accuracy-ppm = <1000>; |
| clocks = <&hfxo>, <&lfxo>; |
| clock-names = "hfxo", "lfxo"; |
| }; |
| }; |
| |
| gpd: global-power-domain { |
| compatible = "nordic,nrf-gpd"; |
| #power-domain-cells = <1>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mram1x: mram@e000000 { |
| compatible = "nordic,mram"; |
| reg = <0xe000000 DT_SIZE_K(2048)>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| erase-block-size = <4096>; |
| write-block-size = <16>; |
| }; |
| |
| cpuapp_uicr: uicr@fff8000 { |
| compatible = "nordic,nrf-uicr-v2"; |
| reg = <0xfff8000 DT_SIZE_K(2)>; |
| domain = <2>; |
| }; |
| |
| cpurad_uicr: uicr@fffa000 { |
| compatible = "nordic,nrf-uicr-v2"; |
| reg = <0xfffa000 DT_SIZE_K(2)>; |
| domain = <3>; |
| }; |
| |
| ficr: ficr@fffe000 { |
| compatible = "nordic,nrf-ficr"; |
| reg = <0xfffe000 DT_SIZE_K(2)>; |
| #nordic,ficr-cells = <1>; |
| }; |
| |
| cpuapp_ram0: sram@22000000 { |
| compatible = "mmio-sram"; |
| reg = <0x22000000 DT_SIZE_K(32)>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x22000000 0x8000>; |
| }; |
| |
| cpurad_ram0: sram@23000000 { |
| compatible = "mmio-sram"; |
| reg = <0x23000000 DT_SIZE_K(192)>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x23000000 0x30000>; |
| }; |
| |
| cpuapp_peripherals: peripheral@52000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x52000000 0x1000000>; |
| |
| cpuapp_hsfll: clock@d000 { |
| compatible = "nordic,nrf-hsfll"; |
| #clock-cells = <0>; |
| reg = <0xd000 0x1000>; |
| clocks = <&fll16m>; |
| clock-frequency = <DT_FREQ_M(320)>; |
| nordic,ficrs = |
| <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, |
| <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, |
| <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; |
| nordic,ficr-names = "vsup", "coarse", "fine"; |
| }; |
| |
| cpuapp_ipct: ipct@13000 { |
| compatible = "nordic,nrf-ipct-local"; |
| reg = <0x13000 0x1000>; |
| status = "disabled"; |
| channels = <4>; |
| interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, |
| <65 NRF_DEFAULT_IRQ_PRIORITY>; |
| }; |
| |
| cpuapp_wdt010: watchdog@14000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x14000 0x1000>; |
| status = "disabled"; |
| interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| }; |
| |
| cpuapp_wdt011: watchdog@15000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x15000 0x1000>; |
| status = "disabled"; |
| interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| }; |
| |
| cpuapp_resetinfo: resetinfo@1e000 { |
| compatible = "nordic,nrf-resetinfo"; |
| reg = <0x1e000 0x1000>; |
| }; |
| |
| cpuapp_ieee802154: ieee802154 { |
| compatible = "nordic,nrf-ieee802154"; |
| status = "disabled"; |
| }; |
| }; |
| |
| cpurad_peripherals: peripheral@53000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x53000000 0x1000000>; |
| |
| cpurad_hsfll: clock@d000 { |
| compatible = "nordic,nrf-hsfll"; |
| #clock-cells = <0>; |
| reg = <0xd000 0x1000>; |
| clocks = <&fll16m>; |
| clock-frequency = <DT_FREQ_M(256)>; |
| nordic,ficrs = |
| <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, |
| <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, |
| <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; |
| nordic,ficr-names = "vsup", "coarse", "fine"; |
| }; |
| |
| cpurad_wdt010: watchdog@13000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x13000 0x1000>; |
| status = "disabled"; |
| interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| }; |
| |
| cpurad_wdt011: watchdog@14000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x14000 0x1000>; |
| status = "disabled"; |
| interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| }; |
| |
| cpurad_resetinfo: resetinfo@1e000 { |
| compatible = "nordic,nrf-resetinfo"; |
| reg = <0x1e000 0x1000>; |
| }; |
| |
| dppic020: dppic@22000 { |
| compatible = "nordic,nrf-dppic-local"; |
| reg = <0x22000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| cpurad_ipct: ipct@24000 { |
| compatible = "nordic,nrf-ipct-local"; |
| reg = <0x24000 0x1000>; |
| status = "disabled"; |
| channels = <8>; |
| interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, |
| <65 NRF_DEFAULT_IRQ_PRIORITY>; |
| }; |
| |
| egu020: egu@25000 { |
| compatible = "nordic,nrf-egu"; |
| reg = <0x25000 0x1000>; |
| status = "disabled"; |
| interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; |
| }; |
| |
| timer020: timer@28000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x28000 0x1000>; |
| status = "disabled"; |
| cc-num = <8>; |
| interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| max-bit-width = <32>; |
| max-frequency = <DT_FREQ_M(32)>; |
| prescaler = <0>; |
| }; |
| |
| timer021: timer@29000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x29000 0x1000>; |
| status = "disabled"; |
| cc-num = <8>; |
| interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| max-bit-width = <32>; |
| max-frequency = <DT_FREQ_M(32)>; |
| prescaler = <0>; |
| }; |
| |
| timer022: timer@2a000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x2a000 0x1000>; |
| status = "disabled"; |
| cc-num = <8>; |
| interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| max-bit-width = <32>; |
| max-frequency = <DT_FREQ_M(32)>; |
| prescaler = <0>; |
| }; |
| |
| rtc: rtc@2b000 { |
| compatible = "nordic,nrf-rtc"; |
| reg = <0x2b000 0x1000>; |
| status = "disabled"; |
| cc-num = <4>; |
| clock-frequency = <32768>; |
| interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| prescaler = <1>; |
| }; |
| |
| radio: radio@2c000 { |
| compatible = "nordic,nrf-radio"; |
| reg = <0x2c000 0x1000>; |
| status = "disabled"; |
| ble-2mbps-supported; |
| ble-coded-phy-supported; |
| cs-supported; |
| dfe-supported; |
| ieee802154-supported; |
| interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&hfxo>; |
| |
| cpurad_ieee802154: ieee802154 { |
| compatible = "nordic,nrf-ieee802154"; |
| status = "disabled"; |
| }; |
| }; |
| |
| ccm030: ccm@3a000 { |
| compatible = "nordic,nrf-ccm"; |
| reg = <0x3a000 0x1000>; |
| interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| ecb030: ecb@3b000 { |
| compatible = "nordic,nrf-ecb"; |
| reg = <0x3b000 0x1000>; |
| interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| ccm031: ccm@3c000 { |
| compatible = "nordic,nrf-ccm"; |
| reg = <0x3c000 0x1000>; |
| interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| ecb031: ecb@3d000 { |
| compatible = "nordic,nrf-ecb"; |
| reg = <0x3d000 0x1000>; |
| status = "disabled"; |
| interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; |
| }; |
| }; |
| |
| tdd_peripherals: peripheral@bf000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xbf000000 0x1000000>; |
| |
| tbm: tbm@3000 { |
| compatible = "nordic,nrf-tbm"; |
| reg = <0x3000 0x408>; |
| status = "disabled"; |
| interrupts = <127 NRF_DEFAULT_IRQ_PRIORITY>; |
| }; |
| |
| tddconf: tddconf@1000 { |
| compatible = "nordic,nrf-tddconf"; |
| reg = <0x1000 0x10>; |
| status = "disabled"; |
| }; |
| }; |
| |
| global_peripherals: peripheral@5f000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x5f000000 0x1000000>; |
| |
| usbhs: usbhs@86000 { |
| compatible = "nordic,nrf-usbhs", "snps,dwc2"; |
| reg = <0x86000 0x1000>, <0x2f700000 0x40000>; |
| reg-names = "wrapper", "core"; |
| interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| num-in-eps = <8>; |
| num-out-eps = <10>; |
| ghwcfg1 = <0xaa555000>; |
| ghwcfg2 = <0x22abfc72>; |
| ghwcfg4 = <0x1e10aa60>; |
| status = "disabled"; |
| }; |
| |
| exmif: spi@95000 { |
| compatible = "nordic,nrf-exmif"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x95000 0x500 0x95500 0xb00>; |
| reg-names = "wrapper", "core"; |
| interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| clock-frequency = <DT_FREQ_M(400)>; |
| fifo-depth = <32>; |
| max-xfer-size = <16>; |
| status = "disabled"; |
| }; |
| |
| cpusec_bellboard: mailbox@99000 { |
| reg = <0x99000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| #mbox-cells = <1>; |
| }; |
| |
| cpuapp_bellboard: mailbox@9a000 { |
| reg = <0x9a000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| #mbox-cells = <1>; |
| }; |
| |
| cpurad_bellboard: mailbox@9b000 { |
| reg = <0x9b000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; |
| #mbox-cells = <1>; |
| }; |
| |
| canpll: clock-controller@8c2000{ |
| compatible = "nordic,nrf-auxpll"; |
| reg = <0x8c2000 0x1000>; |
| interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&hfxo>; |
| #clock-cells = <0>; |
| nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>; |
| nordic,frequency = <0>; |
| nordic,out-div = <2>; |
| nordic,out-drive = <0>; |
| nordic,current-tune = <6>; |
| nordic,sdm-disable; |
| nordic,range = "high"; |
| status = "disabled"; |
| }; |
| |
| cpusys_vevif_tx: mailbox@8c8000 { |
| compatible = "nordic,nrf-vevif-task-tx"; |
| reg = <0x8c8000 0x1000>; |
| status = "disabled"; |
| #mbox-cells = <1>; |
| nordic,tasks = <32>; |
| nordic,tasks-mask = <0xfffff0ff>; |
| }; |
| |
| ipct120: ipct@8d1000 { |
| compatible = "nordic,nrf-ipct-global"; |
| reg = <0x8d1000 0x1000>; |
| status = "disabled"; |
| channels = <8>; |
| global-domain-id = <12>; |
| }; |
| |
| cpuflpr_vpr: vpr@8d4000 { |
| compatible = "nordic,nrf-vpr-coprocessor"; |
| reg = <0x8d4000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8d4000 0x1000>; |
| |
| cpuflpr_vevif_tx: mailbox@0 { |
| compatible = "nordic,nrf-vevif-task-tx"; |
| reg = <0x0 0x1000>; |
| status = "disabled"; |
| #mbox-cells = <1>; |
| nordic,tasks = <32>; |
| nordic,tasks-mask = <0xffff0000>; |
| }; |
| }; |
| |
| can120: can@8d8000 { |
| compatible = "nordic,nrf-can"; |
| reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>; |
| reg-names = "wrapper", "m_can", "message_ram"; |
| interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&canpll>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; |
| status = "disabled"; |
| }; |
| |
| dppic120: dppic@8e1000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x8e1000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| }; |
| |
| timer120: timer@8e2000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x8e2000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| max-bit-width = <32>; |
| max-frequency = <DT_FREQ_M(320)>; |
| prescaler = <0>; |
| }; |
| |
| timer121: timer@8e3000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x8e3000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| max-bit-width = <32>; |
| max-frequency = <DT_FREQ_M(320)>; |
| prescaler = <0>; |
| }; |
| |
| pwm120: pwm@8e4000 { |
| compatible = "nordic,nrf-pwm"; |
| reg = <0x8e4000 0x1000>; |
| status = "disabled"; |
| interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| #pwm-cells = <3>; |
| }; |
| |
| spi120: spi@8e6000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x8e6000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; |
| max-frequency = <DT_FREQ_M(32)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart120: uart@8e6000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x8e6000 0x1000>; |
| status = "disabled"; |
| interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&hsfll120>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| spi121: spi@8e7000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x8e7000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; |
| max-frequency = <DT_FREQ_M(32)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| cpuppr_vpr: vpr@908000 { |
| compatible = "nordic,nrf-vpr-coprocessor"; |
| reg = <0x908000 0x1000>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x908000 0x1000>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| |
| cpuppr_vevif_tx: mailbox@0 { |
| compatible = "nordic,nrf-vevif-task-tx"; |
| reg = <0x0 0x1000>; |
| status = "disabled"; |
| #mbox-cells = <1>; |
| nordic,tasks = <16>; |
| nordic,tasks-mask = <0xfffffff0>; |
| }; |
| }; |
| |
| ipct130: ipct@921000 { |
| compatible = "nordic,nrf-ipct-global"; |
| reg = <0x921000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| channels = <8>; |
| global-domain-id = <13>; |
| }; |
| |
| dppic130: dppic@922000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x922000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| }; |
| |
| rtc130: rtc@928000 { |
| compatible = "nordic,nrf-rtc"; |
| reg = <0x928000 0x1000>; |
| status = "disabled"; |
| cc-num = <4>; |
| clock-frequency = <32768>; |
| interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| clocks = <&lfclk>; |
| prescaler = <1>; |
| }; |
| |
| rtc131: rtc@929000 { |
| compatible = "nordic,nrf-rtc"; |
| reg = <0x929000 0x1000>; |
| status = "disabled"; |
| cc-num = <4>; |
| clock-frequency = <32768>; |
| interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| clocks = <&lfclk>; |
| prescaler = <1>; |
| }; |
| |
| wdt131: watchdog@92b000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x92b000 0x1000>; |
| status = "disabled"; |
| interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| }; |
| |
| wdt132: watchdog@92c000 { |
| compatible = "nordic,nrf-wdt"; |
| reg = <0x92c000 0x1000>; |
| status = "disabled"; |
| interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&lfclk>; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| }; |
| |
| egu130: egu@92d000 { |
| compatible = "nordic,nrf-egu"; |
| reg = <0x92d000 0x1000>; |
| status = "disabled"; |
| interrupts = <301 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| }; |
| |
| gpiote130: gpiote@934000 { |
| compatible = "nordic,nrf-gpiote"; |
| reg = <0x934000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| instance = <130>; |
| }; |
| |
| gpio0: gpio@938000 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x938000 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| gpiote-instance = <&gpiote130>; |
| ngpios = <12>; |
| port = <0>; |
| }; |
| |
| gpio1: gpio@938200 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x938200 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| gpiote-instance = <&gpiote130>; |
| ngpios = <12>; |
| port = <1>; |
| }; |
| |
| gpio2: gpio@938400 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x938400 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| gpiote-instance = <&gpiote130>; |
| ngpios = <12>; |
| port = <2>; |
| }; |
| |
| gpio6: gpio@938c00 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x938c00 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>, |
| <&gpd NRF_GPD_FAST_ACTIVE1>; |
| power-domain-names = "peripheral", "pad"; |
| ngpios = <14>; |
| port = <6>; |
| }; |
| |
| gpio7: gpio@938e00 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x938e00 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>, |
| <&gpd NRF_GPD_FAST_ACTIVE1>; |
| power-domain-names = "peripheral", "pad"; |
| ngpios = <8>; |
| port = <7>; |
| }; |
| |
| gpio9: gpio@939200 { |
| compatible = "nordic,nrf-gpio"; |
| reg = <0x939200 0x200>; |
| status = "disabled"; |
| #gpio-cells = <2>; |
| gpio-controller; |
| power-domains = <&gpd NRF_GPD_SLOW_MAIN>; |
| gpiote-instance = <&gpiote130>; |
| ngpios = <6>; |
| port = <9>; |
| }; |
| |
| dppic131: dppic@981000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x981000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| adc: adc@982000 { |
| compatible = "nordic,nrf-saadc"; |
| reg = <0x982000 0x1000>; |
| interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| comp: comparator@983000 { |
| /* |
| * Use compatible "nordic,nrf-comp" to configure as COMP |
| * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP |
| */ |
| compatible = "nordic,nrf-comp"; |
| reg = <0x983000 0x1000>; |
| status = "disabled"; |
| interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| temp: temperature-sensor@984000 { |
| compatible = "nordic,nrf-temp"; |
| reg = <0x984000 0x1000>; |
| interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| nfct: nfct@985000 { |
| compatible = "nordic,nrf-nfct"; |
| reg = <0x985000 0x1000>; |
| status = "disabled"; |
| interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| dppic132: dppic@991000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x991000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| qdec130: qdec@994000 { |
| compatible = "nordic,nrf-qdec"; |
| reg = <0x994000 0x1000>; |
| status = "disabled"; |
| interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| qdec131: qdec@995000 { |
| compatible = "nordic,nrf-qdec"; |
| reg = <0x995000 0x1000>; |
| status = "disabled"; |
| interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| grtc: grtc@99c000 { |
| compatible = "nordic,nrf-grtc"; |
| reg = <0x99c000 0x1000>; |
| status = "disabled"; |
| cc-num = <16>; |
| /* GRTC uses both LFCLK and FLL16M, but its accuracy and |
| * precision are inherited from LFCLK. that's why this |
| * one is linked here. |
| */ |
| clocks = <&lfclk>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| dppic133: dppic@9a1000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x9a1000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| timer130: timer@9a2000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9a2000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| timer131: timer@9a3000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9a3000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| pwm130: pwm@9a4000 { |
| compatible = "nordic,nrf-pwm"; |
| reg = <0x9a4000 0x1000>; |
| status = "disabled"; |
| interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| #pwm-cells = <3>; |
| }; |
| |
| i2c130: i2c@9a5000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9a5000 0x1000>; |
| status = "disabled"; |
| interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi130: spi@9a5000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9a5000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart130: uart@9a5000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9a5000 0x1000>; |
| status = "disabled"; |
| interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| i2c131: i2c@9a6000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9a6000 0x1000>; |
| status = "disabled"; |
| interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi131: spi@9a6000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9a6000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart131: uart@9a6000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9a6000 0x1000>; |
| status = "disabled"; |
| interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| dppic134: dppic@9b1000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x9b1000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| timer132: timer@9b2000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9b2000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| timer133: timer@9b3000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9b3000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| pwm131: pwm@9b4000 { |
| compatible = "nordic,nrf-pwm"; |
| reg = <0x9b4000 0x1000>; |
| status = "disabled"; |
| interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| #pwm-cells = <3>; |
| }; |
| |
| i2c132: i2c@9b5000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9b5000 0x1000>; |
| status = "disabled"; |
| interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi132: spi@9b5000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9b5000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart132: uart@9b5000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9b5000 0x1000>; |
| status = "disabled"; |
| interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| i2c133: i2c@9b6000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9b6000 0x1000>; |
| status = "disabled"; |
| interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi133: spi@9b6000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9b6000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart133: uart@9b6000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9b6000 0x1000>; |
| status = "disabled"; |
| interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| dppic135: dppic@9c1000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x9c1000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| timer134: timer@9c2000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9c2000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| timer135: timer@9c3000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9c3000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| pwm132: pwm@9c4000 { |
| compatible = "nordic,nrf-pwm"; |
| reg = <0x9c4000 0x1000>; |
| status = "disabled"; |
| interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| #pwm-cells = <3>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| i2c134: i2c@9c5000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9c5000 0x1000>; |
| status = "disabled"; |
| interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi134: spi@9c5000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9c5000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart134: uart@9c5000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9c5000 0x1000>; |
| status = "disabled"; |
| interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| i2c135: i2c@9c6000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9c6000 0x1000>; |
| status = "disabled"; |
| interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi135: spi@9c6000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9c6000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart135: uart@9c6000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9c6000 0x1000>; |
| status = "disabled"; |
| interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| dppic136: dppic@9d1000 { |
| compatible = "nordic,nrf-dppic-global"; |
| reg = <0x9d1000 0x1000>; |
| status = "disabled"; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| timer136: timer@9d2000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9d2000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| timer137: timer@9d3000 { |
| compatible = "nordic,nrf-timer"; |
| reg = <0x9d3000 0x1000>; |
| status = "disabled"; |
| cc-num = <6>; |
| interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-bit-width = <32>; |
| prescaler = <0>; |
| }; |
| |
| pwm133: pwm@9d4000 { |
| compatible = "nordic,nrf-pwm"; |
| reg = <0x9d4000 0x1000>; |
| status = "disabled"; |
| interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| #pwm-cells = <3>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| }; |
| |
| i2c136: i2c@9d5000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9d5000 0x1000>; |
| status = "disabled"; |
| interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi136: spi@9d5000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9d5000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart136: uart@9d5000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9d5000 0x1000>; |
| status = "disabled"; |
| interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| |
| i2c137: i2c@9d6000 { |
| compatible = "nordic,nrf-twim"; |
| reg = <0x9d6000 0x1000>; |
| status = "disabled"; |
| interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| easydma-maxcnt-bits = <15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, |
| <NRF_FUN_TWIM_SCL>; |
| zephyr,pm-device-runtime-auto; |
| }; |
| |
| spi137: spi@9d6000 { |
| compatible = "nordic,nrf-spim"; |
| reg = <0x9d6000 0x1000>; |
| status = "disabled"; |
| easydma-maxcnt-bits = <15>; |
| interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| max-frequency = <DT_FREQ_M(8)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rx-delay-supported; |
| rx-delay = <1>; |
| nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, |
| <NRF_FUN_SPIM_SCK>, |
| <NRF_FUN_SPIS_MISO>, |
| <NRF_FUN_SPIS_SCK>; |
| }; |
| |
| uart137: uart@9d6000 { |
| compatible = "nordic,nrf-uarte"; |
| reg = <0x9d6000 0x1000>; |
| status = "disabled"; |
| interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; |
| clocks = <&fll16m>; |
| power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; |
| nordic,clockpin-enable = <NRF_FUN_UART_TX>; |
| endtx-stoptx-supported; |
| frame-timeout-supported; |
| }; |
| }; |
| }; |
| |
| cpuapp_ppb: cpuapp-ppb-bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpuapp_systick: timer@e000e010 { |
| compatible = "arm,armv8m-systick"; |
| reg = <0xe000e010 0x10>; |
| status = "disabled"; |
| }; |
| |
| cpuapp_nvic: interrupt-controller@e000e100 { |
| compatible = "arm,v8m-nvic"; |
| reg = <0xe000e100 0xc00>; |
| arm,num-irq-priority-bits = <3>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #address-cells = <1>; |
| }; |
| }; |
| |
| cpurad_ppb: cpurad-ppb-bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpurad_systick: timer@e000e010 { |
| compatible = "arm,armv8m-systick"; |
| reg = <0xe000e010 0x10>; |
| status = "disabled"; |
| }; |
| |
| cpurad_nvic: interrupt-controller@e000e100 { |
| compatible = "arm,v8m-nvic"; |
| reg = <0xe000e100 0xc00>; |
| arm,num-irq-priority-bits = <3>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #address-cells = <1>; |
| }; |
| }; |
| |
| cpuppr_private: cpuppr-private-bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpuppr_clic: interrupt-controller@f0000000 { |
| compatible = "nordic,nrf-clic"; |
| reg = <0xf0000000 0x3000>; |
| status = "disabled"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #address-cells = <1>; |
| }; |
| }; |
| |
| cpuflpr_private: cpuflpr-private-bus { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpuflpr_clic: interrupt-controller@f0000000 { |
| compatible = "nordic,nrf-clic"; |
| reg = <0xf0000000 0x3000>; |
| status = "disabled"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #address-cells = <1>; |
| }; |
| }; |
| |
| temp_nrfs: temp { |
| compatible = "nordic,nrf-temp-nrfs"; |
| status = "disabled"; |
| }; |
| }; |
