include: dt-bindings: stm32 clocks: Use "domain" wording when possible
Update stm32 clocks include files to use "domain" when possible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/include/zephyr/dt-bindings/clock/stm32f0_clock.h b/include/zephyr/dt-bindings/clock/stm32f0_clock.h
index 5c4563d..f31bfda 100644
--- a/include/zephyr/dt-bindings/clock/stm32f0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f0_clock.h
@@ -14,7 +14,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
-/** Peripheral clock sources */
+/** Domain clocks */
/** Fixed clocks */
#define STM32_SRC_HSI 0x001
@@ -59,7 +59,7 @@
/** @brief RCC_CFGRx register offset */
#define CFGR3_REG 0x30
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CFGR3 devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/include/zephyr/dt-bindings/clock/stm32f1_clock.h
index 5734865..823937d 100644
--- a/include/zephyr/dt-bindings/clock/stm32f1_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f1_clock.h
@@ -6,7 +6,7 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
-/** Peripheral clock sources */
+/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x014
diff --git a/include/zephyr/dt-bindings/clock/stm32f3_clock.h b/include/zephyr/dt-bindings/clock/stm32f3_clock.h
index a589e6f..a4d5b66 100644
--- a/include/zephyr/dt-bindings/clock/stm32f3_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f3_clock.h
@@ -14,7 +14,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0316, §9.4.13 Clock configuration register (RCC_CFGR3) */
/** Fixed clocks */
@@ -60,7 +60,7 @@
/** @brief RCC_CFGRx register offset */
#define CFGR3_REG 0x30
-/** @brief Device clk sources selection helpers) */
+/** @brief Device domain clocks selection helpers) */
/** CFGR3 devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/include/zephyr/dt-bindings/clock/stm32f4_clock.h
index f0f2299..efcc1f3 100644
--- a/include/zephyr/dt-bindings/clock/stm32f4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f4_clock.h
@@ -6,7 +6,7 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_
-/** Peripheral clock sources */
+/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x030
@@ -19,7 +19,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */
/** PLL clock outputs */
diff --git a/include/zephyr/dt-bindings/clock/stm32g0_clock.h b/include/zephyr/dt-bindings/clock/stm32g0_clock.h
index 96ab0c2..bce36a8 100644
--- a/include/zephyr/dt-bindings/clock/stm32g0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32g0_clock.h
@@ -15,7 +15,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
/** Fixed clocks */
@@ -66,7 +66,7 @@
#define CCIPR_REG 0x54
#define CCIPR2_REG 0x58
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32g4_clock.h b/include/zephyr/dt-bindings/clock/stm32g4_clock.h
index c23e2c0..54bba2c 100644
--- a/include/zephyr/dt-bindings/clock/stm32g4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32g4_clock.h
@@ -17,7 +17,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0440, § Clock configuration register (RCC_CCIPRx) */
/** Fixed clocks */
@@ -70,7 +70,7 @@
#define CCIPR_REG 0x88
#define CCIPR2_REG 0x9C
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/include/zephyr/dt-bindings/clock/stm32h7_clock.h
index dd50bac..52a2785 100644
--- a/include/zephyr/dt-bindings/clock/stm32h7_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32h7_clock.h
@@ -6,7 +6,7 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0468, Table 56 Kernel clock dictribution summary */
@@ -92,14 +92,14 @@
#define D2CCIP2R_REG 0x54
#define D3CCIPR_REG 0x58
-/** @brief Device clk sources selection helpers (RM0399.pdf) */
+/** @brief Device domain clocks selection helpers (RM0399.pdf) */
/** D1CCIPR devices */
#define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG)
#define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
#define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG)
#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG)
#define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG)
-/* device clk sources selection helpers (RM0468.pdf) */
+/* Device domain clocks selection helpers (RM0468.pdf) */
#define OSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
/** D2CCIP1R devices */
#define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32l0_clock.h b/include/zephyr/dt-bindings/clock/stm32l0_clock.h
index 5ce3e24..149ee05 100644
--- a/include/zephyr/dt-bindings/clock/stm32l0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l0_clock.h
@@ -15,7 +15,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0367, §7.3.20 Clock configuration register (RCC_CCIPR) */
/** Fixed clocks */
@@ -60,7 +60,7 @@
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x4C
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32l1_clock.h b/include/zephyr/dt-bindings/clock/stm32l1_clock.h
index 7b6dcb7..90bf5d4 100644
--- a/include/zephyr/dt-bindings/clock/stm32l1_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l1_clock.h
@@ -14,7 +14,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0038.pdf, §6.3.14 Control/status register (RCC_CSR) */
/** Fixed clocks */
diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
index 4228d6f..d078d04 100644
--- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
@@ -17,7 +17,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0351/RM0432/RM0438, § Clock configuration register (RCC_CCIPRx) */
/** Fixed clocks */
@@ -69,7 +69,7 @@
#define CCIPR_REG 0x88
#define CCIPR2_REG 0x9C
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/include/zephyr/dt-bindings/clock/stm32u5_clock.h
index c1429b8..f47c604 100644
--- a/include/zephyr/dt-bindings/clock/stm32u5_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32u5_clock.h
@@ -6,7 +6,7 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0468, Table 56 Kernel clock distribution summary */
@@ -80,7 +80,7 @@
#define CCIPR2_REG 0xE4
#define CCIPR3_REG 0xE8
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR1 devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32wb_clock.h b/include/zephyr/dt-bindings/clock/stm32wb_clock.h
index ba4e488..b31edec 100644
--- a/include/zephyr/dt-bindings/clock/stm32wb_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wb_clock.h
@@ -17,7 +17,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0434, § Clock configuration register (RCC_CCIPRx) */
/** Fixed clocks */
@@ -68,7 +68,7 @@
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x88
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
diff --git a/include/zephyr/dt-bindings/clock/stm32wl_clock.h b/include/zephyr/dt-bindings/clock/stm32wl_clock.h
index 7076bbd..ee042f5 100644
--- a/include/zephyr/dt-bindings/clock/stm32wl_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wl_clock.h
@@ -18,7 +18,7 @@
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
-/** Peripheral clock sources */
+/** Domain clocks */
/* RM0461, §6.4.29 Clock configuration register (RCC_CFGR3) */
/** Fixed clocks */
@@ -67,7 +67,7 @@
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x88
-/** @brief Device clk sources selection helpers */
+/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
