| /* |
| * Copyright (c) 2023 Google LLC. |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /dts-v1/; |
| #include <mem.h> |
| #include <xtensa/xtensa.dtsi> |
| |
| / { |
| model = "nxp_adsp_rt595"; |
| compatible = "nxp"; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "cdns,tensilica-xtensa-lx6"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| device_type = "memory"; |
| compatible = "mmio-sram"; |
| /* Reserve first 512kB of shared memory for ADSP. */ |
| reg = <0x0 DT_SIZE_K(512)>; |
| /* Reset section must always be at 0 and at least 1kB. */ |
| adsp_reset: memory@0 { |
| reg = <0x0 DT_SIZE_K(1)>; |
| }; |
| /* Code and data sections can be moved around and resized if needed. */ |
| adsp_text: memory@400 { |
| reg = <0x400 DT_SIZE_K(255)>; |
| }; |
| /* On RT595 ADSP shared RAM is mapped at offset 0 on the code bus and at |
| * offset 0x800000 on the data bus. |
| */ |
| adsp_data: memory@840000 { |
| reg = <0x840000 DT_SIZE_K(256)>; |
| }; |
| }; |
| |
| chosen { |
| zephyr,sram = &adsp_data; |
| }; |
| }; |