| /* |
| * Copyright (c) 2017-2021, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ |
| #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ |
| |
| #define IMX_CCM_CORESYS_CLK 0 |
| #define IMX_CCM_PLATFORM_CLK 1 |
| #define IMX_CCM_BUS_CLK 2 |
| #define IMX_CCM_LPUART_CLK 3 |
| #define IMX_CCM_LPI2C_CLK 4 |
| #define IMX_CCM_LPSPI_CLK 5 |
| #define IMX_CCM_USDHC1_CLK 6 |
| #define IMX_CCM_USDHC2_CLK 7 |
| #define IMX_CCM_EDMA_CLK 8 |
| #define IMX_CCM_UART1_CLK 9 |
| #define IMX_CCM_CAN_CLK 10 |
| #define IMX_CCM_GPT_CLK 11 |
| #define IMX_CCM_SAI1_CLK 12 |
| #define IMX_CCM_SAI2_CLK 13 |
| #define IMX_CCM_SAI3_CLK 14 |
| #define IMX_CCM_PWM_CLK 15 |
| #define IMX_CCM_UART2_CLK 16 |
| #define IMX_CCM_UART3_CLK 17 |
| #define IMX_CCM_UART4_CLK 18 |
| |
| #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ |
