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| .. espressif-soc-esp32s3-features |
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| ESP32-S3 Features |
| ================= |
| |
| ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi |
| and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor |
| (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, |
| RF module, and numerous peripherals. |
| |
| ESP32-S3 SoC includes the following features: |
| |
| - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz |
| - Additional vector instructions support for AI acceleration |
| - 512KB of SRAM |
| - 384KB of ROM |
| - Wi-Fi 802.11b/g/n |
| - Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate |
| |
| Digital interfaces: |
| |
| - 45 programmable GPIOs |
| - 4x SPI |
| - 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 |
| - 1x DVP 8-bit ~16-bit camera interface |
| - 3x UART |
| - 2x I2C |
| - 2x I2S |
| - 1x RMT (TX/RX) |
| - 1x pulse counter |
| - LED PWM controller, up to 8 channels |
| - 1x full-speed USB OTG |
| - 1x USB Serial/JTAG controller |
| - 2x MCPWM |
| - 1x SDIO host controller with 2 slots |
| - General DMA controller (GDMA), with 5 transmit channels and 5 receive channels |
| - 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) |
| - Addressable RGB LED, driven by GPIO38. |
| |
| Analog interfaces: |
| |
| - 2x 12-bit SAR ADCs, up to 20 channels |
| - 1x temperature sensor |
| - 14x touch sensing IOs |
| |
| Timers: |
| |
| - 4x 54-bit general-purpose timers |
| - 1x 52-bit system timer |
| - 3x watchdog timers |
| |
| Low Power: |
| |
| - Power Management Unit with five power modes |
| - Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM |
| |
| Security: |
| |
| - Secure boot |
| - Flash encryption |
| - 4-Kbit OTP, up to 1792 bits for users |
| - Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) |
| |
| Asymmetric Multiprocessing (AMP) |
| ================================ |
| |
| Boards featuring the ESP32-S3 SoC allows 2 different applications to be executed. Due to its dual-core |
| architecture, each core can be enabled to execute customized tasks in stand-alone mode |
| and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:`ipc` folder as code reference. |
| |
| For more information, check the `ESP32-S3 Datasheet`_ or the `ESP32-S3 Technical Reference Manual`_. |
| |
| .. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf |
| .. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf |
