arch: riscv: custom: add T-Head Xuantie CSR support
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ba6dfc9..2a4e190 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -526,7 +526,6 @@
to handle FP exceptions.
rsource "Kconfig.isa"
-rsource "core/Kconfig"
rsource "custom/Kconfig"
diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt
index b2bf26d..abd9d45 100644
--- a/arch/riscv/core/CMakeLists.txt
+++ b/arch/riscv/core/CMakeLists.txt
@@ -42,5 +42,3 @@
zephyr_linker_sources(RODATA swi_tables.ld)
endif()
endif()
-
-add_subdirectory_ifdef(CONFIG_XUANTIE xuantie)
diff --git a/arch/riscv/core/Kconfig b/arch/riscv/core/Kconfig
deleted file mode 100644
index c3bfe41..0000000
--- a/arch/riscv/core/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-# RISC-V cores configuration options
-
-# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
-# SPDX-License-Identifier: Apache-2.0
-
-config XUANTIE
- bool
- help
- This option signifies the use of a CPU of the XuanTie RISC-V family
-
-rsource "xuantie/Kconfig"
diff --git a/arch/riscv/core/xuantie/CMakeLists.txt b/arch/riscv/core/xuantie/CMakeLists.txt
deleted file mode 100644
index 38a4c40..0000000
--- a/arch/riscv/core/xuantie/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/cache.h)
-
-zephyr_library()
-
-zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO cache_xtheadcmo.c)
-zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO_E907 cache_xtheadcmo_e907.c)
diff --git a/arch/riscv/core/xuantie/Kconfig b/arch/riscv/core/xuantie/Kconfig
deleted file mode 100644
index bb0cf7b..0000000
--- a/arch/riscv/core/xuantie/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
-# SPDX-License-Identifier: Apache-2.0
-
-config XUANTIE_E907
- bool
- select XUANTIE
- select GEN_IRQ_VECTOR_TABLE
- select INCLUDE_RESET_VECTOR
- select RISCV_HAS_CLIC
- select RISCV_MACHINE_TIMER
- select RISCV_PRIVILEGED
- select RISCV_ISA_RV32I
- select RISCV_ISA_EXT_M
- select RISCV_ISA_EXT_A
- select RISCV_ISA_EXT_C
- select RISCV_ISA_EXT_ZICSR
- select RISCV_ISA_EXT_ZIFENCEI
- select RISCV_VECTORED_MODE
-
-if XUANTIE
-
-config CACHE_XTHEADCMO
- bool
- default y
- select CACHE_MANAGEMENT
- select CPU_HAS_ICACHE
- help
- This option enables cache support for XuanTie family of CPUs using the XTHeadCmo extension
-
-if CACHE_XTHEADCMO
-
-config DCACHE_LINE_SIZE
- default 32
-
-config ICACHE_LINE_SIZE
- default 32
-
-config CACHE_XTHEADCMO_E907
- bool
- default y
- depends on XUANTIE_E907
- select CPU_HAS_DCACHE
- help
- This option enables the additional XTHeadCmo cache functions for the E907 cores
-
-endif # CACHE_XTHEADCMO
-
-endif # XUANTIE
diff --git a/arch/riscv/custom/CMakeLists.txt b/arch/riscv/custom/CMakeLists.txt
index 1ef4eee..fab46a8 100644
--- a/arch/riscv/custom/CMakeLists.txt
+++ b/arch/riscv/custom/CMakeLists.txt
@@ -6,3 +6,4 @@
add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei)
add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy)
add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy)
+add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead)
diff --git a/arch/riscv/custom/Kconfig b/arch/riscv/custom/Kconfig
index 01204b6..e14abc7 100644
--- a/arch/riscv/custom/Kconfig
+++ b/arch/riscv/custom/Kconfig
@@ -6,3 +6,10 @@
rsource "andes/Kconfig"
endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
+
+if DT_HAS_XUANTIE_E907_ENABLED
+
+rsource "thead/Kconfig"
+rsource "thead/Kconfig.core"
+
+endif # DT_HAS_XUANTIE_E907_ENABLED
diff --git a/arch/riscv/custom/thead/CMakeLists.txt b/arch/riscv/custom/thead/CMakeLists.txt
new file mode 100644
index 0000000..f2774d8
--- /dev/null
+++ b/arch/riscv/custom/thead/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_THEAD_CMO cache_xtheadcmo.c)
+zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_THEAD_CMO_E907 cache_xtheadcmo_e907.c)
diff --git a/arch/riscv/custom/thead/Kconfig b/arch/riscv/custom/thead/Kconfig
new file mode 100644
index 0000000..4c1d57a
--- /dev/null
+++ b/arch/riscv/custom/thead/Kconfig
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config CPU_HAS_THEAD_CMO
+ bool
+ help
+ The Xuantie core supports XTHeadCmo extension.
+
+config RISCV_CUSTOM_CSR_THEAD_CMO
+ bool
+ depends on CPU_HAS_THEAD_CMO
+ default y if CACHE_MANAGEMENT
+ help
+ This option enables the cache operation for XuanTie family of CPUs.
+
+config RISCV_CUSTOM_CSR_THEAD_CMO_E907
+ bool
+ depends on CPU_HAS_THEAD_CMO
+ depends on DT_HAS_XUANTIE_E907_ENABLED
+ default y if CACHE_MANAGEMENT
+ help
+ This option enables the additional cache operation for XuanTie E907 cores.
diff --git a/arch/riscv/custom/thead/Kconfig.core b/arch/riscv/custom/thead/Kconfig.core
new file mode 100644
index 0000000..3550e91
--- /dev/null
+++ b/arch/riscv/custom/thead/Kconfig.core
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config CPU_XUANTIE_E907
+ bool
+ select GEN_IRQ_VECTOR_TABLE
+ select INCLUDE_RESET_VECTOR
+ select RISCV_HAS_CLIC
+ select RISCV_MACHINE_TIMER
+ select RISCV_PRIVILEGED
+ select RISCV_ISA_RV32I
+ select RISCV_ISA_EXT_M
+ select RISCV_ISA_EXT_A
+ select RISCV_ISA_EXT_C
+ select RISCV_ISA_EXT_ZICSR
+ select RISCV_ISA_EXT_ZIFENCEI
+ select RISCV_VECTORED_MODE
+ select CPU_HAS_ICACHE
+ select CPU_HAS_DCACHE
+ select CPU_HAS_THEAD_CMO
diff --git a/arch/riscv/core/xuantie/cache_xtheadcmo.c b/arch/riscv/custom/thead/cache_xtheadcmo.c
similarity index 100%
rename from arch/riscv/core/xuantie/cache_xtheadcmo.c
rename to arch/riscv/custom/thead/cache_xtheadcmo.c
diff --git a/arch/riscv/core/xuantie/cache_xtheadcmo_e907.c b/arch/riscv/custom/thead/cache_xtheadcmo_e907.c
similarity index 100%
rename from arch/riscv/core/xuantie/cache_xtheadcmo_e907.c
rename to arch/riscv/custom/thead/cache_xtheadcmo_e907.c
diff --git a/dts/bindings/cpu/xuantie,e907.yaml b/dts/bindings/cpu/xuantie,e907.yaml
new file mode 100644
index 0000000..c5dfc52
--- /dev/null
+++ b/dts/bindings/cpu/xuantie,e907.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Xuantie E907 Core CPU
+
+compatible: "xuantie,e907"
+
+include: riscv,cpus.yaml
+
+properties:
+ hardware-exec-breakpoint-count:
+ type: int
+ description: Number of hardware break points
diff --git a/dts/riscv/bflb/bl61x.dtsi b/dts/riscv/bflb/bl61x.dtsi
index 1564933..b2936b8 100644
--- a/dts/riscv/bflb/bl61x.dtsi
+++ b/dts/riscv/bflb/bl61x.dtsi
@@ -79,6 +79,8 @@
compatible = "xuantie,e907", "riscv";
reg = <0>;
riscv,isa = "rv32imafcp";
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
hardware-exec-breakpoint-count = <4>;
status = "okay";
diff --git a/soc/bflb/bl61x/Kconfig b/soc/bflb/bl61x/Kconfig
index bf31161..d13afef 100644
--- a/soc/bflb/bl61x/Kconfig
+++ b/soc/bflb/bl61x/Kconfig
@@ -15,4 +15,5 @@
select SOC_EARLY_INIT_HOOK
select SYSCON
select XIP
- select XUANTIE_E907
+ select CPU_XUANTIE_E907
+ select CACHE_MANAGEMENT
