| /* |
| * Copyright (c) 2017 Linaro Limited |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/f4/stm32f401.dtsi> |
| |
| / { |
| clocks { |
| plli2s: plli2s { |
| #clock-cells = <0>; |
| compatible = "st,stm32f411-plli2s-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| compatible = "st,stm32f411", "st,stm32f4", "simple-bus"; |
| |
| spi5: spi@40015000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 20)>; |
| interrupts = <85 5>; |
| status = "disabled"; |
| }; |
| |
| i2s1: i2s@40013000 { |
| compatible = "st,stm32-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12)>; |
| interrupts = <35 5>; |
| dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL |
| &dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2s4: i2s@40013400 { |
| compatible = "st,stm32-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 13)>; |
| interrupts = <84 5>; |
| dmas = <&dma2 1 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL |
| &dma2 0 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2s5: i2s@40015000 { |
| compatible = "st,stm32-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 20)>; |
| interrupts = <85 5>; |
| dmas = <&dma2 6 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL |
| &dma2 5 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| io-channels = <&adc1 18>; |
| }; |
| }; |
