| /* |
| * Copyright 2024 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| / { |
| aliases { |
| sram-ext = &aps6404l; |
| }; |
| }; |
| |
| &w25q512jvfiq { |
| /* |
| * Lower max FlexSPI frequency to 109MHz, as the PSRAM does not support |
| * higher frequencies at 3.3V |
| */ |
| spi-max-frequency = <109000000>; |
| }; |
| |
| &aps6404l { |
| status = "okay"; |
| }; |
| |
| &pinctrl { |
| pinmux_flexspi_safe: pinmux-flexspi-safe { |
| group0 { |
| pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO35 |
| IO_MUX_QUAD_SPI_PSRAM_IO36 |
| IO_MUX_QUAD_SPI_PSRAM_IO38 |
| IO_MUX_QUAD_SPI_PSRAM_IO39 |
| IO_MUX_QUAD_SPI_PSRAM_IO40 |
| IO_MUX_QUAD_SPI_PSRAM_IO41>; |
| slew-rate = "normal"; |
| }; |
| |
| group1 { |
| pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO37>; |
| slew-rate = "normal"; |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| /* Override pin control state to use one that only changes the PSRAM pin |
| * configuration |
| */ |
| &flexspi { |
| pinctrl-0 = <&pinmux_flexspi_safe>; |
| pinctrl-names = "default"; |
| }; |