commit 7f577b2d5cce16a44815310cde6f3080e047d9dd
author Benjamin Walsh <benjamin.walsh@windriver.com> Tue Dec 13 12:07:49 2016 -0500
committer Maureen Helm <maureen.helm@nxp.com> Thu Dec 15 15:57:10 2016 +0000
tree 799b1395cc4e7d6dcd8df541565324e735269662
parent c01625210802ad319aeee70830dadff9193fe7f3

arm: better handling of IRQ priorities reserved by the kernel

There are now three flags that decide how many priorities are reserved
by the kernel, each one requiring one priority level: Zero Latency
Interrupts, BASEPRI locking (for SVC usage) and faults that are not at
priority -1, so that taking them in an ISR actually triggers the fault
synchronously.

Change-Id: I7f4d760c9110051aeb82dcfd8cd68026a9b74b54
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>

include/arch/arm/cortex_m/nvic.h

diff --git a/include/arch/arm/cortex_m/nvic.h b/include/arch/arm/cortex_m/nvic.h
index 1cc0a13..4deaf8e 100644
--- a/include/arch/arm/cortex_m/nvic.h
+++ b/include/arch/arm/cortex_m/nvic.h
@@ -46,12 +46,29 @@
 /* for assembler, only works with constants */
 #define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff)
 
-#if defined(CONFIG_ZERO_LATENCY_IRQS)
-#define _IRQ_PRIO_OFFSET 3
+#ifdef CONFIG_ZERO_LATENCY_IRQS
+#define ZERO_LATENCY_IRQS_RESERVED_PRIO 1
 #else
-#define _IRQ_PRIO_OFFSET 2
+#define ZERO_LATENCY_IRQS_RESERVED_PRIO 0
 #endif
 
+#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
+#define HAS_BASEPRI_RESERVED_PRIO 1
+#else
+#define HAS_BASEPRI_RESERVED_PRIO 0
+#endif
+
+#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
+#define HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO 1
+#else
+#define HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO 0
+#endif
+
+#define _IRQ_PRIO_OFFSET \
+	(ZERO_LATENCY_IRQS_RESERVED_PRIO + \
+	 HAS_BASEPRI_RESERVED_PRIO + \
+	 HAS_PROGRAMMABLE_FAULT_PRIOS_RESERVED_PRIO)
+
 #define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(_IRQ_PRIO_OFFSET)
 
 /* no exc #0 */