| # Copyright (c) 2025 Renesas Electronics Corporation | |
| # SPDX-License-Identifier: Apache-2.0 | |
| description: Renesas RZ Clock Generator Circuit PLL Clock | |
| compatible: "renesas,rz-cgc-pll" | |
| include: [base.yaml] | |
| properties: | |
| state: | |
| type: string | |
| default: initial | |
| enum: | |
| - initial | |
| - standby | |
| - normal | |
| description: PLL1 state |