| /* |
| * Copyright 2021, 2024 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <nxp/nxp_imx8.dtsi> |
| |
| / { |
| irqsteer: interrupt-controller@51080000 { |
| compatible = "nxp,irqsteer-intc"; |
| reg = <0x51080000 DT_SIZE_K(64)>; |
| power-domains = <&irqstr_pd>; |
| |
| #size-cells = <0>; |
| #address-cells = <1>; |
| |
| master0: interrupt-controller@0 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 19 0 0>; |
| }; |
| |
| master1: interrupt-controller@1 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <1>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 20 0 0>; |
| }; |
| |
| master2: interrupt-controller@2 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <2>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 21 0 0>; |
| }; |
| |
| master3: interrupt-controller@3 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <3>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 22 0 0>; |
| }; |
| |
| master4: interrupt-controller@4 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <4>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 23 0 0>; |
| }; |
| |
| master5: interrupt-controller@5 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <5>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 24 0 0>; |
| }; |
| |
| master6: interrupt-controller@6 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <6>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 25 0 0>; |
| }; |
| |
| master7: interrupt-controller@7 { |
| compatible = "nxp,irqsteer-master"; |
| reg = <7>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupts-extended = <&clic 26 0 0>; |
| }; |
| }; |
| }; |
