drivers: spi: stm32: Use 'st,stm32h7-spi' compatible input when possible
Instead of using or'ed list of Kconfig options listing the compatible
series with what can be called "stm32h7 variant", use the matching
compatible information.
This will prevent to update the driver next time that a compatible series
is ported into zephyr.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c
index 7e3ca9a..61d3e17 100644
--- a/drivers/spi/spi_ll_stm32.c
+++ b/drivers/spi/spi_ll_stm32.c
@@ -32,9 +32,7 @@
* error flag, because STM32F1 SoCs do not support it and STM32CUBE
* for F1 family defines an unused LL_SPI_SR_FRE.
*/
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
#define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCE | LL_SPI_SR_MODF | \
LL_SPI_SR_OVR | LL_SPI_SR_TIFRE)
#else
@@ -259,9 +257,7 @@
/* NOP */
}
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
/* With the STM32MP1, STM32U5 and the STM32H7,
* if the device is the SPI master,
* we need to enable the start of the transfer with
@@ -545,9 +541,7 @@
LL_SPI_DisableCRC(spi);
if (config->cs || !IS_ENABLED(CONFIG_SPI_STM32_USE_HW_SS)) {
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
if (LL_SPI_GetNSSPolarity(spi) == LL_SPI_NSS_POLARITY_LOW)
LL_SPI_SetInternalSSLevel(spi, LL_SPI_SS_LEVEL_HIGH);
diff --git a/drivers/spi/spi_ll_stm32.h b/drivers/spi/spi_ll_stm32.h
index 969c0b9..38c5342 100644
--- a/drivers/spi/spi_ll_stm32.h
+++ b/drivers/spi/spi_ll_stm32.h
@@ -96,9 +96,7 @@
static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
return LL_SPI_IsActiveFlag_TXP(spi);
#else
return LL_SPI_IsActiveFlag_TXE(spi);
@@ -107,9 +105,7 @@
static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
return LL_SPI_IsActiveFlag_RXP(spi);
#else
return LL_SPI_IsActiveFlag_RXNE(spi);
@@ -118,9 +114,7 @@
static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_EnableIT_TXP(spi);
#else
LL_SPI_EnableIT_TXE(spi);
@@ -129,9 +123,7 @@
static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_EnableIT_RXP(spi);
#else
LL_SPI_EnableIT_RXNE(spi);
@@ -140,9 +132,7 @@
static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_EnableIT_UDR(spi);
LL_SPI_EnableIT_OVR(spi);
LL_SPI_EnableIT_CRCERR(spi);
@@ -155,9 +145,7 @@
static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_DisableIT_TXP(spi);
#else
LL_SPI_DisableIT_TXE(spi);
@@ -166,9 +154,7 @@
static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_DisableIT_RXP(spi);
#else
LL_SPI_DisableIT_RXNE(spi);
@@ -177,9 +163,7 @@
static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_DisableIT_UDR(spi);
LL_SPI_DisableIT_OVR(spi);
LL_SPI_DisableIT_CRCERR(spi);
@@ -192,9 +176,7 @@
static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
return LL_SPI_IsActiveFlag_EOT(spi);
#else
return LL_SPI_IsActiveFlag_BSY(spi);
@@ -207,9 +189,7 @@
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_fifo)
static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_01DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
@@ -218,9 +198,7 @@
static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_02DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_HALF);
@@ -230,9 +208,7 @@
static inline void ll_func_disable_spi(SPI_TypeDef *spi)
{
-#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
- defined(CONFIG_SOC_SERIES_STM32H7X) || \
- defined(CONFIG_SOC_SERIES_STM32U5X)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
if (LL_SPI_IsActiveMasterTransfer(spi)) {
LL_SPI_SuspendMasterTransfer(spi);
while (LL_SPI_IsActiveMasterTransfer(spi)) {
