| # Kconfig - STM32 MCU clock control driver config |
| # |
| # Copyright (c) 2017 Linaro |
| # |
| # SPDX-License-Identifier: Apache-2.0 |
| # |
| |
| if SOC_FAMILY_STM32 |
| |
| menuconfig CLOCK_CONTROL_STM32_CUBE |
| bool |
| prompt "STM32 Reset & Clock Control" |
| depends on CLOCK_CONTROL |
| default n if SOC_SERIES_STM32 |
| help |
| Enable driver for Reset & Clock Control subsystem found |
| in STM32 family of MCUs |
| |
| config CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY |
| int "Clock Control Device Priority" |
| default 1 |
| depends on CLOCK_CONTROL_STM32_CUBE |
| help |
| This option controls the priority of clock control |
| device initialization. Higher priority ensures that the device |
| is initialized earlier in the startup cycle. If unsure, leave |
| at default value 1 |
| |
| choice |
| prompt "STM32 System Clock Source" |
| depends on CLOCK_CONTROL_STM32_CUBE |
| default CLOCK_STM32_SYSCLK_SRC_PLL |
| |
| config CLOCK_STM32_SYSCLK_SRC_HSE |
| bool "HSE" |
| help |
| Use HSE as source of SYSCLK |
| |
| config CLOCK_STM32_SYSCLK_SRC_HSI |
| bool "HSI" |
| help |
| Use HSI as source of SYSCLK |
| |
| config CLOCK_STM32_SYSCLK_SRC_PLL |
| bool "PLL" |
| help |
| Use PLL as source of SYSCLK |
| |
| endchoice |
| |
| config CLOCK_STM32_HSE_BYPASS |
| bool "HSE bypass" |
| depends on CLOCK_CONTROL_STM32_CUBE && (CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE) |
| help |
| Enable this option to bypass external high-speed clock (HSE). |
| |
| config CLOCK_STM32_HSE_CLOCK |
| int "HSE clock value" |
| depends on CLOCK_CONTROL_STM32_CUBE && (CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE) |
| help |
| Value of external high-speed clock (HSE). |
| |
| choice |
| prompt "STM32 PLL Clock Source" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default CLOCK_STM32_PLL_SRC_HSI |
| |
| config CLOCK_STM32_PLL_SRC_MSI |
| bool "MSI" |
| help |
| Use MSI as source of PLL |
| |
| config CLOCK_STM32_PLL_SRC_HSI |
| bool "HSI" |
| help |
| Use HSI as source of PLL |
| |
| config CLOCK_STM32_PLL_SRC_HSE |
| bool "HSE" |
| help |
| Use HSE as source of PLL |
| endchoice |
| |
| if SOC_SERIES_STM32F3X |
| |
| config CLOCK_STM32_PLL_PREDIV |
| int "PREDIV Prescaler" |
| depends on CLOCK_CONTROL_STM32_CUBE |
| default 1 |
| range 1 16 |
| help |
| PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16. |
| |
| config CLOCK_STM32_PLL_PREDIV1 |
| int "PREDIV1 Prescaler" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_PLL_SRC_HSE && (SOC_STM32F302XE || SOC_STM32F303XE || SOC_STM32F398XX) |
| default 1 |
| range 1 16 |
| help |
| PREDIV is PLLSCR clock signal prescaler, present on STM32F302xE, STM32F303xE and STM32F39xx SoCs. |
| Allowed values: 1 - 16. |
| |
| config CLOCK_STM32_PLL_MULTIPLIER |
| int "PLL multiplier" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 9 |
| range 2 16 |
| help |
| PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz. |
| |
| endif # SOC_SERIES_STM32F3X |
| |
| if SOC_SERIES_STM32L4X |
| |
| config CLOCK_STM32_PLL_M_DIVISOR |
| int "PLL divisor" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 1 |
| range 1 8 |
| help |
| PLL divisor, allowed values: 1-8. With this ensure that the PLL |
| VCO input frequency ranges from 4 to 16MHz. |
| |
| config CLOCK_STM32_PLL_N_MULTIPLIER |
| int "PLL multiplier" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 20 |
| range 8 86 |
| help |
| PLL multiplier, allowed values: 2-16. PLL output must not |
| exceed 344MHz. |
| |
| config CLOCK_STM32_PLL_P_DIVISOR |
| int "PLL P Divisor" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 7 |
| range 0 17 |
| help |
| PLL P Output divisor, allowed values: 0, 7, 17. |
| |
| config CLOCK_STM32_PLL_Q_DIVISOR |
| int "PLL Q Divisor" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 2 |
| range 0 8 |
| help |
| PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8. |
| |
| config CLOCK_STM32_PLL_R_DIVISOR |
| int "PLL R Divisor" |
| depends on CLOCK_CONTROL_STM32_CUBE && CLOCK_STM32_SYSCLK_SRC_PLL |
| default 4 |
| range 0 8 |
| help |
| PLL R Output divisor, allowed values: 0, 2, 4, 6, 8. |
| |
| endif # SOC_SERIES_STM32L4X |
| |
| config CLOCK_STM32_AHB_PRESCALER |
| int "AHB prescaler" |
| depends on CLOCK_CONTROL_STM32_CUBE |
| default 0 |
| range 0 512 |
| help |
| AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, |
| 256, 512. |
| |
| config CLOCK_STM32_APB1_PRESCALER |
| int "APB1 prescaler" |
| depends on CLOCK_CONTROL_STM32_CUBE |
| default 1 |
| range 1 16 |
| help |
| APB1 Low speed clock (PCLK1) prescaler, allowed values: |
| 1, 2, 4, 8, 16 |
| |
| config CLOCK_STM32_APB2_PRESCALER |
| int "APB2 prescaler" |
| depends on CLOCK_CONTROL_STM32_CUBE |
| default 1 |
| range 1 16 |
| help |
| APB2 High speed clock (PCLK2) prescaler, allowed values: |
| 1, 2, 4, 8, 16 |
| |
| endif # SOC_FAMILY_STM32 |