| commit | 8a4b078c854961d7e8ae2f62dca7bf55ed7edc36 | [log] [tgz] |
|---|---|---|
| author | Georgij Cernysiov <geo.cgv@gmail.com> | Tue Feb 08 12:46:14 2022 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Tue Feb 08 10:20:53 2022 -0500 |
| tree | 1ca782d4621a7dae6c5298eff17505e9c5923801 | |
| parent | 21867fd4d0c5039621a906931b56f2763e93158b [diff] |
include: drivers: clock_control: stm32: fix xtpre Correct DT property to set correct STM32_PLL_XTPRE value. The driver bindings defined `xtpre` instead of used `xtre` in the `DT_PROP` macro. That allows to use F1 PLL clock with division by 2. Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>