| # Copyright (c) 2019 Intel Corporation |
| # SPDX-License-Identifier: Apache-2.0 |
| bool "Designware Interrupt Controller" |
| depends on MULTI_LEVEL_INTERRUPTS |
| Designware Interrupt Controller can be used as a 2nd level interrupt |
| controller which combines several sources of interrupt into one line |
| that is then routed to the 1st level interrupt controller. |
| string "Name for Designware Interrupt Controller" |
| Give a name for the instance of Designware Interrupt Controller |
| int "Parent interrupt number to which DW_ICTL maps" |
| Parent interrupt number to which DW_ICTL maps |
| int "Offset in the SW ISR Table" |
| This indicates the offset in the SW_ISR_TABLE beginning from where |
| the ISRs for Designware Interrupt Controller are assigned. |
| config DW_ICTL_INIT_PRIORITY |
| int "Init priority for DW interrupt controller" |
| DesignWare Interrupt Controller initialization priority. |