/* | |
* Copyright (c) 2021 STMicroelectronics | |
* | |
* SPDX-License-Identifier: Apache-2.0 | |
*/ | |
/* Set div-q to get test clk freq into acceptable SPI freq range */ | |
&pll { | |
/delete-property/ div-q; | |
div-q = <8>; | |
}; | |
/* Define PLL1_Q as SPI1 kernel clock source */ | |
&spi1 { | |
/delete-property/ clocks; | |
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, | |
<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; | |
}; |