boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi

/*
 * Copyright 2022-2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <nxp/s32/S32Z27-BGA594-pinctrl.h>

&pinctrl {
	uart0_default: uart0_default {
		group1 {
			pinmux = <PB10_LIN_0_TX>;
			output-enable;
		};

		group2 {
			pinmux = <PB11_LIN_0_RX>;
			input-enable;
		};
	};

	uart9_default: uart9_default {
		group1 {
			pinmux = <PM6_LIN_9_TX>;
			output-enable;
		};

		group2 {
			pinmux = <PM7_LIN_9_RX>;
			input-enable;
		};
	};

	emdio_default: emdio_default {
		group1 {
			pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>;
			input-enable;
			output-enable;
		};

		group2 {
			pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>;
			input-enable;
			output-enable;
			drive-open-drain;
		};
	};

	eth0_default: eth0_default {
		group1 {
			pinmux = <PF2_ETH_0_RX_CLK>,
				 <PF3_ETH_0_RGMII_RXCTL>,
				 <PF4_ETH_0_RGMII_RXD_0>,
				 <PF5_ETH_0_RGMII_RXD_1>,
				 <PF6_ETH_0_RGMII_RXD_2>,
				 <PF7_ETH_0_RGMII_RXD_3>;
			input-enable;
		};

		group2 {
			pinmux = <PE12_ETH_0_RGMII_TXC>,
				 <PE13_ETH_0_RGMII_TXCTL>,
				 <PE14_ETH_0_RGMII_TXD_0>,
				 <PE15_ETH_0_RGMII_TXD_1>,
				 <PF0_ETH_0_RGMII_TXD_2>,
				 <PF1_ETH_0_RGMII_TXD_3>;
			output-enable;
		};
	};

	canxl0_default: canxl0_default {
		group1 {
			pinmux = <PN2_CANXL_0_RX>;
			input-enable;
		};

		group2 {
			pinmux = <PN1_CANXL_0_TX>;
			output-enable;
		};
	};

	canxl1_default: canxl1_default {
		group1 {
			pinmux = <PM11_CANXL_1_RX>;
			input-enable;
		};

		group2 {
			pinmux = <PM10_CANXL_1_TX>;
			output-enable;
		};
	};

	flexcan0_default: flexcan0_default {
		group1 {
			pinmux = <PA5_CAN_0_RX>;
			input-enable;
		};

		group2 {
			pinmux = <PA4_CAN_0_TX>;
			output-enable;
		};
	};

	flexcan1_default: flexcan1_default {
		group1 {
			pinmux = <PB7_CAN_1_RX>;
			input-enable;
		};

		group2 {
			pinmux = <PB6_CAN_1_TX>;
			output-enable;
		};
	};

	i2c1_default: i2c1_default {
		group1 {
			pinmux = <(PC15_I2C_1_SDA_I | PC15_I2C_1_SDA_O)>,
				 <(PD0_I2C_1_SCL_I | PD0_I2C_1_SCL_O)>;
			input-enable;
			output-enable;
			drive-open-drain;
		};
	};

	i2c2_default: i2c2_default {
		group1 {
			pinmux = <(PJ11_I2C_2_SDA_I | PJ11_I2C_2_SDA_O)>,
				 <(PJ10_I2C_2_SCL_I | PJ10_I2C_2_SCL_O)>;
			input-enable;
			output-enable;
			drive-open-drain;
		};
	};

	qspi0_default: qspi0_default {
		group1 {
			pinmux = <PI4_QSPI_0_DATA_A_O0>, <PH14_QSPI_0_DATA_A_O1>,
				 <PI8_QSPI_0_DATA_A_O2>, <PI1_QSPI_0_DATA_A_O3>,
				 <PI5_QSPI_0_DATA_A_O4>, <PH15_QSPI_0_DATA_A_O5>,
				 <PI7_QSPI_0_DATA_A_O6>, <PI0_QSPI_0_DATA_A_O7>,
				 <PI6_QSPI_0_DQS_A_O>;
			output-enable;
			input-enable;
		};

		group2 {
			pinmux = <PH13_QSPI_0_CS_A0>, <PI9_QSPI_0_CS_A1>,
				 <PI2_QSPI_0_CK_A_B>, <PI3_QSPI_0_CK_A>;
			output-enable;
		};

		group3 {
			pinmux = <PH12_QSPI_0_INTA_B>;
			input-enable;
		};
	};
};